2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.16 2004/02/16 18:51:01 joerg Exp $
34 #include "opt_simos.h"
35 #include "opt_compat_oldpci.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/fcntl.h>
43 #include <sys/kernel.h>
44 #include <sys/queue.h>
45 #include <sys/types.h>
50 #include <vm/vm_extern.h>
53 #include <machine/bus.h>
55 #include <machine/resource.h>
56 #include <machine/md_var.h> /* For the Alpha */
58 #include <bus/pci/i386/pci_cfgreg.h>
61 #include <sys/pciio.h>
64 #include "pci_private.h"
69 #include <machine/rpb.h>
73 #include <machine/smp.h>
76 static devclass_t pci_devclass;
78 static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
81 u_int32_t devid; /* Vendor/device of the card */
83 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
88 struct pci_quirk pci_quirks[] = {
90 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
92 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
93 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
98 /* map register information */
99 #define PCI_MAPMEM 0x01 /* memory map */
100 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
101 #define PCI_MAPPORT 0x04 /* port map */
103 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
104 u_int32_t pci_numdevs = 0;
105 static u_int32_t pci_generation = 0;
108 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
110 struct pci_devinfo *dinfo;
112 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
113 if ((dinfo->cfg.bus == bus) &&
114 (dinfo->cfg.slot == slot) &&
115 (dinfo->cfg.func == func)) {
116 return (dinfo->cfg.dev);
124 pci_find_device (u_int16_t vendor, u_int16_t device)
126 struct pci_devinfo *dinfo;
128 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
129 if ((dinfo->cfg.vendor == vendor) &&
130 (dinfo->cfg.device == device)) {
131 return (dinfo->cfg.dev);
138 /* return base address of memory or port map */
141 pci_mapbase(unsigned mapreg)
144 if ((mapreg & 0x01) == 0)
146 return (mapreg & ~mask);
149 /* return map type of memory or port map */
152 pci_maptype(unsigned mapreg)
154 static u_int8_t maptype[0x10] = {
155 PCI_MAPMEM, PCI_MAPPORT,
157 PCI_MAPMEM, PCI_MAPPORT,
159 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
160 PCI_MAPMEM|PCI_MAPMEMP, 0,
161 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
165 return maptype[mapreg & 0x0f];
168 /* return log2 of map size decoded for memory or port map */
171 pci_mapsize(unsigned testval)
175 testval = pci_mapbase(testval);
178 while ((testval & 1) == 0)
187 /* return log2 of address range supported by map register */
190 pci_maprange(unsigned mapreg)
193 switch (mapreg & 0x07) {
209 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
212 pci_fixancient(pcicfgregs *cfg)
214 if (cfg->hdrtype != 0)
217 /* PCI to PCI bridges use header type 1 */
218 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
222 /* read config data specific to header type 1 device (PCI to PCI bridge) */
225 pci_readppb(device_t pcib, int b, int s, int f)
229 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
233 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
234 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
236 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
238 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
240 PCIB_READ_CONFIG(pcib, b, s, f,
242 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
244 PCIB_READ_CONFIG(pcib, b, s, f,
245 PCIR_IOLIMITL_1, 1));
247 p->membase = PCI_PPBMEMBASE (0,
248 PCIB_READ_CONFIG(pcib, b, s, f,
250 p->memlimit = PCI_PPBMEMLIMIT (0,
251 PCIB_READ_CONFIG(pcib, b, s, f,
252 PCIR_MEMLIMIT_1, 2));
254 p->pmembase = PCI_PPBMEMBASE (
255 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
256 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
258 p->pmemlimit = PCI_PPBMEMLIMIT (
259 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
261 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
266 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
269 pci_readpcb(device_t pcib, int b, int s, int f)
273 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
277 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
278 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
280 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
282 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
283 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
284 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
285 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
287 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
288 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
289 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
290 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
292 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
296 /* extract header type specific config data */
299 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
301 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
302 switch (cfg->hdrtype) {
304 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
305 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
306 cfg->nummaps = PCI_MAXMAPS_0;
309 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
310 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
311 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
312 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
313 cfg->nummaps = PCI_MAXMAPS_1;
314 cfg->hdrspec = pci_readppb(pcib, b, s, f);
317 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
318 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
319 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
320 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
321 cfg->nummaps = PCI_MAXMAPS_2;
322 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
328 /* read configuration header into pcicfgrect structure */
331 pci_read_device(device_t pcib, int b, int s, int f, int width)
333 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
335 pcicfgregs *cfg = NULL;
336 struct pci_devinfo *devlist_entry;
337 struct devlist *devlist_head;
339 devlist_head = &pci_devq;
341 devlist_entry = NULL;
343 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
345 devlist_entry = malloc(width,
346 M_DEVBUF, M_WAITOK | M_ZERO);
347 if (devlist_entry == NULL)
350 cfg = &devlist_entry->cfg;
355 cfg->vendor = REG(PCIR_VENDOR, 2);
356 cfg->device = REG(PCIR_DEVICE, 2);
357 cfg->cmdreg = REG(PCIR_COMMAND, 2);
358 cfg->statreg = REG(PCIR_STATUS, 2);
359 cfg->baseclass = REG(PCIR_CLASS, 1);
360 cfg->subclass = REG(PCIR_SUBCLASS, 1);
361 cfg->progif = REG(PCIR_PROGIF, 1);
362 cfg->revid = REG(PCIR_REVID, 1);
363 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1);
364 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
365 cfg->lattimer = REG(PCIR_LATTIMER, 1);
366 cfg->intpin = REG(PCIR_INTPIN, 1);
367 cfg->intline = REG(PCIR_INTLINE, 1);
369 alpha_platform_assign_pciintr(cfg);
373 if (cfg->intpin != 0) {
376 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
378 /* PCI specific entry found in MP table */
379 if (airq != cfg->intline) {
380 undirect_pci_irq(cfg->intline);
385 * PCI interrupts might be redirected to the
386 * ISA bus according to some MP tables. Use the
387 * same methods as used by the ISA devices
388 * devices to find the proper IOAPIC int pin.
390 airq = isa_apic_irq(cfg->intline);
391 if ((airq >= 0) && (airq != cfg->intline)) {
392 /* XXX: undirect_pci_irq() ? */
393 undirect_isa_irq(cfg->intline);
400 cfg->mingnt = REG(PCIR_MINGNT, 1);
401 cfg->maxlat = REG(PCIR_MAXLAT, 1);
403 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
404 cfg->hdrtype &= ~PCIM_MFDEV;
407 pci_hdrtypedata(pcib, b, s, f, cfg);
409 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
410 pci_read_extcap(pcib, cfg);
412 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
414 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
415 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
416 devlist_entry->conf.pc_sel.pc_func = cfg->func;
417 devlist_entry->conf.pc_hdr = cfg->hdrtype;
419 devlist_entry->conf.pc_subvendor = cfg->subvendor;
420 devlist_entry->conf.pc_subdevice = cfg->subdevice;
421 devlist_entry->conf.pc_vendor = cfg->vendor;
422 devlist_entry->conf.pc_device = cfg->device;
424 devlist_entry->conf.pc_class = cfg->baseclass;
425 devlist_entry->conf.pc_subclass = cfg->subclass;
426 devlist_entry->conf.pc_progif = cfg->progif;
427 devlist_entry->conf.pc_revid = cfg->revid;
432 return (devlist_entry);
437 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
439 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
440 int ptr, nextptr, ptrptr;
442 switch (cfg->hdrtype) {
450 return; /* no extended capabilities support */
452 nextptr = REG(ptrptr, 1); /* sanity check? */
455 * Read capability entries.
457 while (nextptr != 0) {
460 printf("illegal PCI extended capability offset %d\n",
464 /* Find the next entry */
466 nextptr = REG(ptr + 1, 1);
468 /* Process this entry */
469 switch (REG(ptr, 1)) {
470 case 0x01: /* PCI power management */
471 if (cfg->pp_cap == 0) {
472 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
473 cfg->pp_status = ptr + PCIR_POWER_STATUS;
474 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
475 if ((nextptr - ptr) > PCIR_POWER_DATA)
476 cfg->pp_data = ptr + PCIR_POWER_DATA;
486 /* free pcicfgregs structure and all depending data structures */
489 pci_freecfg(struct pci_devinfo *dinfo)
491 struct devlist *devlist_head;
493 devlist_head = &pci_devq;
495 if (dinfo->cfg.hdrspec != NULL)
496 free(dinfo->cfg.hdrspec, M_DEVBUF);
497 /* XXX this hasn't been tested */
498 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
499 free(dinfo, M_DEVBUF);
501 /* increment the generation count */
504 /* we're losing one device */
511 * PCI power manangement
514 pci_set_powerstate_method(device_t dev, device_t child, int state)
516 struct pci_devinfo *dinfo = device_get_ivars(child);
517 pcicfgregs *cfg = &dinfo->cfg;
521 if (cfg->pp_cap != 0) {
522 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
525 case PCI_POWERSTATE_D0:
526 status |= PCIM_PSTAT_D0;
528 case PCI_POWERSTATE_D1:
529 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
530 status |= PCIM_PSTAT_D1;
535 case PCI_POWERSTATE_D2:
536 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
537 status |= PCIM_PSTAT_D2;
542 case PCI_POWERSTATE_D3:
543 status |= PCIM_PSTAT_D3;
549 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
557 pci_get_powerstate_method(device_t dev, device_t child)
559 struct pci_devinfo *dinfo = device_get_ivars(child);
560 pcicfgregs *cfg = &dinfo->cfg;
564 if (cfg->pp_cap != 0) {
565 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
566 switch (status & PCIM_PSTAT_DMASK) {
568 result = PCI_POWERSTATE_D0;
571 result = PCI_POWERSTATE_D1;
574 result = PCI_POWERSTATE_D2;
577 result = PCI_POWERSTATE_D3;
580 result = PCI_POWERSTATE_UNKNOWN;
584 /* No support, device is always at D0 */
585 result = PCI_POWERSTATE_D0;
591 * Some convenience functions for PCI device drivers.
595 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
599 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
601 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
605 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
609 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
611 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
615 pci_enable_busmaster_method(device_t dev, device_t child)
617 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
621 pci_disable_busmaster_method(device_t dev, device_t child)
623 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
627 pci_enable_io_method(device_t dev, device_t child, int space)
631 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN);
634 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN);
640 pci_disable_io_method(device_t dev, device_t child, int space)
644 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN);
647 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN);
653 * This is the user interface to PCI configuration space.
657 pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
659 if ((oflags & FWRITE) && securelevel > 0) {
666 pci_close(dev_t dev, int flag, int devtype, struct thread *td)
672 * Match a single pci_conf structure against an array of pci_match_conf
673 * structures. The first argument, 'matches', is an array of num_matches
674 * pci_match_conf structures. match_buf is a pointer to the pci_conf
675 * structure that will be compared to every entry in the matches array.
676 * This function returns 1 on failure, 0 on success.
679 pci_conf_match(struct pci_match_conf *matches, int num_matches,
680 struct pci_conf *match_buf)
684 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
687 for (i = 0; i < num_matches; i++) {
689 * I'm not sure why someone would do this...but...
691 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
695 * Look at each of the match flags. If it's set, do the
696 * comparison. If the comparison fails, we don't have a
697 * match, go on to the next item if there is one.
699 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
700 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
703 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
704 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
707 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
708 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
711 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
712 && (match_buf->pc_vendor != matches[i].pc_vendor))
715 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
716 && (match_buf->pc_device != matches[i].pc_device))
719 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
720 && (match_buf->pc_class != matches[i].pc_class))
723 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
724 && (match_buf->pd_unit != matches[i].pd_unit))
727 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
728 && (strncmp(matches[i].pd_name, match_buf->pd_name,
729 sizeof(match_buf->pd_name)) != 0))
739 * Locate the parent of a PCI device by scanning the PCI devlist
740 * and return the entry for the parent.
741 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
742 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
746 pci_devlist_get_parent(pcicfgregs *cfg)
748 struct devlist *devlist_head;
749 struct pci_devinfo *dinfo;
750 pcicfgregs *bridge_cfg;
753 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
755 /* If the device is on PCI bus 0, look for the host */
757 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
758 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
759 bridge_cfg = &dinfo->cfg;
760 if (bridge_cfg->baseclass == PCIC_BRIDGE
761 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
762 && bridge_cfg->bus == cfg->bus) {
768 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
770 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
771 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
772 bridge_cfg = &dinfo->cfg;
773 if (bridge_cfg->baseclass == PCIC_BRIDGE
774 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
775 && bridge_cfg->secondarybus == cfg->bus) {
785 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
792 if (!(flag & FWRITE))
799 struct pci_devinfo *dinfo;
800 struct pci_conf_io *cio;
801 struct devlist *devlist_head;
802 struct pci_match_conf *pattern_buf;
807 cio = (struct pci_conf_io *)data;
813 * Hopefully the user won't pass in a null pointer, but it
814 * can't hurt to check.
822 * If the user specified an offset into the device list,
823 * but the list has changed since they last called this
824 * ioctl, tell them that the list has changed. They will
825 * have to get the list from the beginning.
827 if ((cio->offset != 0)
828 && (cio->generation != pci_generation)){
829 cio->num_matches = 0;
830 cio->status = PCI_GETCONF_LIST_CHANGED;
836 * Check to see whether the user has asked for an offset
837 * past the end of our list.
839 if (cio->offset >= pci_numdevs) {
840 cio->num_matches = 0;
841 cio->status = PCI_GETCONF_LAST_DEVICE;
846 /* get the head of the device queue */
847 devlist_head = &pci_devq;
850 * Determine how much room we have for pci_conf structures.
851 * Round the user's buffer size down to the nearest
852 * multiple of sizeof(struct pci_conf) in case the user
853 * didn't specify a multiple of that size.
855 iolen = min(cio->match_buf_len -
856 (cio->match_buf_len % sizeof(struct pci_conf)),
857 pci_numdevs * sizeof(struct pci_conf));
860 * Since we know that iolen is a multiple of the size of
861 * the pciconf union, it's okay to do this.
863 ionum = iolen / sizeof(struct pci_conf);
866 * If this test is true, the user wants the pci_conf
867 * structures returned to match the supplied entries.
869 if ((cio->num_patterns > 0)
870 && (cio->pat_buf_len > 0)) {
872 * pat_buf_len needs to be:
873 * num_patterns * sizeof(struct pci_match_conf)
874 * While it is certainly possible the user just
875 * allocated a large buffer, but set the number of
876 * matches correctly, it is far more likely that
877 * their kernel doesn't match the userland utility
878 * they're using. It's also possible that the user
879 * forgot to initialize some variables. Yes, this
880 * may be overly picky, but I hazard to guess that
881 * it's far more likely to just catch folks that
882 * updated their kernel but not their userland.
884 if ((cio->num_patterns *
885 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
886 /* The user made a mistake, return an error*/
887 cio->status = PCI_GETCONF_ERROR;
888 printf("pci_ioctl: pat_buf_len %d != "
889 "num_patterns (%d) * sizeof(struct "
890 "pci_match_conf) (%d)\npci_ioctl: "
891 "pat_buf_len should be = %d\n",
892 cio->pat_buf_len, cio->num_patterns,
893 (int)sizeof(struct pci_match_conf),
894 (int)sizeof(struct pci_match_conf) *
896 printf("pci_ioctl: do your headers match your "
898 cio->num_matches = 0;
904 * Check the user's buffer to make sure it's readable.
906 if (!useracc((caddr_t)cio->patterns,
907 cio->pat_buf_len, VM_PROT_READ)) {
908 printf("pci_ioctl: pattern buffer %p, "
909 "length %u isn't user accessible for"
910 " READ\n", cio->patterns,
916 * Allocate a buffer to hold the patterns.
918 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
920 error = copyin(cio->patterns, pattern_buf,
924 num_patterns = cio->num_patterns;
926 } else if ((cio->num_patterns > 0)
927 || (cio->pat_buf_len > 0)) {
929 * The user made a mistake, spit out an error.
931 cio->status = PCI_GETCONF_ERROR;
932 cio->num_matches = 0;
933 printf("pci_ioctl: invalid GETCONF arguments\n");
940 * Make sure we can write to the match buffer.
942 if (!useracc((caddr_t)cio->matches,
943 cio->match_buf_len, VM_PROT_WRITE)) {
944 printf("pci_ioctl: match buffer %p, length %u "
945 "isn't user accessible for WRITE\n",
946 cio->matches, cio->match_buf_len);
952 * Go through the list of devices and copy out the devices
953 * that match the user's criteria.
955 for (cio->num_matches = 0, error = 0, i = 0,
956 dinfo = STAILQ_FIRST(devlist_head);
957 (dinfo != NULL) && (cio->num_matches < ionum)
958 && (error == 0) && (i < pci_numdevs);
959 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
964 /* Populate pd_name and pd_unit */
966 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
967 name = device_get_name(dinfo->cfg.dev);
969 strncpy(dinfo->conf.pd_name, name,
970 sizeof(dinfo->conf.pd_name));
971 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
972 dinfo->conf.pd_unit =
973 device_get_unit(dinfo->cfg.dev);
976 if ((pattern_buf == NULL) ||
977 (pci_conf_match(pattern_buf, num_patterns,
978 &dinfo->conf) == 0)) {
981 * If we've filled up the user's buffer,
982 * break out at this point. Since we've
983 * got a match here, we'll pick right back
984 * up at the matching entry. We can also
985 * tell the user that there are more matches
988 if (cio->num_matches >= ionum)
991 error = copyout(&dinfo->conf,
992 &cio->matches[cio->num_matches],
993 sizeof(struct pci_conf));
999 * Set the pointer into the list, so if the user is getting
1000 * n records at a time, where n < pci_numdevs,
1005 * Set the generation, the user will need this if they make
1006 * another ioctl call with offset != 0.
1008 cio->generation = pci_generation;
1011 * If this is the last device, inform the user so he won't
1012 * bother asking for more devices. If dinfo isn't NULL, we
1013 * know that there are more matches in the list because of
1014 * the way the traversal is done.
1017 cio->status = PCI_GETCONF_LAST_DEVICE;
1019 cio->status = PCI_GETCONF_MORE_DEVS;
1021 if (pattern_buf != NULL)
1022 free(pattern_buf, M_TEMP);
1027 io = (struct pci_io *)data;
1028 switch(io->pi_width) {
1033 * Assume that the user-level bus number is
1034 * actually the pciN instance number. We map
1035 * from that to the real pcib+bus combination.
1037 pci = devclass_get_device(pci_devclass,
1040 int b = pcib_get_bus(pci);
1041 pcib = device_get_parent(pci);
1043 PCIB_READ_CONFIG(pcib,
1061 io = (struct pci_io *)data;
1062 switch(io->pi_width) {
1067 * Assume that the user-level bus number is
1068 * actually the pciN instance number. We map
1069 * from that to the real pcib+bus combination.
1071 pci = devclass_get_device(pci_devclass,
1074 int b = pcib_get_bus(pci);
1075 pcib = device_get_parent(pci);
1076 PCIB_WRITE_CONFIG(pcib,
1104 static struct cdevsw pcicdev = {
1111 /* open */ pci_open,
1112 /* close */ pci_close,
1114 /* write */ nowrite,
1115 /* ioctl */ pci_ioctl,
1118 /* strategy */ nostrategy,
1126 * New style pci driver. Parent device is either a pci-host-bridge or a
1127 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1131 pci_print_verbose(struct pci_devinfo *dinfo)
1134 pcicfgregs *cfg = &dinfo->cfg;
1136 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1137 cfg->vendor, cfg->device, cfg->revid);
1138 printf("\tbus=%d, slot=%d, func=%d\n",
1139 cfg->bus, cfg->slot, cfg->func);
1140 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1141 cfg->baseclass, cfg->subclass, cfg->progif,
1142 cfg->hdrtype, cfg->mfdev);
1143 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1144 cfg->subordinatebus, cfg->secondarybus);
1146 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1147 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1148 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1149 cfg->lattimer, cfg->lattimer * 30,
1150 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1151 #endif /* PCI_DEBUG */
1152 if (cfg->intpin > 0)
1153 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1158 pci_porten(device_t pcib, int b, int s, int f)
1160 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1161 & PCIM_CMD_PORTEN) != 0;
1165 pci_memen(device_t pcib, int b, int s, int f)
1167 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1168 & PCIM_CMD_MEMEN) != 0;
1172 * Add a resource based on a pci map register. Return 1 if the map
1173 * register is a 32bit map register or 2 if it is a 64bit register.
1176 pci_add_map(device_t pcib, int b, int s, int f, int reg,
1177 struct resource_list *rl)
1186 #ifdef PCI_ENABLE_IO_MODES
1191 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1193 if (map == 0 || map == 0xffffffff)
1194 return 1; /* skip invalid entry */
1196 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1197 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1198 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
1200 base = pci_mapbase(map);
1201 if (pci_maptype(map) & PCI_MAPMEM)
1202 type = SYS_RES_MEMORY;
1204 type = SYS_RES_IOPORT;
1205 ln2size = pci_mapsize(testval);
1206 ln2range = pci_maprange(testval);
1207 if (ln2range == 64) {
1208 /* Read the other half of a 64bit map register */
1209 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
1213 * This code theoretically does the right thing, but has
1214 * undesirable side effects in some cases where
1215 * peripherals respond oddly to having these bits
1216 * enabled. Leave them alone by default.
1218 #ifdef PCI_ENABLE_IO_MODES
1219 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1220 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1221 cmd |= PCIM_CMD_PORTEN;
1222 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1224 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1225 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1226 cmd |= PCIM_CMD_MEMEN;
1227 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1230 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1232 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1236 resource_list_add(rl, type, reg,
1237 base, base + (1 << ln2size) - 1,
1241 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1242 reg, pci_maptype(base), ln2range,
1243 (unsigned int) base, ln2size);
1246 return (ln2range == 64) ? 2 : 1;
1250 pci_add_resources(device_t pcib, int b, int s, int f, device_t dev)
1252 struct pci_devinfo *dinfo = device_get_ivars(dev);
1253 pcicfgregs *cfg = &dinfo->cfg;
1254 struct resource_list *rl = &dinfo->resources;
1255 struct pci_quirk *q;
1258 for (i = 0; i < cfg->nummaps;) {
1259 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl);
1262 for (q = &pci_quirks[0]; q->devid; q++) {
1263 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1264 && q->type == PCI_QUIRK_MAP_REG)
1265 pci_add_map(pcib, b, s, f, q->arg1, rl);
1268 if (cfg->intpin > 0 && cfg->intline != 255)
1269 resource_list_add(rl, SYS_RES_IRQ, 0,
1270 cfg->intline, cfg->intline, 1);
1274 pci_add_children(device_t dev, int busno)
1276 device_t pcib = device_get_parent(dev);
1280 maxslots = PCIB_MAXSLOTS(pcib);
1282 for (s = 0; s <= maxslots; s++) {
1283 int pcifunchigh = 0;
1284 for (f = 0; f <= pcifunchigh; f++) {
1285 struct pci_devinfo *dinfo =
1286 pci_read_device(pcib, busno, s, f, sizeof *dinfo);
1287 if (dinfo != NULL) {
1288 if (dinfo->cfg.mfdev)
1291 pci_print_verbose(dinfo);
1292 dinfo->cfg.dev = device_add_child(dev, NULL, -1);
1293 device_set_ivars(dinfo->cfg.dev, dinfo);
1294 pci_add_resources(pcib, busno, s, f,
1302 pci_probe(device_t dev)
1304 static int once, busno;
1306 device_set_desc(dev, "PCI bus");
1309 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev));
1312 * Since there can be multiple independently numbered PCI
1313 * busses on some large alpha systems, we can't use the unit
1314 * number to decide what bus we are probing. We ask the parent
1315 * pcib what our bus number is.
1317 busno = pcib_get_bus(dev);
1320 pci_add_children(dev, busno);
1323 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci");
1331 pci_print_resources(struct resource_list *rl, const char *name, int type,
1334 struct resource_list_entry *rle;
1335 int printed, retval;
1339 /* Yes, this is kinda cheating */
1340 SLIST_FOREACH(rle, rl, link) {
1341 if (rle->type == type) {
1343 retval += printf(" %s ", name);
1344 else if (printed > 0)
1345 retval += printf(",");
1347 retval += printf(format, rle->start);
1348 if (rle->count > 1) {
1349 retval += printf("-");
1350 retval += printf(format, rle->start +
1359 pci_print_child(device_t dev, device_t child)
1361 struct pci_devinfo *dinfo;
1362 struct resource_list *rl;
1366 dinfo = device_get_ivars(child);
1368 rl = &dinfo->resources;
1370 retval += bus_print_child_header(dev, child);
1372 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1373 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1374 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1375 if (device_get_flags(dev))
1376 retval += printf(" flags %#x", device_get_flags(dev));
1378 retval += printf(" at device %d.%d", pci_get_slot(child),
1379 pci_get_function(child));
1381 retval += bus_print_child_footer(dev, child);
1387 pci_probe_nomatch(device_t dev, device_t child)
1389 struct pci_devinfo *dinfo;
1395 dinfo = device_get_ivars(child);
1397 desc = pci_ata_match(child);
1398 if (!desc) desc = pci_usb_match(child);
1399 if (!desc) desc = pci_vga_match(child);
1400 if (!desc) desc = pci_chip_match(child);
1402 desc = "unknown card";
1405 device_printf(dev, "<%s>", desc);
1406 if (bootverbose || unknown) {
1407 printf(" (vendor=0x%04x, dev=0x%04x)",
1412 pci_get_slot(child),
1413 pci_get_function(child));
1414 if (cfg->intpin > 0 && cfg->intline != 255) {
1415 printf(" irq %d", cfg->intline);
1423 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1425 struct pci_devinfo *dinfo;
1428 dinfo = device_get_ivars(child);
1432 case PCI_IVAR_SUBVENDOR:
1433 *result = cfg->subvendor;
1435 case PCI_IVAR_SUBDEVICE:
1436 *result = cfg->subdevice;
1438 case PCI_IVAR_VENDOR:
1439 *result = cfg->vendor;
1441 case PCI_IVAR_DEVICE:
1442 *result = cfg->device;
1444 case PCI_IVAR_DEVID:
1445 *result = (cfg->device << 16) | cfg->vendor;
1447 case PCI_IVAR_CLASS:
1448 *result = cfg->baseclass;
1450 case PCI_IVAR_SUBCLASS:
1451 *result = cfg->subclass;
1453 case PCI_IVAR_PROGIF:
1454 *result = cfg->progif;
1456 case PCI_IVAR_REVID:
1457 *result = cfg->revid;
1459 case PCI_IVAR_INTPIN:
1460 *result = cfg->intpin;
1463 *result = cfg->intline;
1469 *result = cfg->slot;
1471 case PCI_IVAR_FUNCTION:
1472 *result = cfg->func;
1474 case PCI_IVAR_SECONDARYBUS:
1475 *result = cfg->secondarybus;
1477 case PCI_IVAR_SUBORDINATEBUS:
1478 *result = cfg->subordinatebus;
1480 case PCI_IVAR_ETHADDR:
1482 * The generic accessor doesn't deal with failure, so
1483 * we set the return value, then return an error.
1494 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1496 struct pci_devinfo *dinfo;
1499 dinfo = device_get_ivars(child);
1503 case PCI_IVAR_SUBVENDOR:
1504 case PCI_IVAR_SUBDEVICE:
1505 case PCI_IVAR_VENDOR:
1506 case PCI_IVAR_DEVICE:
1507 case PCI_IVAR_DEVID:
1508 case PCI_IVAR_CLASS:
1509 case PCI_IVAR_SUBCLASS:
1510 case PCI_IVAR_PROGIF:
1511 case PCI_IVAR_REVID:
1512 case PCI_IVAR_INTPIN:
1516 case PCI_IVAR_FUNCTION:
1517 case PCI_IVAR_ETHADDR:
1518 return EINVAL; /* disallow for now */
1520 case PCI_IVAR_SECONDARYBUS:
1521 cfg->secondarybus = value;
1523 case PCI_IVAR_SUBORDINATEBUS:
1524 cfg->subordinatebus = value;
1532 static struct resource *
1533 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1534 u_long start, u_long end, u_long count, u_int flags)
1536 struct pci_devinfo *dinfo = device_get_ivars(child);
1537 struct resource_list *rl = &dinfo->resources;
1540 pcicfgregs *cfg = &dinfo->cfg;
1542 * Perform lazy resource allocation
1544 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1546 if (device_get_parent(child) == dev) {
1548 * If device doesn't have an interrupt routed, and is
1549 * deserving of an interrupt, try to assign it one.
1551 if ((type == SYS_RES_IRQ) &&
1552 (cfg->intline == 255 || cfg->intline == 0) &&
1553 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
1554 cfg->intline = PCIB_ROUTE_INTERRUPT(
1555 device_get_parent(dev), child,
1557 if (cfg->intline != 255) {
1558 pci_write_config(child, PCIR_INTLINE,
1560 resource_list_add(rl, SYS_RES_IRQ, 0,
1561 cfg->intline, cfg->intline, 1);
1566 return resource_list_alloc(rl, dev, child, type, rid,
1567 start, end, count, flags);
1571 pci_release_resource(device_t dev, device_t child, int type, int rid,
1574 struct pci_devinfo *dinfo = device_get_ivars(child);
1575 struct resource_list *rl = &dinfo->resources;
1577 return resource_list_release(rl, dev, child, type, rid, r);
1581 pci_set_resource(device_t dev, device_t child, int type, int rid,
1582 u_long start, u_long count)
1584 struct pci_devinfo *dinfo = device_get_ivars(child);
1585 struct resource_list *rl = &dinfo->resources;
1587 resource_list_add(rl, type, rid, start, start + count - 1, count);
1592 pci_get_resource(device_t dev, device_t child, int type, int rid,
1593 u_long *startp, u_long *countp)
1595 struct pci_devinfo *dinfo = device_get_ivars(child);
1596 struct resource_list *rl = &dinfo->resources;
1597 struct resource_list_entry *rle;
1599 rle = resource_list_find(rl, type, rid);
1604 *startp = rle->start;
1606 *countp = rle->count;
1612 pci_delete_resource(device_t dev, device_t child, int type, int rid)
1614 printf("pci_delete_resource: PCI resources can not be deleted\n");
1618 pci_read_config_method(device_t dev, device_t child, int reg, int width)
1620 struct pci_devinfo *dinfo = device_get_ivars(child);
1621 pcicfgregs *cfg = &dinfo->cfg;
1623 return PCIB_READ_CONFIG(device_get_parent(dev),
1624 cfg->bus, cfg->slot, cfg->func,
1629 pci_write_config_method(device_t dev, device_t child, int reg,
1630 u_int32_t val, int width)
1632 struct pci_devinfo *dinfo = device_get_ivars(child);
1633 pcicfgregs *cfg = &dinfo->cfg;
1635 PCIB_WRITE_CONFIG(device_get_parent(dev),
1636 cfg->bus, cfg->slot, cfg->func,
1641 pci_modevent(module_t mod, int what, void *arg)
1645 STAILQ_INIT(&pci_devq);
1655 static device_method_t pci_methods[] = {
1656 /* Device interface */
1657 DEVMETHOD(device_probe, pci_probe),
1658 DEVMETHOD(device_attach, bus_generic_attach),
1659 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1660 DEVMETHOD(device_suspend, bus_generic_suspend),
1661 DEVMETHOD(device_resume, bus_generic_resume),
1664 DEVMETHOD(bus_print_child, pci_print_child),
1665 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1666 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1667 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1668 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1669 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1670 DEVMETHOD(bus_release_resource, pci_release_resource),
1671 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1672 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1673 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1674 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1675 DEVMETHOD(bus_set_resource, pci_set_resource),
1676 DEVMETHOD(bus_get_resource, pci_get_resource),
1677 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1680 DEVMETHOD(pci_read_config, pci_read_config_method),
1681 DEVMETHOD(pci_write_config, pci_write_config_method),
1682 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1683 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1684 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1685 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1686 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1687 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1692 static driver_t pci_driver = {
1698 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);