sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.94 2008/07/05 12:22:37 sephe Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include "opt_polling.h"
  76 #include "opt_ethernet.h"
  77
  78 #include <sys/param.h>
  79 #include <sys/bus.h>
  80 #include <sys/endian.h>
  81 #include <sys/kernel.h>
  82 #include <sys/ktr.h>
  83 #include <sys/interrupt.h>
  84 #include <sys/mbuf.h>
  85 #include <sys/malloc.h>
  86 #include <sys/queue.h>
  87 #include <sys/rman.h>
  88 #include <sys/serialize.h>
  89 #include <sys/socket.h>
  90 #include <sys/sockio.h>
  91 #include <sys/sysctl.h>
  92
  93 #include <net/bpf.h>
  94 #include <net/ethernet.h>
  95 #include <net/if.h>
  96 #include <net/if_arp.h>
  97 #include <net/if_dl.h>
  98 #include <net/if_media.h>
  99 #include <net/if_types.h>
 100 #include <net/ifq_var.h>
 101 #include <net/vlan/if_vlan_var.h>
 102 #include <net/vlan/if_vlan_ether.h>
 103
 104 #include <dev/netif/mii_layer/mii.h>
 105 #include <dev/netif/mii_layer/miivar.h>
 106 #include <dev/netif/mii_layer/brgphyreg.h>
 107
 108 #include <bus/pci/pcidevs.h>
 109 #include <bus/pci/pcireg.h>
 110 #include <bus/pci/pcivar.h>
 111
 112 #include <dev/netif/bge/if_bgereg.h>
 113
 114 /* "device miibus" required.  See GENERIC if you get errors here. */
 115 #include "miibus_if.h"
 116
 117 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 118 #define BGE_MIN_FRAME           60
 119
 120 /*
 121  * Various supported device vendors/types and their names. Note: the
 122  * spec seems to indicate that the hardware still has Alteon's vendor
 123  * ID burned into it, though it will always be overriden by the vendor
 124  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 125  */
 126 #define BGE_DEVDESC_MAX         64      /* Maximum device description length */
 127
 128 static struct bge_type bge_devs[] = {
 129         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 130                 "3COM 3C996 Gigabit Ethernet" },
 131
 132         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 133                 "Alteon BCM5700 Gigabit Ethernet" },
 134         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 135                 "Alteon BCM5701 Gigabit Ethernet" },
 136
 137         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 138                 "Altima AC1000 Gigabit Ethernet" },
 139         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 140                 "Altima AC1002 Gigabit Ethernet" },
 141         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 142                 "Altima AC9100 Gigabit Ethernet" },
 143
 144         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 145                 "Apple BCM5701 Gigabit Ethernet" },
 146
 147         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 148                 "Broadcom BCM5700 Gigabit Ethernet" },
 149         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 150                 "Broadcom BCM5701 Gigabit Ethernet" },
 151         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 152                 "Broadcom BCM5702 Gigabit Ethernet" },
 153         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 154                 "Broadcom BCM5702X Gigabit Ethernet" },
 155         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 156                 "Broadcom BCM5702 Gigabit Ethernet" },
 157         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 158                 "Broadcom BCM5703 Gigabit Ethernet" },
 159         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 160                 "Broadcom BCM5703X Gigabit Ethernet" },
 161         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 162                 "Broadcom BCM5703 Gigabit Ethernet" },
 163         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 164                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 165         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 166                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 167         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 168                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 169         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 170                 "Broadcom BCM5705 Gigabit Ethernet" },
 171         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 172                 "Broadcom BCM5705F Gigabit Ethernet" },
 173         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 174                 "Broadcom BCM5705K Gigabit Ethernet" },
 175         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 176                 "Broadcom BCM5705M Gigabit Ethernet" },
 177         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 178                 "Broadcom BCM5705M Gigabit Ethernet" },
 179         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 180                 "Broadcom BCM5714C Gigabit Ethernet" },
 181         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 182                 "Broadcom BCM5714S Gigabit Ethernet" },
 183         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 184                 "Broadcom BCM5715 Gigabit Ethernet" },
 185         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 186                 "Broadcom BCM5715S Gigabit Ethernet" },
 187         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 188                 "Broadcom BCM5720 Gigabit Ethernet" },
 189         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 190                 "Broadcom BCM5721 Gigabit Ethernet" },
 191         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 192                 "Broadcom BCM5722 Gigabit Ethernet" },
 193         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 194                 "Broadcom BCM5750 Gigabit Ethernet" },
 195         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 196                 "Broadcom BCM5750M Gigabit Ethernet" },
 197         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 198                 "Broadcom BCM5751 Gigabit Ethernet" },
 199         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 200                 "Broadcom BCM5751F Gigabit Ethernet" },
 201         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 202                 "Broadcom BCM5751M Gigabit Ethernet" },
 203         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 204                 "Broadcom BCM5752 Gigabit Ethernet" },
 205         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 206                 "Broadcom BCM5752M Gigabit Ethernet" },
 207         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 208                 "Broadcom BCM5753 Gigabit Ethernet" },
 209         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 210                 "Broadcom BCM5753F Gigabit Ethernet" },
 211         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 212                 "Broadcom BCM5753M Gigabit Ethernet" },
 213         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 214                 "Broadcom BCM5754 Gigabit Ethernet" },
 215         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 216                 "Broadcom BCM5754M Gigabit Ethernet" },
 217         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 218                 "Broadcom BCM5755 Gigabit Ethernet" },
 219         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 220                 "Broadcom BCM5755M Gigabit Ethernet" },
 221         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 222                 "Broadcom BCM5756 Gigabit Ethernet" },
 223         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 224                 "Broadcom BCM5780 Gigabit Ethernet" },
 225         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 226                 "Broadcom BCM5780S Gigabit Ethernet" },
 227         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 228                 "Broadcom BCM5781 Gigabit Ethernet" },
 229         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 230                 "Broadcom BCM5782 Gigabit Ethernet" },
 231         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 232                 "Broadcom BCM5786 Gigabit Ethernet" },
 233         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 234                 "Broadcom BCM5787 Gigabit Ethernet" },
 235         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 236                 "Broadcom BCM5787F Gigabit Ethernet" },
 237         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 238                 "Broadcom BCM5787M Gigabit Ethernet" },
 239         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 240                 "Broadcom BCM5788 Gigabit Ethernet" },
 241         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 242                 "Broadcom BCM5789 Gigabit Ethernet" },
 243         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 244                 "Broadcom BCM5901 Fast Ethernet" },
 245         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 246                 "Broadcom BCM5901A2 Fast Ethernet" },
 247         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 248                 "Broadcom BCM5903M Fast Ethernet" },
 249
 250         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 251                 "SysKonnect Gigabit Ethernet" },
 252
 253         { 0, 0, NULL }
 254 };
 255
 256 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 257 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 258 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 259 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 260 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 261
 262 static int      bge_probe(device_t);
 263 static int      bge_attach(device_t);
 264 static int      bge_detach(device_t);
 265 static void     bge_txeof(struct bge_softc *);
 266 static void     bge_rxeof(struct bge_softc *);
 267
 268 static void     bge_tick(void *);
 269 static void     bge_stats_update(struct bge_softc *);
 270 static void     bge_stats_update_regs(struct bge_softc *);
 271 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 272
 273 #ifdef DEVICE_POLLING
 274 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 275 #endif
 276 static void     bge_intr(void *);
 277 static void     bge_enable_intr(struct bge_softc *);
 278 static void     bge_disable_intr(struct bge_softc *);
 279 static void     bge_start(struct ifnet *);
 280 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 281 static void     bge_init(void *);
 282 static void     bge_stop(struct bge_softc *);
 283 static void     bge_watchdog(struct ifnet *);
 284 static void     bge_shutdown(device_t);
 285 static int      bge_suspend(device_t);
 286 static int      bge_resume(device_t);
 287 static int      bge_ifmedia_upd(struct ifnet *);
 288 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 289
 290 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 291 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 292
 293 static void     bge_setmulti(struct bge_softc *);
 294 static void     bge_setpromisc(struct bge_softc *);
 295
 296 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 297 static void     bge_free_jumbo_mem(struct bge_softc *);
 298 static struct bge_jslot
 299                 *bge_jalloc(struct bge_softc *);
 300 static void     bge_jfree(void *);
 301 static void     bge_jref(void *);
 302 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 303 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 304 static int      bge_init_rx_ring_std(struct bge_softc *);
 305 static void     bge_free_rx_ring_std(struct bge_softc *);
 306 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 307 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 308 static void     bge_free_tx_ring(struct bge_softc *);
 309 static int      bge_init_tx_ring(struct bge_softc *);
 310
 311 static int      bge_chipinit(struct bge_softc *);
 312 static int      bge_blockinit(struct bge_softc *);
 313
 314 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 315 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 316 #ifdef notdef
 317 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 318 #endif
 319 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 320 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 321
 322 static int      bge_miibus_readreg(device_t, int, int);
 323 static int      bge_miibus_writereg(device_t, int, int, int);
 324 static void     bge_miibus_statchg(device_t);
 325 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 326 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 327 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 328
 329 static void     bge_reset(struct bge_softc *);
 330
 331 static void     bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 332 static void     bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 333                                  bus_size_t, int);
 334 static int      bge_dma_alloc(struct bge_softc *);
 335 static void     bge_dma_free(struct bge_softc *);
 336 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 337                                     bus_dma_tag_t *, bus_dmamap_t *,
 338                                     void **, bus_addr_t *);
 339 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 340
 341 static void     bge_coal_change(struct bge_softc *);
 342 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 343 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 344 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 345 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 346 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 347
 348 /*
 349  * Set following tunable to 1 for some IBM blade servers with the DNLK
 350  * switch module. Auto negotiation is broken for those configurations.
 351  */
 352 static int      bge_fake_autoneg = 0;
 353 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 354
 355 /* Interrupt moderation control variables. */
 356 static int      bge_rx_coal_ticks = 150;        /* usec */
 357 static int      bge_tx_coal_ticks = 1000000;    /* usec */
 358 static int      bge_rx_max_coal_bds = 16;
 359 static int      bge_tx_max_coal_bds = 32;
 360
 361 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 362 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 363 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 364 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 365
 366 #if !defined(KTR_IF_BGE)
 367 #define KTR_IF_BGE      KTR_ALL
 368 #endif
 369 KTR_INFO_MASTER(if_bge);
 370 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr", 0);
 371 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt", 0);
 372 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt", 0);
 373 #define logif(name)     KTR_LOG(if_bge_ ## name)
 374
 375 static device_method_t bge_methods[] = {
 376         /* Device interface */
 377         DEVMETHOD(device_probe,         bge_probe),
 378         DEVMETHOD(device_attach,        bge_attach),
 379         DEVMETHOD(device_detach,        bge_detach),
 380         DEVMETHOD(device_shutdown,      bge_shutdown),
 381         DEVMETHOD(device_suspend,       bge_suspend),
 382         DEVMETHOD(device_resume,        bge_resume),
 383
 384         /* bus interface */
 385         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 386         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 387
 388         /* MII interface */
 389         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 390         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 391         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 392
 393         { 0, 0 }
 394 };
 395
 396 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 397 static devclass_t bge_devclass;
 398
 399 DECLARE_DUMMY_MODULE(if_bge);
 400 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 401 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 402
 403 static uint32_t
 404 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 405 {
 406         device_t dev = sc->bge_dev;
 407         uint32_t val;
 408
 409         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 410         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 411         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 412         return (val);
 413 }
 414
 415 static void
 416 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 417 {
 418         device_t dev = sc->bge_dev;
 419
 420         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 421         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 422         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 423 }
 424
 425 #ifdef notdef
 426 static uint32_t
 427 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 428 {
 429         device_t dev = sc->bge_dev;
 430
 431         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 432         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 433 }
 434 #endif
 435
 436 static void
 437 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 438 {
 439         device_t dev = sc->bge_dev;
 440
 441         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 442         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 443 }
 444
 445 static void
 446 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 447 {
 448         CSR_WRITE_4(sc, off, val);
 449 }
 450
 451 /*
 452  * Read a byte of data stored in the EEPROM at address 'addr.' The
 453  * BCM570x supports both the traditional bitbang interface and an
 454  * auto access interface for reading the EEPROM. We use the auto
 455  * access method.
 456  */
 457 static uint8_t
 458 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 459 {
 460         int i;
 461         uint32_t byte = 0;
 462
 463         /*
 464          * Enable use of auto EEPROM access so we can avoid
 465          * having to use the bitbang method.
 466          */
 467         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 468
 469         /* Reset the EEPROM, load the clock period. */
 470         CSR_WRITE_4(sc, BGE_EE_ADDR,
 471             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 472         DELAY(20);
 473
 474         /* Issue the read EEPROM command. */
 475         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 476
 477         /* Wait for completion */
 478         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 479                 DELAY(10);
 480                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 481                         break;
 482         }
 483
 484         if (i == BGE_TIMEOUT) {
 485                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 486                 return(1);
 487         }
 488
 489         /* Get result. */
 490         byte = CSR_READ_4(sc, BGE_EE_DATA);
 491
 492         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 493
 494         return(0);
 495 }
 496
 497 /*
 498  * Read a sequence of bytes from the EEPROM.
 499  */
 500 static int
 501 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 502 {
 503         size_t i;
 504         int err;
 505         uint8_t byte;
 506
 507         for (byte = 0, err = 0, i = 0; i < len; i++) {
 508                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 509                 if (err)
 510                         break;
 511                 *(dest + i) = byte;
 512         }
 513
 514         return(err ? 1 : 0);
 515 }
 516
 517 static int
 518 bge_miibus_readreg(device_t dev, int phy, int reg)
 519 {
 520         struct bge_softc *sc = device_get_softc(dev);
 521         struct ifnet *ifp = &sc->arpcom.ac_if;
 522         uint32_t val, autopoll;
 523         int i;
 524
 525         /*
 526          * Broadcom's own driver always assumes the internal
 527          * PHY is at GMII address 1. On some chips, the PHY responds
 528          * to accesses at all addresses, which could cause us to
 529          * bogusly attach the PHY 32 times at probe type. Always
 530          * restricting the lookup to address 1 is simpler than
 531          * trying to figure out which chips revisions should be
 532          * special-cased.
 533          */
 534         if (phy != 1)
 535                 return(0);
 536
 537         /* Reading with autopolling on may trigger PCI errors */
 538         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 539         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 540                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 541                 DELAY(40);
 542         }
 543
 544         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 545             BGE_MIPHY(phy)|BGE_MIREG(reg));
 546
 547         for (i = 0; i < BGE_TIMEOUT; i++) {
 548                 DELAY(10);
 549                 val = CSR_READ_4(sc, BGE_MI_COMM);
 550                 if (!(val & BGE_MICOMM_BUSY))
 551                         break;
 552         }
 553
 554         if (i == BGE_TIMEOUT) {
 555                 if_printf(ifp, "PHY read timed out "
 556                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 557                 val = 0;
 558                 goto done;
 559         }
 560
 561         DELAY(5);
 562         val = CSR_READ_4(sc, BGE_MI_COMM);
 563
 564 done:
 565         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 566                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 567                 DELAY(40);
 568         }
 569
 570         if (val & BGE_MICOMM_READFAIL)
 571                 return(0);
 572
 573         return(val & 0xFFFF);
 574 }
 575
 576 static int
 577 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 578 {
 579         struct bge_softc *sc = device_get_softc(dev);
 580         uint32_t autopoll;
 581         int i;
 582
 583         /*
 584          * See the related comment in bge_miibus_readreg()
 585          */
 586         if (phy != 1)
 587                 return(0);
 588
 589         /* Reading with autopolling on may trigger PCI errors */
 590         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 591         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 592                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 593                 DELAY(40);
 594         }
 595
 596         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 597             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 598
 599         for (i = 0; i < BGE_TIMEOUT; i++) {
 600                 DELAY(10);
 601                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 602                         DELAY(5);
 603                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 604                         break;
 605                 }
 606         }
 607
 608         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 609                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 610                 DELAY(40);
 611         }
 612
 613         if (i == BGE_TIMEOUT) {
 614                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 615                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
 616                 return(0);
 617         }
 618
 619         return(0);
 620 }
 621
 622 static void
 623 bge_miibus_statchg(device_t dev)
 624 {
 625         struct bge_softc *sc;
 626         struct mii_data *mii;
 627
 628         sc = device_get_softc(dev);
 629         mii = device_get_softc(sc->bge_miibus);
 630
 631         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 632         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 633                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 634         } else {
 635                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 636         }
 637
 638         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 639                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 640         } else {
 641                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 642         }
 643 }
 644
 645 /*
 646  * Memory management for jumbo frames.
 647  */
 648 static int
 649 bge_alloc_jumbo_mem(struct bge_softc *sc)
 650 {
 651         struct ifnet *ifp = &sc->arpcom.ac_if;
 652         struct bge_jslot *entry;
 653         uint8_t *ptr;
 654         bus_addr_t paddr;
 655         int i, error;
 656
 657         /*
 658          * Create tag for jumbo mbufs.
 659          * This is really a bit of a kludge. We allocate a special
 660          * jumbo buffer pool which (thanks to the way our DMA
 661          * memory allocation works) will consist of contiguous
 662          * pages. This means that even though a jumbo buffer might
 663          * be larger than a page size, we don't really need to
 664          * map it into more than one DMA segment. However, the
 665          * default mbuf tag will result in multi-segment mappings,
 666          * so we have to create a special jumbo mbuf tag that
 667          * lets us get away with mapping the jumbo buffers as
 668          * a single segment. I think eventually the driver should
 669          * be changed so that it uses ordinary mbufs and cluster
 670          * buffers, i.e. jumbo frames can span multiple DMA
 671          * descriptors. But that's a project for another day.
 672          */
 673
 674         /*
 675          * Create DMA stuffs for jumbo RX ring.
 676          */
 677         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 678                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 679                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 680                                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
 681                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 682         if (error) {
 683                 if_printf(ifp, "could not create jumbo RX ring\n");
 684                 return error;
 685         }
 686
 687         /*
 688          * Create DMA stuffs for jumbo buffer block.
 689          */
 690         error = bge_dma_block_alloc(sc, BGE_JMEM,
 691                                     &sc->bge_cdata.bge_jumbo_tag,
 692                                     &sc->bge_cdata.bge_jumbo_map,
 693                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 694                                     &paddr);
 695         if (error) {
 696                 if_printf(ifp, "could not create jumbo buffer\n");
 697                 return error;
 698         }
 699
 700         SLIST_INIT(&sc->bge_jfree_listhead);
 701
 702         /*
 703          * Now divide it up into 9K pieces and save the addresses
 704          * in an array. Note that we play an evil trick here by using
 705          * the first few bytes in the buffer to hold the the address
 706          * of the softc structure for this interface. This is because
 707          * bge_jfree() needs it, but it is called by the mbuf management
 708          * code which will not pass it to us explicitly.
 709          */
 710         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 711                 entry = &sc->bge_cdata.bge_jslots[i];
 712                 entry->bge_sc = sc;
 713                 entry->bge_buf = ptr;
 714                 entry->bge_paddr = paddr;
 715                 entry->bge_inuse = 0;
 716                 entry->bge_slot = i;
 717                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 718
 719                 ptr += BGE_JLEN;
 720                 paddr += BGE_JLEN;
 721         }
 722         return 0;
 723 }
 724
 725 static void
 726 bge_free_jumbo_mem(struct bge_softc *sc)
 727 {
 728         /* Destroy jumbo RX ring. */
 729         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 730                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 731                            sc->bge_ldata.bge_rx_jumbo_ring);
 732
 733         /* Destroy jumbo buffer block. */
 734         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 735                            sc->bge_cdata.bge_jumbo_map,
 736                            sc->bge_ldata.bge_jumbo_buf);
 737 }
 738
 739 /*
 740  * Allocate a jumbo buffer.
 741  */
 742 static struct bge_jslot *
 743 bge_jalloc(struct bge_softc *sc)
 744 {
 745         struct bge_jslot *entry;
 746
 747         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 748         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 749         if (entry) {
 750                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 751                 entry->bge_inuse = 1;
 752         } else {
 753                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 754         }
 755         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 756         return(entry);
 757 }
 758
 759 /*
 760  * Adjust usage count on a jumbo buffer.
 761  */
 762 static void
 763 bge_jref(void *arg)
 764 {
 765         struct bge_jslot *entry = (struct bge_jslot *)arg;
 766         struct bge_softc *sc = entry->bge_sc;
 767
 768         if (sc == NULL)
 769                 panic("bge_jref: can't find softc pointer!");
 770
 771         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 772                 panic("bge_jref: asked to reference buffer "
 773                     "that we don't manage!");
 774         } else if (entry->bge_inuse == 0) {
 775                 panic("bge_jref: buffer already free!");
 776         } else {
 777                 atomic_add_int(&entry->bge_inuse, 1);
 778         }
 779 }
 780
 781 /*
 782  * Release a jumbo buffer.
 783  */
 784 static void
 785 bge_jfree(void *arg)
 786 {
 787         struct bge_jslot *entry = (struct bge_jslot *)arg;
 788         struct bge_softc *sc = entry->bge_sc;
 789
 790         if (sc == NULL)
 791                 panic("bge_jfree: can't find softc pointer!");
 792
 793         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 794                 panic("bge_jfree: asked to free buffer that we don't manage!");
 795         } else if (entry->bge_inuse == 0) {
 796                 panic("bge_jfree: buffer already free!");
 797         } else {
 798                 /*
 799                  * Possible MP race to 0, use the serializer.  The atomic insn
 800                  * is still needed for races against bge_jref().
 801                  */
 802                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 803                 atomic_subtract_int(&entry->bge_inuse, 1);
 804                 if (entry->bge_inuse == 0) {
 805                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 806                                           entry, jslot_link);
 807                 }
 808                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 809         }
 810 }
 811
 812
 813 /*
 814  * Intialize a standard receive ring descriptor.
 815  */
 816 static int
 817 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 818 {
 819         struct mbuf *m_new = NULL;
 820         struct bge_dmamap_arg ctx;
 821         bus_dma_segment_t seg;
 822         struct bge_rx_bd *r;
 823         int error;
 824
 825         if (m == NULL) {
 826                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 827                 if (m_new == NULL)
 828                         return ENOBUFS;
 829         } else {
 830                 m_new = m;
 831                 m_new->m_data = m_new->m_ext.ext_buf;
 832         }
 833         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 834
 835         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 836                 m_adj(m_new, ETHER_ALIGN);
 837
 838         ctx.bge_maxsegs = 1;
 839         ctx.bge_segs = &seg;
 840         error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
 841                                      sc->bge_cdata.bge_rx_std_dmamap[i],
 842                                      m_new, bge_dma_map_mbuf, &ctx,
 843                                      BUS_DMA_NOWAIT);
 844         if (error || ctx.bge_maxsegs == 0) {
 845                 if (m == NULL)
 846                         m_freem(m_new);
 847                 return ENOMEM;
 848         }
 849
 850         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 851
 852         r = &sc->bge_ldata.bge_rx_std_ring[i];
 853         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
 854         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
 855         r->bge_flags = BGE_RXBDFLAG_END;
 856         r->bge_len = m_new->m_len;
 857         r->bge_idx = i;
 858
 859         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
 860                         sc->bge_cdata.bge_rx_std_dmamap[i],
 861                         BUS_DMASYNC_PREREAD);
 862         return 0;
 863 }
 864
 865 /*
 866  * Initialize a jumbo receive ring descriptor. This allocates
 867  * a jumbo buffer from the pool managed internally by the driver.
 868  */
 869 static int
 870 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 871 {
 872         struct mbuf *m_new = NULL;
 873         struct bge_jslot *buf;
 874         struct bge_rx_bd *r;
 875         bus_addr_t paddr;
 876
 877         if (m == NULL) {
 878                 /* Allocate the mbuf. */
 879                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 880                 if (m_new == NULL)
 881                         return(ENOBUFS);
 882
 883                 /* Allocate the jumbo buffer */
 884                 buf = bge_jalloc(sc);
 885                 if (buf == NULL) {
 886                         m_freem(m_new);
 887                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 888                             "-- packet dropped!\n");
 889                         return ENOBUFS;
 890                 }
 891
 892                 /* Attach the buffer to the mbuf. */
 893                 m_new->m_ext.ext_arg = buf;
 894                 m_new->m_ext.ext_buf = buf->bge_buf;
 895                 m_new->m_ext.ext_free = bge_jfree;
 896                 m_new->m_ext.ext_ref = bge_jref;
 897                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 898
 899                 m_new->m_flags |= M_EXT;
 900         } else {
 901                 KKASSERT(m->m_flags & M_EXT);
 902                 m_new = m;
 903                 buf = m_new->m_ext.ext_arg;
 904         }
 905         m_new->m_data = m_new->m_ext.ext_buf;
 906         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 907
 908         paddr = buf->bge_paddr;
 909         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
 910                 m_adj(m_new, ETHER_ALIGN);
 911                 paddr += ETHER_ALIGN;
 912         }
 913
 914         /* Set up the descriptor. */
 915         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 916
 917         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
 918         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
 919         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
 920         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 921         r->bge_len = m_new->m_len;
 922         r->bge_idx = i;
 923
 924         return 0;
 925 }
 926
 927 /*
 928  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 929  * that's 1MB or memory, which is a lot. For now, we fill only the first
 930  * 256 ring entries and hope that our CPU is fast enough to keep up with
 931  * the NIC.
 932  */
 933 static int
 934 bge_init_rx_ring_std(struct bge_softc *sc)
 935 {
 936         int i;
 937
 938         for (i = 0; i < BGE_SSLOTS; i++) {
 939                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 940                         return(ENOBUFS);
 941         };
 942
 943         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
 944                         sc->bge_cdata.bge_rx_std_ring_map,
 945                         BUS_DMASYNC_PREWRITE);
 946
 947         sc->bge_std = i - 1;
 948         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 949
 950         return(0);
 951 }
 952
 953 static void
 954 bge_free_rx_ring_std(struct bge_softc *sc)
 955 {
 956         int i;
 957
 958         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 959                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 960                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
 961                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
 962                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 963                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 964                 }
 965                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
 966                     sizeof(struct bge_rx_bd));
 967         }
 968 }
 969
 970 static int
 971 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 972 {
 973         int i;
 974         struct bge_rcb *rcb;
 975
 976         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 977                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 978                         return(ENOBUFS);
 979         };
 980
 981         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 982                         sc->bge_cdata.bge_rx_jumbo_ring_map,
 983                         BUS_DMASYNC_PREWRITE);
 984
 985         sc->bge_jumbo = i - 1;
 986
 987         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
 988         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 989         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 990
 991         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 992
 993         return(0);
 994 }
 995
 996 static void
 997 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 998 {
 999         int i;
1000
1001         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1002                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1003                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1004                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1005                 }
1006                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1007                     sizeof(struct bge_rx_bd));
1008         }
1009 }
1010
1011 static void
1012 bge_free_tx_ring(struct bge_softc *sc)
1013 {
1014         int i;
1015
1016         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1017                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1018                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1019                                           sc->bge_cdata.bge_tx_dmamap[i]);
1020                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1021                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1022                 }
1023                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1024                     sizeof(struct bge_tx_bd));
1025         }
1026 }
1027
1028 static int
1029 bge_init_tx_ring(struct bge_softc *sc)
1030 {
1031         sc->bge_txcnt = 0;
1032         sc->bge_tx_saved_considx = 0;
1033         sc->bge_tx_prodidx = 0;
1034
1035         /* Initialize transmit producer index for host-memory send ring. */
1036         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1037
1038         /* 5700 b2 errata */
1039         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1040                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1041
1042         CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1043         /* 5700 b2 errata */
1044         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1045                 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1046
1047         return(0);
1048 }
1049
1050 static void
1051 bge_setmulti(struct bge_softc *sc)
1052 {
1053         struct ifnet *ifp;
1054         struct ifmultiaddr *ifma;
1055         uint32_t hashes[4] = { 0, 0, 0, 0 };
1056         int h, i;
1057
1058         ifp = &sc->arpcom.ac_if;
1059
1060         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1061                 for (i = 0; i < 4; i++)
1062                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1063                 return;
1064         }
1065
1066         /* First, zot all the existing filters. */
1067         for (i = 0; i < 4; i++)
1068                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1069
1070         /* Now program new ones. */
1071         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1072                 if (ifma->ifma_addr->sa_family != AF_LINK)
1073                         continue;
1074                 h = ether_crc32_le(
1075                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1076                     ETHER_ADDR_LEN) & 0x7f;
1077                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1078         }
1079
1080         for (i = 0; i < 4; i++)
1081                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1082 }
1083
1084 /*
1085  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1086  * self-test results.
1087  */
1088 static int
1089 bge_chipinit(struct bge_softc *sc)
1090 {
1091         int i;
1092         uint32_t dma_rw_ctl;
1093
1094         /* Set endian type before we access any non-PCI registers. */
1095         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1096
1097         /*
1098          * Check the 'ROM failed' bit on the RX CPU to see if
1099          * self-tests passed.
1100          */
1101         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1102                 if_printf(&sc->arpcom.ac_if,
1103                           "RX CPU self-diagnostics failed!\n");
1104                 return(ENODEV);
1105         }
1106
1107         /* Clear the MAC control register */
1108         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1109
1110         /*
1111          * Clear the MAC statistics block in the NIC's
1112          * internal memory.
1113          */
1114         for (i = BGE_STATS_BLOCK;
1115             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1116                 BGE_MEMWIN_WRITE(sc, i, 0);
1117
1118         for (i = BGE_STATUS_BLOCK;
1119             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1120                 BGE_MEMWIN_WRITE(sc, i, 0);
1121
1122         /* Set up the PCI DMA control register. */
1123         if (sc->bge_flags & BGE_FLAG_PCIE) {
1124                 /* PCI Express */
1125                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1126                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1127                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1128         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1129                 /* PCI-X bus */
1130                 if (BGE_IS_5714_FAMILY(sc)) {
1131                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1132                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1133                         /* XXX magic values, Broadcom-supplied Linux driver */
1134                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1135                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1136                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1137                         } else {
1138                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1139                         }
1140                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1141                         /*
1142                          * The 5704 uses a different encoding of read/write
1143                          * watermarks.
1144                          */
1145                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1146                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1147                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1148                 } else {
1149                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1150                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1151                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1152                             (0x0F);
1153                 }
1154
1155                 /*
1156                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1157                  * for hardware bugs.
1158                  */
1159                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1160                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1161                         uint32_t tmp;
1162
1163                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1164                         if (tmp == 0x6 || tmp == 0x7)
1165                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1166                 }
1167         } else {
1168                 /* Conventional PCI bus */
1169                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1170                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1171                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1172                     (0x0F);
1173         }
1174
1175         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1176             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1177             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1178                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1179         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1180
1181         /*
1182          * Set up general mode register.
1183          */
1184         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1185             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1186             BGE_MODECTL_TX_NO_PHDR_CSUM);
1187
1188         /*
1189          * Disable memory write invalidate.  Apparently it is not supported
1190          * properly by these devices.
1191          */
1192         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1193
1194         /* Set the timer prescaler (always 66Mhz) */
1195         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1196
1197         return(0);
1198 }
1199
1200 static int
1201 bge_blockinit(struct bge_softc *sc)
1202 {
1203         struct bge_rcb *rcb;
1204         bus_size_t vrcb;
1205         bge_hostaddr taddr;
1206         uint32_t val;
1207         int i;
1208
1209         /*
1210          * Initialize the memory window pointer register so that
1211          * we can access the first 32K of internal NIC RAM. This will
1212          * allow us to set up the TX send ring RCBs and the RX return
1213          * ring RCBs, plus other things which live in NIC memory.
1214          */
1215         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1216
1217         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1218
1219         if (!BGE_IS_5705_PLUS(sc)) {
1220                 /* Configure mbuf memory pool */
1221                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1222                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1223                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1224                 else
1225                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1226
1227                 /* Configure DMA resource pool */
1228                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1229                     BGE_DMA_DESCRIPTORS);
1230                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1231         }
1232
1233         /* Configure mbuf pool watermarks */
1234         if (BGE_IS_5705_PLUS(sc)) {
1235                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1236                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1237         } else {
1238                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1239                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1240         }
1241         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1242
1243         /* Configure DMA resource watermarks */
1244         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1245         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1246
1247         /* Enable buffer manager */
1248         if (!BGE_IS_5705_PLUS(sc)) {
1249                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1250                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1251
1252                 /* Poll for buffer manager start indication */
1253                 for (i = 0; i < BGE_TIMEOUT; i++) {
1254                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1255                                 break;
1256                         DELAY(10);
1257                 }
1258
1259                 if (i == BGE_TIMEOUT) {
1260                         if_printf(&sc->arpcom.ac_if,
1261                                   "buffer manager failed to start\n");
1262                         return(ENXIO);
1263                 }
1264         }
1265
1266         /* Enable flow-through queues */
1267         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1268         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1269
1270         /* Wait until queue initialization is complete */
1271         for (i = 0; i < BGE_TIMEOUT; i++) {
1272                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1273                         break;
1274                 DELAY(10);
1275         }
1276
1277         if (i == BGE_TIMEOUT) {
1278                 if_printf(&sc->arpcom.ac_if,
1279                           "flow-through queue init failed\n");
1280                 return(ENXIO);
1281         }
1282
1283         /* Initialize the standard RX ring control block */
1284         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1285         rcb->bge_hostaddr.bge_addr_lo =
1286             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1287         rcb->bge_hostaddr.bge_addr_hi =
1288             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1289         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1290             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1291         if (BGE_IS_5705_PLUS(sc))
1292                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1293         else
1294                 rcb->bge_maxlen_flags =
1295                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1296         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1297         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1298         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1299         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1300         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1301
1302         /*
1303          * Initialize the jumbo RX ring control block
1304          * We set the 'ring disabled' bit in the flags
1305          * field until we're actually ready to start
1306          * using this ring (i.e. once we set the MTU
1307          * high enough to require it).
1308          */
1309         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1310                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1311
1312                 rcb->bge_hostaddr.bge_addr_lo =
1313                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1314                 rcb->bge_hostaddr.bge_addr_hi =
1315                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1316                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1317                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1318                     BUS_DMASYNC_PREREAD);
1319                 rcb->bge_maxlen_flags =
1320                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1321                     BGE_RCB_FLAG_RING_DISABLED);
1322                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1323                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1324                     rcb->bge_hostaddr.bge_addr_hi);
1325                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1326                     rcb->bge_hostaddr.bge_addr_lo);
1327                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1328                     rcb->bge_maxlen_flags);
1329                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1330
1331                 /* Set up dummy disabled mini ring RCB */
1332                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1333                 rcb->bge_maxlen_flags =
1334                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1335                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1336                     rcb->bge_maxlen_flags);
1337         }
1338
1339         /*
1340          * Set the BD ring replentish thresholds. The recommended
1341          * values are 1/8th the number of descriptors allocated to
1342          * each ring.
1343          */
1344         if (BGE_IS_5705_PLUS(sc))
1345                 val = 8;
1346         else
1347                 val = BGE_STD_RX_RING_CNT / 8;
1348         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1349         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1350
1351         /*
1352          * Disable all unused send rings by setting the 'ring disabled'
1353          * bit in the flags field of all the TX send ring control blocks.
1354          * These are located in NIC memory.
1355          */
1356         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1357         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1358                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1359                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1360                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1361                 vrcb += sizeof(struct bge_rcb);
1362         }
1363
1364         /* Configure TX RCB 0 (we use only the first ring) */
1365         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1366         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1367         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1368         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1369         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1370             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1371         if (!BGE_IS_5705_PLUS(sc)) {
1372                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1373                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1374         }
1375
1376         /* Disable all unused RX return rings */
1377         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1378         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1379                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1380                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1381                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1382                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1383                     BGE_RCB_FLAG_RING_DISABLED));
1384                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1385                 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1386                     (i * (sizeof(uint64_t))), 0);
1387                 vrcb += sizeof(struct bge_rcb);
1388         }
1389
1390         /* Initialize RX ring indexes */
1391         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1392         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1393         CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1394
1395         /*
1396          * Set up RX return ring 0
1397          * Note that the NIC address for RX return rings is 0x00000000.
1398          * The return rings live entirely within the host, so the
1399          * nicaddr field in the RCB isn't used.
1400          */
1401         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1402         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1403         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1404         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1405         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1406         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1407             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1408
1409         /* Set random backoff seed for TX */
1410         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1411             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1412             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1413             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1414             BGE_TX_BACKOFF_SEED_MASK);
1415
1416         /* Set inter-packet gap */
1417         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1418
1419         /*
1420          * Specify which ring to use for packets that don't match
1421          * any RX rules.
1422          */
1423         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1424
1425         /*
1426          * Configure number of RX lists. One interrupt distribution
1427          * list, sixteen active lists, one bad frames class.
1428          */
1429         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1430
1431         /* Inialize RX list placement stats mask. */
1432         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1433         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1434
1435         /* Disable host coalescing until we get it set up */
1436         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1437
1438         /* Poll to make sure it's shut down. */
1439         for (i = 0; i < BGE_TIMEOUT; i++) {
1440                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1441                         break;
1442                 DELAY(10);
1443         }
1444
1445         if (i == BGE_TIMEOUT) {
1446                 if_printf(&sc->arpcom.ac_if,
1447                           "host coalescing engine failed to idle\n");
1448                 return(ENXIO);
1449         }
1450
1451         /* Set up host coalescing defaults */
1452         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1453         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1454         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1455         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1456         if (!BGE_IS_5705_PLUS(sc)) {
1457                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1458                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1459         }
1460         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1461         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1462
1463         /* Set up address of statistics block */
1464         if (!BGE_IS_5705_PLUS(sc)) {
1465                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1466                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1467                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1468                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1469
1470                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1471                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1472                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1473         }
1474
1475         /* Set up address of status block */
1476         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1477             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1478         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1479             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1480         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1481         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1482
1483         /* Turn on host coalescing state machine */
1484         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1485
1486         /* Turn on RX BD completion state machine and enable attentions */
1487         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1488             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1489
1490         /* Turn on RX list placement state machine */
1491         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1492
1493         /* Turn on RX list selector state machine. */
1494         if (!BGE_IS_5705_PLUS(sc))
1495                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1496
1497         /* Turn on DMA, clear stats */
1498         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1499             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1500             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1501             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1502             ((sc->bge_flags & BGE_FLAG_TBI) ?
1503              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1504
1505         /* Set misc. local control, enable interrupts on attentions */
1506         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1507
1508 #ifdef notdef
1509         /* Assert GPIO pins for PHY reset */
1510         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1511             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1512         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1513             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1514 #endif
1515
1516         /* Turn on DMA completion state machine */
1517         if (!BGE_IS_5705_PLUS(sc))
1518                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1519
1520         /* Turn on write DMA state machine */
1521         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1522         if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1523             sc->bge_asicrev == BGE_ASICREV_BCM5787)
1524                 val |= (1 << 29);       /* Enable host coalescing bug fix. */
1525         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1526
1527         /* Turn on read DMA state machine */
1528         CSR_WRITE_4(sc, BGE_RDMA_MODE,
1529             BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1530
1531         /* Turn on RX data completion state machine */
1532         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1533
1534         /* Turn on RX BD initiator state machine */
1535         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1536
1537         /* Turn on RX data and RX BD initiator state machine */
1538         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1539
1540         /* Turn on Mbuf cluster free state machine */
1541         if (!BGE_IS_5705_PLUS(sc))
1542                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1543
1544         /* Turn on send BD completion state machine */
1545         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1546
1547         /* Turn on send data completion state machine */
1548         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1549
1550         /* Turn on send data initiator state machine */
1551         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1552
1553         /* Turn on send BD initiator state machine */
1554         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1555
1556         /* Turn on send BD selector state machine */
1557         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1558
1559         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1560         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1561             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1562
1563         /* ack/clear link change events */
1564         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1565             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1566             BGE_MACSTAT_LINK_CHANGED);
1567         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1568
1569         /* Enable PHY auto polling (for MII/GMII only) */
1570         if (sc->bge_flags & BGE_FLAG_TBI) {
1571                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1572         } else {
1573                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1574                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1575                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1576                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1577                             BGE_EVTENB_MI_INTERRUPT);
1578                 }
1579         }
1580
1581         /*
1582          * Clear any pending link state attention.
1583          * Otherwise some link state change events may be lost until attention
1584          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1585          * It's not necessary on newer BCM chips - perhaps enabling link
1586          * state change attentions implies clearing pending attention.
1587          */
1588         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1589             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1590             BGE_MACSTAT_LINK_CHANGED);
1591
1592         /* Enable link state change attentions. */
1593         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1594
1595         return(0);
1596 }
1597
1598 /*
1599  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1600  * against our list and return its name if we find a match. Note
1601  * that since the Broadcom controller contains VPD support, we
1602  * can get the device name string from the controller itself instead
1603  * of the compiled-in string. This is a little slow, but it guarantees
1604  * we'll always announce the right product name.
1605  */
1606 static int
1607 bge_probe(device_t dev)
1608 {
1609         struct bge_softc *sc;
1610         struct bge_type *t;
1611         char *descbuf;
1612         uint16_t product, vendor;
1613
1614         product = pci_get_device(dev);
1615         vendor = pci_get_vendor(dev);
1616
1617         for (t = bge_devs; t->bge_name != NULL; t++) {
1618                 if (vendor == t->bge_vid && product == t->bge_did)
1619                         break;
1620         }
1621
1622         if (t->bge_name == NULL)
1623                 return(ENXIO);
1624
1625         sc = device_get_softc(dev);
1626         descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1627         ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1628             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1629         device_set_desc_copy(dev, descbuf);
1630         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1631                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1632         kfree(descbuf, M_TEMP);
1633         return(0);
1634 }
1635
1636 static int
1637 bge_attach(device_t dev)
1638 {
1639         struct ifnet *ifp;
1640         struct bge_softc *sc;
1641         uint32_t hwcfg = 0;
1642         uint32_t mac_addr = 0;
1643         int error = 0, rid;
1644         uint8_t ether_addr[ETHER_ADDR_LEN];
1645
1646         sc = device_get_softc(dev);
1647         sc->bge_dev = dev;
1648         callout_init(&sc->bge_stat_timer);
1649         lwkt_serialize_init(&sc->bge_jslot_serializer);
1650
1651         /*
1652          * Map control/status registers.
1653          */
1654         pci_enable_busmaster(dev);
1655
1656         rid = BGE_PCI_BAR0;
1657         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1658             RF_ACTIVE);
1659
1660         if (sc->bge_res == NULL) {
1661                 device_printf(dev, "couldn't map memory\n");
1662                 return ENXIO;
1663         }
1664
1665         sc->bge_btag = rman_get_bustag(sc->bge_res);
1666         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1667
1668         /* Save ASIC rev. */
1669         sc->bge_chipid =
1670             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1671             BGE_PCIMISCCTL_ASICREV;
1672         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1673         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1674
1675         /* Save chipset family. */
1676         switch (sc->bge_asicrev) {
1677         case BGE_ASICREV_BCM5700:
1678         case BGE_ASICREV_BCM5701:
1679         case BGE_ASICREV_BCM5703:
1680         case BGE_ASICREV_BCM5704:
1681                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1682                 break;
1683
1684         case BGE_ASICREV_BCM5714_A0:
1685         case BGE_ASICREV_BCM5780:
1686         case BGE_ASICREV_BCM5714:
1687                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1688                 /* Fall through */
1689
1690         case BGE_ASICREV_BCM5750:
1691         case BGE_ASICREV_BCM5752:
1692         case BGE_ASICREV_BCM5755:
1693         case BGE_ASICREV_BCM5787:
1694                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1695                 /* Fall through */
1696
1697         case BGE_ASICREV_BCM5705:
1698                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1699                 break;
1700         }
1701
1702         /*
1703          * Set various quirk flags.
1704          */
1705
1706         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1707         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1708             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1709              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1710               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1711             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1712                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1713
1714         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1715             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1716                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1717
1718         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1719             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1720                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1721
1722         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1723                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1724
1725         if (BGE_IS_5705_PLUS(sc)) {
1726                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1727                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1728                         uint32_t product = pci_get_device(dev);
1729
1730                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1731                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1732                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1733                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1734                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1735                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1736                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1737                 }
1738         }
1739
1740         /* Allocate interrupt */
1741         rid = 0;
1742
1743         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1744             RF_SHAREABLE | RF_ACTIVE);
1745
1746         if (sc->bge_irq == NULL) {
1747                 device_printf(dev, "couldn't map interrupt\n");
1748                 error = ENXIO;
1749                 goto fail;
1750         }
1751
1752         /*
1753          * Check if this is a PCI-X or PCI Express device.
1754          */
1755         if (BGE_IS_5705_PLUS(sc)) {
1756                 uint32_t reg;
1757
1758                 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
1759                 if ((reg & 0xff) == BGE_PCIE_CAPID)
1760                         sc->bge_flags |= BGE_FLAG_PCIE;
1761         } else {
1762                 /*
1763                  * Check if the device is in PCI-X Mode.
1764                  * (This bit is not valid on PCI Express controllers.)
1765                  */
1766                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1767                     BGE_PCISTATE_PCI_BUSMODE) == 0)
1768                         sc->bge_flags |= BGE_FLAG_PCIX;
1769         }
1770
1771         ifp = &sc->arpcom.ac_if;
1772         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1773
1774         /* Try to reset the chip. */
1775         bge_reset(sc);
1776
1777         if (bge_chipinit(sc)) {
1778                 device_printf(dev, "chip initialization failed\n");
1779                 error = ENXIO;
1780                 goto fail;
1781         }
1782
1783         /*
1784          * Get station address from the EEPROM.
1785          */
1786         mac_addr = bge_readmem_ind(sc, 0x0c14);
1787         if ((mac_addr >> 16) == 0x484b) {
1788                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1789                 ether_addr[1] = (uint8_t)mac_addr;
1790                 mac_addr = bge_readmem_ind(sc, 0x0c18);
1791                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1792                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1793                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1794                 ether_addr[5] = (uint8_t)mac_addr;
1795         } else if (bge_read_eeprom(sc, ether_addr,
1796             BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1797                 device_printf(dev, "failed to read station address\n");
1798                 error = ENXIO;
1799                 goto fail;
1800         }
1801
1802         /* 5705/5750 limits RX return ring to 512 entries. */
1803         if (BGE_IS_5705_PLUS(sc))
1804                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1805         else
1806                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1807
1808         error = bge_dma_alloc(sc);
1809         if (error)
1810                 goto fail;
1811
1812         /* Set default tuneable values. */
1813         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1814         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1815         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1816         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1817         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1818
1819         /* Set up ifnet structure */
1820         ifp->if_softc = sc;
1821         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1822         ifp->if_ioctl = bge_ioctl;
1823         ifp->if_start = bge_start;
1824 #ifdef DEVICE_POLLING
1825         ifp->if_poll = bge_poll;
1826 #endif
1827         ifp->if_watchdog = bge_watchdog;
1828         ifp->if_init = bge_init;
1829         ifp->if_mtu = ETHERMTU;
1830         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1831         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1832         ifq_set_ready(&ifp->if_snd);
1833
1834         /*
1835          * 5700 B0 chips do not support checksumming correctly due
1836          * to hardware bugs.
1837          */
1838         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1839                 ifp->if_capabilities |= IFCAP_HWCSUM;
1840                 ifp->if_hwassist = BGE_CSUM_FEATURES;
1841         }
1842         ifp->if_capenable = ifp->if_capabilities;
1843
1844         /*
1845          * Figure out what sort of media we have by checking the
1846          * hardware config word in the first 32k of NIC internal memory,
1847          * or fall back to examining the EEPROM if necessary.
1848          * Note: on some BCM5700 cards, this value appears to be unset.
1849          * If that's the case, we have to rely on identifying the NIC
1850          * by its PCI subsystem ID, as we do below for the SysKonnect
1851          * SK-9D41.
1852          */
1853         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1854                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1855         else {
1856                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1857                                     sizeof(hwcfg))) {
1858                         device_printf(dev, "failed to read EEPROM\n");
1859                         error = ENXIO;
1860                         goto fail;
1861                 }
1862                 hwcfg = ntohl(hwcfg);
1863         }
1864
1865         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1866                 sc->bge_flags |= BGE_FLAG_TBI;
1867
1868         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1869         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1870                 sc->bge_flags |= BGE_FLAG_TBI;
1871
1872         if (sc->bge_flags & BGE_FLAG_TBI) {
1873                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1874                     bge_ifmedia_upd, bge_ifmedia_sts);
1875                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1876                 ifmedia_add(&sc->bge_ifmedia,
1877                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1878                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1879                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1880                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1881         } else {
1882                 /*
1883                  * Do transceiver setup.
1884                  */
1885                 if (mii_phy_probe(dev, &sc->bge_miibus,
1886                     bge_ifmedia_upd, bge_ifmedia_sts)) {
1887                         device_printf(dev, "MII without any PHY!\n");
1888                         error = ENXIO;
1889                         goto fail;
1890                 }
1891         }
1892
1893         /*
1894          * When using the BCM5701 in PCI-X mode, data corruption has
1895          * been observed in the first few bytes of some received packets.
1896          * Aligning the packet buffer in memory eliminates the corruption.
1897          * Unfortunately, this misaligns the packet payloads.  On platforms
1898          * which do not support unaligned accesses, we will realign the
1899          * payloads by copying the received packets.
1900          */
1901         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1902             (sc->bge_flags & BGE_FLAG_PCIX))
1903                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
1904
1905         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1906             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1907                 sc->bge_link_upd = bge_bcm5700_link_upd;
1908                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
1909         } else if (sc->bge_flags & BGE_FLAG_TBI) {
1910                 sc->bge_link_upd = bge_tbi_link_upd;
1911                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1912         } else {
1913                 sc->bge_link_upd = bge_copper_link_upd;
1914                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1915         }
1916
1917         /*
1918          * Create sysctl nodes.
1919          */
1920         sysctl_ctx_init(&sc->bge_sysctl_ctx);
1921         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
1922                                               SYSCTL_STATIC_CHILDREN(_hw),
1923                                               OID_AUTO,
1924                                               device_get_nameunit(dev),
1925                                               CTLFLAG_RD, 0, "");
1926         if (sc->bge_sysctl_tree == NULL) {
1927                 device_printf(dev, "can't add sysctl node\n");
1928                 error = ENXIO;
1929                 goto fail;
1930         }
1931
1932         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1933                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1934                         OID_AUTO, "rx_coal_ticks",
1935                         CTLTYPE_INT | CTLFLAG_RW,
1936                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
1937                         "Receive coalescing ticks (usec).");
1938         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1939                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1940                         OID_AUTO, "tx_coal_ticks",
1941                         CTLTYPE_INT | CTLFLAG_RW,
1942                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
1943                         "Transmit coalescing ticks (usec).");
1944         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1945                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1946                         OID_AUTO, "rx_max_coal_bds",
1947                         CTLTYPE_INT | CTLFLAG_RW,
1948                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
1949                         "Receive max coalesced BD count.");
1950         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1951                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1952                         OID_AUTO, "tx_max_coal_bds",
1953                         CTLTYPE_INT | CTLFLAG_RW,
1954                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
1955                         "Transmit max coalesced BD count.");
1956
1957         /*
1958          * Call MI attach routine.
1959          */
1960         ether_ifattach(ifp, ether_addr, NULL);
1961
1962         error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1963                                bge_intr, sc, &sc->bge_intrhand,
1964                                ifp->if_serializer);
1965         if (error) {
1966                 ether_ifdetach(ifp);
1967                 device_printf(dev, "couldn't set up irq\n");
1968                 goto fail;
1969         }
1970
1971         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bge_irq));
1972         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1973
1974         return(0);
1975 fail:
1976         bge_detach(dev);
1977         return(error);
1978 }
1979
1980 static int
1981 bge_detach(device_t dev)
1982 {
1983         struct bge_softc *sc = device_get_softc(dev);
1984
1985         if (device_is_attached(dev)) {
1986                 struct ifnet *ifp = &sc->arpcom.ac_if;
1987
1988                 lwkt_serialize_enter(ifp->if_serializer);
1989                 bge_stop(sc);
1990                 bge_reset(sc);
1991                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1992                 lwkt_serialize_exit(ifp->if_serializer);
1993
1994                 ether_ifdetach(ifp);
1995         }
1996
1997         if (sc->bge_flags & BGE_FLAG_TBI)
1998                 ifmedia_removeall(&sc->bge_ifmedia);
1999         if (sc->bge_miibus)
2000                 device_delete_child(dev, sc->bge_miibus);
2001         bus_generic_detach(dev);
2002
2003         if (sc->bge_irq != NULL)
2004                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2005
2006         if (sc->bge_res != NULL)
2007                 bus_release_resource(dev, SYS_RES_MEMORY,
2008                     BGE_PCI_BAR0, sc->bge_res);
2009
2010         if (sc->bge_sysctl_tree != NULL)
2011                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2012
2013         bge_dma_free(sc);
2014
2015         return 0;
2016 }
2017
2018 static void
2019 bge_reset(struct bge_softc *sc)
2020 {
2021         device_t dev;
2022         uint32_t cachesize, command, pcistate, reset;
2023         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2024         int i, val = 0;
2025
2026         dev = sc->bge_dev;
2027
2028         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
2029                 if (sc->bge_flags & BGE_FLAG_PCIE)
2030                         write_op = bge_writemem_direct;
2031                 else
2032                         write_op = bge_writemem_ind;
2033         } else {
2034                 write_op = bge_writereg_ind;
2035         }
2036
2037         /* Save some important PCI state. */
2038         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2039         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2040         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2041
2042         pci_write_config(dev, BGE_PCI_MISC_CTL,
2043             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2044             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2045
2046         /* Disable fastboot on controllers that support it. */
2047         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2048             sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2049             sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2050                 if (bootverbose)
2051                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2052                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2053         }
2054
2055         /*
2056          * Write the magic number to SRAM at offset 0xB50.
2057          * When firmware finishes its initialization it will
2058          * write ~BGE_MAGIC_NUMBER to the same location.
2059          */
2060         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2061
2062         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2063
2064         /* XXX: Broadcom Linux driver. */
2065         if (sc->bge_flags & BGE_FLAG_PCIE) {
2066                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2067                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2068                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2069                         /* Prevent PCIE link training during global reset */
2070                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2071                         reset |= (1<<29);
2072                 }
2073         }
2074
2075         /*
2076          * Set GPHY Power Down Override to leave GPHY
2077          * powered up in D0 uninitialized.
2078          */
2079         if (BGE_IS_5705_PLUS(sc))
2080                 reset |= 0x04000000;
2081
2082         /* Issue global reset */
2083         write_op(sc, BGE_MISC_CFG, reset);
2084
2085         DELAY(1000);
2086
2087         /* XXX: Broadcom Linux driver. */
2088         if (sc->bge_flags & BGE_FLAG_PCIE) {
2089                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2090                         uint32_t v;
2091
2092                         DELAY(500000); /* wait for link training to complete */
2093                         v = pci_read_config(dev, 0xc4, 4);
2094                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2095                 }
2096                 /*
2097                  * Set PCIE max payload size to 128 bytes and
2098                  * clear error status.
2099                  */
2100                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2101         }
2102
2103         /* Reset some of the PCI state that got zapped by reset */
2104         pci_write_config(dev, BGE_PCI_MISC_CTL,
2105             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2106             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2107         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2108         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2109         write_op(sc, BGE_MISC_CFG, (65 << 1));
2110
2111         /* Enable memory arbiter. */
2112         if (BGE_IS_5714_FAMILY(sc)) {
2113                 uint32_t val;
2114
2115                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2116                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2117         } else {
2118                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2119         }
2120
2121         /*
2122          * Poll until we see the 1's complement of the magic number.
2123          * This indicates that the firmware initialization
2124          * is complete.
2125          */
2126         for (i = 0; i < BGE_TIMEOUT; i++) {
2127                 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2128                 if (val == ~BGE_MAGIC_NUMBER)
2129                         break;
2130                 DELAY(10);
2131         }
2132
2133         if (i == BGE_TIMEOUT) {
2134                 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out,"
2135                           "found 0x%08x\n", val);
2136                 return;
2137         }
2138
2139         /*
2140          * XXX Wait for the value of the PCISTATE register to
2141          * return to its original pre-reset state. This is a
2142          * fairly good indicator of reset completion. If we don't
2143          * wait for the reset to fully complete, trying to read
2144          * from the device's non-PCI registers may yield garbage
2145          * results.
2146          */
2147         for (i = 0; i < BGE_TIMEOUT; i++) {
2148                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2149                         break;
2150                 DELAY(10);
2151         }
2152
2153         if (sc->bge_flags & BGE_FLAG_PCIE) {
2154                 reset = bge_readmem_ind(sc, 0x7c00);
2155                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2156         }
2157
2158         /* Fix up byte swapping */
2159         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2160             BGE_MODECTL_BYTESWAP_DATA);
2161
2162         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2163
2164         /*
2165          * The 5704 in TBI mode apparently needs some special
2166          * adjustment to insure the SERDES drive level is set
2167          * to 1.2V.
2168          */
2169         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2170             (sc->bge_flags & BGE_FLAG_TBI)) {
2171                 uint32_t serdescfg;
2172
2173                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2174                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2175                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2176         }
2177
2178         /* XXX: Broadcom Linux driver. */
2179         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2180             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2181                 uint32_t v;
2182
2183                 v = CSR_READ_4(sc, 0x7c00);
2184                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2185         }
2186
2187         DELAY(10000);
2188 }
2189
2190 /*
2191  * Frame reception handling. This is called if there's a frame
2192  * on the receive return list.
2193  *
2194  * Note: we have to be able to handle two possibilities here:
2195  * 1) the frame is from the jumbo recieve ring
2196  * 2) the frame is from the standard receive ring
2197  */
2198
2199 static void
2200 bge_rxeof(struct bge_softc *sc)
2201 {
2202         struct ifnet *ifp;
2203         int stdcnt = 0, jumbocnt = 0;
2204 #ifdef ETHER_INPUT_CHAIN
2205         struct mbuf_chain chain[MAXCPU];
2206 #endif
2207
2208         if (sc->bge_rx_saved_considx ==
2209             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2210                 return;
2211
2212 #ifdef ETHER_INPUT_CHAIN
2213         ether_input_chain_init(chain);
2214 #endif
2215
2216         ifp = &sc->arpcom.ac_if;
2217
2218         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2219                         sc->bge_cdata.bge_rx_return_ring_map,
2220                         BUS_DMASYNC_POSTREAD);
2221         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2222                         sc->bge_cdata.bge_rx_std_ring_map,
2223                         BUS_DMASYNC_POSTREAD);
2224         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2225                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2226                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2227                                 BUS_DMASYNC_POSTREAD);
2228         }
2229
2230         while (sc->bge_rx_saved_considx !=
2231                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2232                 struct bge_rx_bd        *cur_rx;
2233                 uint32_t                rxidx;
2234                 struct mbuf             *m = NULL;
2235                 uint16_t                vlan_tag = 0;
2236                 int                     have_tag = 0;
2237
2238                 cur_rx =
2239             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2240
2241                 rxidx = cur_rx->bge_idx;
2242                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2243                 logif(rx_pkt);
2244
2245                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2246                         have_tag = 1;
2247                         vlan_tag = cur_rx->bge_vlan_tag;
2248                 }
2249
2250                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2251                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2252                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2253                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2254                         jumbocnt++;
2255                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2256                                 ifp->if_ierrors++;
2257                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2258                                 continue;
2259                         }
2260                         if (bge_newbuf_jumbo(sc,
2261                             sc->bge_jumbo, NULL) == ENOBUFS) {
2262                                 ifp->if_ierrors++;
2263                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2264                                 continue;
2265                         }
2266                 } else {
2267                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2268                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2269                                         sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2270                                         BUS_DMASYNC_POSTREAD);
2271                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2272                                 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2273                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2274                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2275                         stdcnt++;
2276                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2277                                 ifp->if_ierrors++;
2278                                 bge_newbuf_std(sc, sc->bge_std, m);
2279                                 continue;
2280                         }
2281                         if (bge_newbuf_std(sc, sc->bge_std,
2282                             NULL) == ENOBUFS) {
2283                                 ifp->if_ierrors++;
2284                                 bge_newbuf_std(sc, sc->bge_std, m);
2285                                 continue;
2286                         }
2287                 }
2288
2289                 ifp->if_ipackets++;
2290 #ifndef __i386__
2291                 /*
2292                  * The i386 allows unaligned accesses, but for other
2293                  * platforms we must make sure the payload is aligned.
2294                  */
2295                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2296                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2297                             cur_rx->bge_len);
2298                         m->m_data += ETHER_ALIGN;
2299                 }
2300 #endif
2301                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2302                 m->m_pkthdr.rcvif = ifp;
2303
2304                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2305                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2306                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2307                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2308                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2309                         }
2310                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2311                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2312                                 m->m_pkthdr.csum_data =
2313                                         cur_rx->bge_tcp_udp_csum;
2314                                 m->m_pkthdr.csum_flags |=
2315                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2316                         }
2317                 }
2318
2319                 /*
2320                  * If we received a packet with a vlan tag, pass it
2321                  * to vlan_input() instead of ether_input().
2322                  */
2323                 if (have_tag) {
2324                         m->m_flags |= M_VLANTAG;
2325                         m->m_pkthdr.ether_vlantag = vlan_tag;
2326                         have_tag = vlan_tag = 0;
2327                 }
2328 #ifdef ETHER_INPUT_CHAIN
2329 #ifdef ETHER_INPUT2
2330                 ether_input_chain2(ifp, m, chain);
2331 #else
2332                 ether_input_chain(ifp, m, chain);
2333 #endif
2334 #else
2335                 ifp->if_input(ifp, m);
2336 #endif
2337         }
2338
2339 #ifdef ETHER_INPUT_CHAIN
2340         ether_input_dispatch(chain);
2341 #endif
2342
2343         if (stdcnt > 0) {
2344                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2345                                 sc->bge_cdata.bge_rx_std_ring_map,
2346                                 BUS_DMASYNC_PREWRITE);
2347         }
2348
2349         if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2350                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2351                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2352                                 BUS_DMASYNC_PREWRITE);
2353         }
2354
2355         CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2356         if (stdcnt)
2357                 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2358         if (jumbocnt)
2359                 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2360 }
2361
2362 static void
2363 bge_txeof(struct bge_softc *sc)
2364 {
2365         struct bge_tx_bd *cur_tx = NULL;
2366         struct ifnet *ifp;
2367
2368         if (sc->bge_tx_saved_considx ==
2369             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2370                 return;
2371
2372         ifp = &sc->arpcom.ac_if;
2373
2374         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2375                         sc->bge_cdata.bge_tx_ring_map,
2376                         BUS_DMASYNC_POSTREAD);
2377
2378         /*
2379          * Go through our tx ring and free mbufs for those
2380          * frames that have been sent.
2381          */
2382         while (sc->bge_tx_saved_considx !=
2383                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2384                 uint32_t idx = 0;
2385
2386                 idx = sc->bge_tx_saved_considx;
2387                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2388                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2389                         ifp->if_opackets++;
2390                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2391                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2392                                         sc->bge_cdata.bge_tx_dmamap[idx],
2393                                         BUS_DMASYNC_POSTWRITE);
2394                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2395                             sc->bge_cdata.bge_tx_dmamap[idx]);
2396                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2397                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2398                 }
2399                 sc->bge_txcnt--;
2400                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2401                 logif(tx_pkt);
2402         }
2403
2404         if (cur_tx != NULL &&
2405             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2406             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2407                 ifp->if_flags &= ~IFF_OACTIVE;
2408
2409         if (sc->bge_txcnt == 0)
2410                 ifp->if_timer = 0;
2411
2412         if (!ifq_is_empty(&ifp->if_snd))
2413                 if_devstart(ifp);
2414 }
2415
2416 #ifdef DEVICE_POLLING
2417
2418 static void
2419 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2420 {
2421         struct bge_softc *sc = ifp->if_softc;
2422         uint32_t status;
2423
2424         switch(cmd) {
2425         case POLL_REGISTER:
2426                 bge_disable_intr(sc);
2427                 break;
2428         case POLL_DEREGISTER:
2429                 bge_enable_intr(sc);
2430                 break;
2431         case POLL_AND_CHECK_STATUS:
2432                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2433                                 sc->bge_cdata.bge_status_map,
2434                                 BUS_DMASYNC_POSTREAD);
2435
2436                 /*
2437                  * Process link state changes.
2438                  */
2439                 status = CSR_READ_4(sc, BGE_MAC_STS);
2440                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2441                         sc->bge_link_evt = 0;
2442                         sc->bge_link_upd(sc, status);
2443                 }
2444                 /* fall through */
2445         case POLL_ONLY:
2446                 if (ifp->if_flags & IFF_RUNNING) {
2447                         bge_rxeof(sc);
2448                         bge_txeof(sc);
2449                 }
2450                 break;
2451         }
2452 }
2453
2454 #endif
2455
2456 static void
2457 bge_intr(void *xsc)
2458 {
2459         struct bge_softc *sc = xsc;
2460         struct ifnet *ifp = &sc->arpcom.ac_if;
2461         uint32_t status;
2462
2463         logif(intr);
2464
2465         /*
2466          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2467          * disable interrupts by writing nonzero like we used to, since with
2468          * our current organization this just gives complications and
2469          * pessimizations for re-enabling interrupts.  We used to have races
2470          * instead of the necessary complications.  Disabling interrupts
2471          * would just reduce the chance of a status update while we are
2472          * running (by switching to the interrupt-mode coalescence
2473          * parameters), but this chance is already very low so it is more
2474          * efficient to get another interrupt than prevent it.
2475          *
2476          * We do the ack first to ensure another interrupt if there is a
2477          * status update after the ack.  We don't check for the status
2478          * changing later because it is more efficient to get another
2479          * interrupt than prevent it, not quite as above (not checking is
2480          * a smaller optimization than not toggling the interrupt enable,
2481          * since checking doesn't involve PCI accesses and toggling require
2482          * the status check).  So toggling would probably be a pessimization
2483          * even with MSI.  It would only be needed for using a task queue.
2484          */
2485         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2486
2487         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2488                         sc->bge_cdata.bge_status_map,
2489                         BUS_DMASYNC_POSTREAD);
2490
2491         /*
2492          * Process link state changes.
2493          */
2494         status = CSR_READ_4(sc, BGE_MAC_STS);
2495         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2496                 sc->bge_link_evt = 0;
2497                 sc->bge_link_upd(sc, status);
2498         }
2499
2500         if (ifp->if_flags & IFF_RUNNING) {
2501                 /* Check RX return ring producer/consumer */
2502                 bge_rxeof(sc);
2503
2504                 /* Check TX ring producer/consumer */
2505                 bge_txeof(sc);
2506         }
2507
2508         if (sc->bge_coal_chg)
2509                 bge_coal_change(sc);
2510 }
2511
2512 static void
2513 bge_tick(void *xsc)
2514 {
2515         struct bge_softc *sc = xsc;
2516         struct ifnet *ifp = &sc->arpcom.ac_if;
2517
2518         lwkt_serialize_enter(ifp->if_serializer);
2519
2520         if (BGE_IS_5705_PLUS(sc))
2521                 bge_stats_update_regs(sc);
2522         else
2523                 bge_stats_update(sc);
2524
2525         if (sc->bge_flags & BGE_FLAG_TBI) {
2526                 /*
2527                  * Since in TBI mode auto-polling can't be used we should poll
2528                  * link status manually. Here we register pending link event
2529                  * and trigger interrupt.
2530                  */
2531                 sc->bge_link_evt++;
2532                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2533         } else if (!sc->bge_link) {
2534                 mii_tick(device_get_softc(sc->bge_miibus));
2535         }
2536
2537         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2538
2539         lwkt_serialize_exit(ifp->if_serializer);
2540 }
2541
2542 static void
2543 bge_stats_update_regs(struct bge_softc *sc)
2544 {
2545         struct ifnet *ifp = &sc->arpcom.ac_if;
2546         struct bge_mac_stats_regs stats;
2547         uint32_t *s;
2548         int i;
2549
2550         s = (uint32_t *)&stats;
2551         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2552                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2553                 s++;
2554         }
2555
2556         ifp->if_collisions +=
2557            (stats.dot3StatsSingleCollisionFrames +
2558            stats.dot3StatsMultipleCollisionFrames +
2559            stats.dot3StatsExcessiveCollisions +
2560            stats.dot3StatsLateCollisions) -
2561            ifp->if_collisions;
2562 }
2563
2564 static void
2565 bge_stats_update(struct bge_softc *sc)
2566 {
2567         struct ifnet *ifp = &sc->arpcom.ac_if;
2568         bus_size_t stats;
2569
2570         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2571
2572 #define READ_STAT(sc, stats, stat)      \
2573         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2574
2575         ifp->if_collisions +=
2576            (READ_STAT(sc, stats,
2577                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2578             READ_STAT(sc, stats,
2579                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2580             READ_STAT(sc, stats,
2581                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2582             READ_STAT(sc, stats,
2583                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2584            ifp->if_collisions;
2585
2586 #undef READ_STAT
2587
2588 #ifdef notdef
2589         ifp->if_collisions +=
2590            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2591            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2592            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2593            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2594            ifp->if_collisions;
2595 #endif
2596 }
2597
2598 /*
2599  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2600  * pointers to descriptors.
2601  */
2602 static int
2603 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2604 {
2605         struct bge_tx_bd *d = NULL;
2606         uint16_t csum_flags = 0;
2607         struct bge_dmamap_arg ctx;
2608         bus_dma_segment_t segs[BGE_NSEG_NEW];
2609         bus_dmamap_t map;
2610         int error, maxsegs, idx, i;
2611         struct mbuf *m_head = *m_head0;
2612
2613         if (m_head->m_pkthdr.csum_flags) {
2614                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2615                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2616                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2617                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2618                 if (m_head->m_flags & M_LASTFRAG)
2619                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2620                 else if (m_head->m_flags & M_FRAG)
2621                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2622         }
2623
2624         idx = *txidx;
2625         map = sc->bge_cdata.bge_tx_dmamap[idx];
2626
2627         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2628         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2629                 ("not enough segments %d\n", maxsegs));
2630
2631         if (maxsegs > BGE_NSEG_NEW)
2632                 maxsegs = BGE_NSEG_NEW;
2633
2634         /*
2635          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2636          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2637          * but when such padded frames employ the bge IP/TCP checksum
2638          * offload, the hardware checksum assist gives incorrect results
2639          * (possibly from incorporating its own padding into the UDP/TCP
2640          * checksum; who knows).  If we pad such runts with zeros, the
2641          * onboard checksum comes out correct.  We do this by pretending
2642          * the mbuf chain has too many fragments so the coalescing code
2643          * below can assemble the packet into a single buffer that's
2644          * padded out to the mininum frame size.
2645          */
2646         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2647             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2648                 error = EFBIG;
2649         } else {
2650                 ctx.bge_segs = segs;
2651                 ctx.bge_maxsegs = maxsegs;
2652                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2653                                              m_head, bge_dma_map_mbuf, &ctx,
2654                                              BUS_DMA_NOWAIT);
2655         }
2656         if (error == EFBIG || ctx.bge_maxsegs == 0) {
2657                 struct mbuf *m_new;
2658
2659                 m_new = m_defrag(m_head, MB_DONTWAIT);
2660                 if (m_new == NULL) {
2661                         if_printf(&sc->arpcom.ac_if,
2662                                   "could not defrag TX mbuf\n");
2663                         error = ENOBUFS;
2664                         goto back;
2665                 } else {
2666                         m_head = m_new;
2667                         *m_head0 = m_head;
2668                 }
2669
2670                 /*
2671                  * Manually pad short frames, and zero the pad space
2672                  * to avoid leaking data.
2673                  */
2674                 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2675                     m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2676                         int pad_len = BGE_MIN_FRAME - m_head->m_pkthdr.len;
2677
2678                         bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
2679                               pad_len);
2680                         m_head->m_pkthdr.len += pad_len;
2681                         m_head->m_len = m_head->m_pkthdr.len;
2682                 }
2683
2684                 ctx.bge_segs = segs;
2685                 ctx.bge_maxsegs = maxsegs;
2686                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2687                                              m_head, bge_dma_map_mbuf, &ctx,
2688                                              BUS_DMA_NOWAIT);
2689                 if (error || ctx.bge_maxsegs == 0) {
2690                         if_printf(&sc->arpcom.ac_if,
2691                                   "could not defrag TX mbuf\n");
2692                         if (error == 0)
2693                                 error = EFBIG;
2694                         goto back;
2695                 }
2696         } else if (error) {
2697                 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2698                 goto back;
2699         }
2700
2701         bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2702
2703         for (i = 0; ; i++) {
2704                 d = &sc->bge_ldata.bge_tx_ring[idx];
2705
2706                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2707                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2708                 d->bge_len = segs[i].ds_len;
2709                 d->bge_flags = csum_flags;
2710
2711                 if (i == ctx.bge_maxsegs - 1)
2712                         break;
2713                 BGE_INC(idx, BGE_TX_RING_CNT);
2714         }
2715         /* Mark the last segment as end of packet... */
2716         d->bge_flags |= BGE_TXBDFLAG_END;
2717
2718         /* Set vlan tag to the first segment of the packet. */
2719         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2720         if (m_head->m_flags & M_VLANTAG) {
2721                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2722                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2723         } else {
2724                 d->bge_vlan_tag = 0;
2725         }
2726
2727         /*
2728          * Insure that the map for this transmission is placed at
2729          * the array index of the last descriptor in this chain.
2730          */
2731         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2732         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2733         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2734         sc->bge_txcnt += ctx.bge_maxsegs;
2735
2736         BGE_INC(idx, BGE_TX_RING_CNT);
2737         *txidx = idx;
2738 back:
2739         if (error) {
2740                 m_freem(m_head);
2741                 *m_head0 = NULL;
2742         }
2743         return error;
2744 }
2745
2746 /*
2747  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2748  * to the mbuf data regions directly in the transmit descriptors.
2749  */
2750 static void
2751 bge_start(struct ifnet *ifp)
2752 {
2753         struct bge_softc *sc = ifp->if_softc;
2754         struct mbuf *m_head = NULL;
2755         uint32_t prodidx;
2756         int need_trans;
2757
2758         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2759                 return;
2760
2761         prodidx = sc->bge_tx_prodidx;
2762
2763         need_trans = 0;
2764         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2765                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2766                 if (m_head == NULL)
2767                         break;
2768
2769                 /*
2770                  * XXX
2771                  * The code inside the if() block is never reached since we
2772                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2773                  * requests to checksum TCP/UDP in a fragmented packet.
2774                  *
2775                  * XXX
2776                  * safety overkill.  If this is a fragmented packet chain
2777                  * with delayed TCP/UDP checksums, then only encapsulate
2778                  * it if we have enough descriptors to handle the entire
2779                  * chain at once.
2780                  * (paranoia -- may not actually be needed)
2781                  */
2782                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2783                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2784                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2785                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
2786                                 ifp->if_flags |= IFF_OACTIVE;
2787                                 ifq_prepend(&ifp->if_snd, m_head);
2788                                 break;
2789                         }
2790                 }
2791
2792                 /*
2793                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2794                  * descriptors of the end of the ring.  Also make
2795                  * sure there are BGE_NSEG_SPARE descriptors for
2796                  * jumbo buffers' defragmentation.
2797                  */
2798                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2799                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2800                         ifp->if_flags |= IFF_OACTIVE;
2801                         ifq_prepend(&ifp->if_snd, m_head);
2802                         break;
2803                 }
2804
2805                 /*
2806                  * Pack the data into the transmit ring. If we
2807                  * don't have room, set the OACTIVE flag and wait
2808                  * for the NIC to drain the ring.
2809                  */
2810                 if (bge_encap(sc, &m_head, &prodidx)) {
2811                         ifp->if_flags |= IFF_OACTIVE;
2812                         break;
2813                 }
2814                 need_trans = 1;
2815
2816                 ETHER_BPF_MTAP(ifp, m_head);
2817         }
2818
2819         if (!need_trans)
2820                 return;
2821
2822         /* Transmit */
2823         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2824         /* 5700 b2 errata */
2825         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2826                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2827
2828         sc->bge_tx_prodidx = prodidx;
2829
2830         /*
2831          * Set a timeout in case the chip goes out to lunch.
2832          */
2833         ifp->if_timer = 5;
2834 }
2835
2836 static void
2837 bge_init(void *xsc)
2838 {
2839         struct bge_softc *sc = xsc;
2840         struct ifnet *ifp = &sc->arpcom.ac_if;
2841         uint16_t *m;
2842
2843         ASSERT_SERIALIZED(ifp->if_serializer);
2844
2845         if (ifp->if_flags & IFF_RUNNING)
2846                 return;
2847
2848         /* Cancel pending I/O and flush buffers. */
2849         bge_stop(sc);
2850         bge_reset(sc);
2851         bge_chipinit(sc);
2852
2853         /*
2854          * Init the various state machines, ring
2855          * control blocks and firmware.
2856          */
2857         if (bge_blockinit(sc)) {
2858                 if_printf(ifp, "initialization failure\n");
2859                 return;
2860         }
2861
2862         /* Specify MTU. */
2863         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2864             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2865
2866         /* Load our MAC address. */
2867         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2868         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2869         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2870
2871         /* Enable or disable promiscuous mode as needed. */
2872         bge_setpromisc(sc);
2873
2874         /* Program multicast filter. */
2875         bge_setmulti(sc);
2876
2877         /* Init RX ring. */
2878         bge_init_rx_ring_std(sc);
2879
2880         /*
2881          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2882          * memory to insure that the chip has in fact read the first
2883          * entry of the ring.
2884          */
2885         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2886                 uint32_t                v, i;
2887                 for (i = 0; i < 10; i++) {
2888                         DELAY(20);
2889                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2890                         if (v == (MCLBYTES - ETHER_ALIGN))
2891                                 break;
2892                 }
2893                 if (i == 10)
2894                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2895         }
2896
2897         /* Init jumbo RX ring. */
2898         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2899                 bge_init_rx_ring_jumbo(sc);
2900
2901         /* Init our RX return ring index */
2902         sc->bge_rx_saved_considx = 0;
2903
2904         /* Init TX ring. */
2905         bge_init_tx_ring(sc);
2906
2907         /* Turn on transmitter */
2908         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2909
2910         /* Turn on receiver */
2911         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2912
2913         /* Tell firmware we're alive. */
2914         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2915
2916         /* Enable host interrupts if polling(4) is not enabled. */
2917         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2918 #ifdef DEVICE_POLLING
2919         if (ifp->if_flags & IFF_POLLING)
2920                 bge_disable_intr(sc);
2921         else
2922 #endif
2923         bge_enable_intr(sc);
2924
2925         bge_ifmedia_upd(ifp);
2926
2927         ifp->if_flags |= IFF_RUNNING;
2928         ifp->if_flags &= ~IFF_OACTIVE;
2929
2930         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2931 }
2932
2933 /*
2934  * Set media options.
2935  */
2936 static int
2937 bge_ifmedia_upd(struct ifnet *ifp)
2938 {
2939         struct bge_softc *sc = ifp->if_softc;
2940
2941         /* If this is a 1000baseX NIC, enable the TBI port. */
2942         if (sc->bge_flags & BGE_FLAG_TBI) {
2943                 struct ifmedia *ifm = &sc->bge_ifmedia;
2944
2945                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2946                         return(EINVAL);
2947
2948                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2949                 case IFM_AUTO:
2950                         /*
2951                          * The BCM5704 ASIC appears to have a special
2952                          * mechanism for programming the autoneg
2953                          * advertisement registers in TBI mode.
2954                          */
2955                         if (!bge_fake_autoneg &&
2956                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2957                                 uint32_t sgdig;
2958
2959                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2960                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2961                                 sgdig |= BGE_SGDIGCFG_AUTO |
2962                                          BGE_SGDIGCFG_PAUSE_CAP |
2963                                          BGE_SGDIGCFG_ASYM_PAUSE;
2964                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2965                                             sgdig | BGE_SGDIGCFG_SEND);
2966                                 DELAY(5);
2967                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2968                         }
2969                         break;
2970                 case IFM_1000_SX:
2971                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2972                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2973                                     BGE_MACMODE_HALF_DUPLEX);
2974                         } else {
2975                                 BGE_SETBIT(sc, BGE_MAC_MODE,
2976                                     BGE_MACMODE_HALF_DUPLEX);
2977                         }
2978                         break;
2979                 default:
2980                         return(EINVAL);
2981                 }
2982         } else {
2983                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2984
2985                 sc->bge_link_evt++;
2986                 sc->bge_link = 0;
2987                 if (mii->mii_instance) {
2988                         struct mii_softc *miisc;
2989
2990                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2991                                 mii_phy_reset(miisc);
2992                 }
2993                 mii_mediachg(mii);
2994         }
2995         return(0);
2996 }
2997
2998 /*
2999  * Report current media status.
3000  */
3001 static void
3002 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3003 {
3004         struct bge_softc *sc = ifp->if_softc;
3005
3006         if (sc->bge_flags & BGE_FLAG_TBI) {
3007                 ifmr->ifm_status = IFM_AVALID;
3008                 ifmr->ifm_active = IFM_ETHER;
3009                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3010                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3011                         ifmr->ifm_status |= IFM_ACTIVE;
3012                 } else {
3013                         ifmr->ifm_active |= IFM_NONE;
3014                         return;
3015                 }
3016
3017                 ifmr->ifm_active |= IFM_1000_SX;
3018                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3019                         ifmr->ifm_active |= IFM_HDX;
3020                 else
3021                         ifmr->ifm_active |= IFM_FDX;
3022         } else {
3023                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3024
3025                 mii_pollstat(mii);
3026                 ifmr->ifm_active = mii->mii_media_active;
3027                 ifmr->ifm_status = mii->mii_media_status;
3028         }
3029 }
3030
3031 static int
3032 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3033 {
3034         struct bge_softc *sc = ifp->if_softc;
3035         struct ifreq *ifr = (struct ifreq *)data;
3036         int mask, error = 0;
3037
3038         ASSERT_SERIALIZED(ifp->if_serializer);
3039
3040         switch (command) {
3041         case SIOCSIFMTU:
3042                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3043                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3044                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3045                         error = EINVAL;
3046                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3047                         ifp->if_mtu = ifr->ifr_mtu;
3048                         ifp->if_flags &= ~IFF_RUNNING;
3049                         bge_init(sc);
3050                 }
3051                 break;
3052         case SIOCSIFFLAGS:
3053                 if (ifp->if_flags & IFF_UP) {
3054                         if (ifp->if_flags & IFF_RUNNING) {
3055                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3056
3057                                 /*
3058                                  * If only the state of the PROMISC flag
3059                                  * changed, then just use the 'set promisc
3060                                  * mode' command instead of reinitializing
3061                                  * the entire NIC. Doing a full re-init
3062                                  * means reloading the firmware and waiting
3063                                  * for it to start up, which may take a
3064                                  * second or two.  Similarly for ALLMULTI.
3065                                  */
3066                                 if (mask & IFF_PROMISC)
3067                                         bge_setpromisc(sc);
3068                                 if (mask & IFF_ALLMULTI)
3069                                         bge_setmulti(sc);
3070                         } else {
3071                                 bge_init(sc);
3072                         }
3073                 } else {
3074                         if (ifp->if_flags & IFF_RUNNING)
3075                                 bge_stop(sc);
3076                 }
3077                 sc->bge_if_flags = ifp->if_flags;
3078                 break;
3079         case SIOCADDMULTI:
3080         case SIOCDELMULTI:
3081                 if (ifp->if_flags & IFF_RUNNING)
3082                         bge_setmulti(sc);
3083                 break;
3084         case SIOCSIFMEDIA:
3085         case SIOCGIFMEDIA:
3086                 if (sc->bge_flags & BGE_FLAG_TBI) {
3087                         error = ifmedia_ioctl(ifp, ifr,
3088                             &sc->bge_ifmedia, command);
3089                 } else {
3090                         struct mii_data *mii;
3091
3092                         mii = device_get_softc(sc->bge_miibus);
3093                         error = ifmedia_ioctl(ifp, ifr,
3094                                               &mii->mii_media, command);
3095                 }
3096                 break;
3097         case SIOCSIFCAP:
3098                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3099                 if (mask & IFCAP_HWCSUM) {
3100                         ifp->if_capenable ^= IFCAP_HWCSUM;
3101                         if (IFCAP_HWCSUM & ifp->if_capenable)
3102                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3103                         else
3104                                 ifp->if_hwassist = 0;
3105                 }
3106                 break;
3107         default:
3108                 error = ether_ioctl(ifp, command, data);
3109                 break;
3110         }
3111         return error;
3112 }
3113
3114 static void
3115 bge_watchdog(struct ifnet *ifp)
3116 {
3117         struct bge_softc *sc = ifp->if_softc;
3118
3119         if_printf(ifp, "watchdog timeout -- resetting\n");
3120
3121         ifp->if_flags &= ~IFF_RUNNING;
3122         bge_init(sc);
3123
3124         ifp->if_oerrors++;
3125
3126         if (!ifq_is_empty(&ifp->if_snd))
3127                 if_devstart(ifp);
3128 }
3129
3130 /*
3131  * Stop the adapter and free any mbufs allocated to the
3132  * RX and TX lists.
3133  */
3134 static void
3135 bge_stop(struct bge_softc *sc)
3136 {
3137         struct ifnet *ifp = &sc->arpcom.ac_if;
3138         struct ifmedia_entry *ifm;
3139         struct mii_data *mii = NULL;
3140         int mtmp, itmp;
3141
3142         ASSERT_SERIALIZED(ifp->if_serializer);
3143
3144         if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3145                 mii = device_get_softc(sc->bge_miibus);
3146
3147         callout_stop(&sc->bge_stat_timer);
3148
3149         /*
3150          * Disable all of the receiver blocks
3151          */
3152         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3153         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3154         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3155         if (!BGE_IS_5705_PLUS(sc))
3156                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3157         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3158         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3159         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3160
3161         /*
3162          * Disable all of the transmit blocks
3163          */
3164         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3165         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3166         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3167         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3168         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3169         if (!BGE_IS_5705_PLUS(sc))
3170                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3171         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3172
3173         /*
3174          * Shut down all of the memory managers and related
3175          * state machines.
3176          */
3177         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3178         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3179         if (!BGE_IS_5705_PLUS(sc))
3180                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3181         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3182         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3183         if (!BGE_IS_5705_PLUS(sc)) {
3184                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3185                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3186         }
3187
3188         /* Disable host interrupts. */
3189         bge_disable_intr(sc);
3190
3191         /*
3192          * Tell firmware we're shutting down.
3193          */
3194         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3195
3196         /* Free the RX lists. */
3197         bge_free_rx_ring_std(sc);
3198
3199         /* Free jumbo RX list. */
3200         if (BGE_IS_JUMBO_CAPABLE(sc))
3201                 bge_free_rx_ring_jumbo(sc);
3202
3203         /* Free TX buffers. */
3204         bge_free_tx_ring(sc);
3205
3206         /*
3207          * Isolate/power down the PHY, but leave the media selection
3208          * unchanged so that things will be put back to normal when
3209          * we bring the interface back up.
3210          *
3211          * 'mii' may be NULL in the following cases:
3212          * - The device uses TBI.
3213          * - bge_stop() is called by bge_detach().
3214          */
3215         if (mii != NULL) {
3216                 itmp = ifp->if_flags;
3217                 ifp->if_flags |= IFF_UP;
3218                 ifm = mii->mii_media.ifm_cur;
3219                 mtmp = ifm->ifm_media;
3220                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3221                 mii_mediachg(mii);
3222                 ifm->ifm_media = mtmp;
3223                 ifp->if_flags = itmp;
3224         }
3225
3226         sc->bge_link = 0;
3227         sc->bge_coal_chg = 0;
3228
3229         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3230
3231         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3232         ifp->if_timer = 0;
3233 }
3234
3235 /*
3236  * Stop all chip I/O so that the kernel's probe routines don't
3237  * get confused by errant DMAs when rebooting.
3238  */
3239 static void
3240 bge_shutdown(device_t dev)
3241 {
3242         struct bge_softc *sc = device_get_softc(dev);
3243         struct ifnet *ifp = &sc->arpcom.ac_if;
3244
3245         lwkt_serialize_enter(ifp->if_serializer);
3246         bge_stop(sc);
3247         bge_reset(sc);
3248         lwkt_serialize_exit(ifp->if_serializer);
3249 }
3250
3251 static int
3252 bge_suspend(device_t dev)
3253 {
3254         struct bge_softc *sc = device_get_softc(dev);
3255         struct ifnet *ifp = &sc->arpcom.ac_if;
3256
3257         lwkt_serialize_enter(ifp->if_serializer);
3258         bge_stop(sc);
3259         lwkt_serialize_exit(ifp->if_serializer);
3260
3261         return 0;
3262 }
3263
3264 static int
3265 bge_resume(device_t dev)
3266 {
3267         struct bge_softc *sc = device_get_softc(dev);
3268         struct ifnet *ifp = &sc->arpcom.ac_if;
3269
3270         lwkt_serialize_enter(ifp->if_serializer);
3271
3272         if (ifp->if_flags & IFF_UP) {
3273                 bge_init(sc);
3274
3275                 if (!ifq_is_empty(&ifp->if_snd))
3276                         if_devstart(ifp);
3277         }
3278
3279         lwkt_serialize_exit(ifp->if_serializer);
3280
3281         return 0;
3282 }
3283
3284 static void
3285 bge_setpromisc(struct bge_softc *sc)
3286 {
3287         struct ifnet *ifp = &sc->arpcom.ac_if;
3288
3289         if (ifp->if_flags & IFF_PROMISC)
3290                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3291         else
3292                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3293 }
3294
3295 static void
3296 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3297 {
3298         struct bge_dmamap_arg *ctx = arg;
3299
3300         if (error)
3301                 return;
3302
3303         KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3304                 ("only one segment is allowed\n"));
3305
3306         ctx->bge_segs[0] = *segs;
3307 }
3308
3309 static void
3310 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3311                  bus_size_t mapsz __unused, int error)
3312 {
3313         struct bge_dmamap_arg *ctx = arg;
3314         int i;
3315
3316         if (error)
3317                 return;
3318
3319         if (nsegs > ctx->bge_maxsegs) {
3320                 ctx->bge_maxsegs = 0;
3321                 return;
3322         }
3323
3324         ctx->bge_maxsegs = nsegs;
3325         for (i = 0; i < nsegs; ++i)
3326                 ctx->bge_segs[i] = segs[i];
3327 }
3328
3329 static void
3330 bge_dma_free(struct bge_softc *sc)
3331 {
3332         int i;
3333
3334         /* Destroy RX/TX mbuf DMA stuffs. */
3335         if (sc->bge_cdata.bge_mtag != NULL) {
3336                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3337                         if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3338                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3339                                     sc->bge_cdata.bge_rx_std_dmamap[i]);
3340                         }
3341                 }
3342
3343                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3344                         if (sc->bge_cdata.bge_tx_dmamap[i]) {
3345                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3346                                     sc->bge_cdata.bge_tx_dmamap[i]);
3347                         }
3348                 }
3349                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3350         }
3351
3352         /* Destroy standard RX ring */
3353         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3354                            sc->bge_cdata.bge_rx_std_ring_map,
3355                            sc->bge_ldata.bge_rx_std_ring);
3356
3357         if (BGE_IS_JUMBO_CAPABLE(sc))
3358                 bge_free_jumbo_mem(sc);
3359
3360         /* Destroy RX return ring */
3361         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3362                            sc->bge_cdata.bge_rx_return_ring_map,
3363                            sc->bge_ldata.bge_rx_return_ring);
3364
3365         /* Destroy TX ring */
3366         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3367                            sc->bge_cdata.bge_tx_ring_map,
3368                            sc->bge_ldata.bge_tx_ring);
3369
3370         /* Destroy status block */
3371         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3372                            sc->bge_cdata.bge_status_map,
3373                            sc->bge_ldata.bge_status_block);
3374
3375         /* Destroy statistics block */
3376         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3377                            sc->bge_cdata.bge_stats_map,
3378                            sc->bge_ldata.bge_stats);
3379
3380         /* Destroy the parent tag */
3381         if (sc->bge_cdata.bge_parent_tag != NULL)
3382                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3383 }
3384
3385 static int
3386 bge_dma_alloc(struct bge_softc *sc)
3387 {
3388         struct ifnet *ifp = &sc->arpcom.ac_if;
3389         int nseg, i, error;
3390
3391         /*
3392          * Allocate the parent bus DMA tag appropriate for PCI.
3393          */
3394         error = bus_dma_tag_create(NULL, 1, 0,
3395                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3396                                    NULL, NULL,
3397                                    MAXBSIZE, BGE_NSEG_NEW,
3398                                    BUS_SPACE_MAXSIZE_32BIT,
3399                                    0, &sc->bge_cdata.bge_parent_tag);
3400         if (error) {
3401                 if_printf(ifp, "could not allocate parent dma tag\n");
3402                 return error;
3403         }
3404
3405         /*
3406          * Create DMA tag for mbufs.
3407          */
3408         nseg = BGE_NSEG_NEW;
3409         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3410                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3411                                    NULL, NULL,
3412                                    MCLBYTES * nseg, nseg, MCLBYTES,
3413                                    BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3414         if (error) {
3415                 if_printf(ifp, "could not allocate mbuf dma tag\n");
3416                 return error;
3417         }
3418
3419         /*
3420          * Create DMA maps for TX/RX mbufs.
3421          */
3422         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3423                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3424                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3425                 if (error) {
3426                         int j;
3427
3428                         for (j = 0; j < i; ++j) {
3429                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3430                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3431                         }
3432                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3433                         sc->bge_cdata.bge_mtag = NULL;
3434
3435                         if_printf(ifp, "could not create DMA map for RX\n");
3436                         return error;
3437                 }
3438         }
3439
3440         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3441                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3442                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3443                 if (error) {
3444                         int j;
3445
3446                         for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3447                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3448                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3449                         }
3450                         for (j = 0; j < i; ++j) {
3451                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3452                                         sc->bge_cdata.bge_tx_dmamap[j]);
3453                         }
3454                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3455                         sc->bge_cdata.bge_mtag = NULL;
3456
3457                         if_printf(ifp, "could not create DMA map for TX\n");
3458                         return error;
3459                 }
3460         }
3461
3462         /*
3463          * Create DMA stuffs for standard RX ring.
3464          */
3465         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3466                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3467                                     &sc->bge_cdata.bge_rx_std_ring_map,
3468                                     (void **)&sc->bge_ldata.bge_rx_std_ring,
3469                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3470         if (error) {
3471                 if_printf(ifp, "could not create std RX ring\n");
3472                 return error;
3473         }
3474
3475         /*
3476          * Create jumbo buffer pool.
3477          */
3478         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3479                 error = bge_alloc_jumbo_mem(sc);
3480                 if (error) {
3481                         if_printf(ifp, "could not create jumbo buffer pool\n");
3482                         return error;
3483                 }
3484         }
3485
3486         /*
3487          * Create DMA stuffs for RX return ring.
3488          */
3489         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3490                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3491                                     &sc->bge_cdata.bge_rx_return_ring_map,
3492                                     (void **)&sc->bge_ldata.bge_rx_return_ring,
3493                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3494         if (error) {
3495                 if_printf(ifp, "could not create RX ret ring\n");
3496                 return error;
3497         }
3498
3499         /*
3500          * Create DMA stuffs for TX ring.
3501          */
3502         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3503                                     &sc->bge_cdata.bge_tx_ring_tag,
3504                                     &sc->bge_cdata.bge_tx_ring_map,
3505                                     (void **)&sc->bge_ldata.bge_tx_ring,
3506                                     &sc->bge_ldata.bge_tx_ring_paddr);
3507         if (error) {
3508                 if_printf(ifp, "could not create TX ring\n");
3509                 return error;
3510         }
3511
3512         /*
3513          * Create DMA stuffs for status block.
3514          */
3515         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3516                                     &sc->bge_cdata.bge_status_tag,
3517                                     &sc->bge_cdata.bge_status_map,
3518                                     (void **)&sc->bge_ldata.bge_status_block,
3519                                     &sc->bge_ldata.bge_status_block_paddr);
3520         if (error) {
3521                 if_printf(ifp, "could not create status block\n");
3522                 return error;
3523         }
3524
3525         /*
3526          * Create DMA stuffs for statistics block.
3527          */
3528         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3529                                     &sc->bge_cdata.bge_stats_tag,
3530                                     &sc->bge_cdata.bge_stats_map,
3531                                     (void **)&sc->bge_ldata.bge_stats,
3532                                     &sc->bge_ldata.bge_stats_paddr);
3533         if (error) {
3534                 if_printf(ifp, "could not create stats block\n");
3535                 return error;
3536         }
3537         return 0;
3538 }
3539
3540 static int
3541 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3542                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3543 {
3544         struct ifnet *ifp = &sc->arpcom.ac_if;
3545         struct bge_dmamap_arg ctx;
3546         bus_dma_segment_t seg;
3547         int error;
3548
3549         /*
3550          * Create DMA tag
3551          */
3552         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3553                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3554                                    NULL, NULL, size, 1, size, 0, tag);
3555         if (error) {
3556                 if_printf(ifp, "could not allocate dma tag\n");
3557                 return error;
3558         }
3559
3560         /*
3561          * Allocate DMA'able memory
3562          */
3563         error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3564                                  map);
3565         if (error) {
3566                 if_printf(ifp, "could not allocate dma memory\n");
3567                 bus_dma_tag_destroy(*tag);
3568                 *tag = NULL;
3569                 return error;
3570         }
3571
3572         /*
3573          * Load the DMA'able memory
3574          */
3575         ctx.bge_maxsegs = 1;
3576         ctx.bge_segs = &seg;
3577         error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3578                                 BUS_DMA_WAITOK);
3579         if (error) {
3580                 if_printf(ifp, "could not load dma memory\n");
3581                 bus_dmamem_free(*tag, *addr, *map);
3582                 bus_dma_tag_destroy(*tag);
3583                 *tag = NULL;
3584                 return error;
3585         }
3586         *paddr = ctx.bge_segs[0].ds_addr;
3587
3588         return 0;
3589 }
3590
3591 static void
3592 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3593 {
3594         if (tag != NULL) {
3595                 bus_dmamap_unload(tag, map);
3596                 bus_dmamem_free(tag, addr, map);
3597                 bus_dma_tag_destroy(tag);
3598         }
3599 }
3600
3601 /*
3602  * Grrr. The link status word in the status block does
3603  * not work correctly on the BCM5700 rev AX and BX chips,
3604  * according to all available information. Hence, we have
3605  * to enable MII interrupts in order to properly obtain
3606  * async link changes. Unfortunately, this also means that
3607  * we have to read the MAC status register to detect link
3608  * changes, thereby adding an additional register access to
3609  * the interrupt handler.
3610  *
3611  * XXX: perhaps link state detection procedure used for
3612  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3613  */
3614 static void
3615 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3616 {
3617         struct ifnet *ifp = &sc->arpcom.ac_if;
3618         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3619
3620         mii_pollstat(mii);
3621
3622         if (!sc->bge_link &&
3623             (mii->mii_media_status & IFM_ACTIVE) &&
3624             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3625                 sc->bge_link++;
3626                 if (bootverbose)
3627                         if_printf(ifp, "link UP\n");
3628         } else if (sc->bge_link &&
3629             (!(mii->mii_media_status & IFM_ACTIVE) ||
3630             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3631                 sc->bge_link = 0;
3632                 if (bootverbose)
3633                         if_printf(ifp, "link DOWN\n");
3634         }
3635
3636         /* Clear the interrupt. */
3637         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3638         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3639         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3640 }
3641
3642 static void
3643 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3644 {
3645         struct ifnet *ifp = &sc->arpcom.ac_if;
3646
3647 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3648
3649         /*
3650          * Sometimes PCS encoding errors are detected in
3651          * TBI mode (on fiber NICs), and for some reason
3652          * the chip will signal them as link changes.
3653          * If we get a link change event, but the 'PCS
3654          * encoding error' bit in the MAC status register
3655          * is set, don't bother doing a link check.
3656          * This avoids spurious "gigabit link up" messages
3657          * that sometimes appear on fiber NICs during
3658          * periods of heavy traffic.
3659          */
3660         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3661                 if (!sc->bge_link) {
3662                         sc->bge_link++;
3663                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3664                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3665                                     BGE_MACMODE_TBI_SEND_CFGS);
3666                         }
3667                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3668
3669                         if (bootverbose)
3670                                 if_printf(ifp, "link UP\n");
3671
3672                         ifp->if_link_state = LINK_STATE_UP;
3673                         if_link_state_change(ifp);
3674                 }
3675         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3676                 if (sc->bge_link) {
3677                         sc->bge_link = 0;
3678
3679                         if (bootverbose)
3680                                 if_printf(ifp, "link DOWN\n");
3681
3682                         ifp->if_link_state = LINK_STATE_DOWN;
3683                         if_link_state_change(ifp);
3684                 }
3685         }
3686
3687 #undef PCS_ENCODE_ERR
3688
3689         /* Clear the attention. */
3690         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3691             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3692             BGE_MACSTAT_LINK_CHANGED);
3693 }
3694
3695 static void
3696 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3697 {
3698         /*
3699          * Check that the AUTOPOLL bit is set before
3700          * processing the event as a real link change.
3701          * Turning AUTOPOLL on and off in the MII read/write
3702          * functions will often trigger a link status
3703          * interrupt for no reason.
3704          */
3705         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3706                 struct ifnet *ifp = &sc->arpcom.ac_if;
3707                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3708
3709                 mii_pollstat(mii);
3710
3711                 if (!sc->bge_link &&
3712                     (mii->mii_media_status & IFM_ACTIVE) &&
3713                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3714                         sc->bge_link++;
3715                         if (bootverbose)
3716                                 if_printf(ifp, "link UP\n");
3717                 } else if (sc->bge_link &&
3718                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3719                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3720                         sc->bge_link = 0;
3721                         if (bootverbose)
3722                                 if_printf(ifp, "link DOWN\n");
3723                 }
3724         }
3725
3726         /* Clear the attention. */
3727         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3728             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3729             BGE_MACSTAT_LINK_CHANGED);
3730 }
3731
3732 static int
3733 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3734 {
3735         struct bge_softc *sc = arg1;
3736
3737         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3738                                    &sc->bge_rx_coal_ticks,
3739                                    BGE_RX_COAL_TICKS_CHG);
3740 }
3741
3742 static int
3743 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3744 {
3745         struct bge_softc *sc = arg1;
3746
3747         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3748                                    &sc->bge_tx_coal_ticks,
3749                                    BGE_TX_COAL_TICKS_CHG);
3750 }
3751
3752 static int
3753 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3754 {
3755         struct bge_softc *sc = arg1;
3756
3757         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3758                                    &sc->bge_rx_max_coal_bds,
3759                                    BGE_RX_MAX_COAL_BDS_CHG);
3760 }
3761
3762 static int
3763 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3764 {
3765         struct bge_softc *sc = arg1;
3766
3767         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3768                                    &sc->bge_tx_max_coal_bds,
3769                                    BGE_TX_MAX_COAL_BDS_CHG);
3770 }
3771
3772 static int
3773 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3774                     uint32_t coal_chg_mask)
3775 {
3776         struct bge_softc *sc = arg1;
3777         struct ifnet *ifp = &sc->arpcom.ac_if;
3778         int error = 0, v;
3779
3780         lwkt_serialize_enter(ifp->if_serializer);
3781
3782         v = *coal;
3783         error = sysctl_handle_int(oidp, &v, 0, req);
3784         if (!error && req->newptr != NULL) {
3785                 if (v < 0) {
3786                         error = EINVAL;
3787                 } else {
3788                         *coal = v;
3789                         sc->bge_coal_chg |= coal_chg_mask;
3790                 }
3791         }
3792
3793         lwkt_serialize_exit(ifp->if_serializer);
3794         return error;
3795 }
3796
3797 static void
3798 bge_coal_change(struct bge_softc *sc)
3799 {
3800         struct ifnet *ifp = &sc->arpcom.ac_if;
3801         uint32_t val;
3802
3803         ASSERT_SERIALIZED(ifp->if_serializer);
3804
3805         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3806                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3807                             sc->bge_rx_coal_ticks);
3808                 DELAY(10);
3809                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3810
3811                 if (bootverbose) {
3812                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3813                                   sc->bge_rx_coal_ticks);
3814                 }
3815         }
3816
3817         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3818                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3819                             sc->bge_tx_coal_ticks);
3820                 DELAY(10);
3821                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3822
3823                 if (bootverbose) {
3824                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3825                                   sc->bge_tx_coal_ticks);
3826                 }
3827         }
3828
3829         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3830                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3831                             sc->bge_rx_max_coal_bds);
3832                 DELAY(10);
3833                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3834
3835                 if (bootverbose) {
3836                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
3837                                   sc->bge_rx_max_coal_bds);
3838                 }
3839         }
3840
3841         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3842                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3843                             sc->bge_tx_max_coal_bds);
3844                 DELAY(10);
3845                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3846
3847                 if (bootverbose) {
3848                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3849                                   sc->bge_tx_max_coal_bds);
3850                 }
3851         }
3852
3853         sc->bge_coal_chg = 0;
3854 }
3855
3856 static void
3857 bge_enable_intr(struct bge_softc *sc)
3858 {
3859         struct ifnet *ifp = &sc->arpcom.ac_if;
3860
3861         lwkt_serialize_handler_enable(ifp->if_serializer);
3862
3863         /*
3864          * Enable interrupt.
3865          */
3866         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3867
3868         /*
3869          * Unmask the interrupt when we stop polling.
3870          */
3871         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3872
3873         /*
3874          * Trigger another interrupt, since above writing
3875          * to interrupt mailbox0 may acknowledge pending
3876          * interrupt.
3877          */
3878         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3879 }
3880
3881 static void
3882 bge_disable_intr(struct bge_softc *sc)
3883 {
3884         struct ifnet *ifp = &sc->arpcom.ac_if;
3885
3886         /*
3887          * Mask the interrupt when we start polling.
3888          */
3889         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3890
3891         /*
3892          * Acknowledge possible asserted interrupt.
3893          */
3894         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3895
3896         lwkt_serialize_handler_disable(ifp->if_serializer);
3897 }