sys/net/i4b/layer1/ifpi2/i4b_ifpi2_pci.c

   1 /*
   2  *   Copyright (c) 2001 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpi2_pci.c: AVM Fritz!Card PCI hardware driver
  34  *      --------------------------------------------------
  35  *
  36  *      $Id$
  37  *
  38  * $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.6.2.2 2002/05/15 08:12:42 gj Exp $
  39  * $DragonFly: src/sys/net/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.14 2006/12/22 23:44:56 swildner Exp $
  40  *
  41  *      last edit-date: [Fri Jan 12 17:01:26 2001]
  42  *
  43  *---------------------------------------------------------------------------*/
  44
  45 #include "use_ifpi2.h"
  46 #include "use_pci.h"
  47 #include "opt_i4b.h"
  48
  49 #if (NIFPI2 > 0) && (NPCI > 0)
  50
  51 #include <sys/param.h>
  52 #include <sys/kernel.h>
  53 #include <sys/systm.h>
  54 #include <sys/mbuf.h>
  55 #include <sys/bus.h>
  56 #include <sys/rman.h>
  57 #include <sys/socket.h>
  58 #include <sys/thread2.h>
  59
  60 #include <bus/pci/pcireg.h>
  61 #include <bus/pci/pcivar.h>
  62
  63 #include <net/if.h>
  64 #include <net/i4b/include/machine/i4b_debug.h>
  65 #include <net/i4b/include/machine/i4b_ioctl.h>
  66 #include <net/i4b/include/machine/i4b_trace.h>
  67
  68 #include "../../include/i4b_global.h"
  69 #include "../../include/i4b_mbuf.h"
  70
  71 #include "../i4b_l1.h"
  72 #include "../isic/i4b_isic.h"
  73 /*#include "../isic/i4b_isac.h"*/
  74 #include "../isic/i4b_hscx.h"
  75
  76 #include "i4b_ifpi2_ext.h"
  77 #include "i4b_ifpi2_isacsx.h"
  78
  79 #define PCI_AVMA1_VID 0x1244
  80 #define PCI_AVMA1_V2_DID 0x0e00
  81
  82 /* prototypes */
  83 static void avma1pp2_disable(device_t);
  84
  85 static void avma1pp2_intr(void *);
  86 static void hscx_write_reg(int, u_int, struct l1_softc *);
  87 static u_char hscx_read_reg(int, struct l1_softc *);
  88 static u_int hscx_read_reg_int(int, struct l1_softc *);
  89 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  90 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  91 static void avma1pp2_hscx_int_handler(struct l1_softc *);
  92 static void avma1pp2_hscx_intr(int, u_int, struct l1_softc *);
  93 static void avma1pp2_init_linktab(struct l1_softc *);
  94 static void avma1pp2_bchannel_setup(int, int, int, int);
  95 static void avma1pp2_bchannel_start(int, int);
  96 static void avma1pp2_hscx_init(struct l1_softc *, int, int);
  97 static void avma1pp2_bchannel_stat(int, int, bchan_statistics_t *);
  98 static void avma1pp2_set_linktab(int, int, drvr_link_t *);
  99 static isdn_link_t * avma1pp2_ret_linktab(int, int);
 100 static int avma1pp2_pci_probe(device_t);
 101 static int avma1pp2_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
 102 int avma1pp2_attach_avma1pp(device_t);
 103 static void ifpi2_isacsx_intr(struct l1_softc *sc);
 104
 105 static device_method_t avma1pp2_pci_methods[] = {
 106         /* Device interface */
 107         DEVMETHOD(device_probe,         avma1pp2_pci_probe),
 108         DEVMETHOD(device_attach,        avma1pp2_attach_avma1pp),
 109         DEVMETHOD(device_shutdown,      avma1pp2_disable),
 110
 111         /* bus interface */
 112         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 113         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 114
 115         { 0, 0 }
 116 };
 117
 118 static driver_t avma1pp2_pci_driver = {
 119         "ifpi2-",
 120         avma1pp2_pci_methods,
 121         sizeof(struct l1_softc)
 122 };
 123
 124 static devclass_t avma1pp2_pci_devclass;
 125
 126 DRIVER_MODULE(avma1pp2, pci, avma1pp2_pci_driver, avma1pp2_pci_devclass, 0, 0);
 127
 128 /* jump table for multiplex routines */
 129
 130 struct i4b_l1mux_func avma1pp2_l1mux_func = {
 131         avma1pp2_ret_linktab,
 132         avma1pp2_set_linktab,
 133         ifpi2_mph_command_req,
 134         ifpi2_ph_data_req,
 135         ifpi2_ph_activate_req,
 136 };
 137
 138 struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
 139
 140 /*---------------------------------------------------------------------------*
 141  *      AVM PCI Fritz!Card V. 2 special registers
 142  *---------------------------------------------------------------------------*/
 143
 144 /*
 145  *      AVM PCI Status Latch 0 read only bits
 146  */
 147 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active high */
 148 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active high */
 149 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active high */
 150 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 151 /* actually active high */
 152 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 153
 154 /*
 155  *      AVM PCI Status Latch 0 read only bits
 156  */
 157 #define ASL_TIMERRESET          0x04
 158 #define ASL_ENABLE_INT          0x08
 159
 160 /*
 161  * "HSCX" status bits
 162  */
 163 #define  HSCX_STAT_RME          0x01
 164 #define  HSCX_STAT_RDO          0x10
 165 #define  HSCX_STAT_CRCVFRRAB    0x0E
 166 #define  HSCX_STAT_CRCVFR       0x06
 167 #define  HSCX_STAT_RML_MASK     0x3f00
 168
 169 /*
 170  * "HSCX" interrupt bits
 171  */
 172 #define  HSCX_INT_XPR           0x80
 173 #define  HSCX_INT_XDU           0x40
 174 #define  HSCX_INT_RPR           0x20
 175 #define  HSCX_INT_MASK          0xE0
 176
 177 /*
 178  * "HSCX" command bits
 179  */
 180 #define  HSCX_CMD_XRS           0x80
 181 #define  HSCX_CMD_XME           0x01
 182 #define  HSCX_CMD_RRS           0x20
 183 #define  HSCX_CMD_XML_MASK      0x3f00
 184
 185 /* "HSCX" mode bits */
 186 #define HSCX_MODE_ITF_FLG       0x01
 187 #define HSCX_MODE_TRANS         0x02
 188
 189 /* offsets to various registers in the ASIC, evidently */
 190 #define  STAT0_OFFSET           0x02
 191
 192 #define  HSCX_FIFO1             0x10
 193 #define  HSCX_FIFO2             0x18
 194
 195 #define  HSCX_STAT1             0x14
 196 #define  HSCX_STAT2             0x1c
 197
 198 #define  ISACSX_INDEX           0x04
 199 #define  ISACSX_DATA            0x08
 200
 201 /*
 202  * Commands and parameters are sent to the "HSCX" as a long, but the
 203  * fields are handled as bytes.
 204  *
 205  * The long contains:
 206  *      (prot << 16)|(txl << 8)|cmd
 207  *
 208  * where:
 209  *      prot = protocol to use
 210  *      txl = transmit length
 211  *      cmd = the command to be executed
 212  *
 213  * The fields are defined as u_char in struct l1_softc.
 214  *
 215  * Macro to coalesce the byte fields into a u_int
 216  */
 217 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 218                                         | (sc->avma1pp_prot << 16))
 219
 220 /*
 221  * to prevent deactivating the "HSCX" when both channels are active we
 222  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 223  * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
 224  * It is set high to allow room for new flags.
 225  */
 226 #define HSCX_AVMA1PP_ACTIVE     0x1000
 227
 228 /*---------------------------------------------------------------------------*
 229  *      AVM read fifo routines
 230  *---------------------------------------------------------------------------*/
 231
 232 static void
 233 avma1pp2_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 234 {
 235         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 236         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 237         int i;
 238
 239         switch (what) {
 240                 case ISIC_WHAT_ISAC:
 241                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
 242                         /* evidently each byte must be read as a long */
 243                         for (i = 0; i < size; i++)
 244                                 ((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 245                         break;
 246                 case ISIC_WHAT_HSCXA:
 247                         hscx_read_fifo(0, buf, size, sc);
 248                         break;
 249                 case ISIC_WHAT_HSCXB:
 250                         hscx_read_fifo(1, buf, size, sc);
 251                         break;
 252         }
 253 }
 254
 255 static void
 256 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 257 {
 258         u_int32_t *ip;
 259         size_t cnt;
 260         int dataoff;
 261         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 262         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 263
 264         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 265
 266         ip = (u_int32_t *)buf;
 267         cnt = 0;
 268         /* what if len isn't a multiple of sizeof(int) and buf is */
 269         /* too small ???? */
 270         while (cnt < len)
 271         {
 272                 *ip++ = bus_space_read_4(btag, bhandle, dataoff);
 273                 cnt += 4;
 274         }
 275 }
 276
 277 /*---------------------------------------------------------------------------*
 278  *      AVM write fifo routines
 279  *---------------------------------------------------------------------------*/
 280 static void
 281 avma1pp2_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 282 {
 283         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 284         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 285         int i;
 286
 287         switch (what) {
 288                 case ISIC_WHAT_ISAC:
 289                         bus_space_write_4(btag, bhandle,  ISACSX_INDEX, 0);
 290                         /* evidently each byte must written as a long */
 291                         for (i = 0; i < size; i++)
 292                                 bus_space_write_4(btag, bhandle,  ISACSX_DATA, ((unsigned char *)buf)[i]);
 293                         break;
 294                 case ISIC_WHAT_HSCXA:
 295                         hscx_write_fifo(0, buf, size, sc);
 296                         break;
 297                 case ISIC_WHAT_HSCXB:
 298                         hscx_write_fifo(1, buf, size, sc);
 299                         break;
 300         }
 301 }
 302
 303 static void
 304 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 305 {
 306         u_int32_t *ip;
 307         size_t cnt;
 308         int dataoff;
 309         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 310         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 311         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 312
 313         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 314
 315         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 316         sc->avma1pp_txl = 0;
 317         if (Bchan->out_mbuf_cur == NULL)
 318         {
 319           if (Bchan->bprot != BPROT_NONE)
 320                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 321         }
 322         if (len != sc->sc_bfifolen)
 323                 sc->avma1pp_txl = len;
 324
 325         cnt = 0; /* borrow cnt */
 326         AVMA1PPSETCMDLONG(cnt);
 327         hscx_write_reg(chan, cnt, sc);
 328
 329         ip = (u_int32_t *)buf;
 330         cnt = 0;
 331         while (cnt < len)
 332         {
 333                 bus_space_write_4(btag, bhandle, dataoff, *ip);
 334                 ip++;
 335                 cnt += 4;
 336         }
 337 }
 338
 339 /*---------------------------------------------------------------------------*
 340  *      AVM write register routines
 341  *---------------------------------------------------------------------------*/
 342
 343 static void
 344 avma1pp2_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 345 {
 346         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 347         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 348
 349         switch (what) {
 350                 case ISIC_WHAT_ISAC:
 351                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 352                         bus_space_write_4(btag, bhandle, ISACSX_DATA, data);
 353                         break;
 354                 case ISIC_WHAT_HSCXA:
 355                         hscx_write_reg(0, data, sc);
 356                         break;
 357                 case ISIC_WHAT_HSCXB:
 358                         hscx_write_reg(1, data, sc);
 359                         break;
 360         }
 361 }
 362
 363 static void
 364 hscx_write_reg(int chan, u_int val, struct l1_softc *sc)
 365 {
 366         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 367         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 368         u_int off;
 369
 370         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 371
 372         bus_space_write_4(btag, bhandle, off, val);
 373 }
 374
 375 /*---------------------------------------------------------------------------*
 376  *      AVM read register routines
 377  *---------------------------------------------------------------------------*/
 378 static u_int8_t
 379 avma1pp2_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 380 {
 381         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 382         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 383         u_int8_t val;
 384
 385         switch (what) {
 386                 case ISIC_WHAT_ISAC:
 387                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 388                         val = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 389                         return(val);
 390                 case ISIC_WHAT_HSCXA:
 391                         return hscx_read_reg(0, sc);
 392                 case ISIC_WHAT_HSCXB:
 393                         return hscx_read_reg(1, sc);
 394         }
 395         return 0;
 396 }
 397
 398 static u_char
 399 hscx_read_reg(int chan, struct l1_softc *sc)
 400 {
 401         return(hscx_read_reg_int(chan, sc) & 0xff);
 402 }
 403
 404 /*
 405  * need to be able to return an int because the RBCH is in the 2nd
 406  * byte.
 407  */
 408 static u_int
 409 hscx_read_reg_int(int chan, struct l1_softc *sc)
 410 {
 411         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 412         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 413         u_int off;
 414
 415         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 416         return(bus_space_read_4(btag, bhandle, off));
 417 }
 418
 419 /*---------------------------------------------------------------------------*
 420  *      avma1pp2_probe - probe for a card
 421  *---------------------------------------------------------------------------*/
 422 static int
 423 avma1pp2_pci_probe(device_t dev)
 424 {
 425         u_int16_t               did, vid;
 426
 427         vid = pci_get_vendor(dev);
 428         did = pci_get_device(dev);
 429
 430         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_V2_DID)) {
 431                 device_set_desc(dev, "AVM Fritz!Card PCI Version 2");
 432                 return(0);
 433         }
 434
 435         return(ENXIO);
 436 }
 437
 438 /*---------------------------------------------------------------------------*
 439  *      avma1pp2_attach_avma1pp - attach Fritz!Card PCI
 440  *---------------------------------------------------------------------------*/
 441 int
 442 avma1pp2_attach_avma1pp(device_t dev)
 443 {
 444         struct l1_softc *sc;
 445         u_int v;
 446         int unit, error = 0;
 447         u_int16_t did, vid;
 448         void *ih = 0;
 449         bus_space_handle_t bhandle;
 450         bus_space_tag_t btag;
 451
 452         crit_enter();
 453
 454         vid = pci_get_vendor(dev);
 455         did = pci_get_device(dev);
 456         sc = device_get_softc(dev);
 457         unit = device_get_unit(dev);
 458         bzero(sc, sizeof(struct l1_softc));
 459
 460         /* probably not really required */
 461         if(unit > IFPI2_MAXUNIT) {
 462                 kprintf("ifpi2-%d: Error, unit > IFPI_MAXUNIT!\n", unit);
 463                 crit_exit();
 464                 return(ENXIO);
 465         }
 466
 467         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_V2_DID)) {
 468                 kprintf("ifpi2-%d: unknown device!?\n", unit);
 469                 goto fail;
 470         }
 471
 472         ifpi2_scp[unit] = sc;
 473
 474         sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
 475         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
 476                 &sc->sc_resources.io_rid[0],
 477                 0, ~0, 1, RF_ACTIVE);
 478
 479         if (sc->sc_resources.io_base[0] == NULL) {
 480                 kprintf("ifpi2-%d: couldn't map IO port\n", unit);
 481                 error = ENXIO;
 482                 goto fail;
 483         }
 484
 485         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 486         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 487
 488         /* Allocate interrupt */
 489         sc->sc_resources.irq_rid = 0;
 490         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 491                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 492
 493         if (sc->sc_resources.irq == NULL) {
 494                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 495                 kprintf("ifpi2-%d: couldn't map interrupt\n", unit);
 496                 error = ENXIO;
 497                 goto fail;
 498         }
 499
 500         error = bus_setup_intr(dev, sc->sc_resources.irq, 0,
 501                                avma1pp2_intr, sc, &ih, NULL);
 502
 503         if (error) {
 504                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 505                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 506                 kprintf("ifpi2-%d: couldn't set up irq\n", unit);
 507                 goto fail;
 508         }
 509
 510         sc->sc_unit = unit;
 511
 512         /* end of new-bus stuff */
 513
 514         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 515
 516         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 517         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 518
 519         /* setup access routines */
 520
 521         sc->clearirq = NULL;
 522         sc->readreg = avma1pp2_read_reg;
 523         sc->writereg = avma1pp2_write_reg;
 524
 525         sc->readfifo = avma1pp2_read_fifo;
 526         sc->writefifo = avma1pp2_write_fifo;
 527
 528         /* setup card type */
 529
 530         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI_V2;
 531
 532         /* setup IOM bus type */
 533
 534         sc->sc_bustyp = BUS_TYPE_IOM2;
 535
 536         /* set up some other miscellaneous things */
 537         sc->sc_ipac = 0;
 538         sc->sc_bfifolen = HSCX_FIFO_LEN;
 539
 540         /* reset the card */
 541         /* the Linux driver does this to clear any pending ISAC interrupts */
 542         v = 0;
 543         v = ISAC_READ(I_RMODED);
 544 #ifdef AVMA1PCI_V2_DEBUG
 545         kprintf("avma1pp2_attach: I_MODED %x...", v);
 546 #endif
 547         v = ISAC_READ(I_ISTAD);
 548 #ifdef AVMA1PCI_V2_DEBUG
 549         kprintf("avma1pp2_attach: I_ISTAD %x...", v);
 550 #endif
 551         v = ISAC_READ(I_ISTA);
 552 #ifdef AVMA1PCI_V2_DEBUG
 553         kprintf("avma1pp2_attach: I_ISTA %x...", v);
 554 #endif
 555         ISAC_WRITE(I_MASKD, 0xff);
 556         ISAC_WRITE(I_MASK, 0xff);
 557         /* the Linux driver does this to clear any pending HSCX interrupts */
 558         v = hscx_read_reg_int(0, sc);
 559 #ifdef AVMA1PCI_V2_DEBUG
 560         kprintf("avma1pp2_attach: 0 HSCX_STAT %x...", v);
 561 #endif
 562         v = hscx_read_reg_int(1, sc);
 563 #ifdef AVMA1PCI_V2_DEBUG
 564         kprintf("avma1pp2_attach: 1 HSCX_STAT %x\n", v);
 565 #endif
 566
 567         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET);
 568         DELAY(SEC_DELAY/100); /* 10 ms */
 569         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_ENABLE_INT);
 570         DELAY(SEC_DELAY/100); /* 10 ms */
 571
 572    /* from here to the end would normally be done in isic_pciattach */
 573
 574          kprintf("ifpi2-%d: ISACSX %s\n", unit, "PSB3186");
 575
 576         /* init the ISAC */
 577         ifpi2_isacsx_init(sc);
 578
 579         /* init the "HSCX" */
 580         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 581
 582         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 583
 584         /* can't use the normal B-Channel stuff */
 585         avma1pp2_init_linktab(sc);
 586
 587         /* set trace level */
 588
 589         sc->sc_trace = TRACE_OFF;
 590
 591         sc->sc_state = ISAC_IDLE;
 592
 593         sc->sc_ibuf = NULL;
 594         sc->sc_ib = NULL;
 595         sc->sc_ilen = 0;
 596
 597         sc->sc_obuf = NULL;
 598         sc->sc_op = NULL;
 599         sc->sc_ol = 0;
 600         sc->sc_freeflag = 0;
 601
 602         sc->sc_obuf2 = NULL;
 603         sc->sc_freeflag2 = 0;
 604
 605         callout_init(&sc->sc_T3_timeout);
 606         callout_init(&sc->sc_T4_timeout);
 607
 608         /* init higher protocol layers */
 609
 610         i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp2_l1mux_func);
 611
 612   fail:
 613         crit_exit();
 614         return(error);
 615 }
 616
 617 /*
 618  * this is the real interrupt routine
 619  */
 620 static void
 621 avma1pp2_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 622 {
 623         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 624         int activity = -1;
 625         u_int param = 0;
 626
 627         NDBGL1(L1_H_IRQ, "%#x", stat);
 628
 629         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 630         {
 631                 chan->stat_XDU++;
 632                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 633                 /* abort the transmission */
 634                 sc->avma1pp_txl = 0;
 635                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 636                 AVMA1PPSETCMDLONG(param);
 637                 hscx_write_reg(h_chan, param, sc);
 638                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 639                 AVMA1PPSETCMDLONG(param);
 640                 hscx_write_reg(h_chan, param, sc);
 641
 642                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 643                 {
 644                         i4b_Bfreembuf(chan->out_mbuf_head);
 645                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 646                 }
 647         }
 648
 649         /*
 650          * The following is based on examination of the Linux driver.
 651          *
 652          * The logic here is different than with a "real" HSCX; all kinds
 653          * of information (interrupt/status bits) are in stat.
 654          *              HSCX_INT_RPR indicates a receive interrupt
 655          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 656          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 657          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 658          *                      CRC/framing errors are only reported in this state.
 659          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 660          *                                      CRC/framing error
 661          */
 662
 663         if(stat & HSCX_INT_RPR)
 664         {
 665                 int fifo_data_len;
 666                 int error = 0;
 667                 /* always have to read the FIFO, so use a scratch buffer */
 668                 u_char scrbuf[HSCX_FIFO_LEN];
 669
 670                 if(stat & HSCX_STAT_RDO)
 671                 {
 672                         chan->stat_RDO++;
 673                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 674                         error++;
 675                 }
 676
 677                 /*
 678                  * check whether we're receiving data for an inactive B-channel
 679                  * and discard it. This appears to happen for telephony when
 680                  * both B-channels are active and one is deactivated. Since
 681                  * it is not really possible to deactivate the channel in that
 682                  * case (the ASIC seems to deactivate _both_ channels), the
 683                  * "deactivated" channel keeps receiving data which can lead
 684                  * to exhaustion of mbufs and a kernel panic.
 685                  *
 686                  * This is a hack, but it's the only solution I can think of
 687                  * without having the documentation for the ASIC.
 688                  * GJ - 28 Nov 1999
 689                  */
 690                  if (chan->state == HSCX_IDLE)
 691                  {
 692                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 693                         error++;
 694                  }
 695
 696                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 697
 698                 if(fifo_data_len == 0)
 699                         fifo_data_len = sc->sc_bfifolen;
 700
 701                 /* ALWAYS read data from HSCX fifo */
 702
 703                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 704                 chan->rxcount += fifo_data_len;
 705
 706                 /* all error conditions checked, now decide and take action */
 707
 708                 if(error == 0)
 709                 {
 710                         if(chan->in_mbuf == NULL)
 711                         {
 712                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 713                                         panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!\n");
 714                                 chan->in_cbptr = chan->in_mbuf->m_data;
 715                                 chan->in_len = 0;
 716                         }
 717
 718                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 719                         {
 720                                 /* OK to copy the data */
 721                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 722                                 chan->in_cbptr += fifo_data_len;
 723                                 chan->in_len += fifo_data_len;
 724
 725                                 /* setup mbuf data length */
 726
 727                                 chan->in_mbuf->m_len = chan->in_len;
 728                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 729
 730                                 if(sc->sc_trace & TRACE_B_RX)
 731                                 {
 732                                         i4b_trace_hdr_t hdr;
 733                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 734                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 735                                         hdr.dir = FROM_NT;
 736                                         hdr.count = ++sc->sc_trace_bcount;
 737                                         MICROTIME(hdr.time);
 738                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 739                                 }
 740
 741                                 if (stat & HSCX_STAT_RME)
 742                                 {
 743                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 744                                   {
 745                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 746                                          activity = ACT_RX;
 747
 748                                          /* mark buffer ptr as unused */
 749
 750                                          chan->in_mbuf = NULL;
 751                                          chan->in_cbptr = NULL;
 752                                          chan->in_len = 0;
 753                                   }
 754                                   else
 755                                   {
 756                                                 chan->stat_CRC++;
 757                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 758                                           if (chan->in_mbuf != NULL)
 759                                           {
 760                                                   i4b_Bfreembuf(chan->in_mbuf);
 761                                                   chan->in_mbuf = NULL;
 762                                                   chan->in_cbptr = NULL;
 763                                                   chan->in_len = 0;
 764                                           }
 765                                   }
 766                                 }
 767                         } /* END enough space in mbuf */
 768                         else
 769                         {
 770                                  if(chan->bprot == BPROT_NONE)
 771                                  {
 772                                           /* setup mbuf data length */
 773
 774                                           chan->in_mbuf->m_len = chan->in_len;
 775                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 776
 777                                           if(sc->sc_trace & TRACE_B_RX)
 778                                           {
 779                                                         i4b_trace_hdr_t hdr;
 780                                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 781                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 782                                                         hdr.dir = FROM_NT;
 783                                                         hdr.count = ++sc->sc_trace_bcount;
 784                                                         MICROTIME(hdr.time);
 785                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 786                                                 }
 787
 788                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 789                                                  activity = ACT_RX;
 790
 791                                           /* move rx'd data to rx queue */
 792
 793                                           if(!(IF_QFULL(&chan->rx_queue)))
 794                                           {
 795                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 796                                           }
 797                                           else
 798                                           {
 799                                                 i4b_Bfreembuf(chan->in_mbuf);
 800                                           }
 801                                           /* signal upper layer that data are available */
 802                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 803
 804                                           /* alloc new buffer */
 805
 806                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 807                                                  panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!\n");
 808
 809                                           /* setup new data ptr */
 810
 811                                           chan->in_cbptr = chan->in_mbuf->m_data;
 812
 813                                           /* OK to copy the data */
 814                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 815
 816                                           chan->in_cbptr += fifo_data_len;
 817                                           chan->in_len = fifo_data_len;
 818
 819                                           chan->rxcount += fifo_data_len;
 820                                         }
 821                                  else
 822                                         {
 823                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 824                                           chan->in_cbptr = chan->in_mbuf->m_data;
 825                                           chan->in_len = 0;
 826                                         }
 827                           }
 828                 } /* if(error == 0) */
 829                 else
 830                 {
 831                         /* land here for RDO */
 832                         if (chan->in_mbuf != NULL)
 833                         {
 834                                 i4b_Bfreembuf(chan->in_mbuf);
 835                                 chan->in_mbuf = NULL;
 836                                 chan->in_cbptr = NULL;
 837                                 chan->in_len = 0;
 838                         }
 839                         sc->avma1pp_txl = 0;
 840                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 841                         AVMA1PPSETCMDLONG(param);
 842                         hscx_write_reg(h_chan, param, sc);
 843                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 844                         AVMA1PPSETCMDLONG(param);
 845                         hscx_write_reg(h_chan, param, sc);
 846                 }
 847         }
 848
 849
 850         /* transmit fifo empty, new data can be written to fifo */
 851
 852         if(stat & HSCX_INT_XPR)
 853         {
 854                 /*
 855                  * for a description what is going on here, please have
 856                  * a look at isic_bchannel_start() in i4b_bchan.c !
 857                  */
 858
 859                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 860
 861                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 862                 {
 863                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 864
 865                         if(chan->out_mbuf_head == NULL)
 866                         {
 867                                 chan->state &= ~HSCX_TX_ACTIVE;
 868                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 869                         }
 870                         else
 871                         {
 872                                 chan->state |= HSCX_TX_ACTIVE;
 873                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 874                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 875                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 876
 877                                 if(sc->sc_trace & TRACE_B_TX)
 878                                 {
 879                                         i4b_trace_hdr_t hdr;
 880                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 881                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 882                                         hdr.dir = FROM_TE;
 883                                         hdr.count = ++sc->sc_trace_bcount;
 884                                         MICROTIME(hdr.time);
 885                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 886                                 }
 887
 888                                 if(chan->bprot == BPROT_NONE)
 889                                 {
 890                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 891                                                 activity = ACT_TX;
 892                                 }
 893                                 else
 894                                 {
 895                                         activity = ACT_TX;
 896                                 }
 897                         }
 898                 }
 899
 900                 avma1pp2_hscx_fifo(chan, sc);
 901         }
 902
 903         /* call timeout handling routine */
 904
 905         if(activity == ACT_RX || activity == ACT_TX)
 906                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 907 }
 908
 909 /*
 910  * this is the main routine which checks each channel and then calls
 911  * the real interrupt routine as appropriate
 912  */
 913 static void
 914 avma1pp2_hscx_int_handler(struct l1_softc *sc)
 915 {
 916         u_int stat;
 917
 918         /* has to be a u_int because the byte count is in the 2nd byte */
 919         stat = hscx_read_reg_int(0, sc);
 920         if (stat & HSCX_INT_MASK)
 921           avma1pp2_hscx_intr(0, stat, sc);
 922         stat = hscx_read_reg_int(1, sc);
 923         if (stat & HSCX_INT_MASK)
 924           avma1pp2_hscx_intr(1, stat, sc);
 925 }
 926
 927 static void
 928 avma1pp2_disable(device_t dev)
 929 {
 930         struct l1_softc *sc = device_get_softc(dev);
 931         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 932         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 933
 934         /* could still be wrong, but it seems to help */
 935         bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0x00);
 936 }
 937
 938 static void
 939 avma1pp2_intr(void *xsc)
 940 {
 941         u_char stat;
 942         struct l1_softc *sc;
 943         bus_space_handle_t bhandle;
 944         bus_space_tag_t btag;
 945
 946         sc = xsc;
 947         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 948         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 949
 950         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 951         NDBGL1(L1_H_IRQ, "stat %x", stat);
 952         /* was there an interrupt from this card ? */
 953         if ((stat & ASL_IRQ_Pending) == 0)
 954                 return; /* no */
 955         /* For slow machines loop as long as an interrupt is active */
 956         for (; ((stat & ASL_IRQ_Pending) != 0) ;)
 957         {
 958                 /* interrupts are high active */
 959                 if (stat & ASL_IRQ_TIMER)
 960                         NDBGL1(L1_H_IRQ, "timer interrupt ???");
 961                 if (stat & ASL_IRQ_HSCX)
 962                 {
 963                         NDBGL1(L1_H_IRQ, "HSCX");
 964                         avma1pp2_hscx_int_handler(sc);
 965                 }
 966                 if (stat & ASL_IRQ_ISAC)
 967                 {
 968                        NDBGL1(L1_H_IRQ, "ISAC");
 969                        ifpi2_isacsx_intr(sc);
 970                 }
 971                 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 972                 NDBGL1(L1_H_IRQ, "stat %x", stat);
 973
 974         }
 975 }
 976
 977 static void
 978 avma1pp2_hscx_init(struct l1_softc *sc, int h_chan, int activate)
 979 {
 980         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 981         u_int param = 0;
 982
 983         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
 984                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
 985
 986         sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
 987
 988         if (activate == 0)
 989         {
 990                 /* only deactivate if both channels are idle */
 991                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
 992                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
 993                 {
 994                         return;
 995                 }
 996                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 997                 sc->avma1pp_prot = HSCX_MODE_TRANS;
 998                 AVMA1PPSETCMDLONG(param);
 999                 hscx_write_reg(h_chan, param, sc);
1000                 return;
1001         }
1002         if(chan->bprot == BPROT_RHDLC)
1003         {
1004                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1005
1006                 /* HDLC Frames, transparent mode 0 */
1007                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1008                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1009                 AVMA1PPSETCMDLONG(param);
1010                 hscx_write_reg(h_chan, param, sc);
1011                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1012                 AVMA1PPSETCMDLONG(param);
1013                 hscx_write_reg(h_chan, param, sc);
1014                 sc->avma1pp_cmd = 0;
1015         }
1016         else
1017         {
1018                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1019
1020                 /* Raw Telephony, extended transparent mode 1 */
1021                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1022                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1023                 AVMA1PPSETCMDLONG(param);
1024                 hscx_write_reg(h_chan, param, sc);
1025                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1026                 AVMA1PPSETCMDLONG(param);
1027                 hscx_write_reg(h_chan, param, sc);
1028                 sc->avma1pp_cmd = 0;
1029         }
1030 }
1031
1032 static void
1033 avma1pp2_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1034 {
1035         struct l1_softc *sc = ifpi2_scp[unit];
1036         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1037
1038         crit_enter();
1039
1040         if(activate == 0)
1041         {
1042                 /* deactivation */
1043                 chan->state = HSCX_IDLE;
1044                 avma1pp2_hscx_init(sc, h_chan, activate);
1045         }
1046
1047         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1048                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1049
1050         /* general part */
1051
1052         chan->unit = sc->sc_unit;       /* unit number */
1053         chan->channel = h_chan;         /* B channel */
1054         chan->bprot = bprot;            /* B channel protocol */
1055         chan->state = HSCX_IDLE;        /* B channel state */
1056
1057         /* receiver part */
1058
1059         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1060
1061         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1062
1063         chan->rxcount = 0;              /* reset rx counter */
1064
1065         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1066
1067         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1068         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1069         chan->in_len = 0;               /* reset mbuf data len */
1070
1071         /* transmitter part */
1072
1073         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1074
1075         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1076
1077         chan->txcount = 0;              /* reset tx counter */
1078
1079         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1080
1081         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1082         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1083         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1084         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1085
1086         if(activate != 0)
1087         {
1088                 /* activation */
1089                 avma1pp2_hscx_init(sc, h_chan, activate);
1090                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1091         }
1092
1093         crit_exit();
1094 }
1095
1096 static void
1097 avma1pp2_bchannel_start(int unit, int h_chan)
1098 {
1099         struct l1_softc *sc = ifpi2_scp[unit];
1100         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1101         int activity = -1;
1102
1103         crit_enter();
1104         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1105         {
1106                 crit_exit();
1107                 return;                         /* yes, leave */
1108         }
1109
1110         /* get next mbuf from queue */
1111
1112         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1113
1114         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1115         {
1116                 crit_exit();
1117                 return;                         /* yes, exit */
1118         }
1119
1120         /* init current mbuf values */
1121
1122         chan->out_mbuf_cur = chan->out_mbuf_head;
1123         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1124         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1125
1126         /* activity indicator for timeout handling */
1127
1128         if(chan->bprot == BPROT_NONE)
1129         {
1130                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1131                         activity = ACT_TX;
1132         }
1133         else
1134         {
1135                 activity = ACT_TX;
1136         }
1137
1138         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1139
1140         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1141         {
1142                 i4b_trace_hdr_t hdr;
1143                 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1144                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1145                 hdr.dir = FROM_TE;
1146                 hdr.count = ++sc->sc_trace_bcount;
1147                 MICROTIME(hdr.time);
1148                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1149         }
1150
1151         avma1pp2_hscx_fifo(chan, sc);
1152
1153         /* call timeout handling routine */
1154
1155         if(activity == ACT_RX || activity == ACT_TX)
1156                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1157
1158         crit_exit();
1159 }
1160
1161 /*---------------------------------------------------------------------------*
1162  *      return the address of isic drivers linktab
1163  *---------------------------------------------------------------------------*/
1164 static isdn_link_t *
1165 avma1pp2_ret_linktab(int unit, int channel)
1166 {
1167         struct l1_softc *sc = ifpi2_scp[unit];
1168         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1169
1170         return(&chan->isic_isdn_linktab);
1171 }
1172
1173 /*---------------------------------------------------------------------------*
1174  *      set the driver linktab in the b channel softc
1175  *---------------------------------------------------------------------------*/
1176 static void
1177 avma1pp2_set_linktab(int unit, int channel, drvr_link_t *dlt)
1178 {
1179         struct l1_softc *sc = ifpi2_scp[unit];
1180         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1181
1182         chan->isic_drvr_linktab = dlt;
1183 }
1184
1185
1186 /*---------------------------------------------------------------------------*
1187  *      initialize our local linktab
1188  *---------------------------------------------------------------------------*/
1189 static void
1190 avma1pp2_init_linktab(struct l1_softc *sc)
1191 {
1192         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1193         isdn_link_t *lt = &chan->isic_isdn_linktab;
1194
1195         /* make sure the hardware driver is known to layer 4 */
1196         /* avoid overwriting if already set */
1197         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1198         {
1199                 ctrl_types[CTRL_PASSIVE].set_linktab = i4b_l1_set_linktab;
1200                 ctrl_types[CTRL_PASSIVE].get_linktab = i4b_l1_ret_linktab;
1201         }
1202
1203         /* local setup */
1204         lt->unit = sc->sc_unit;
1205         lt->channel = HSCX_CH_A;
1206         lt->bch_config = avma1pp2_bchannel_setup;
1207         lt->bch_tx_start = avma1pp2_bchannel_start;
1208         lt->bch_stat = avma1pp2_bchannel_stat;
1209         lt->tx_queue = &chan->tx_queue;
1210
1211         /* used by non-HDLC data transfers, i.e. telephony drivers */
1212         lt->rx_queue = &chan->rx_queue;
1213
1214         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1215         lt->rx_mbuf = &chan->in_mbuf;
1216
1217         chan = &sc->sc_chan[HSCX_CH_B];
1218         lt = &chan->isic_isdn_linktab;
1219
1220         lt->unit = sc->sc_unit;
1221         lt->channel = HSCX_CH_B;
1222         lt->bch_config = avma1pp2_bchannel_setup;
1223         lt->bch_tx_start = avma1pp2_bchannel_start;
1224         lt->bch_stat = avma1pp2_bchannel_stat;
1225         lt->tx_queue = &chan->tx_queue;
1226
1227         /* used by non-HDLC data transfers, i.e. telephony drivers */
1228         lt->rx_queue = &chan->rx_queue;
1229
1230         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1231         lt->rx_mbuf = &chan->in_mbuf;
1232 }
1233
1234 /*
1235  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1236  */
1237 static void
1238 avma1pp2_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1239 {
1240         struct l1_softc *sc = ifpi2_scp[unit];
1241         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1242
1243         crit_enter();
1244
1245         bsp->outbytes = chan->txcount;
1246         bsp->inbytes = chan->rxcount;
1247
1248         chan->txcount = 0;
1249         chan->rxcount = 0;
1250
1251         crit_exit();
1252 }
1253
1254 /*---------------------------------------------------------------------------*
1255  *      fill HSCX fifo with data from the current mbuf
1256  *      Put this here until it can go into i4b_hscx.c
1257  *---------------------------------------------------------------------------*/
1258 static int
1259 avma1pp2_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1260 {
1261         int len;
1262         int nextlen;
1263         int i;
1264         int cmd = 0;
1265         /* using a scratch buffer simplifies writing to the FIFO */
1266         u_char scrbuf[HSCX_FIFO_LEN];
1267
1268         len = 0;
1269
1270         /*
1271          * fill the HSCX tx fifo with data from the current mbuf. if
1272          * current mbuf holds less data than HSCX fifo length, try to
1273          * get the next mbuf from (a possible) mbuf chain. if there is
1274          * not enough data in a single mbuf or in a chain, then this
1275          * is the last mbuf and we tell the HSCX that it has to send
1276          * CRC and closing flag
1277          */
1278
1279         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1280         {
1281                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1282
1283 #ifdef NOTDEF
1284                 kprintf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1285                         chan->out_mbuf_head,
1286                         chan->out_mbuf_cur,
1287                         chan->out_mbuf_cur_ptr,
1288                         chan->out_mbuf_cur_len,
1289                         len,
1290                         nextlen);
1291 #endif
1292
1293                 cmd |= HSCX_CMDR_XTF;
1294                 /* collect the data in the scratch buffer */
1295                 for (i = 0; i < nextlen; i++)
1296                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1297
1298                 len += nextlen;
1299                 chan->txcount += nextlen;
1300
1301                 chan->out_mbuf_cur_ptr += nextlen;
1302                 chan->out_mbuf_cur_len -= nextlen;
1303
1304                 if(chan->out_mbuf_cur_len == 0)
1305                 {
1306                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1307                         {
1308                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1309                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1310
1311                                 if(sc->sc_trace & TRACE_B_TX)
1312                                 {
1313                                         i4b_trace_hdr_t hdr;
1314                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1315                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1316                                         hdr.dir = FROM_TE;
1317                                         hdr.count = ++sc->sc_trace_bcount;
1318                                         MICROTIME(hdr.time);
1319                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1320                                 }
1321                         }
1322                         else
1323                         {
1324                                 if (chan->bprot != BPROT_NONE)
1325                                         cmd |= HSCX_CMDR_XME;
1326                                 i4b_Bfreembuf(chan->out_mbuf_head);
1327                                 chan->out_mbuf_head = NULL;
1328                         }
1329                 }
1330         }
1331         /* write what we have from the scratch buf to the HSCX fifo */
1332         if (len != 0)
1333                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1334         return(cmd);
1335 }
1336
1337 /*---------------------------------------------------------------------------*
1338  *      ifpi2 - ISAC interrupt routine
1339  *---------------------------------------------------------------------------*/
1340 static void
1341 ifpi2_isacsx_intr(struct l1_softc *sc)
1342 {
1343         u_char isacsx_irq_stat;
1344
1345         for(;;)
1346         {
1347                 /* get isac irq status */
1348                 /* ISTA tells us whether it was a C/I or HDLC int. */
1349                 isacsx_irq_stat = ISAC_READ(I_ISTA);
1350
1351                 if(isacsx_irq_stat)
1352                         ifpi2_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
1353                 else
1354                         break;
1355         }
1356
1357         ISAC_WRITE(I_MASKD, 0xff);
1358         ISAC_WRITE(I_MASK, 0xff);
1359
1360         DELAY(100);
1361
1362         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1363         ISAC_WRITE(I_MASK, isacsx_imask);
1364 }
1365
1366 /*---------------------------------------------------------------------------*
1367  *      ifpi2_recover - try to recover from irq lockup
1368  *---------------------------------------------------------------------------*/
1369 void
1370 ifpi2_recover(struct l1_softc *sc)
1371 {
1372         kprintf("ifpi2_recover %d\n", sc->sc_unit);
1373 #if 0 /* fix me later */
1374         u_char byte;
1375
1376         /* get isac irq status */
1377
1378         byte = ISAC_READ(I_ISTA);
1379
1380         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1381
1382         if(byte & ISACSX_ISTA_EXI)
1383                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1384
1385         if(byte & ISACSX_ISTA_CISQ)
1386         {
1387                 byte = ISAC_READ(I_CIRR);
1388
1389                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1390
1391                 if(byte & ISACSX_CIRR_SQC)
1392                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1393         }
1394
1395         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISACSX_IMASK);
1396
1397         ISAC_WRITE(I_MASKD, 0xff);
1398         ISAC_WRITE(I_MASK, 0xff);
1399         DELAY(100);
1400         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1401         ISAC_WRITE(I_MASK, isacsx_imask);
1402 #endif
1403 }
1404
1405
1406 #endif /* NIFPI2 > 0 */