2 * Copyright © 2010 Daniel Vetter
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * $FreeBSD: src/sys/dev/drm2/i915/i915_gem_gtt.c,v 1.1 2012/05/22 11:07:44 kib Exp $
26 #include <sys/sfbuf.h>
28 #include <dev/drm/drmP.h>
29 #include <dev/drm/drm.h>
32 #include "intel_drv.h"
34 /* PPGTT support for Sandybdrige/Gen6 and later */
36 i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
37 unsigned first_entry, unsigned num_entries)
42 unsigned act_pd, first_pte, last_pte, i;
44 act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
45 first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
47 scratch_pte = GEN6_PTE_ADDR_ENCODE(ppgtt->scratch_page_dma_addr);
48 scratch_pte |= GEN6_PTE_VALID | GEN6_PTE_CACHE_LLC;
51 last_pte = first_pte + num_entries;
52 if (last_pte > I915_PPGTT_PT_ENTRIES)
53 last_pte = I915_PPGTT_PT_ENTRIES;
55 sf = sf_buf_alloc(ppgtt->pt_pages[act_pd]);
56 pt_vaddr = (uint32_t *)(uintptr_t)sf_buf_kva(sf);
58 for (i = first_pte; i < last_pte; i++)
59 pt_vaddr[i] = scratch_pte;
63 num_entries -= last_pte - first_pte;
71 i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
73 struct drm_i915_private *dev_priv;
74 struct i915_hw_ppgtt *ppgtt;
75 u_int first_pd_entry_in_global_pt, i;
77 dev_priv = dev->dev_private;
80 * ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
81 * entries. For aliasing ppgtt support we just steal them at the end for
84 first_pd_entry_in_global_pt = 512 * 1024 - I915_PPGTT_PD_ENTRIES;
86 ppgtt = kmalloc(sizeof(*ppgtt), DRM_I915_GEM, M_WAITOK | M_ZERO);
88 ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
89 ppgtt->pt_pages = kmalloc(sizeof(vm_page_t) * ppgtt->num_pd_entries,
90 DRM_I915_GEM, M_WAITOK | M_ZERO);
92 for (i = 0; i < ppgtt->num_pd_entries; i++) {
93 ppgtt->pt_pages[i] = vm_page_alloc(NULL, 0,
94 VM_ALLOC_NORMAL | VM_ALLOC_ZERO);
95 if (ppgtt->pt_pages[i] == NULL) {
96 dev_priv->mm.aliasing_ppgtt = ppgtt;
97 i915_gem_cleanup_aliasing_ppgtt(dev);
102 ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt.scratch_page_dma;
104 i915_ppgtt_clear_range(ppgtt, 0, ppgtt->num_pd_entries *
105 I915_PPGTT_PT_ENTRIES);
106 ppgtt->pd_offset = (first_pd_entry_in_global_pt) * sizeof(uint32_t);
107 dev_priv->mm.aliasing_ppgtt = ppgtt;
112 i915_ppgtt_insert_pages(struct i915_hw_ppgtt *ppgtt, unsigned first_entry,
113 unsigned num_entries, vm_page_t *pages, uint32_t pte_flags)
115 uint32_t *pt_vaddr, pte;
117 unsigned act_pd, first_pte;
118 unsigned last_pte, i;
119 vm_paddr_t page_addr;
121 act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
122 first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
124 while (num_entries) {
125 last_pte = first_pte + num_entries;
126 if (last_pte > I915_PPGTT_PT_ENTRIES)
127 last_pte = I915_PPGTT_PT_ENTRIES;
129 sf = sf_buf_alloc(ppgtt->pt_pages[act_pd]);
130 pt_vaddr = (uint32_t *)(uintptr_t)sf_buf_kva(sf);
132 for (i = first_pte; i < last_pte; i++) {
133 page_addr = VM_PAGE_TO_PHYS(*pages);
134 pte = GEN6_PTE_ADDR_ENCODE(page_addr);
135 pt_vaddr[i] = pte | pte_flags;
142 num_entries -= last_pte - first_pte;
149 i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
150 struct drm_i915_gem_object *obj, enum i915_cache_level cache_level)
152 struct drm_device *dev;
153 struct drm_i915_private *dev_priv;
157 dev_priv = dev->dev_private;
158 pte_flags = GEN6_PTE_VALID;
160 switch (cache_level) {
161 case I915_CACHE_LLC_MLC:
162 pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
165 pte_flags |= GEN6_PTE_CACHE_LLC;
167 case I915_CACHE_NONE:
168 pte_flags |= GEN6_PTE_UNCACHED;
174 i915_ppgtt_insert_pages(ppgtt, obj->gtt_space->start >> PAGE_SHIFT,
175 obj->base.size >> PAGE_SHIFT, obj->pages, pte_flags);
178 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
179 struct drm_i915_gem_object *obj)
181 i915_ppgtt_clear_range(ppgtt, obj->gtt_space->start >> PAGE_SHIFT,
182 obj->base.size >> PAGE_SHIFT);
186 i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
188 struct drm_i915_private *dev_priv;
189 struct i915_hw_ppgtt *ppgtt;
193 dev_priv = dev->dev_private;
194 ppgtt = dev_priv->mm.aliasing_ppgtt;
197 dev_priv->mm.aliasing_ppgtt = NULL;
199 for (i = 0; i < ppgtt->num_pd_entries; i++) {
200 m = ppgtt->pt_pages[i];
202 vm_page_busy_wait(m, FALSE, "i915gem");
203 vm_page_unwire(m, 0);
207 drm_free(ppgtt->pt_pages, DRM_I915_GEM);
208 drm_free(ppgtt, DRM_I915_GEM);
213 cache_level_to_agp_type(struct drm_device *dev, enum i915_cache_level
217 switch (cache_level) {
218 case I915_CACHE_LLC_MLC:
219 if (INTEL_INFO(dev)->gen >= 6)
220 return (AGP_USER_CACHED_MEMORY_LLC_MLC);
222 * Older chipsets do not have this extra level of CPU
223 * cacheing, so fallthrough and request the PTE simply
227 return (AGP_USER_CACHED_MEMORY);
230 case I915_CACHE_NONE:
231 return (AGP_USER_MEMORY);
236 do_idling(struct drm_i915_private *dev_priv)
238 bool ret = dev_priv->mm.interruptible;
240 if (dev_priv->mm.gtt.do_idle_maps) {
241 dev_priv->mm.interruptible = false;
242 if (i915_gpu_idle(dev_priv->dev, false)) {
243 DRM_ERROR("Couldn't idle GPU\n");
244 /* Wait a bit, in hopes it avoids the hang */
253 undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
256 if (dev_priv->mm.gtt.do_idle_maps)
257 dev_priv->mm.interruptible = interruptible;
261 i915_gem_restore_gtt_mappings(struct drm_device *dev)
263 struct drm_i915_private *dev_priv;
264 struct drm_i915_gem_object *obj;
266 dev_priv = dev->dev_private;
268 /* First fill our portion of the GTT with scratch pages */
269 intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
270 (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
272 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
273 i915_gem_clflush_object(obj);
274 i915_gem_gtt_rebind_object(obj, obj->cache_level);
277 intel_gtt_chipset_flush();
281 i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj)
283 unsigned int agp_type;
285 agp_type = cache_level_to_agp_type(obj->base.dev, obj->cache_level);
286 intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
287 obj->base.size >> PAGE_SHIFT, obj->pages, agp_type);
292 i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
293 enum i915_cache_level cache_level)
295 struct drm_device *dev;
296 struct drm_i915_private *dev_priv;
297 unsigned int agp_type;
300 dev_priv = dev->dev_private;
301 agp_type = cache_level_to_agp_type(dev, cache_level);
303 intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
304 obj->base.size >> PAGE_SHIFT, obj->pages, agp_type);
308 i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
310 struct drm_device *dev = obj->base.dev;
311 struct drm_i915_private *dev_priv = dev->dev_private;
315 dev_priv = dev->dev_private;
317 interruptible = do_idling(dev_priv);
319 intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,
320 obj->base.size >> PAGE_SHIFT);
322 undo_idling(dev_priv, interruptible);