sys/dev/drm/i915kms/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_irq.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <sys/sfbuf.h>
  31
  32 #include <dev/drm/drmP.h>
  33 #include <dev/drm/drm.h>
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "intel_drv.h"
  37
  38 static void i915_capture_error_state(struct drm_device *dev);
  39 static u32 ring_last_seqno(struct intel_ring_buffer *ring);
  40
  41 /**
  42  * Interrupts that are always left unmasked.
  43  *
  44  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  45  * we leave them always unmasked in IMR and then control enabling them through
  46  * PIPESTAT alone.
  47  */
  48 #define I915_INTERRUPT_ENABLE_FIX                       \
  49         (I915_ASLE_INTERRUPT |                          \
  50          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  52          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  53          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  54          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  55
  56 /** Interrupts that we mask and unmask at runtime. */
  57 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  58
  59 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  60                                  PIPE_VBLANK_INTERRUPT_STATUS)
  61
  62 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  63                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  64
  65 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  66                                          DRM_I915_VBLANK_PIPE_B)
  67
  68 /* For display hotplug interrupt */
  69 static void
  70 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  71 {
  72         if ((dev_priv->irq_mask & mask) != 0) {
  73                 dev_priv->irq_mask &= ~mask;
  74                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  75                 POSTING_READ(DEIMR);
  76         }
  77 }
  78
  79 static inline void
  80 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  81 {
  82         if ((dev_priv->irq_mask & mask) != mask) {
  83                 dev_priv->irq_mask |= mask;
  84                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  85                 POSTING_READ(DEIMR);
  86         }
  87 }
  88
  89 void
  90 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  91 {
  92         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  93                 u32 reg = PIPESTAT(pipe);
  94
  95                 dev_priv->pipestat[pipe] |= mask;
  96                 /* Enable the interrupt, clear any pending status */
  97                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  98                 POSTING_READ(reg);
  99         }
 100 }
 101
 102 void
 103 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 104 {
 105         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 106                 u32 reg = PIPESTAT(pipe);
 107
 108                 dev_priv->pipestat[pipe] &= ~mask;
 109                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 110                 POSTING_READ(reg);
 111         }
 112 }
 113
 114 /**
 115  * intel_enable_asle - enable ASLE interrupt for OpRegion
 116  */
 117 void intel_enable_asle(struct drm_device *dev)
 118 {
 119         drm_i915_private_t *dev_priv = dev->dev_private;
 120
 121         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 122
 123         if (HAS_PCH_SPLIT(dev))
 124                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 125         else {
 126                 i915_enable_pipestat(dev_priv, 1,
 127                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 128                 if (INTEL_INFO(dev)->gen >= 4)
 129                         i915_enable_pipestat(dev_priv, 0,
 130                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 131         }
 132
 133         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 134 }
 135
 136 /**
 137  * i915_pipe_enabled - check if a pipe is enabled
 138  * @dev: DRM device
 139  * @pipe: pipe to check
 140  *
 141  * Reading certain registers when the pipe is disabled can hang the chip.
 142  * Use this routine to make sure the PLL is running and the pipe is active
 143  * before reading such registers if unsure.
 144  */
 145 static int
 146 i915_pipe_enabled(struct drm_device *dev, int pipe)
 147 {
 148         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 149         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 150 }
 151
 152 /* Called from drm generic code, passed a 'crtc', which
 153  * we use as a pipe index
 154  */
 155 static u32
 156 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 157 {
 158         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 159         unsigned long high_frame;
 160         unsigned long low_frame;
 161         u32 high1, high2, low;
 162
 163         if (!i915_pipe_enabled(dev, pipe)) {
 164                 DRM_DEBUG("trying to get vblank count for disabled "
 165                                 "pipe %c\n", pipe_name(pipe));
 166                 return 0;
 167         }
 168
 169         high_frame = PIPEFRAME(pipe);
 170         low_frame = PIPEFRAMEPIXEL(pipe);
 171
 172         /*
 173          * High & low register fields aren't synchronized, so make sure
 174          * we get a low value that's stable across two reads of the high
 175          * register.
 176          */
 177         do {
 178                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 179                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 180                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 181         } while (high1 != high2);
 182
 183         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 184         low >>= PIPE_FRAME_LOW_SHIFT;
 185         return (high1 << 8) | low;
 186 }
 187
 188 static u32
 189 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 190 {
 191         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 192         int reg = PIPE_FRMCOUNT_GM45(pipe);
 193
 194         if (!i915_pipe_enabled(dev, pipe)) {
 195                 DRM_DEBUG("i915: trying to get vblank count for disabled "
 196                                  "pipe %c\n", pipe_name(pipe));
 197                 return 0;
 198         }
 199
 200         return I915_READ(reg);
 201 }
 202
 203 static int
 204 i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 205     int *vpos, int *hpos)
 206 {
 207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 208         u32 vbl = 0, position = 0;
 209         int vbl_start, vbl_end, htotal, vtotal;
 210         bool in_vbl = true;
 211         int ret = 0;
 212
 213         if (!i915_pipe_enabled(dev, pipe)) {
 214                 DRM_DEBUG("i915: trying to get scanoutpos for disabled "
 215                                  "pipe %c\n", pipe_name(pipe));
 216                 return 0;
 217         }
 218
 219         /* Get vtotal. */
 220         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 221
 222         if (INTEL_INFO(dev)->gen >= 4) {
 223                 /* No obvious pixelcount register. Only query vertical
 224                  * scanout position from Display scan line register.
 225                  */
 226                 position = I915_READ(PIPEDSL(pipe));
 227
 228                 /* Decode into vertical scanout position. Don't have
 229                  * horizontal scanout position.
 230                  */
 231                 *vpos = position & 0x1fff;
 232                 *hpos = 0;
 233         } else {
 234                 /* Have access to pixelcount since start of frame.
 235                  * We can split this into vertical and horizontal
 236                  * scanout position.
 237                  */
 238                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 239
 240                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 241                 *vpos = position / htotal;
 242                 *hpos = position - (*vpos * htotal);
 243         }
 244
 245         /* Query vblank area. */
 246         vbl = I915_READ(VBLANK(pipe));
 247
 248         /* Test position against vblank region. */
 249         vbl_start = vbl & 0x1fff;
 250         vbl_end = (vbl >> 16) & 0x1fff;
 251
 252         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 253                 in_vbl = false;
 254
 255         /* Inside "upper part" of vblank area? Apply corrective offset: */
 256         if (in_vbl && (*vpos >= vbl_start))
 257                 *vpos = *vpos - vtotal;
 258
 259         /* Readouts valid? */
 260         if (vbl > 0)
 261                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 262
 263         /* In vblank? */
 264         if (in_vbl)
 265                 ret |= DRM_SCANOUTPOS_INVBL;
 266
 267         return ret;
 268 }
 269
 270 static int
 271 i915_get_vblank_timestamp(struct drm_device *dev, int pipe, int *max_error,
 272     struct timeval *vblank_time, unsigned flags)
 273 {
 274         struct drm_i915_private *dev_priv = dev->dev_private;
 275         struct drm_crtc *crtc;
 276
 277         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 278                 DRM_ERROR("Invalid crtc %d\n", pipe);
 279                 return -EINVAL;
 280         }
 281
 282         /* Get drm_crtc to timestamp: */
 283         crtc = intel_get_crtc_for_pipe(dev, pipe);
 284         if (crtc == NULL) {
 285                 DRM_ERROR("Invalid crtc %d\n", pipe);
 286                 return -EINVAL;
 287         }
 288
 289         if (!crtc->enabled) {
 290 #if 0
 291                 DRM_DEBUG("crtc %d is disabled\n", pipe);
 292 #endif
 293                 return -EBUSY;
 294         }
 295
 296         /* Helper routine in DRM core does all the work: */
 297         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 298                                                      vblank_time, flags,
 299                                                      crtc);
 300 }
 301
 302 /*
 303  * Handle hotplug events outside the interrupt handler proper.
 304  */
 305 static void
 306 i915_hotplug_work_func(void *context, int pending)
 307 {
 308         drm_i915_private_t *dev_priv = context;
 309         struct drm_device *dev = dev_priv->dev;
 310         struct drm_mode_config *mode_config;
 311         struct intel_encoder *encoder;
 312
 313         DRM_DEBUG("running encoder hotplug functions\n");
 314         dev_priv = context;
 315         dev = dev_priv->dev;
 316
 317         mode_config = &dev->mode_config;
 318
 319         lockmgr(&mode_config->lock, LK_EXCLUSIVE);
 320         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 321
 322         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 323                 if (encoder->hot_plug)
 324                         encoder->hot_plug(encoder);
 325
 326         lockmgr(&mode_config->lock, LK_RELEASE);
 327
 328         /* Just fire off a uevent and let userspace tell us what to do */
 329 #if 0
 330         drm_helper_hpd_irq_event(dev);
 331 #endif
 332 }
 333
 334 static void i915_handle_rps_change(struct drm_device *dev)
 335 {
 336         drm_i915_private_t *dev_priv = dev->dev_private;
 337         u32 busy_up, busy_down, max_avg, min_avg;
 338         u8 new_delay = dev_priv->cur_delay;
 339
 340         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 341         busy_up = I915_READ(RCPREVBSYTUPAVG);
 342         busy_down = I915_READ(RCPREVBSYTDNAVG);
 343         max_avg = I915_READ(RCBMAXAVG);
 344         min_avg = I915_READ(RCBMINAVG);
 345
 346         /* Handle RCS change request from hw */
 347         if (busy_up > max_avg) {
 348                 if (dev_priv->cur_delay != dev_priv->max_delay)
 349                         new_delay = dev_priv->cur_delay - 1;
 350                 if (new_delay < dev_priv->max_delay)
 351                         new_delay = dev_priv->max_delay;
 352         } else if (busy_down < min_avg) {
 353                 if (dev_priv->cur_delay != dev_priv->min_delay)
 354                         new_delay = dev_priv->cur_delay + 1;
 355                 if (new_delay > dev_priv->min_delay)
 356                         new_delay = dev_priv->min_delay;
 357         }
 358
 359         if (ironlake_set_drps(dev, new_delay))
 360                 dev_priv->cur_delay = new_delay;
 361
 362         return;
 363 }
 364
 365 static void notify_ring(struct drm_device *dev,
 366                         struct intel_ring_buffer *ring)
 367 {
 368         struct drm_i915_private *dev_priv = dev->dev_private;
 369         u32 seqno;
 370
 371         if (ring->obj == NULL)
 372                 return;
 373
 374         seqno = ring->get_seqno(ring);
 375
 376         lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
 377         ring->irq_seqno = seqno;
 378         wakeup(ring);
 379         lockmgr(&ring->irq_lock, LK_RELEASE);
 380
 381         if (i915_enable_hangcheck) {
 382                 dev_priv->hangcheck_count = 0;
 383                 callout_reset(&dev_priv->hangcheck_timer,
 384                     DRM_I915_HANGCHECK_PERIOD, i915_hangcheck_elapsed, dev);
 385         }
 386 }
 387
 388 static void
 389 gen6_pm_rps_work_func(void *arg, int pending)
 390 {
 391         struct drm_device *dev;
 392         drm_i915_private_t *dev_priv;
 393         u8 new_delay;
 394         u32 pm_iir, pm_imr;
 395
 396         dev_priv = (drm_i915_private_t *)arg;
 397         dev = dev_priv->dev;
 398         new_delay = dev_priv->cur_delay;
 399
 400         lockmgr(&dev_priv->rps_lock, LK_EXCLUSIVE);
 401         pm_iir = dev_priv->pm_iir;
 402         dev_priv->pm_iir = 0;
 403         pm_imr = I915_READ(GEN6_PMIMR);
 404         I915_WRITE(GEN6_PMIMR, 0);
 405         lockmgr(&dev_priv->rps_lock, LK_RELEASE);
 406
 407         if (!pm_iir)
 408                 return;
 409
 410         DRM_LOCK(dev);
 411         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 412                 if (dev_priv->cur_delay != dev_priv->max_delay)
 413                         new_delay = dev_priv->cur_delay + 1;
 414                 if (new_delay > dev_priv->max_delay)
 415                         new_delay = dev_priv->max_delay;
 416         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
 417                 gen6_gt_force_wake_get(dev_priv);
 418                 if (dev_priv->cur_delay != dev_priv->min_delay)
 419                         new_delay = dev_priv->cur_delay - 1;
 420                 if (new_delay < dev_priv->min_delay) {
 421                         new_delay = dev_priv->min_delay;
 422                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 423                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
 424                                    ((new_delay << 16) & 0x3f0000));
 425                 } else {
 426                         /* Make sure we continue to get down interrupts
 427                          * until we hit the minimum frequency */
 428                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 429                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
 430                 }
 431                 gen6_gt_force_wake_put(dev_priv);
 432         }
 433
 434         gen6_set_rps(dev, new_delay);
 435         dev_priv->cur_delay = new_delay;
 436
 437         /*
 438          * rps_lock not held here because clearing is non-destructive. There is
 439          * an *extremely* unlikely race with gen6_rps_enable() that is prevented
 440          * by holding struct_mutex for the duration of the write.
 441          */
 442         DRM_UNLOCK(dev);
 443 }
 444
 445 static void pch_irq_handler(struct drm_device *dev)
 446 {
 447         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 448         u32 pch_iir;
 449         int pipe;
 450
 451         pch_iir = I915_READ(SDEIIR);
 452
 453         if (pch_iir & SDE_AUDIO_POWER_MASK)
 454                 DRM_DEBUG("i915: PCH audio power change on port %d\n",
 455                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 456                                  SDE_AUDIO_POWER_SHIFT);
 457
 458         if (pch_iir & SDE_GMBUS)
 459                 DRM_DEBUG("i915: PCH GMBUS interrupt\n");
 460
 461         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 462                 DRM_DEBUG("i915: PCH HDCP audio interrupt\n");
 463
 464         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 465                 DRM_DEBUG("i915: PCH transcoder audio interrupt\n");
 466
 467         if (pch_iir & SDE_POISON)
 468                 DRM_ERROR("i915: PCH poison interrupt\n");
 469
 470         if (pch_iir & SDE_FDI_MASK)
 471                 for_each_pipe(pipe)
 472                         DRM_DEBUG("  pipe %c FDI IIR: 0x%08x\n",
 473                                          pipe_name(pipe),
 474                                          I915_READ(FDI_RX_IIR(pipe)));
 475
 476         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 477                 DRM_DEBUG("i915: PCH transcoder CRC done interrupt\n");
 478
 479         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 480                 DRM_DEBUG("i915: PCH transcoder CRC error interrupt\n");
 481
 482         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 483                 DRM_DEBUG("i915: PCH transcoder B underrun interrupt\n");
 484         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 485                 DRM_DEBUG("PCH transcoder A underrun interrupt\n");
 486 }
 487
 488 static void
 489 ivybridge_irq_handler(void *arg)
 490 {
 491         struct drm_device *dev = (struct drm_device *) arg;
 492         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 493         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 494 #if 0
 495         struct drm_i915_master_private *master_priv;
 496 #endif
 497
 498         atomic_inc(&dev_priv->irq_received);
 499
 500         /* disable master interrupt before clearing iir  */
 501         de_ier = I915_READ(DEIER);
 502         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 503         POSTING_READ(DEIER);
 504
 505         de_iir = I915_READ(DEIIR);
 506         gt_iir = I915_READ(GTIIR);
 507         pch_iir = I915_READ(SDEIIR);
 508         pm_iir = I915_READ(GEN6_PMIIR);
 509
 510         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
 511                 goto done;
 512
 513 #if 0
 514         if (dev->primary->master) {
 515                 master_priv = dev->primary->master->driver_priv;
 516                 if (master_priv->sarea_priv)
 517                         master_priv->sarea_priv->last_dispatch =
 518                                 READ_BREADCRUMB(dev_priv);
 519         }
 520 #else
 521         if (dev_priv->sarea_priv)
 522                 dev_priv->sarea_priv->last_dispatch =
 523                     READ_BREADCRUMB(dev_priv);
 524 #endif
 525
 526         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 527                 notify_ring(dev, &dev_priv->rings[RCS]);
 528         if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
 529                 notify_ring(dev, &dev_priv->rings[VCS]);
 530         if (gt_iir & GT_BLT_USER_INTERRUPT)
 531                 notify_ring(dev, &dev_priv->rings[BCS]);
 532
 533         if (de_iir & DE_GSE_IVB) {
 534 #if 1
 535                 KIB_NOTYET();
 536 #else
 537                 intel_opregion_gse_intr(dev);
 538 #endif
 539         }
 540
 541         if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
 542                 intel_prepare_page_flip(dev, 0);
 543                 intel_finish_page_flip_plane(dev, 0);
 544         }
 545
 546         if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
 547                 intel_prepare_page_flip(dev, 1);
 548                 intel_finish_page_flip_plane(dev, 1);
 549         }
 550
 551         if (de_iir & DE_PIPEA_VBLANK_IVB)
 552                 drm_handle_vblank(dev, 0);
 553
 554         if (de_iir & DE_PIPEB_VBLANK_IVB)
 555                 drm_handle_vblank(dev, 1);
 556
 557         /* check event from PCH */
 558         if (de_iir & DE_PCH_EVENT_IVB) {
 559                 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 560                         taskqueue_enqueue(dev_priv->tq, &dev_priv->hotplug_task);
 561                 pch_irq_handler(dev);
 562         }
 563
 564         if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 565                 lockmgr(&dev_priv->rps_lock, LK_EXCLUSIVE);
 566                 if ((dev_priv->pm_iir & pm_iir) != 0)
 567                         kprintf("Missed a PM interrupt\n");
 568                 dev_priv->pm_iir |= pm_iir;
 569                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 570                 POSTING_READ(GEN6_PMIMR);
 571                 lockmgr(&dev_priv->rps_lock, LK_RELEASE);
 572                 taskqueue_enqueue(dev_priv->tq, &dev_priv->rps_task);
 573         }
 574
 575         /* should clear PCH hotplug event before clear CPU irq */
 576         I915_WRITE(SDEIIR, pch_iir);
 577         I915_WRITE(GTIIR, gt_iir);
 578         I915_WRITE(DEIIR, de_iir);
 579         I915_WRITE(GEN6_PMIIR, pm_iir);
 580
 581 done:
 582         I915_WRITE(DEIER, de_ier);
 583         POSTING_READ(DEIER);
 584 }
 585
 586 static void
 587 ironlake_irq_handler(void *arg)
 588 {
 589         struct drm_device *dev = arg;
 590         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 591         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 592         u32 hotplug_mask;
 593 #if 0
 594         struct drm_i915_master_private *master_priv;
 595 #endif
 596         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 597
 598         atomic_inc(&dev_priv->irq_received);
 599
 600         if (IS_GEN6(dev))
 601                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 602
 603         /* disable master interrupt before clearing iir  */
 604         de_ier = I915_READ(DEIER);
 605         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 606         POSTING_READ(DEIER);
 607
 608         de_iir = I915_READ(DEIIR);
 609         gt_iir = I915_READ(GTIIR);
 610         pch_iir = I915_READ(SDEIIR);
 611         pm_iir = I915_READ(GEN6_PMIIR);
 612
 613         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 614             (!IS_GEN6(dev) || pm_iir == 0))
 615                 goto done;
 616
 617         if (HAS_PCH_CPT(dev))
 618                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 619         else
 620                 hotplug_mask = SDE_HOTPLUG_MASK;
 621
 622 #if 0
 623         if (dev->primary->master) {
 624                 master_priv = dev->primary->master->driver_priv;
 625                 if (master_priv->sarea_priv)
 626                         master_priv->sarea_priv->last_dispatch =
 627                                 READ_BREADCRUMB(dev_priv);
 628         }
 629 #else
 630                 if (dev_priv->sarea_priv)
 631                         dev_priv->sarea_priv->last_dispatch =
 632                             READ_BREADCRUMB(dev_priv);
 633 #endif
 634
 635         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 636                 notify_ring(dev, &dev_priv->rings[RCS]);
 637         if (gt_iir & bsd_usr_interrupt)
 638                 notify_ring(dev, &dev_priv->rings[VCS]);
 639         if (gt_iir & GT_BLT_USER_INTERRUPT)
 640                 notify_ring(dev, &dev_priv->rings[BCS]);
 641
 642         if (de_iir & DE_GSE) {
 643 #if 1
 644                 KIB_NOTYET();
 645 #else
 646                 intel_opregion_gse_intr(dev);
 647 #endif
 648         }
 649
 650         if (de_iir & DE_PLANEA_FLIP_DONE) {
 651                 intel_prepare_page_flip(dev, 0);
 652                 intel_finish_page_flip_plane(dev, 0);
 653         }
 654
 655         if (de_iir & DE_PLANEB_FLIP_DONE) {
 656                 intel_prepare_page_flip(dev, 1);
 657                 intel_finish_page_flip_plane(dev, 1);
 658         }
 659
 660         if (de_iir & DE_PIPEA_VBLANK)
 661                 drm_handle_vblank(dev, 0);
 662
 663         if (de_iir & DE_PIPEB_VBLANK)
 664                 drm_handle_vblank(dev, 1);
 665
 666         /* check event from PCH */
 667         if (de_iir & DE_PCH_EVENT) {
 668                 if (pch_iir & hotplug_mask)
 669                         taskqueue_enqueue(dev_priv->tq,
 670                             &dev_priv->hotplug_task);
 671                 pch_irq_handler(dev);
 672         }
 673
 674         if (de_iir & DE_PCU_EVENT) {
 675                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 676                 i915_handle_rps_change(dev);
 677         }
 678
 679         if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 680                 lockmgr(&dev_priv->rps_lock, LK_EXCLUSIVE);
 681                 if ((dev_priv->pm_iir & pm_iir) != 0)
 682                         kprintf("Missed a PM interrupt\n");
 683                 dev_priv->pm_iir |= pm_iir;
 684                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 685                 POSTING_READ(GEN6_PMIMR);
 686                 lockmgr(&dev_priv->rps_lock, LK_RELEASE);
 687                 taskqueue_enqueue(dev_priv->tq, &dev_priv->rps_task);
 688         }
 689
 690         /* should clear PCH hotplug event before clear CPU irq */
 691         I915_WRITE(SDEIIR, pch_iir);
 692         I915_WRITE(GTIIR, gt_iir);
 693         I915_WRITE(DEIIR, de_iir);
 694         I915_WRITE(GEN6_PMIIR, pm_iir);
 695
 696 done:
 697         I915_WRITE(DEIER, de_ier);
 698         POSTING_READ(DEIER);
 699 }
 700
 701 /**
 702  * i915_error_work_func - do process context error handling work
 703  * @work: work struct
 704  *
 705  * Fire an error uevent so userspace can see that a hang or error
 706  * was detected.
 707  */
 708 static void
 709 i915_error_work_func(void *context, int pending)
 710 {
 711         drm_i915_private_t *dev_priv = context;
 712         struct drm_device *dev = dev_priv->dev;
 713
 714         /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); */
 715
 716         if (atomic_load_acq_int(&dev_priv->mm.wedged)) {
 717                 DRM_DEBUG("i915: resetting chip\n");
 718                 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); */
 719                 if (!i915_reset(dev, GRDOM_RENDER)) {
 720                         atomic_store_rel_int(&dev_priv->mm.wedged, 0);
 721                         /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); */
 722                 }
 723                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 724                 dev_priv->error_completion++;
 725                 wakeup(&dev_priv->error_completion);
 726                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 727         }
 728 }
 729
 730 static void i915_report_and_clear_eir(struct drm_device *dev)
 731 {
 732         struct drm_i915_private *dev_priv = dev->dev_private;
 733         u32 eir = I915_READ(EIR);
 734         int pipe;
 735
 736         if (!eir)
 737                 return;
 738
 739         kprintf("i915: render error detected, EIR: 0x%08x\n", eir);
 740
 741         if (IS_G4X(dev)) {
 742                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 743                         u32 ipeir = I915_READ(IPEIR_I965);
 744
 745                         kprintf("  IPEIR: 0x%08x\n",
 746                                I915_READ(IPEIR_I965));
 747                         kprintf("  IPEHR: 0x%08x\n",
 748                                I915_READ(IPEHR_I965));
 749                         kprintf("  INSTDONE: 0x%08x\n",
 750                                I915_READ(INSTDONE_I965));
 751                         kprintf("  INSTPS: 0x%08x\n",
 752                                I915_READ(INSTPS));
 753                         kprintf("  INSTDONE1: 0x%08x\n",
 754                                I915_READ(INSTDONE1));
 755                         kprintf("  ACTHD: 0x%08x\n",
 756                                I915_READ(ACTHD_I965));
 757                         I915_WRITE(IPEIR_I965, ipeir);
 758                         POSTING_READ(IPEIR_I965);
 759                 }
 760                 if (eir & GM45_ERROR_PAGE_TABLE) {
 761                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 762                         kprintf("page table error\n");
 763                         kprintf("  PGTBL_ER: 0x%08x\n",
 764                                pgtbl_err);
 765                         I915_WRITE(PGTBL_ER, pgtbl_err);
 766                         POSTING_READ(PGTBL_ER);
 767                 }
 768         }
 769
 770         if (!IS_GEN2(dev)) {
 771                 if (eir & I915_ERROR_PAGE_TABLE) {
 772                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 773                         kprintf("page table error\n");
 774                         kprintf("  PGTBL_ER: 0x%08x\n",
 775                                pgtbl_err);
 776                         I915_WRITE(PGTBL_ER, pgtbl_err);
 777                         POSTING_READ(PGTBL_ER);
 778                 }
 779         }
 780
 781         if (eir & I915_ERROR_MEMORY_REFRESH) {
 782                 kprintf("memory refresh error:\n");
 783                 for_each_pipe(pipe)
 784                         kprintf("pipe %c stat: 0x%08x\n",
 785                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
 786                 /* pipestat has already been acked */
 787         }
 788         if (eir & I915_ERROR_INSTRUCTION) {
 789                 kprintf("instruction error\n");
 790                 kprintf("  INSTPM: 0x%08x\n",
 791                        I915_READ(INSTPM));
 792                 if (INTEL_INFO(dev)->gen < 4) {
 793                         u32 ipeir = I915_READ(IPEIR);
 794
 795                         kprintf("  IPEIR: 0x%08x\n",
 796                                I915_READ(IPEIR));
 797                         kprintf("  IPEHR: 0x%08x\n",
 798                                I915_READ(IPEHR));
 799                         kprintf("  INSTDONE: 0x%08x\n",
 800                                I915_READ(INSTDONE));
 801                         kprintf("  ACTHD: 0x%08x\n",
 802                                I915_READ(ACTHD));
 803                         I915_WRITE(IPEIR, ipeir);
 804                         POSTING_READ(IPEIR);
 805                 } else {
 806                         u32 ipeir = I915_READ(IPEIR_I965);
 807
 808                         kprintf("  IPEIR: 0x%08x\n",
 809                                I915_READ(IPEIR_I965));
 810                         kprintf("  IPEHR: 0x%08x\n",
 811                                I915_READ(IPEHR_I965));
 812                         kprintf("  INSTDONE: 0x%08x\n",
 813                                I915_READ(INSTDONE_I965));
 814                         kprintf("  INSTPS: 0x%08x\n",
 815                                I915_READ(INSTPS));
 816                         kprintf("  INSTDONE1: 0x%08x\n",
 817                                I915_READ(INSTDONE1));
 818                         kprintf("  ACTHD: 0x%08x\n",
 819                                I915_READ(ACTHD_I965));
 820                         I915_WRITE(IPEIR_I965, ipeir);
 821                         POSTING_READ(IPEIR_I965);
 822                 }
 823         }
 824
 825         I915_WRITE(EIR, eir);
 826         POSTING_READ(EIR);
 827         eir = I915_READ(EIR);
 828         if (eir) {
 829                 /*
 830                  * some errors might have become stuck,
 831                  * mask them.
 832                  */
 833                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 834                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 835                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 836         }
 837 }
 838
 839 /**
 840  * i915_handle_error - handle an error interrupt
 841  * @dev: drm device
 842  *
 843  * Do some basic checking of regsiter state at error interrupt time and
 844  * dump it to the syslog.  Also call i915_capture_error_state() to make
 845  * sure we get a record and make it available in debugfs.  Fire a uevent
 846  * so userspace knows something bad happened (should trigger collection
 847  * of a ring dump etc.).
 848  */
 849 void i915_handle_error(struct drm_device *dev, bool wedged)
 850 {
 851         struct drm_i915_private *dev_priv = dev->dev_private;
 852
 853         i915_capture_error_state(dev);
 854         i915_report_and_clear_eir(dev);
 855
 856         if (wedged) {
 857                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 858                 dev_priv->error_completion = 0;
 859                 dev_priv->mm.wedged = 1;
 860                 /* unlock acts as rel barrier for store to wedged */
 861                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 862
 863                 /*
 864                  * Wakeup waiting processes so they don't hang
 865                  */
 866                 lockmgr(&dev_priv->rings[RCS].irq_lock, LK_EXCLUSIVE);
 867                 wakeup(&dev_priv->rings[RCS]);
 868                 lockmgr(&dev_priv->rings[RCS].irq_lock, LK_RELEASE);
 869                 if (HAS_BSD(dev)) {
 870                         lockmgr(&dev_priv->rings[VCS].irq_lock, LK_EXCLUSIVE);
 871                         wakeup(&dev_priv->rings[VCS]);
 872                         lockmgr(&dev_priv->rings[VCS].irq_lock, LK_RELEASE);
 873                 }
 874                 if (HAS_BLT(dev)) {
 875                         lockmgr(&dev_priv->rings[BCS].irq_lock, LK_EXCLUSIVE);
 876                         wakeup(&dev_priv->rings[BCS]);
 877                         lockmgr(&dev_priv->rings[BCS].irq_lock, LK_RELEASE);
 878                 }
 879         }
 880
 881         taskqueue_enqueue(dev_priv->tq, &dev_priv->error_task);
 882 }
 883
 884 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 885 {
 886         drm_i915_private_t *dev_priv = dev->dev_private;
 887         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 889         struct drm_i915_gem_object *obj;
 890         struct intel_unpin_work *work;
 891         bool stall_detected;
 892
 893         /* Ignore early vblank irqs */
 894         if (intel_crtc == NULL)
 895                 return;
 896
 897         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 898         work = intel_crtc->unpin_work;
 899
 900         if (work == NULL || work->pending || !work->enable_stall_check) {
 901                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 902                 lockmgr(&dev->event_lock, LK_RELEASE);
 903                 return;
 904         }
 905
 906         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 907         obj = work->pending_flip_obj;
 908         if (INTEL_INFO(dev)->gen >= 4) {
 909                 int dspsurf = DSPSURF(intel_crtc->plane);
 910                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
 911         } else {
 912                 int dspaddr = DSPADDR(intel_crtc->plane);
 913                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
 914                                                         crtc->y * crtc->fb->pitches[0] +
 915                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 916         }
 917
 918         lockmgr(&dev->event_lock, LK_RELEASE);
 919
 920         if (stall_detected) {
 921                 DRM_DEBUG("Pageflip stall detected\n");
 922                 intel_prepare_page_flip(dev, intel_crtc->plane);
 923         }
 924 }
 925
 926 static void
 927 i915_driver_irq_handler(void *arg)
 928 {
 929         struct drm_device *dev = (struct drm_device *)arg;
 930         drm_i915_private_t *dev_priv = (drm_i915_private_t *)dev->dev_private;
 931 #if 0
 932         struct drm_i915_master_private *master_priv;
 933 #endif
 934         u32 iir, new_iir;
 935         u32 pipe_stats[I915_MAX_PIPES];
 936         u32 vblank_status;
 937         int vblank = 0;
 938         int irq_received;
 939         int pipe;
 940         bool blc_event = false;
 941
 942         atomic_inc(&dev_priv->irq_received);
 943
 944         iir = I915_READ(IIR);
 945
 946         if (INTEL_INFO(dev)->gen >= 4)
 947                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 948         else
 949                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 950
 951         for (;;) {
 952                 irq_received = iir != 0;
 953
 954                 /* Can't rely on pipestat interrupt bit in iir as it might
 955                  * have been cleared after the pipestat interrupt was received.
 956                  * It doesn't set the bit in iir again, but it still produces
 957                  * interrupts (for non-MSI).
 958                  */
 959                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 960                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 961                         i915_handle_error(dev, false);
 962
 963                 for_each_pipe(pipe) {
 964                         int reg = PIPESTAT(pipe);
 965                         pipe_stats[pipe] = I915_READ(reg);
 966
 967                         /*
 968                          * Clear the PIPE*STAT regs before the IIR
 969                          */
 970                         if (pipe_stats[pipe] & 0x8000ffff) {
 971                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 972                                         DRM_DEBUG("pipe %c underrun\n",
 973                                                          pipe_name(pipe));
 974                                 I915_WRITE(reg, pipe_stats[pipe]);
 975                                 irq_received = 1;
 976                         }
 977                 }
 978                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 979
 980                 if (!irq_received)
 981                         break;
 982
 983                 /* Consume port.  Then clear IIR or we'll miss events */
 984                 if ((I915_HAS_HOTPLUG(dev)) &&
 985                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 986                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 987
 988                         DRM_DEBUG("i915: hotplug event received, stat 0x%08x\n",
 989                                   hotplug_status);
 990                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 991                                 taskqueue_enqueue(dev_priv->tq,
 992                                     &dev_priv->hotplug_task);
 993
 994                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 995                         I915_READ(PORT_HOTPLUG_STAT);
 996                 }
 997
 998                 I915_WRITE(IIR, iir);
 999                 new_iir = I915_READ(IIR); /* Flush posted writes */
1000
1001 #if 0
1002                 if (dev->primary->master) {
1003                         master_priv = dev->primary->master->driver_priv;
1004                         if (master_priv->sarea_priv)
1005                                 master_priv->sarea_priv->last_dispatch =
1006                                         READ_BREADCRUMB(dev_priv);
1007                 }
1008 #else
1009                 if (dev_priv->sarea_priv)
1010                         dev_priv->sarea_priv->last_dispatch =
1011                             READ_BREADCRUMB(dev_priv);
1012 #endif
1013
1014                 if (iir & I915_USER_INTERRUPT)
1015                         notify_ring(dev, &dev_priv->rings[RCS]);
1016                 if (iir & I915_BSD_USER_INTERRUPT)
1017                         notify_ring(dev, &dev_priv->rings[VCS]);
1018
1019                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1020                         intel_prepare_page_flip(dev, 0);
1021                         if (dev_priv->flip_pending_is_done)
1022                                 intel_finish_page_flip_plane(dev, 0);
1023                 }
1024
1025                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1026                         intel_prepare_page_flip(dev, 1);
1027                         if (dev_priv->flip_pending_is_done)
1028                                 intel_finish_page_flip_plane(dev, 1);
1029                 }
1030
1031                 for_each_pipe(pipe) {
1032                         if (pipe_stats[pipe] & vblank_status &&
1033                             drm_handle_vblank(dev, pipe)) {
1034                                 vblank++;
1035                                 if (!dev_priv->flip_pending_is_done) {
1036                                         i915_pageflip_stall_check(dev, pipe);
1037                                         intel_finish_page_flip(dev, pipe);
1038                                 }
1039                         }
1040
1041                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1042                                 blc_event = true;
1043                 }
1044
1045
1046                 if (blc_event || (iir & I915_ASLE_INTERRUPT)) {
1047 #if 1
1048                         KIB_NOTYET();
1049 #else
1050                         intel_opregion_asle_intr(dev);
1051 #endif
1052                 }
1053
1054                 /* With MSI, interrupts are only generated when iir
1055                  * transitions from zero to nonzero.  If another bit got
1056                  * set while we were handling the existing iir bits, then
1057                  * we would never get another interrupt.
1058                  *
1059                  * This is fine on non-MSI as well, as if we hit this path
1060                  * we avoid exiting the interrupt handler only to generate
1061                  * another one.
1062                  *
1063                  * Note that for MSI this could cause a stray interrupt report
1064                  * if an interrupt landed in the time between writing IIR and
1065                  * the posting read.  This should be rare enough to never
1066                  * trigger the 99% of 100,000 interrupts test for disabling
1067                  * stray interrupts.
1068                  */
1069                 iir = new_iir;
1070         }
1071 }
1072
1073 static int i915_emit_irq(struct drm_device * dev)
1074 {
1075         drm_i915_private_t *dev_priv = dev->dev_private;
1076 #if 0
1077         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1078 #endif
1079
1080         i915_kernel_lost_context(dev);
1081
1082         DRM_DEBUG("i915: emit_irq\n");
1083
1084         dev_priv->counter++;
1085         if (dev_priv->counter > 0x7FFFFFFFUL)
1086                 dev_priv->counter = 1;
1087 #if 0
1088         if (master_priv->sarea_priv)
1089                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1090 #else
1091         if (dev_priv->sarea_priv)
1092                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
1093 #endif
1094
1095         if (BEGIN_LP_RING(4) == 0) {
1096                 OUT_RING(MI_STORE_DWORD_INDEX);
1097                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1098                 OUT_RING(dev_priv->counter);
1099                 OUT_RING(MI_USER_INTERRUPT);
1100                 ADVANCE_LP_RING();
1101         }
1102
1103         return dev_priv->counter;
1104 }
1105
1106 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1107 {
1108         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1109 #if 0
1110         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1111 #endif
1112         int ret;
1113         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1114
1115         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
1116                   READ_BREADCRUMB(dev_priv));
1117
1118 #if 0
1119         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1120                 if (master_priv->sarea_priv)
1121                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1122                 return 0;
1123         }
1124
1125         if (master_priv->sarea_priv)
1126                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1127 #else
1128         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1129                 if (dev_priv->sarea_priv) {
1130                         dev_priv->sarea_priv->last_dispatch =
1131                                 READ_BREADCRUMB(dev_priv);
1132                 }
1133                 return 0;
1134         }
1135
1136         if (dev_priv->sarea_priv)
1137                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1138 #endif
1139
1140         ret = 0;
1141         lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
1142         if (ring->irq_get(ring)) {
1143                 DRM_UNLOCK(dev);
1144                 while (ret == 0 && READ_BREADCRUMB(dev_priv) < irq_nr) {
1145                         ret = -lksleep(ring, &ring->irq_lock, PCATCH,
1146                             "915wtq", 3 * hz);
1147                 }
1148                 ring->irq_put(ring);
1149                 lockmgr(&ring->irq_lock, LK_RELEASE);
1150                 DRM_LOCK(dev);
1151         } else {
1152                 lockmgr(&ring->irq_lock, LK_RELEASE);
1153                 if (_intel_wait_for(dev, READ_BREADCRUMB(dev_priv) >= irq_nr,
1154                      3000, 1, "915wir"))
1155                         ret = -EBUSY;
1156         }
1157
1158         if (ret == -EBUSY) {
1159                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1160                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1161         }
1162
1163         return ret;
1164 }
1165
1166 /* Needs the lock as it touches the ring.
1167  */
1168 int i915_irq_emit(struct drm_device *dev, void *data,
1169                          struct drm_file *file_priv)
1170 {
1171         drm_i915_private_t *dev_priv = dev->dev_private;
1172         drm_i915_irq_emit_t *emit = data;
1173         int result;
1174
1175         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1176                 DRM_ERROR("called with no initialization\n");
1177                 return -EINVAL;
1178         }
1179
1180         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1181
1182         DRM_LOCK(dev);
1183         result = i915_emit_irq(dev);
1184         DRM_UNLOCK(dev);
1185
1186         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1187                 DRM_ERROR("copy_to_user\n");
1188                 return -EFAULT;
1189         }
1190
1191         return 0;
1192 }
1193
1194 /* Doesn't need the hardware lock.
1195  */
1196 int i915_irq_wait(struct drm_device *dev, void *data,
1197                          struct drm_file *file_priv)
1198 {
1199         drm_i915_private_t *dev_priv = dev->dev_private;
1200         drm_i915_irq_wait_t *irqwait = data;
1201
1202         if (!dev_priv) {
1203                 DRM_ERROR("called with no initialization\n");
1204                 return -EINVAL;
1205         }
1206
1207         return i915_wait_irq(dev, irqwait->irq_seq);
1208 }
1209
1210 /* Called from drm generic code, passed 'crtc' which
1211  * we use as a pipe index
1212  */
1213 static int
1214 i915_enable_vblank(struct drm_device *dev, int pipe)
1215 {
1216         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1217
1218         if (!i915_pipe_enabled(dev, pipe))
1219                 return -EINVAL;
1220
1221         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1222         if (INTEL_INFO(dev)->gen >= 4)
1223                 i915_enable_pipestat(dev_priv, pipe,
1224                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1225         else
1226                 i915_enable_pipestat(dev_priv, pipe,
1227                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1228
1229         /* maintain vblank delivery even in deep C-states */
1230         if (dev_priv->info->gen == 3)
1231                 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1232         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1233
1234         return 0;
1235 }
1236
1237 static int
1238 ironlake_enable_vblank(struct drm_device *dev, int pipe)
1239 {
1240         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1241
1242         if (!i915_pipe_enabled(dev, pipe))
1243                 return -EINVAL;
1244
1245         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1246         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1247             DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1248         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1249
1250         return 0;
1251 }
1252
1253 static int
1254 ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1255 {
1256         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1257
1258         if (!i915_pipe_enabled(dev, pipe))
1259                 return -EINVAL;
1260
1261         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1262         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1263                                     DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1264         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1265
1266         return 0;
1267 }
1268
1269
1270 /* Called from drm generic code, passed 'crtc' which
1271  * we use as a pipe index
1272  */
1273 static void
1274 i915_disable_vblank(struct drm_device *dev, int pipe)
1275 {
1276         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1277
1278         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1279         if (dev_priv->info->gen == 3)
1280                 I915_WRITE(INSTPM,
1281                            INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1282
1283         i915_disable_pipestat(dev_priv, pipe,
1284             PIPE_VBLANK_INTERRUPT_ENABLE |
1285             PIPE_START_VBLANK_INTERRUPT_ENABLE);
1286         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1287 }
1288
1289 static void
1290 ironlake_disable_vblank(struct drm_device *dev, int pipe)
1291 {
1292         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1293
1294         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1295         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1296             DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1297         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1298 }
1299
1300 static void
1301 ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1302 {
1303         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1304
1305         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1306         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1307                                      DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1308         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1309 }
1310
1311 /* Set the vblank monitor pipe
1312  */
1313 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1314                          struct drm_file *file_priv)
1315 {
1316         drm_i915_private_t *dev_priv = dev->dev_private;
1317
1318         if (!dev_priv) {
1319                 DRM_ERROR("called with no initialization\n");
1320                 return -EINVAL;
1321         }
1322
1323         return 0;
1324 }
1325
1326 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1327                          struct drm_file *file_priv)
1328 {
1329         drm_i915_private_t *dev_priv = dev->dev_private;
1330         drm_i915_vblank_pipe_t *pipe = data;
1331
1332         if (!dev_priv) {
1333                 DRM_ERROR("called with no initialization\n");
1334                 return -EINVAL;
1335         }
1336
1337         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1338
1339         return 0;
1340 }
1341
1342 /**
1343  * Schedule buffer swap at given vertical blank.
1344  */
1345 int i915_vblank_swap(struct drm_device *dev, void *data,
1346                      struct drm_file *file_priv)
1347 {
1348         /* The delayed swap mechanism was fundamentally racy, and has been
1349          * removed.  The model was that the client requested a delayed flip/swap
1350          * from the kernel, then waited for vblank before continuing to perform
1351          * rendering.  The problem was that the kernel might wake the client
1352          * up before it dispatched the vblank swap (since the lock has to be
1353          * held while touching the ringbuffer), in which case the client would
1354          * clear and start the next frame before the swap occurred, and
1355          * flicker would occur in addition to likely missing the vblank.
1356          *
1357          * In the absence of this ioctl, userland falls back to a correct path
1358          * of waiting for a vblank, then dispatching the swap on its own.
1359          * Context switching to userland and back is plenty fast enough for
1360          * meeting the requirements of vblank swapping.
1361          */
1362         return -EINVAL;
1363 }
1364
1365 static u32
1366 ring_last_seqno(struct intel_ring_buffer *ring)
1367 {
1368
1369         if (list_empty(&ring->request_list))
1370                 return (0);
1371         else
1372                 return (list_entry(ring->request_list.prev,
1373                     struct drm_i915_gem_request, list)->seqno);
1374 }
1375
1376 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1377 {
1378         if (list_empty(&ring->request_list) ||
1379             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1380                 /* Issue a wake-up to catch stuck h/w. */
1381                 if (ring->waiting_seqno) {
1382                         DRM_ERROR(
1383 "Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1384                                   ring->name,
1385                                   ring->waiting_seqno,
1386                                   ring->get_seqno(ring));
1387                         wakeup(ring);
1388                         *err = true;
1389                 }
1390                 return true;
1391         }
1392         return false;
1393 }
1394
1395 static bool kick_ring(struct intel_ring_buffer *ring)
1396 {
1397         struct drm_device *dev = ring->dev;
1398         struct drm_i915_private *dev_priv = dev->dev_private;
1399         u32 tmp = I915_READ_CTL(ring);
1400         if (tmp & RING_WAIT) {
1401                 DRM_ERROR("Kicking stuck wait on %s\n",
1402                           ring->name);
1403                 I915_WRITE_CTL(ring, tmp);
1404                 return true;
1405         }
1406         return false;
1407 }
1408
1409 /**
1410  * This is called when the chip hasn't reported back with completed
1411  * batchbuffers in a long time. The first time this is called we simply record
1412  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1413  * again, we assume the chip is wedged and try to fix it.
1414  */
1415 void
1416 i915_hangcheck_elapsed(void *context)
1417 {
1418         struct drm_device *dev = (struct drm_device *)context;
1419         drm_i915_private_t *dev_priv = dev->dev_private;
1420         uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
1421         bool err = false;
1422
1423         if (!i915_enable_hangcheck)
1424                 return;
1425
1426         /* If all work is done then ACTHD clearly hasn't advanced. */
1427         if (i915_hangcheck_ring_idle(&dev_priv->rings[RCS], &err) &&
1428             i915_hangcheck_ring_idle(&dev_priv->rings[VCS], &err) &&
1429             i915_hangcheck_ring_idle(&dev_priv->rings[BCS], &err)) {
1430                 dev_priv->hangcheck_count = 0;
1431                 if (err)
1432                         goto repeat;
1433                 return;
1434         }
1435
1436         if (INTEL_INFO(dev)->gen < 4) {
1437                 instdone = I915_READ(INSTDONE);
1438                 instdone1 = 0;
1439         } else {
1440                 instdone = I915_READ(INSTDONE_I965);
1441                 instdone1 = I915_READ(INSTDONE1);
1442         }
1443         acthd = intel_ring_get_active_head(&dev_priv->rings[RCS]);
1444         acthd_bsd = HAS_BSD(dev) ?
1445                 intel_ring_get_active_head(&dev_priv->rings[VCS]) : 0;
1446         acthd_blt = HAS_BLT(dev) ?
1447                 intel_ring_get_active_head(&dev_priv->rings[BCS]) : 0;
1448
1449         if (dev_priv->last_acthd == acthd &&
1450             dev_priv->last_acthd_bsd == acthd_bsd &&
1451             dev_priv->last_acthd_blt == acthd_blt &&
1452             dev_priv->last_instdone == instdone &&
1453             dev_priv->last_instdone1 == instdone1) {
1454                 if (dev_priv->hangcheck_count++ > 1) {
1455                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1456                         i915_handle_error(dev, true);
1457
1458                         if (!IS_GEN2(dev)) {
1459                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1460                                  * If so we can simply poke the RB_WAIT bit
1461                                  * and break the hang. This should work on
1462                                  * all but the second generation chipsets.
1463                                  */
1464                                 if (kick_ring(&dev_priv->rings[RCS]))
1465                                         goto repeat;
1466
1467                                 if (HAS_BSD(dev) &&
1468                                     kick_ring(&dev_priv->rings[VCS]))
1469                                         goto repeat;
1470
1471                                 if (HAS_BLT(dev) &&
1472                                     kick_ring(&dev_priv->rings[BCS]))
1473                                         goto repeat;
1474                         }
1475
1476                         return;
1477                 }
1478         } else {
1479                 dev_priv->hangcheck_count = 0;
1480
1481                 dev_priv->last_acthd = acthd;
1482                 dev_priv->last_acthd_bsd = acthd_bsd;
1483                 dev_priv->last_acthd_blt = acthd_blt;
1484                 dev_priv->last_instdone = instdone;
1485                 dev_priv->last_instdone1 = instdone1;
1486         }
1487
1488 repeat:
1489         /* Reset timer case chip hangs without another request being added */
1490         callout_reset(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD,
1491             i915_hangcheck_elapsed, dev);
1492 }
1493
1494 /* drm_dma.h hooks
1495 */
1496 static void
1497 ironlake_irq_preinstall(struct drm_device *dev)
1498 {
1499         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1500
1501         atomic_set(&dev_priv->irq_received, 0);
1502
1503         TASK_INIT(&dev_priv->hotplug_task, 0, i915_hotplug_work_func,
1504             dev->dev_private);
1505         TASK_INIT(&dev_priv->error_task, 0, i915_error_work_func,
1506             dev->dev_private);
1507         TASK_INIT(&dev_priv->rps_task, 0, gen6_pm_rps_work_func,
1508             dev->dev_private);
1509
1510         I915_WRITE(HWSTAM, 0xeffe);
1511
1512         /* XXX hotplug from PCH */
1513
1514         I915_WRITE(DEIMR, 0xffffffff);
1515         I915_WRITE(DEIER, 0x0);
1516         POSTING_READ(DEIER);
1517
1518         /* and GT */
1519         I915_WRITE(GTIMR, 0xffffffff);
1520         I915_WRITE(GTIER, 0x0);
1521         POSTING_READ(GTIER);
1522
1523         /* south display irq */
1524         I915_WRITE(SDEIMR, 0xffffffff);
1525         I915_WRITE(SDEIER, 0x0);
1526         POSTING_READ(SDEIER);
1527 }
1528
1529 /*
1530  * Enable digital hotplug on the PCH, and configure the DP short pulse
1531  * duration to 2ms (which is the minimum in the Display Port spec)
1532  *
1533  * This register is the same on all known PCH chips.
1534  */
1535
1536 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1537 {
1538         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1539         u32     hotplug;
1540
1541         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1542         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1543         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1544         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1545         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1546         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1547 }
1548
1549 static int ironlake_irq_postinstall(struct drm_device *dev)
1550 {
1551         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1552         /* enable kind of interrupts always enabled */
1553         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1554                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1555         u32 render_irqs;
1556         u32 hotplug_mask;
1557
1558         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1559         dev_priv->irq_mask = ~display_mask;
1560
1561         /* should always can generate irq */
1562         I915_WRITE(DEIIR, I915_READ(DEIIR));
1563         I915_WRITE(DEIMR, dev_priv->irq_mask);
1564         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1565         POSTING_READ(DEIER);
1566
1567         dev_priv->gt_irq_mask = ~0;
1568
1569         I915_WRITE(GTIIR, I915_READ(GTIIR));
1570         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1571
1572         if (IS_GEN6(dev))
1573                 render_irqs =
1574                         GT_USER_INTERRUPT |
1575                         GT_GEN6_BSD_USER_INTERRUPT |
1576                         GT_BLT_USER_INTERRUPT;
1577         else
1578                 render_irqs =
1579                         GT_USER_INTERRUPT |
1580                         GT_PIPE_NOTIFY |
1581                         GT_BSD_USER_INTERRUPT;
1582         I915_WRITE(GTIER, render_irqs);
1583         POSTING_READ(GTIER);
1584
1585         if (HAS_PCH_CPT(dev)) {
1586                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1587                                 SDE_PORTB_HOTPLUG_CPT |
1588                                 SDE_PORTC_HOTPLUG_CPT |
1589                                 SDE_PORTD_HOTPLUG_CPT);
1590         } else {
1591                 hotplug_mask = (SDE_CRT_HOTPLUG |
1592                                 SDE_PORTB_HOTPLUG |
1593                                 SDE_PORTC_HOTPLUG |
1594                                 SDE_PORTD_HOTPLUG |
1595                                 SDE_AUX_MASK);
1596         }
1597
1598         dev_priv->pch_irq_mask = ~hotplug_mask;
1599
1600         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1601         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1602         I915_WRITE(SDEIER, hotplug_mask);
1603         POSTING_READ(SDEIER);
1604
1605         ironlake_enable_pch_hotplug(dev);
1606
1607         if (IS_IRONLAKE_M(dev)) {
1608                 /* Clear & enable PCU event interrupts */
1609                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1610                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1611                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1612         }
1613
1614         return 0;
1615 }
1616
1617 static int
1618 ivybridge_irq_postinstall(struct drm_device *dev)
1619 {
1620         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1621         /* enable kind of interrupts always enabled */
1622         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1623                 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1624                 DE_PLANEB_FLIP_DONE_IVB;
1625         u32 render_irqs;
1626         u32 hotplug_mask;
1627
1628         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1629         dev_priv->irq_mask = ~display_mask;
1630
1631         /* should always can generate irq */
1632         I915_WRITE(DEIIR, I915_READ(DEIIR));
1633         I915_WRITE(DEIMR, dev_priv->irq_mask);
1634         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1635                    DE_PIPEB_VBLANK_IVB);
1636         POSTING_READ(DEIER);
1637
1638         dev_priv->gt_irq_mask = ~0;
1639
1640         I915_WRITE(GTIIR, I915_READ(GTIIR));
1641         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1642
1643         render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1644                 GT_BLT_USER_INTERRUPT;
1645         I915_WRITE(GTIER, render_irqs);
1646         POSTING_READ(GTIER);
1647
1648         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1649                         SDE_PORTB_HOTPLUG_CPT |
1650                         SDE_PORTC_HOTPLUG_CPT |
1651                         SDE_PORTD_HOTPLUG_CPT);
1652         dev_priv->pch_irq_mask = ~hotplug_mask;
1653
1654         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1655         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1656         I915_WRITE(SDEIER, hotplug_mask);
1657         POSTING_READ(SDEIER);
1658
1659         ironlake_enable_pch_hotplug(dev);
1660
1661         return 0;
1662 }
1663
1664 static void
1665 i915_driver_irq_preinstall(struct drm_device * dev)
1666 {
1667         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1668         int pipe;
1669
1670         atomic_set(&dev_priv->irq_received, 0);
1671
1672         TASK_INIT(&dev_priv->hotplug_task, 0, i915_hotplug_work_func,
1673             dev->dev_private);
1674         TASK_INIT(&dev_priv->error_task, 0, i915_error_work_func,
1675             dev->dev_private);
1676         TASK_INIT(&dev_priv->rps_task, 0, gen6_pm_rps_work_func,
1677             dev->dev_private);
1678
1679         if (I915_HAS_HOTPLUG(dev)) {
1680                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1681                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1682         }
1683
1684         I915_WRITE(HWSTAM, 0xeffe);
1685         for_each_pipe(pipe)
1686                 I915_WRITE(PIPESTAT(pipe), 0);
1687         I915_WRITE(IMR, 0xffffffff);
1688         I915_WRITE(IER, 0x0);
1689         POSTING_READ(IER);
1690 }
1691
1692 /*
1693  * Must be called after intel_modeset_init or hotplug interrupts won't be
1694  * enabled correctly.
1695  */
1696 static int
1697 i915_driver_irq_postinstall(struct drm_device *dev)
1698 {
1699         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1700         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1701         u32 error_mask;
1702
1703         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1704
1705         /* Unmask the interrupts that we always want on. */
1706         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1707
1708         dev_priv->pipestat[0] = 0;
1709         dev_priv->pipestat[1] = 0;
1710
1711         if (I915_HAS_HOTPLUG(dev)) {
1712                 /* Enable in IER... */
1713                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1714                 /* and unmask in IMR */
1715                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1716         }
1717
1718         /*
1719          * Enable some error detection, note the instruction error mask
1720          * bit is reserved, so we leave it masked.
1721          */
1722         if (IS_G4X(dev)) {
1723                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1724                                GM45_ERROR_MEM_PRIV |
1725                                GM45_ERROR_CP_PRIV |
1726                                I915_ERROR_MEMORY_REFRESH);
1727         } else {
1728                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1729                                I915_ERROR_MEMORY_REFRESH);
1730         }
1731         I915_WRITE(EMR, error_mask);
1732
1733         I915_WRITE(IMR, dev_priv->irq_mask);
1734         I915_WRITE(IER, enable_mask);
1735         POSTING_READ(IER);
1736
1737         if (I915_HAS_HOTPLUG(dev)) {
1738                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1739
1740                 /* Note HDMI and DP share bits */
1741                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1742                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1743                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1744                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1745                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1746                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1747                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1748                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1749                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1750                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1751                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1752                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1753
1754                         /* Programming the CRT detection parameters tends
1755                            to generate a spurious hotplug event about three
1756                            seconds later.  So just do it once.
1757                         */
1758                         if (IS_G4X(dev))
1759                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1760                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1761                 }
1762
1763                 /* Ignore TV since it's buggy */
1764
1765                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1766         }
1767
1768 #if 1
1769         KIB_NOTYET();
1770 #else
1771         intel_opregion_enable_asle(dev);
1772 #endif
1773
1774         return 0;
1775 }
1776
1777 static void
1778 ironlake_irq_uninstall(struct drm_device *dev)
1779 {
1780         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1781
1782         if (dev_priv == NULL)
1783                 return;
1784
1785         dev_priv->vblank_pipe = 0;
1786
1787         I915_WRITE(HWSTAM, 0xffffffff);
1788
1789         I915_WRITE(DEIMR, 0xffffffff);
1790         I915_WRITE(DEIER, 0x0);
1791         I915_WRITE(DEIIR, I915_READ(DEIIR));
1792
1793         I915_WRITE(GTIMR, 0xffffffff);
1794         I915_WRITE(GTIER, 0x0);
1795         I915_WRITE(GTIIR, I915_READ(GTIIR));
1796
1797         I915_WRITE(SDEIMR, 0xffffffff);
1798         I915_WRITE(SDEIER, 0x0);
1799         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1800
1801         taskqueue_drain(dev_priv->tq, &dev_priv->hotplug_task);
1802         taskqueue_drain(dev_priv->tq, &dev_priv->error_task);
1803         taskqueue_drain(dev_priv->tq, &dev_priv->rps_task);
1804 }
1805
1806 static void i915_driver_irq_uninstall(struct drm_device * dev)
1807 {
1808         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1809         int pipe;
1810
1811         if (!dev_priv)
1812                 return;
1813
1814         dev_priv->vblank_pipe = 0;
1815
1816         if (I915_HAS_HOTPLUG(dev)) {
1817                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1818                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1819         }
1820
1821         I915_WRITE(HWSTAM, 0xffffffff);
1822         for_each_pipe(pipe)
1823                 I915_WRITE(PIPESTAT(pipe), 0);
1824         I915_WRITE(IMR, 0xffffffff);
1825         I915_WRITE(IER, 0x0);
1826
1827         for_each_pipe(pipe)
1828                 I915_WRITE(PIPESTAT(pipe),
1829                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
1830         I915_WRITE(IIR, I915_READ(IIR));
1831
1832         taskqueue_drain(dev_priv->tq, &dev_priv->hotplug_task);
1833         taskqueue_drain(dev_priv->tq, &dev_priv->error_task);
1834         taskqueue_drain(dev_priv->tq, &dev_priv->rps_task);
1835 }
1836
1837 void
1838 intel_irq_init(struct drm_device *dev)
1839 {
1840
1841         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1842         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1843         if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
1844                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1845                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1846         }
1847
1848         if (drm_core_check_feature(dev, DRIVER_MODESET))
1849                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
1850         else
1851                 dev->driver->get_vblank_timestamp = NULL;
1852         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
1853
1854         if (IS_IVYBRIDGE(dev)) {
1855                 /* Share pre & uninstall handlers with ILK/SNB */
1856                 dev->driver->irq_handler = ivybridge_irq_handler;
1857                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1858                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
1859                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1860                 dev->driver->enable_vblank = ivybridge_enable_vblank;
1861                 dev->driver->disable_vblank = ivybridge_disable_vblank;
1862         } else if (HAS_PCH_SPLIT(dev)) {
1863                 dev->driver->irq_handler = ironlake_irq_handler;
1864                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1865                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
1866                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1867                 dev->driver->enable_vblank = ironlake_enable_vblank;
1868                 dev->driver->disable_vblank = ironlake_disable_vblank;
1869         } else {
1870                 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
1871                 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
1872                 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
1873                 dev->driver->irq_handler = i915_driver_irq_handler;
1874                 dev->driver->enable_vblank = i915_enable_vblank;
1875                 dev->driver->disable_vblank = i915_disable_vblank;
1876         }
1877 }
1878
1879 static struct drm_i915_error_object *
1880 i915_error_object_create(struct drm_i915_private *dev_priv,
1881     struct drm_i915_gem_object *src)
1882 {
1883         struct drm_i915_error_object *dst;
1884         struct sf_buf *sf;
1885         void *d, *s;
1886         int page, page_count;
1887         u32 reloc_offset;
1888
1889         if (src == NULL || src->pages == NULL)
1890                 return NULL;
1891
1892         page_count = src->base.size / PAGE_SIZE;
1893
1894         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), DRM_I915_GEM,
1895             M_NOWAIT);
1896         if (dst == NULL)
1897                 return (NULL);
1898
1899         reloc_offset = src->gtt_offset;
1900         for (page = 0; page < page_count; page++) {
1901                 d = kmalloc(PAGE_SIZE, DRM_I915_GEM, M_NOWAIT);
1902                 if (d == NULL)
1903                         goto unwind;
1904
1905                 if (reloc_offset < dev_priv->mm.gtt_mappable_end) {
1906                         /* Simply ignore tiling or any overlapping fence.
1907                          * It's part of the error state, and this hopefully
1908                          * captures what the GPU read.
1909                          */
1910                         s = pmap_mapdev_attr(src->base.dev->agp->base +
1911                             reloc_offset, PAGE_SIZE, PAT_WRITE_COMBINING);
1912                         memcpy(d, s, PAGE_SIZE);
1913                         pmap_unmapdev((vm_offset_t)s, PAGE_SIZE);
1914                 } else {
1915                         drm_clflush_pages(&src->pages[page], 1);
1916
1917                         sf = sf_buf_alloc(src->pages[page]);
1918                         if (sf != NULL) {
1919                                 s = (void *)(uintptr_t)sf_buf_kva(sf);
1920                                 memcpy(d, s, PAGE_SIZE);
1921                                 sf_buf_free(sf);
1922                         } else {
1923                                 bzero(d, PAGE_SIZE);
1924                                 strcpy(d, "XXXKIB");
1925                         }
1926
1927                         drm_clflush_pages(&src->pages[page], 1);
1928                 }
1929
1930                 dst->pages[page] = d;
1931
1932                 reloc_offset += PAGE_SIZE;
1933         }
1934         dst->page_count = page_count;
1935         dst->gtt_offset = src->gtt_offset;
1936
1937         return (dst);
1938
1939 unwind:
1940         while (page--)
1941                 drm_free(dst->pages[page], DRM_I915_GEM);
1942         drm_free(dst, DRM_I915_GEM);
1943         return (NULL);
1944 }
1945
1946 static void
1947 i915_error_object_free(struct drm_i915_error_object *obj)
1948 {
1949         int page;
1950
1951         if (obj == NULL)
1952                 return;
1953
1954         for (page = 0; page < obj->page_count; page++)
1955                 drm_free(obj->pages[page], DRM_I915_GEM);
1956
1957         drm_free(obj, DRM_I915_GEM);
1958 }
1959
1960 static void
1961 i915_error_state_free(struct drm_device *dev,
1962                       struct drm_i915_error_state *error)
1963 {
1964         int i;
1965
1966         for (i = 0; i < DRM_ARRAY_SIZE(error->ring); i++) {
1967                 i915_error_object_free(error->ring[i].batchbuffer);
1968                 i915_error_object_free(error->ring[i].ringbuffer);
1969                 drm_free(error->ring[i].requests, DRM_I915_GEM);
1970         }
1971
1972         drm_free(error->active_bo, DRM_I915_GEM);
1973         drm_free(error->overlay, DRM_I915_GEM);
1974         drm_free(error, DRM_I915_GEM);
1975 }
1976
1977 static u32
1978 capture_bo_list(struct drm_i915_error_buffer *err, int count,
1979     struct list_head *head)
1980 {
1981         struct drm_i915_gem_object *obj;
1982         int i = 0;
1983
1984         list_for_each_entry(obj, head, mm_list) {
1985                 err->size = obj->base.size;
1986                 err->name = obj->base.name;
1987                 err->seqno = obj->last_rendering_seqno;
1988                 err->gtt_offset = obj->gtt_offset;
1989                 err->read_domains = obj->base.read_domains;
1990                 err->write_domain = obj->base.write_domain;
1991                 err->fence_reg = obj->fence_reg;
1992                 err->pinned = 0;
1993                 if (obj->pin_count > 0)
1994                         err->pinned = 1;
1995                 if (obj->user_pin_count > 0)
1996                         err->pinned = -1;
1997                 err->tiling = obj->tiling_mode;
1998                 err->dirty = obj->dirty;
1999                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
2000                 err->ring = obj->ring ? obj->ring->id : -1;
2001                 err->cache_level = obj->cache_level;
2002
2003                 if (++i == count)
2004                         break;
2005
2006                 err++;
2007         }
2008
2009         return (i);
2010 }
2011
2012 static void
2013 i915_gem_record_fences(struct drm_device *dev,
2014     struct drm_i915_error_state *error)
2015 {
2016         struct drm_i915_private *dev_priv = dev->dev_private;
2017         int i;
2018
2019         /* Fences */
2020         switch (INTEL_INFO(dev)->gen) {
2021         case 7:
2022         case 6:
2023                 for (i = 0; i < 16; i++)
2024                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
2025                 break;
2026         case 5:
2027         case 4:
2028                 for (i = 0; i < 16; i++)
2029                         error->fence[i] = I915_READ64(FENCE_REG_965_0 +
2030                             (i * 8));
2031                 break;
2032         case 3:
2033                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2034                         for (i = 0; i < 8; i++)
2035                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
2036                                     (i * 4));
2037         case 2:
2038                 for (i = 0; i < 8; i++)
2039                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
2040                 break;
2041
2042         }
2043 }
2044
2045 static struct drm_i915_error_object *
2046 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
2047                              struct intel_ring_buffer *ring)
2048 {
2049         struct drm_i915_gem_object *obj;
2050         u32 seqno;
2051
2052         if (!ring->get_seqno)
2053                 return (NULL);
2054
2055         seqno = ring->get_seqno(ring);
2056         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
2057                 if (obj->ring != ring)
2058                         continue;
2059
2060                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
2061                         continue;
2062
2063                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
2064                         continue;
2065
2066                 /* We need to copy these to an anonymous buffer as the simplest
2067                  * method to avoid being overwritten by userspace.
2068                  */
2069                 return (i915_error_object_create(dev_priv, obj));
2070         }
2071
2072         return NULL;
2073 }
2074
2075 static void
2076 i915_record_ring_state(struct drm_device *dev,
2077     struct drm_i915_error_state *error,
2078     struct intel_ring_buffer *ring)
2079 {
2080         struct drm_i915_private *dev_priv = dev->dev_private;
2081
2082         if (INTEL_INFO(dev)->gen >= 6) {
2083                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
2084                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
2085                 error->semaphore_mboxes[ring->id][0]
2086                         = I915_READ(RING_SYNC_0(ring->mmio_base));
2087                 error->semaphore_mboxes[ring->id][1]
2088                         = I915_READ(RING_SYNC_1(ring->mmio_base));
2089         }
2090
2091         if (INTEL_INFO(dev)->gen >= 4) {
2092                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
2093                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
2094                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
2095                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
2096                 if (ring->id == RCS) {
2097                         error->instdone1 = I915_READ(INSTDONE1);
2098                         error->bbaddr = I915_READ64(BB_ADDR);
2099                 }
2100         } else {
2101                 error->ipeir[ring->id] = I915_READ(IPEIR);
2102                 error->ipehr[ring->id] = I915_READ(IPEHR);
2103                 error->instdone[ring->id] = I915_READ(INSTDONE);
2104         }
2105
2106         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
2107         error->seqno[ring->id] = ring->get_seqno(ring);
2108         error->acthd[ring->id] = intel_ring_get_active_head(ring);
2109         error->head[ring->id] = I915_READ_HEAD(ring);
2110         error->tail[ring->id] = I915_READ_TAIL(ring);
2111
2112         error->cpu_ring_head[ring->id] = ring->head;
2113         error->cpu_ring_tail[ring->id] = ring->tail;
2114 }
2115
2116 static void
2117 i915_gem_record_rings(struct drm_device *dev,
2118     struct drm_i915_error_state *error)
2119 {
2120         struct drm_i915_private *dev_priv = dev->dev_private;
2121         struct drm_i915_gem_request *request;
2122         int i, count;
2123
2124         for (i = 0; i < I915_NUM_RINGS; i++) {
2125                 struct intel_ring_buffer *ring = &dev_priv->rings[i];
2126
2127                 if (ring->obj == NULL)
2128                         continue;
2129
2130                 i915_record_ring_state(dev, error, ring);
2131
2132                 error->ring[i].batchbuffer =
2133                         i915_error_first_batchbuffer(dev_priv, ring);
2134
2135                 error->ring[i].ringbuffer =
2136                         i915_error_object_create(dev_priv, ring->obj);
2137
2138                 count = 0;
2139                 list_for_each_entry(request, &ring->request_list, list)
2140                         count++;
2141
2142                 error->ring[i].num_requests = count;
2143                 error->ring[i].requests = kmalloc(count *
2144                     sizeof(struct drm_i915_error_request), DRM_I915_GEM,
2145                     M_WAITOK);
2146                 if (error->ring[i].requests == NULL) {
2147                         error->ring[i].num_requests = 0;
2148                         continue;
2149                 }
2150
2151                 count = 0;
2152                 list_for_each_entry(request, &ring->request_list, list) {
2153                         struct drm_i915_error_request *erq;
2154
2155                         erq = &error->ring[i].requests[count++];
2156                         erq->seqno = request->seqno;
2157                         erq->jiffies = request->emitted_jiffies;
2158                         erq->tail = request->tail;
2159                 }
2160         }
2161 }
2162
2163 static void
2164 i915_capture_error_state(struct drm_device *dev)
2165 {
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167         struct drm_i915_gem_object *obj;
2168         struct drm_i915_error_state *error;
2169         int i, pipe;
2170
2171         lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE);
2172         error = dev_priv->first_error;
2173         lockmgr(&dev_priv->error_lock, LK_RELEASE);
2174         if (error != NULL)
2175                 return;
2176
2177         /* Account for pipe specific data like PIPE*STAT */
2178         error = kmalloc(sizeof(*error), DRM_I915_GEM, M_NOWAIT | M_ZERO);
2179         if (error == NULL) {
2180                 DRM_DEBUG("out of memory, not capturing error state\n");
2181                 return;
2182         }
2183
2184         DRM_INFO("capturing error event; look for more information in "
2185             "sysctl hw.dri.%d.info.i915_error_state\n", dev->sysctl_node_idx);
2186
2187         error->eir = I915_READ(EIR);
2188         error->pgtbl_er = I915_READ(PGTBL_ER);
2189         for_each_pipe(pipe)
2190                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
2191
2192         if (INTEL_INFO(dev)->gen >= 6) {
2193                 error->error = I915_READ(ERROR_GEN6);
2194                 error->done_reg = I915_READ(DONE_REG);
2195         }
2196
2197         i915_gem_record_fences(dev, error);
2198         i915_gem_record_rings(dev, error);
2199
2200         /* Record buffers on the active and pinned lists. */
2201         error->active_bo = NULL;
2202         error->pinned_bo = NULL;
2203
2204         i = 0;
2205         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
2206                 i++;
2207         error->active_bo_count = i;
2208         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
2209                 i++;
2210         error->pinned_bo_count = i - error->active_bo_count;
2211
2212         error->active_bo = NULL;
2213         error->pinned_bo = NULL;
2214         if (i) {
2215                 error->active_bo = kmalloc(sizeof(*error->active_bo) * i,
2216                     DRM_I915_GEM, M_NOWAIT);
2217                 if (error->active_bo)
2218                         error->pinned_bo = error->active_bo +
2219                             error->active_bo_count;
2220         }
2221
2222         if (error->active_bo)
2223                 error->active_bo_count = capture_bo_list(error->active_bo,
2224                     error->active_bo_count, &dev_priv->mm.active_list);
2225
2226         if (error->pinned_bo)
2227                 error->pinned_bo_count = capture_bo_list(error->pinned_bo,
2228                     error->pinned_bo_count, &dev_priv->mm.pinned_list);
2229
2230         microtime(&error->time);
2231
2232         error->overlay = intel_overlay_capture_error_state(dev);
2233         error->display = intel_display_capture_error_state(dev);
2234
2235         lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE);
2236         if (dev_priv->first_error == NULL) {
2237                 dev_priv->first_error = error;
2238                 error = NULL;
2239         }
2240         lockmgr(&dev_priv->error_lock, LK_RELEASE);
2241
2242         if (error != NULL)
2243                 i915_error_state_free(dev, error);
2244 }
2245
2246 void
2247 i915_destroy_error_state(struct drm_device *dev)
2248 {
2249         struct drm_i915_private *dev_priv = dev->dev_private;
2250         struct drm_i915_error_state *error;
2251
2252         lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE);
2253         error = dev_priv->first_error;
2254         dev_priv->first_error = NULL;
2255         lockmgr(&dev_priv->error_lock, LK_RELEASE);
2256
2257         if (error != NULL)
2258                 i915_error_state_free(dev, error);
2259 }