i386 - Get completely rid of APIC_IO
[dragonfly.git] / sys / platform / pc32 / i386 / machdep.c
CommitLineData
984263bc
MD
1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
39 */
40
1f2de5d4
MD
41#include "use_apm.h"
42#include "use_ether.h"
43#include "use_npx.h"
44#include "use_isa.h"
984263bc
MD
45#include "opt_atalk.h"
46#include "opt_compat.h"
47#include "opt_cpu.h"
48#include "opt_ddb.h"
49#include "opt_directio.h"
50#include "opt_inet.h"
51#include "opt_ipx.h"
52#include "opt_maxmem.h"
53#include "opt_msgbuf.h"
54#include "opt_perfmon.h"
55#include "opt_swap.h"
984263bc
MD
56#include "opt_userconfig.h"
57
58#include <sys/param.h>
59#include <sys/systm.h>
60#include <sys/sysproto.h>
61#include <sys/signalvar.h>
62#include <sys/kernel.h>
63#include <sys/linker.h>
64#include <sys/malloc.h>
65#include <sys/proc.h>
895c1f85 66#include <sys/priv.h>
984263bc
MD
67#include <sys/buf.h>
68#include <sys/reboot.h>
984263bc
MD
69#include <sys/mbuf.h>
70#include <sys/msgbuf.h>
71#include <sys/sysent.h>
72#include <sys/sysctl.h>
73#include <sys/vmmeter.h>
74#include <sys/bus.h>
a722be49 75#include <sys/upcall.h>
cb7f4ab1 76#include <sys/usched.h>
527fddf7 77#include <sys/reg.h>
984263bc
MD
78
79#include <vm/vm.h>
80#include <vm/vm_param.h>
81#include <sys/lock.h>
82#include <vm/vm_kern.h>
83#include <vm/vm_object.h>
84#include <vm/vm_page.h>
85#include <vm/vm_map.h>
86#include <vm/vm_pager.h>
87#include <vm/vm_extern.h>
88
4b5f931b 89#include <sys/thread2.h>
684a93c4 90#include <sys/mplock2.h>
4b5f931b 91
984263bc
MD
92#include <sys/user.h>
93#include <sys/exec.h>
94#include <sys/cons.h>
95
96#include <ddb/ddb.h>
97
984263bc 98#include <machine/cpu.h>
984263bc
MD
99#include <machine/clock.h>
100#include <machine/specialreg.h>
101#include <machine/bootinfo.h>
984263bc
MD
102#include <machine/md_var.h>
103#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
85100692 104#include <machine/globaldata.h> /* CPU_prvspace */
984263bc 105#include <machine/smp.h>
984263bc
MD
106#ifdef PERFMON
107#include <machine/perfmon.h>
108#endif
109#include <machine/cputypes.h>
110
111#ifdef OLD_BUS_ARCH
21ce0dfa 112#include <bus/isa/isa_device.h>
984263bc 113#endif
a9295349 114#include <machine_base/isa/intr_machdep.h>
1f2de5d4 115#include <bus/isa/rtc.h>
984263bc
MD
116#include <machine/vm86.h>
117#include <sys/random.h>
118#include <sys/ptrace.h>
119#include <machine/sigframe.h>
120
79b62055
MN
121#include <sys/machintr.h>
122
ff1a75a1
MD
123#define PHYSMAP_ENTRIES 10
124
d678dc17
MN
125extern void init386(int first);
126extern void dblfault_handler(void);
984263bc
MD
127
128extern void printcpuinfo(void); /* XXX header file */
129extern void finishidentcpu(void);
130extern void panicifcpuunsupported(void);
131extern void initializecpu(void);
132
d678dc17 133static void cpu_startup(void *);
642a6e88 134#ifndef CPU_DISABLE_SSE
d678dc17
MN
135static void set_fpregs_xmm(struct save87 *, struct savexmm *);
136static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
642a6e88 137#endif /* CPU_DISABLE_SSE */
984263bc
MD
138#ifdef DIRECTIO
139extern void ffs_rawread_setup(void);
140#endif /* DIRECTIO */
8a8d5d85 141static void init_locks(void);
984263bc 142
ba39e2e0 143SYSINIT(cpu, SI_BOOT2_SMP, SI_ORDER_FIRST, cpu_startup, NULL)
984263bc 144
984263bc
MD
145int _udatasel, _ucodesel;
146u_int atdevbase;
c2751817
MD
147#ifdef SMP
148int64_t tsc_offsets[MAXCPU];
149#else
150int64_t tsc_offsets[1];
151#endif
984263bc
MD
152
153#if defined(SWTCH_OPTIM_STATS)
154extern int swtch_optim_stats;
155SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
156 CTLFLAG_RD, &swtch_optim_stats, 0, "");
157SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
158 CTLFLAG_RD, &tlb_flush_count, 0, "");
159#endif
160
984263bc 161int physmem = 0;
984263bc 162
1876681a
SZ
163u_long ebda_addr = 0;
164
984263bc
MD
165static int
166sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
167{
168 int error = sysctl_handle_int(oidp, 0, ctob(physmem), req);
169 return (error);
170}
171
172SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_INT|CTLFLAG_RD,
173 0, 0, sysctl_hw_physmem, "IU", "");
174
175static int
176sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
177{
178 int error = sysctl_handle_int(oidp, 0,
12e4aaff 179 ctob(physmem - vmstats.v_wire_count), req);
984263bc
MD
180 return (error);
181}
182
183SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
184 0, 0, sysctl_hw_usermem, "IU", "");
185
186static int
187sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
188{
189 int error = sysctl_handle_int(oidp, 0,
190 i386_btop(avail_end - avail_start), req);
191 return (error);
192}
193
194SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
195 0, 0, sysctl_hw_availpages, "I", "");
196
1bda0d3d
MD
197vm_paddr_t Maxmem;
198vm_paddr_t Realmem;
984263bc 199
ff1a75a1 200vm_paddr_t phys_avail[PHYSMAP_ENTRIES*2+2];
b24cd69c
AH
201vm_paddr_t dump_avail[PHYSMAP_ENTRIES*2+2];
202
984263bc
MD
203
204static vm_offset_t buffer_sva, buffer_eva;
205vm_offset_t clean_sva, clean_eva;
206static vm_offset_t pager_sva, pager_eva;
207static struct trapframe proc0_tf;
208
209static void
f123d5a1 210cpu_startup(void *dummy)
984263bc 211{
c9faf524 212 caddr_t v;
984263bc 213 vm_size_t size = 0;
e4846942 214 vm_offset_t firstaddr;
984263bc
MD
215
216 if (boothowto & RB_VERBOSE)
217 bootverbose++;
218
219 /*
220 * Good {morning,afternoon,evening,night}.
221 */
26be20a0 222 kprintf("%s", version);
984263bc
MD
223 startrtclock();
224 printcpuinfo();
225 panicifcpuunsupported();
226#ifdef PERFMON
227 perfmon_init();
228#endif
15dc6550 229 kprintf("real memory = %ju (%ju MB)\n",
1bda0d3d
MD
230 (intmax_t)Realmem,
231 (intmax_t)Realmem / 1024 / 1024);
984263bc
MD
232 /*
233 * Display any holes after the first chunk of extended memory.
234 */
235 if (bootverbose) {
236 int indx;
237
26be20a0 238 kprintf("Physical memory chunk(s):\n");
984263bc 239 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
6ef943a3 240 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
984263bc 241
26be20a0 242 kprintf("0x%08llx - 0x%08llx, %llu bytes (%llu pages)\n",
984263bc
MD
243 phys_avail[indx], phys_avail[indx + 1] - 1, size1,
244 size1 / PAGE_SIZE);
245 }
246 }
247
248 /*
984263bc
MD
249 * Allocate space for system data structures.
250 * The first available kernel virtual address is in "v".
251 * As pages of kernel virtual memory are allocated, "v" is incremented.
252 * As pages of memory are allocated and cleared,
253 * "firstaddr" is incremented.
254 * An index into the kernel page table corresponding to the
255 * virtual memory address maintained in "v" is kept in "mapaddr".
256 */
257
258 /*
259 * Make two passes. The first pass calculates how much memory is
260 * needed and allocates it. The second pass assigns virtual
261 * addresses to the various data structures.
262 */
263 firstaddr = 0;
264again:
265 v = (caddr_t)firstaddr;
266
267#define valloc(name, type, num) \
268 (name) = (type *)v; v = (caddr_t)((name)+(num))
269#define valloclim(name, type, num, lim) \
270 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
271
984263bc
MD
272 /*
273 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
274 * For the first 64MB of ram nominally allocate sufficient buffers to
275 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
276 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
277 * the buffer cache we limit the eventual kva reservation to
278 * maxbcache bytes.
279 *
280 * factor represents the 1/4 x ram conversion.
281 */
282 if (nbuf == 0) {
283 int factor = 4 * BKVASIZE / 1024;
284 int kbytes = physmem * (PAGE_SIZE / 1024);
285
286 nbuf = 50;
287 if (kbytes > 4096)
288 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
289 if (kbytes > 65536)
290 nbuf += (kbytes - 65536) * 2 / (factor * 5);
291 if (maxbcache && nbuf > maxbcache / BKVASIZE)
292 nbuf = maxbcache / BKVASIZE;
293 }
294
295 /*
296 * Do not allow the buffer_map to be more then 1/2 the size of the
297 * kernel_map.
298 */
e4846942
MD
299 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
300 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
26be20a0 301 kprintf("Warning: nbufs capped at %d\n", nbuf);
984263bc
MD
302 }
303
948209ce
MD
304 /* limit to 128 on i386 */
305 nswbuf = max(min(nbuf/4, 128), 16);
984263bc
MD
306#ifdef NSWBUF_MIN
307 if (nswbuf < NSWBUF_MIN)
308 nswbuf = NSWBUF_MIN;
309#endif
310#ifdef DIRECTIO
311 ffs_rawread_setup();
312#endif
313
314 valloc(swbuf, struct buf, nswbuf);
315 valloc(buf, struct buf, nbuf);
984263bc
MD
316
317 /*
318 * End of first pass, size has been calculated so allocate memory
319 */
320 if (firstaddr == 0) {
321 size = (vm_size_t)(v - firstaddr);
e4846942 322 firstaddr = kmem_alloc(&kernel_map, round_page(size));
984263bc
MD
323 if (firstaddr == 0)
324 panic("startup: no room for tables");
325 goto again;
326 }
327
328 /*
329 * End of second pass, addresses have been assigned
330 */
331 if ((vm_size_t)(v - firstaddr) != size)
332 panic("startup: table size inconsistency");
333
e4846942
MD
334 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
335 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
336 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
337 (nbuf*BKVASIZE));
338 buffer_map.system_map = 1;
339 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
340 (nswbuf*MAXPHYS) + pager_map_size);
341 pager_map.system_map = 1;
984263bc 342
984263bc
MD
343#if defined(USERCONFIG)
344 userconfig();
345 cninit(); /* the preferred console may have changed */
346#endif
347
15dc6550 348 kprintf("avail memory = %ju (%ju MB)\n",
f9ab53b8 349 (intmax_t)ptoa(vmstats.v_free_count),
15dc6550 350 (intmax_t)ptoa(vmstats.v_free_count) / 1024 / 1024);
984263bc
MD
351
352 /*
353 * Set up buffers, so they can be used to read disk labels.
354 */
355 bufinit();
356 vm_pager_bufferinit();
357
358#ifdef SMP
359 /*
360 * OK, enough kmem_alloc/malloc state should be up, lets get on with it!
361 */
362 mp_start(); /* fire up the APs and APICs */
363 mp_announce();
364#endif /* SMP */
365 cpu_setregs();
366}
367
984263bc
MD
368/*
369 * Send an interrupt to process.
370 *
371 * Stack is set up to allow sigcode stored
372 * at top to call routine, followed by kcall
373 * to sigreturn routine below. After sigreturn
374 * resets the signal mask, the stack, and the
375 * frame pointer, it returns to the user
376 * specified pc, psl.
377 */
984263bc 378void
f123d5a1 379sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
984263bc 380{
065b709a
SS
381 struct lwp *lp = curthread->td_lwp;
382 struct proc *p = lp->lwp_proc;
984263bc
MD
383 struct trapframe *regs;
384 struct sigacts *psp = p->p_sigacts;
385 struct sigframe sf, *sfp;
386 int oonstack;
387
065b709a
SS
388 regs = lp->lwp_md.md_regs;
389 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
984263bc
MD
390
391 /* save user context */
392 bzero(&sf, sizeof(struct sigframe));
393 sf.sf_uc.uc_sigmask = *mask;
065b709a 394 sf.sf_uc.uc_stack = lp->lwp_sigstk;
984263bc 395 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
4e7c41c5 396 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_gs, sizeof(struct trapframe));
984263bc 397
ce3d8c4d
MD
398 /* make the size of the saved context visible to userland */
399 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
400
4b486183
MD
401 /* save mailbox pending state for syscall interlock semantics */
402 if (p->p_flag & P_MAILBOX)
403 sf.sf_uc.uc_mcontext.mc_xflags |= PGEX_MAILBOX;
404
984263bc 405 /* Allocate and validate space for the signal handler context. */
08f2f1bb 406 if ((lp->lwp_flag & LWP_ALTSTACK) != 0 && !oonstack &&
984263bc 407 SIGISMEMBER(psp->ps_sigonstack, sig)) {
065b709a
SS
408 sfp = (struct sigframe *)(lp->lwp_sigstk.ss_sp +
409 lp->lwp_sigstk.ss_size - sizeof(struct sigframe));
410 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
4e7c41c5 411 } else {
984263bc 412 sfp = (struct sigframe *)regs->tf_esp - 1;
4e7c41c5 413 }
984263bc
MD
414
415 /* Translate the signal is appropriate */
416 if (p->p_sysent->sv_sigtbl) {
417 if (sig <= p->p_sysent->sv_sigsize)
418 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
419 }
420
421 /* Build the argument list for the signal handler. */
422 sf.sf_signum = sig;
423 sf.sf_ucontext = (register_t)&sfp->sf_uc;
065b709a 424 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
984263bc
MD
425 /* Signal handler installed with SA_SIGINFO. */
426 sf.sf_siginfo = (register_t)&sfp->sf_si;
427 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
428
429 /* fill siginfo structure */
430 sf.sf_si.si_signo = sig;
431 sf.sf_si.si_code = code;
432 sf.sf_si.si_addr = (void*)regs->tf_err;
433 }
434 else {
435 /* Old FreeBSD-style arguments. */
436 sf.sf_siginfo = code;
437 sf.sf_addr = regs->tf_err;
438 sf.sf_ahu.sf_handler = catcher;
439 }
440
441 /*
442 * If we're a vm86 process, we want to save the segment registers.
443 * We also change eflags to be our emulated eflags, not the actual
444 * eflags.
445 */
446 if (regs->tf_eflags & PSL_VM) {
447 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
065b709a 448 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
984263bc
MD
449
450 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
451 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
452 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
453 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
454
455 if (vm86->vm86_has_vme == 0)
456 sf.sf_uc.uc_mcontext.mc_eflags =
457 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
458 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
459
460 /*
461 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
462 * syscalls made by the signal handler. This just avoids
463 * wasting time for our lazy fixup of such faults. PSL_NT
464 * does nothing in vm86 mode, but vm86 programs can set it
465 * almost legitimately in probes for old cpu types.
466 */
467 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
468 }
469
470 /*
1b251f0a
MD
471 * Save the FPU state and reinit the FP unit
472 */
473 npxpush(&sf.sf_uc.uc_mcontext);
474
475 /*
984263bc
MD
476 * Copy the sigframe out to the user's stack.
477 */
478 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
479 /*
480 * Something is wrong with the stack pointer.
481 * ...Kill the process.
482 */
b276424c 483 sigexit(lp, SIGILL);
984263bc
MD
484 }
485
486 regs->tf_esp = (int)sfp;
487 regs->tf_eip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
8688c24a
AE
488
489 /*
490 * i386 abi specifies that the direction flag must be cleared
491 * on function entry
492 */
493 regs->tf_eflags &= ~(PSL_T|PSL_D);
494
984263bc
MD
495 regs->tf_cs = _ucodesel;
496 regs->tf_ds = _udatasel;
497 regs->tf_es = _udatasel;
dd4ad62d
MD
498
499 /*
500 * Allow the signal handler to inherit %fs in addition to %gs as
4e7c41c5
MD
501 * the userland program might be using both.
502 *
503 * However, if a T_PROTFLT occured the segment registers could be
504 * totally broken. They must be reset in order to be able to
505 * return to userland.
dd4ad62d 506 */
4e7c41c5
MD
507 if (regs->tf_trapno == T_PROTFLT) {
508 regs->tf_fs = _udatasel;
509 regs->tf_gs = _udatasel;
510 }
984263bc
MD
511 regs->tf_ss = _udatasel;
512}
513
514/*
4a22e893 515 * Sanitize the trapframe for a virtual kernel passing control to a custom
4e7c41c5
MD
516 * VM context. Remove any items that would otherwise create a privilage
517 * issue.
4a22e893 518 *
4e7c41c5
MD
519 * XXX at the moment we allow userland to set the resume flag. Is this a
520 * bad idea?
4a22e893
MD
521 */
522int
523cpu_sanitize_frame(struct trapframe *frame)
524{
525 frame->tf_cs = _ucodesel;
526 frame->tf_ds = _udatasel;
4e7c41c5
MD
527 frame->tf_es = _udatasel; /* XXX allow userland this one too? */
528#if 0
4a22e893 529 frame->tf_fs = _udatasel;
4e7c41c5
MD
530 frame->tf_gs = _udatasel;
531#endif
4a22e893 532 frame->tf_ss = _udatasel;
4e7c41c5 533 frame->tf_eflags &= (PSL_RF | PSL_USERCHANGE);
4a22e893
MD
534 frame->tf_eflags |= PSL_RESERVED_DEFAULT | PSL_I;
535 return(0);
536}
537
4e7c41c5
MD
538int
539cpu_sanitize_tls(struct savetls *tls)
540{
541 struct segment_descriptor *desc;
542 int i;
543
544 for (i = 0; i < NGTLS; ++i) {
545 desc = &tls->tls[i];
546 if (desc->sd_dpl == 0 && desc->sd_type == 0)
547 continue;
548 if (desc->sd_def32 == 0)
549 return(ENXIO);
550 if (desc->sd_type != SDT_MEMRWA)
551 return(ENXIO);
552 if (desc->sd_dpl != SEL_UPL)
553 return(ENXIO);
554 if (desc->sd_xx != 0 || desc->sd_p != 1)
555 return(ENXIO);
556 }
557 return(0);
558}
559
4a22e893 560/*
65957d54 561 * sigreturn(ucontext_t *sigcntxp)
41c20dac 562 *
984263bc
MD
563 * System call to cleanup state after a signal
564 * has been taken. Reset signal mask and
565 * stack state from context left by sendsig (above).
566 * Return to previous pc and psl as specified by
567 * context left by sendsig. Check carefully to
568 * make sure that the user has not modified the
569 * state to gain improper privileges.
3919ced0
MD
570 *
571 * MPSAFE
984263bc
MD
572 */
573#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
574#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
575
576int
753fd850 577sys_sigreturn(struct sigreturn_args *uap)
984263bc 578{
065b709a 579 struct lwp *lp = curthread->td_lwp;
4b486183 580 struct proc *p = lp->lwp_proc;
984263bc 581 struct trapframe *regs;
1b251f0a 582 ucontext_t uc;
984263bc 583 ucontext_t *ucp;
1b251f0a
MD
584 int cs;
585 int eflags;
586 int error;
984263bc 587
1b251f0a
MD
588 /*
589 * We have to copy the information into kernel space so userland
590 * can't modify it while we are sniffing it.
591 */
065b709a 592 regs = lp->lwp_md.md_regs;
1b251f0a
MD
593 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
594 if (error)
595 return (error);
596 ucp = &uc;
984263bc
MD
597 eflags = ucp->uc_mcontext.mc_eflags;
598
599 if (eflags & PSL_VM) {
600 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
601 struct vm86_kernel *vm86;
602
603 /*
604 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
605 * set up the vm86 area, and we can't enter vm86 mode.
606 */
065b709a 607 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
984263bc 608 return (EINVAL);
065b709a 609 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
984263bc
MD
610 if (vm86->vm86_inited == 0)
611 return (EINVAL);
612
613 /* go back to user mode if both flags are set */
614 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
08f2f1bb 615 trapsignal(lp, SIGBUS, 0);
984263bc
MD
616
617 if (vm86->vm86_has_vme) {
618 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
619 (eflags & VME_USERCHANGE) | PSL_VM;
620 } else {
621 vm86->vm86_eflags = eflags; /* save VIF, VIP */
e2742650
MD
622 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
623 (eflags & VM_USERCHANGE) | PSL_VM;
984263bc 624 }
4e7c41c5 625 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
984263bc
MD
626 tf->tf_eflags = eflags;
627 tf->tf_vm86_ds = tf->tf_ds;
628 tf->tf_vm86_es = tf->tf_es;
629 tf->tf_vm86_fs = tf->tf_fs;
4e7c41c5 630 tf->tf_vm86_gs = tf->tf_gs;
984263bc
MD
631 tf->tf_ds = _udatasel;
632 tf->tf_es = _udatasel;
4e7c41c5 633#if 0
984263bc 634 tf->tf_fs = _udatasel;
4e7c41c5
MD
635 tf->tf_gs = _udatasel;
636#endif
984263bc
MD
637 } else {
638 /*
639 * Don't allow users to change privileged or reserved flags.
640 */
641 /*
642 * XXX do allow users to change the privileged flag PSL_RF.
643 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
644 * should sometimes set it there too. tf_eflags is kept in
645 * the signal context during signal handling and there is no
646 * other place to remember it, so the PSL_RF bit may be
647 * corrupted by the signal handler without us knowing.
648 * Corruption of the PSL_RF bit at worst causes one more or
649 * one less debugger trap, so allowing it is fairly harmless.
650 */
651 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
26be20a0 652 kprintf("sigreturn: eflags = 0x%x\n", eflags);
984263bc
MD
653 return(EINVAL);
654 }
655
656 /*
657 * Don't allow users to load a valid privileged %cs. Let the
658 * hardware check for invalid selectors, excess privilege in
659 * other selectors, invalid %eip's and invalid %esp's.
660 */
661 cs = ucp->uc_mcontext.mc_cs;
662 if (!CS_SECURE(cs)) {
26be20a0 663 kprintf("sigreturn: cs = 0x%x\n", cs);
08f2f1bb 664 trapsignal(lp, SIGBUS, T_PROTFLT);
984263bc
MD
665 return(EINVAL);
666 }
4e7c41c5 667 bcopy(&ucp->uc_mcontext.mc_gs, regs, sizeof(struct trapframe));
984263bc
MD
668 }
669
4b486183 670 /*
1b251f0a
MD
671 * Restore the FPU state from the frame
672 */
3919ced0 673 crit_enter();
1b251f0a
MD
674 npxpop(&ucp->uc_mcontext);
675
676 /*
4b486183
MD
677 * Merge saved signal mailbox pending flag to maintain interlock
678 * semantics against system calls.
679 */
680 if (ucp->uc_mcontext.mc_xflags & PGEX_MAILBOX)
681 p->p_flag |= P_MAILBOX;
682
984263bc 683 if (ucp->uc_mcontext.mc_onstack & 1)
065b709a 684 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
984263bc 685 else
065b709a 686 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
984263bc 687
065b709a
SS
688 lp->lwp_sigmask = ucp->uc_sigmask;
689 SIG_CANTMASK(lp->lwp_sigmask);
3919ced0 690 crit_exit();
984263bc
MD
691 return(EJUSTRETURN);
692}
693
694/*
a722be49
MD
695 * Stack frame on entry to function. %eax will contain the function vector,
696 * %ecx will contain the function data. flags, ecx, and eax will have
697 * already been pushed on the stack.
698 */
699struct upc_frame {
700 register_t eax;
701 register_t ecx;
0a455ac5 702 register_t edx;
a722be49
MD
703 register_t flags;
704 register_t oldip;
705};
706
707void
708sendupcall(struct vmupcall *vu, int morepending)
709{
065b709a 710 struct lwp *lp = curthread->td_lwp;
a722be49
MD
711 struct trapframe *regs;
712 struct upcall upcall;
713 struct upc_frame upc_frame;
6e58b5df 714 int crit_count = 0;
a722be49
MD
715
716 /*
69c61fbe
MD
717 * If we are a virtual kernel running an emulated user process
718 * context, switch back to the virtual kernel context before
719 * trying to post the signal.
720 */
39005e16 721 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
69c61fbe 722 lp->lwp_md.md_regs->tf_trapno = 0;
287ebb09 723 vkernel_trap(lp, lp->lwp_md.md_regs);
69c61fbe
MD
724 }
725
726 /*
a722be49
MD
727 * Get the upcall data structure
728 */
065b709a 729 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
6e58b5df
MD
730 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
731 ) {
a722be49 732 vu->vu_pending = 0;
26be20a0 733 kprintf("bad upcall address\n");
a722be49
MD
734 return;
735 }
736
737 /*
738 * If the data structure is already marked pending or has a critical
739 * section count, mark the data structure as pending and return
740 * without doing an upcall. vu_pending is left set.
741 */
6e58b5df
MD
742 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
743 if (upcall.upc_pending < vu->vu_pending) {
744 upcall.upc_pending = vu->vu_pending;
065b709a 745 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df 746 sizeof(upcall.upc_pending));
a722be49
MD
747 }
748 return;
749 }
750
751 /*
752 * We can run this upcall now, clear vu_pending.
753 *
754 * Bump our critical section count and set or clear the
755 * user pending flag depending on whether more upcalls are
756 * pending. The user will be responsible for calling
757 * upc_dispatch(-1) to process remaining upcalls.
758 */
759 vu->vu_pending = 0;
6e58b5df 760 upcall.upc_pending = morepending;
f9235b6d 761 ++crit_count;
065b709a 762 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df
MD
763 sizeof(upcall.upc_pending));
764 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
765 sizeof(int));
a722be49
MD
766
767 /*
768 * Construct a stack frame and issue the upcall
769 */
065b709a 770 regs = lp->lwp_md.md_regs;
a722be49
MD
771 upc_frame.eax = regs->tf_eax;
772 upc_frame.ecx = regs->tf_ecx;
0a455ac5 773 upc_frame.edx = regs->tf_edx;
a722be49
MD
774 upc_frame.flags = regs->tf_eflags;
775 upc_frame.oldip = regs->tf_eip;
776 if (copyout(&upc_frame, (void *)(regs->tf_esp - sizeof(upc_frame)),
777 sizeof(upc_frame)) != 0) {
26be20a0 778 kprintf("bad stack on upcall\n");
a722be49
MD
779 } else {
780 regs->tf_eax = (register_t)vu->vu_func;
781 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 782 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD
783 regs->tf_eip = (register_t)vu->vu_ctx;
784 regs->tf_esp -= sizeof(upc_frame);
785 }
786}
787
788/*
789 * fetchupcall occurs in the context of a system call, which means that
0a455ac5
MD
790 * we have to return EJUSTRETURN in order to prevent eax and edx from
791 * being overwritten by the syscall return value.
a722be49
MD
792 *
793 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
794 * and the function pointer in %eax.
795 */
796int
d678dc17 797fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
a722be49
MD
798{
799 struct upc_frame upc_frame;
065b709a 800 struct lwp *lp = curthread->td_lwp;
a722be49
MD
801 struct trapframe *regs;
802 int error;
6e58b5df
MD
803 struct upcall upcall;
804 int crit_count;
a722be49 805
065b709a 806 regs = lp->lwp_md.md_regs;
a722be49 807
065b709a 808 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
a722be49
MD
809 if (error == 0) {
810 if (vu) {
811 /*
812 * This jumps us to the next ready context.
813 */
814 vu->vu_pending = 0;
065b709a 815 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
6e58b5df
MD
816 crit_count = 0;
817 if (error == 0)
818 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 819 ++crit_count;
a722be49 820 if (error == 0)
6e58b5df 821 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
a722be49
MD
822 regs->tf_eax = (register_t)vu->vu_func;
823 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 824 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD
825 regs->tf_eip = (register_t)vu->vu_ctx;
826 regs->tf_esp = (register_t)rsp;
827 } else {
828 /*
829 * This returns us to the originally interrupted code.
830 */
831 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
832 regs->tf_eax = upc_frame.eax;
833 regs->tf_ecx = upc_frame.ecx;
0a455ac5 834 regs->tf_edx = upc_frame.edx;
6e58b5df
MD
835 regs->tf_eflags = (regs->tf_eflags & ~PSL_USERCHANGE) |
836 (upc_frame.flags & PSL_USERCHANGE);
a722be49
MD
837 regs->tf_eip = upc_frame.oldip;
838 regs->tf_esp = (register_t)((char *)rsp + sizeof(upc_frame));
839 }
840 }
841 if (error == 0)
842 error = EJUSTRETURN;
843 return(error);
844}
845
846/*
984263bc
MD
847 * Machine dependent boot() routine
848 *
849 * I haven't seen anything to put here yet
850 * Possibly some stuff might be grafted back here from boot()
851 */
852void
853cpu_boot(int howto)
854{
855}
856
857/*
858 * Shutdown the CPU as much as possible
859 */
860void
861cpu_halt(void)
862{
863 for (;;)
1184892f 864 __asm__ __volatile("hlt");
984263bc
MD
865}
866
867/*
8ad65e08
MD
868 * cpu_idle() represents the idle LWKT. You cannot return from this function
869 * (unless you want to blow things up!). Instead we look for runnable threads
870 * and loop or halt as appropriate. Giant is not held on entry to the thread.
984263bc 871 *
26a0694b 872 * The main loop is entered with a critical section held, we must release
a2a5ad0d
MD
873 * the critical section before doing anything else. lwkt_switch() will
874 * check for pending interrupts due to entering and exiting its own
875 * critical section.
26a0694b 876 *
a2a5ad0d
MD
877 * Note on cpu_idle_hlt: On an SMP system we rely on a scheduler IPI
878 * to wake a HLTed cpu up. However, there are cases where the idlethread
879 * will be entered with the possibility that no IPI will occur and in such
880 * cases lwkt_switch() sets TDF_IDLE_NOHLT.
984263bc 881 */
96728c05 882static int cpu_idle_hlt = 1;
60f945af
MD
883static int cpu_idle_hltcnt;
884static int cpu_idle_spincnt;
984263bc
MD
885SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
886 &cpu_idle_hlt, 0, "Idle loop HLT enable");
60f945af
MD
887SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
888 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
889SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
890 &cpu_idle_spincnt, 0, "Idle loop entry spins");
984263bc 891
f9d8cd12
MD
892static void
893cpu_idle_default_hook(void)
894{
895 /*
896 * We must guarentee that hlt is exactly the instruction
897 * following the sti.
898 */
899 __asm __volatile("sti; hlt");
900}
901
902/* Other subsystems (e.g., ACPI) can hook this later. */
903void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
904
984263bc
MD
905void
906cpu_idle(void)
907{
a2a5ad0d
MD
908 struct thread *td = curthread;
909
26a0694b 910 crit_exit();
f9235b6d 911 KKASSERT(td->td_critcount == 0);
8ad65e08 912 for (;;) {
a2a5ad0d
MD
913 /*
914 * See if there are any LWKTs ready to go.
915 */
8ad65e08 916 lwkt_switch();
a2a5ad0d
MD
917
918 /*
919 * If we are going to halt call splz unconditionally after
920 * CLIing to catch any interrupt races. Note that we are
921 * at SPL0 and interrupts are enabled.
922 */
923 if (cpu_idle_hlt && !lwkt_runnable() &&
924 (td->td_flags & TDF_IDLE_NOHLT) == 0) {
a2a5ad0d
MD
925 __asm __volatile("cli");
926 splz();
8b6d0f3f 927 if (!lwkt_runnable())
c5724852 928 cpu_idle_hook();
8b6d0f3f
MD
929#ifdef SMP
930 else
c5724852 931 handle_cpu_contention_mask();
8b6d0f3f 932#endif
60f945af 933 ++cpu_idle_hltcnt;
8ad65e08 934 } else {
a2a5ad0d 935 td->td_flags &= ~TDF_IDLE_NOHLT;
60f945af 936 splz();
8b6d0f3f 937#ifdef SMP
c5724852
MD
938 __asm __volatile("sti");
939 handle_cpu_contention_mask();
8b6d0f3f 940#else
8ad65e08 941 __asm __volatile("sti");
8b6d0f3f 942#endif
60f945af 943 ++cpu_idle_spincnt;
8ad65e08 944 }
984263bc
MD
945 }
946}
947
7ad8cc6c
SW
948#ifdef SMP
949
984263bc 950/*
b402c633
MD
951 * This routine is called when the only runnable threads require
952 * the MP lock, and the scheduler couldn't get it. On a real cpu
953 * we let the scheduler spin.
954 */
955void
c5724852 956handle_cpu_contention_mask(void)
b402c633 957{
c5724852
MD
958 cpumask_t mask;
959
960 mask = cpu_contention_mask;
961 cpu_ccfence();
b68e846f 962 if (mask && bsfl(mask) != mycpu->gd_cpuid)
c5724852 963 DELAY(2);
b402c633
MD
964}
965
966/*
06615ccb
MD
967 * This routine is called if a spinlock has been held through the
968 * exponential backoff period and is seriously contested. On a real cpu
969 * we let it spin.
970 */
971void
972cpu_spinlock_contested(void)
973{
974 cpu_pause();
975}
976
7ad8cc6c
SW
977#endif
978
06615ccb 979/*
984263bc
MD
980 * Clear registers on exec
981 */
982void
08f2f1bb 983exec_setregs(u_long entry, u_long stack, u_long ps_strings)
984263bc 984{
08f2f1bb
SS
985 struct thread *td = curthread;
986 struct lwp *lp = td->td_lwp;
987 struct pcb *pcb = td->td_pcb;
bb3cd951 988 struct trapframe *regs = lp->lwp_md.md_regs;
984263bc 989
984263bc
MD
990 /* was i386_user_cleanup() in NetBSD */
991 user_ldt_free(pcb);
984263bc
MD
992
993 bzero((char *)regs, sizeof(struct trapframe));
994 regs->tf_eip = entry;
995 regs->tf_esp = stack;
996 regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
997 regs->tf_ss = _udatasel;
998 regs->tf_ds = _udatasel;
999 regs->tf_es = _udatasel;
1000 regs->tf_fs = _udatasel;
4e7c41c5 1001 regs->tf_gs = _udatasel;
984263bc
MD
1002 regs->tf_cs = _ucodesel;
1003
1004 /* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
1005 regs->tf_ebx = ps_strings;
1006
1007 /*
1008 * Reset the hardware debug registers if they were in use.
1009 * They won't have any meaning for the newly exec'd process.
1010 */
1011 if (pcb->pcb_flags & PCB_DBREGS) {
1012 pcb->pcb_dr0 = 0;
1013 pcb->pcb_dr1 = 0;
1014 pcb->pcb_dr2 = 0;
1015 pcb->pcb_dr3 = 0;
1016 pcb->pcb_dr6 = 0;
1017 pcb->pcb_dr7 = 0;
08f2f1bb 1018 if (pcb == td->td_pcb) {
984263bc
MD
1019 /*
1020 * Clear the debug registers on the running
1021 * CPU, otherwise they will end up affecting
1022 * the next process we switch to.
1023 */
1024 reset_dbregs();
1025 }
1026 pcb->pcb_flags &= ~PCB_DBREGS;
1027 }
1028
1029 /*
1030 * Initialize the math emulator (if any) for the current process.
1031 * Actually, just clear the bit that says that the emulator has
1032 * been initialized. Initialization is delayed until the process
1033 * traps to the emulator (if it is done at all) mainly because
1034 * emulators don't provide an entry point for initialization.
1035 */
08f2f1bb 1036 pcb->pcb_flags &= ~FP_SOFTFP;
984263bc
MD
1037
1038 /*
a02705a9
MD
1039 * note: do not set CR0_TS here. npxinit() must do it after clearing
1040 * gd_npxthread. Otherwise a preemptive interrupt thread may panic
1041 * in npxdna().
984263bc 1042 */
a02705a9
MD
1043 crit_enter();
1044 load_cr0(rcr0() | CR0_MP);
984263bc
MD
1045
1046#if NNPX > 0
1047 /* Initialize the npx (if any) for the current process. */
1048 npxinit(__INITIAL_NPXCW__);
1049#endif
a02705a9 1050 crit_exit();
984263bc 1051
90b9818c
MD
1052 /*
1053 * note: linux emulator needs edx to be 0x0 on entry, which is
c0510e9a
MD
1054 * handled in execve simply by setting the 64 bit syscall
1055 * return value to 0.
90b9818c 1056 */
984263bc
MD
1057}
1058
1059void
1060cpu_setregs(void)
1061{
1062 unsigned int cr0;
1063
1064 cr0 = rcr0();
1065 cr0 |= CR0_NE; /* Done by npxinit() */
1066 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
4db955e1 1067 cr0 |= CR0_WP | CR0_AM;
984263bc
MD
1068 load_cr0(cr0);
1069 load_gs(_udatasel);
1070}
1071
1072static int
1073sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1074{
1075 int error;
1076 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1077 req);
1078 if (!error && req->newptr)
1079 resettodr();
1080 return (error);
1081}
1082
1083SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1084 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1085
1086SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1087 CTLFLAG_RW, &disable_rtc_set, 0, "");
1088
1089SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1090 CTLFLAG_RD, &bootinfo, bootinfo, "");
1091
1092SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1093 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1094
b13267a5 1095extern u_long bootdev; /* not a cdev_t - encoding is different */
984263bc 1096SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
b13267a5 1097 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
984263bc
MD
1098
1099/*
1100 * Initialize 386 and configure to run kernel
1101 */
1102
1103/*
1104 * Initialize segments & interrupt table
1105 */
1106
1107int _default_ldt;
1108union descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1109static struct gate_descriptor idt0[NIDT];
1110struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1111union descriptor ldt[NLDT]; /* local descriptor table */
17a9f566
MD
1112
1113/* table descriptors - used to load tables by cpu */
984263bc 1114struct region_descriptor r_gdt, r_idt;
984263bc 1115
984263bc
MD
1116#if defined(I586_CPU) && !defined(NO_F00F_HACK)
1117extern int has_f00f_bug;
1118#endif
1119
1120static struct i386tss dblfault_tss;
1121static char dblfault_stack[PAGE_SIZE];
1122
1123extern struct user *proc0paddr;
1124
1125
1126/* software prototypes -- in more palatable form */
1127struct soft_segment_descriptor gdt_segs[] = {
1128/* GNULL_SEL 0 Null Descriptor */
1129{ 0x0, /* segment base address */
1130 0x0, /* length */
1131 0, /* segment type */
1132 0, /* segment descriptor priority level */
1133 0, /* segment descriptor present */
1134 0, 0,
1135 0, /* default 32 vs 16 bit size */
1136 0 /* limit granularity (byte/page units)*/ },
1137/* GCODE_SEL 1 Code Descriptor for kernel */
1138{ 0x0, /* segment base address */
1139 0xfffff, /* length - all address space */
1140 SDT_MEMERA, /* segment type */
1141 0, /* segment descriptor priority level */
1142 1, /* segment descriptor present */
1143 0, 0,
1144 1, /* default 32 vs 16 bit size */
1145 1 /* limit granularity (byte/page units)*/ },
1146/* GDATA_SEL 2 Data Descriptor for kernel */
1147{ 0x0, /* segment base address */
1148 0xfffff, /* length - all address space */
1149 SDT_MEMRWA, /* segment type */
1150 0, /* segment descriptor priority level */
1151 1, /* segment descriptor present */
1152 0, 0,
1153 1, /* default 32 vs 16 bit size */
1154 1 /* limit granularity (byte/page units)*/ },
1155/* GPRIV_SEL 3 SMP Per-Processor Private Data Descriptor */
1156{ 0x0, /* segment base address */
1157 0xfffff, /* length - all address space */
1158 SDT_MEMRWA, /* segment type */
1159 0, /* segment descriptor priority level */
1160 1, /* segment descriptor present */
1161 0, 0,
1162 1, /* default 32 vs 16 bit size */
1163 1 /* limit granularity (byte/page units)*/ },
1164/* GPROC0_SEL 4 Proc 0 Tss Descriptor */
1165{
1166 0x0, /* segment base address */
1167 sizeof(struct i386tss)-1,/* length - all address space */
1168 SDT_SYS386TSS, /* segment type */
1169 0, /* segment descriptor priority level */
1170 1, /* segment descriptor present */
1171 0, 0,
1172 0, /* unused - default 32 vs 16 bit size */
1173 0 /* limit granularity (byte/page units)*/ },
1174/* GLDT_SEL 5 LDT Descriptor */
1175{ (int) ldt, /* segment base address */
1176 sizeof(ldt)-1, /* length - all address space */
1177 SDT_SYSLDT, /* segment type */
1178 SEL_UPL, /* segment descriptor priority level */
1179 1, /* segment descriptor present */
1180 0, 0,
1181 0, /* unused - default 32 vs 16 bit size */
1182 0 /* limit granularity (byte/page units)*/ },
1183/* GUSERLDT_SEL 6 User LDT Descriptor per process */
1184{ (int) ldt, /* segment base address */
1185 (512 * sizeof(union descriptor)-1), /* length */
1186 SDT_SYSLDT, /* segment type */
1187 0, /* segment descriptor priority level */
1188 1, /* segment descriptor present */
1189 0, 0,
1190 0, /* unused - default 32 vs 16 bit size */
1191 0 /* limit granularity (byte/page units)*/ },
1192/* GTGATE_SEL 7 Null Descriptor - Placeholder */
1193{ 0x0, /* segment base address */
1194 0x0, /* length - all address space */
1195 0, /* segment type */
1196 0, /* segment descriptor priority level */
1197 0, /* segment descriptor present */
1198 0, 0,
1199 0, /* default 32 vs 16 bit size */
1200 0 /* limit granularity (byte/page units)*/ },
1201/* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
1202{ 0x400, /* segment base address */
1203 0xfffff, /* length */
1204 SDT_MEMRWA, /* segment type */
1205 0, /* segment descriptor priority level */
1206 1, /* segment descriptor present */
1207 0, 0,
1208 1, /* default 32 vs 16 bit size */
1209 1 /* limit granularity (byte/page units)*/ },
1210/* GPANIC_SEL 9 Panic Tss Descriptor */
1211{ (int) &dblfault_tss, /* segment base address */
1212 sizeof(struct i386tss)-1,/* length - all address space */
1213 SDT_SYS386TSS, /* segment type */
1214 0, /* segment descriptor priority level */
1215 1, /* segment descriptor present */
1216 0, 0,
1217 0, /* unused - default 32 vs 16 bit size */
1218 0 /* limit granularity (byte/page units)*/ },
1219/* GBIOSCODE32_SEL 10 BIOS 32-bit interface (32bit Code) */
1220{ 0, /* segment base address (overwritten) */
1221 0xfffff, /* length */
1222 SDT_MEMERA, /* segment type */
1223 0, /* segment descriptor priority level */
1224 1, /* segment descriptor present */
1225 0, 0,
1226 0, /* default 32 vs 16 bit size */
1227 1 /* limit granularity (byte/page units)*/ },
1228/* GBIOSCODE16_SEL 11 BIOS 32-bit interface (16bit Code) */
1229{ 0, /* segment base address (overwritten) */
1230 0xfffff, /* length */
1231 SDT_MEMERA, /* segment type */
1232 0, /* segment descriptor priority level */
1233 1, /* segment descriptor present */
1234 0, 0,
1235 0, /* default 32 vs 16 bit size */
1236 1 /* limit granularity (byte/page units)*/ },
1237/* GBIOSDATA_SEL 12 BIOS 32-bit interface (Data) */
1238{ 0, /* segment base address (overwritten) */
1239 0xfffff, /* length */
1240 SDT_MEMRWA, /* segment type */
1241 0, /* segment descriptor priority level */
1242 1, /* segment descriptor present */
1243 0, 0,
1244 1, /* default 32 vs 16 bit size */
1245 1 /* limit granularity (byte/page units)*/ },
1246/* GBIOSUTIL_SEL 13 BIOS 16-bit interface (Utility) */
1247{ 0, /* segment base address (overwritten) */
1248 0xfffff, /* length */
1249 SDT_MEMRWA, /* segment type */
1250 0, /* segment descriptor priority level */
1251 1, /* segment descriptor present */
1252 0, 0,
1253 0, /* default 32 vs 16 bit size */
1254 1 /* limit granularity (byte/page units)*/ },
1255/* GBIOSARGS_SEL 14 BIOS 16-bit interface (Arguments) */
1256{ 0, /* segment base address (overwritten) */
1257 0xfffff, /* length */
1258 SDT_MEMRWA, /* segment type */
1259 0, /* segment descriptor priority level */
1260 1, /* segment descriptor present */
1261 0, 0,
1262 0, /* default 32 vs 16 bit size */
1263 1 /* limit granularity (byte/page units)*/ },
806bf111
MD
1264/* GTLS_START 15 TLS */
1265{ 0x0, /* segment base address */
1266 0x0, /* length */
1267 0, /* segment type */
1268 0, /* segment descriptor priority level */
1269 0, /* segment descriptor present */
1270 0, 0,
1271 0, /* default 32 vs 16 bit size */
1272 0 /* limit granularity (byte/page units)*/ },
1273/* GTLS_START+1 16 TLS */
1274{ 0x0, /* segment base address */
1275 0x0, /* length */
1276 0, /* segment type */
1277 0, /* segment descriptor priority level */
1278 0, /* segment descriptor present */
1279 0, 0,
1280 0, /* default 32 vs 16 bit size */
1281 0 /* limit granularity (byte/page units)*/ },
1282/* GTLS_END 17 TLS */
1283{ 0x0, /* segment base address */
1284 0x0, /* length */
1285 0, /* segment type */
1286 0, /* segment descriptor priority level */
1287 0, /* segment descriptor present */
1288 0, 0,
1289 0, /* default 32 vs 16 bit size */
1290 0 /* limit granularity (byte/page units)*/ },
984263bc
MD
1291};
1292
1293static struct soft_segment_descriptor ldt_segs[] = {
1294 /* Null Descriptor - overwritten by call gate */
1295{ 0x0, /* segment base address */
1296 0x0, /* length - all address space */
1297 0, /* segment type */
1298 0, /* segment descriptor priority level */
1299 0, /* segment descriptor present */
1300 0, 0,
1301 0, /* default 32 vs 16 bit size */
1302 0 /* limit granularity (byte/page units)*/ },
1303 /* Null Descriptor - overwritten by call gate */
1304{ 0x0, /* segment base address */
1305 0x0, /* length - all address space */
1306 0, /* segment type */
1307 0, /* segment descriptor priority level */
1308 0, /* segment descriptor present */
1309 0, 0,
1310 0, /* default 32 vs 16 bit size */
1311 0 /* limit granularity (byte/page units)*/ },
1312 /* Null Descriptor - overwritten by call gate */
1313{ 0x0, /* segment base address */
1314 0x0, /* length - all address space */
1315 0, /* segment type */
1316 0, /* segment descriptor priority level */
1317 0, /* segment descriptor present */
1318 0, 0,
1319 0, /* default 32 vs 16 bit size */
1320 0 /* limit granularity (byte/page units)*/ },
1321 /* Code Descriptor for user */
1322{ 0x0, /* segment base address */
1323 0xfffff, /* length - all address space */
1324 SDT_MEMERA, /* segment type */
1325 SEL_UPL, /* segment descriptor priority level */
1326 1, /* segment descriptor present */
1327 0, 0,
1328 1, /* default 32 vs 16 bit size */
1329 1 /* limit granularity (byte/page units)*/ },
1330 /* Null Descriptor - overwritten by call gate */
1331{ 0x0, /* segment base address */
1332 0x0, /* length - all address space */
1333 0, /* segment type */
1334 0, /* segment descriptor priority level */
1335 0, /* segment descriptor present */
1336 0, 0,
1337 0, /* default 32 vs 16 bit size */
1338 0 /* limit granularity (byte/page units)*/ },
1339 /* Data Descriptor for user */
1340{ 0x0, /* segment base address */
1341 0xfffff, /* length - all address space */
1342 SDT_MEMRWA, /* segment type */
1343 SEL_UPL, /* segment descriptor priority level */
1344 1, /* segment descriptor present */
1345 0, 0,
1346 1, /* default 32 vs 16 bit size */
1347 1 /* limit granularity (byte/page units)*/ },
1348};
1349
1350void
f123d5a1 1351setidt(int idx, inthand_t *func, int typ, int dpl, int selec)
984263bc
MD
1352{
1353 struct gate_descriptor *ip;
1354
1355 ip = idt + idx;
1356 ip->gd_looffset = (int)func;
1357 ip->gd_selector = selec;
1358 ip->gd_stkcpy = 0;
1359 ip->gd_xx = 0;
1360 ip->gd_type = typ;
1361 ip->gd_dpl = dpl;
1362 ip->gd_p = 1;
1363 ip->gd_hioffset = ((int)func)>>16 ;
1364}
1365
1366#define IDTVEC(name) __CONCAT(X,name)
1367
1368extern inthand_t
1369 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1370 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1371 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
f7bc9806
MD
1372 IDTVEC(page), IDTVEC(mchk), IDTVEC(fpu), IDTVEC(align),
1373 IDTVEC(xmm), IDTVEC(syscall),
1374 IDTVEC(rsvd0);
a64ba182 1375extern inthand_t
f9a13fc4 1376 IDTVEC(int0x80_syscall);
984263bc 1377
f7bc9806
MD
1378#ifdef DEBUG_INTERRUPTS
1379extern inthand_t *Xrsvdary[256];
1380#endif
1381
984263bc 1382void
f123d5a1 1383sdtossd(struct segment_descriptor *sd, struct soft_segment_descriptor *ssd)
984263bc
MD
1384{
1385 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1386 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1387 ssd->ssd_type = sd->sd_type;
1388 ssd->ssd_dpl = sd->sd_dpl;
1389 ssd->ssd_p = sd->sd_p;
1390 ssd->ssd_def32 = sd->sd_def32;
1391 ssd->ssd_gran = sd->sd_gran;
1392}
1393
984263bc
MD
1394/*
1395 * Populate the (physmap) array with base/bound pairs describing the
1396 * available physical memory in the system, then test this memory and
1397 * build the phys_avail array describing the actually-available memory.
1398 *
1399 * If we cannot accurately determine the physical memory map, then use
1400 * value from the 0xE801 call, and failing that, the RTC.
1401 *
1402 * Total memory size may be set by the kernel environment variable
1403 * hw.physmem or the compile-time define MAXMEM.
1404 */
1405static void
1406getmemsize(int first)
1407{
b24cd69c 1408 int i, physmap_idx, pa_indx, da_indx;
984263bc
MD
1409 int hasbrokenint12;
1410 u_int basemem, extmem;
1411 struct vm86frame vmf;
1412 struct vm86context vmc;
ff1a75a1
MD
1413 vm_offset_t pa;
1414 vm_offset_t physmap[PHYSMAP_ENTRIES*2];
b5b32410 1415 pt_entry_t *pte;
555da584 1416 quad_t maxmem;
984263bc
MD
1417 struct {
1418 u_int64_t base;
1419 u_int64_t length;
1420 u_int32_t type;
1421 } *smap;
28abdbbb 1422 quad_t dcons_addr, dcons_size;
984263bc 1423
984263bc
MD
1424 bzero(&vmf, sizeof(struct vm86frame));
1425 bzero(physmap, sizeof(physmap));
1426 basemem = 0;
1427
1428 /*
1429 * Some newer BIOSes has broken INT 12H implementation which cause
1430 * kernel panic immediately. In this case, we need to scan SMAP
1431 * with INT 15:E820 first, then determine base memory size.
1432 */
2ed482dc
MN
1433 hasbrokenint12 = 0;
1434 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
984263bc
MD
1435 if (hasbrokenint12) {
1436 goto int15e820;
1437 }
1438
1439 /*
7febcc6e
MD
1440 * Perform "base memory" related probes & setup. If we get a crazy
1441 * value give the bios some scribble space just in case.
984263bc
MD
1442 */
1443 vm86_intcall(0x12, &vmf);
1444 basemem = vmf.vmf_ax;
1445 if (basemem > 640) {
26be20a0 1446 kprintf("Preposterous BIOS basemem of %uK, "
7febcc6e
MD
1447 "truncating to < 640K\n", basemem);
1448 basemem = 636;
984263bc
MD
1449 }
1450
1451 /*
1452 * XXX if biosbasemem is now < 640, there is a `hole'
1453 * between the end of base memory and the start of
1454 * ISA memory. The hole may be empty or it may
1455 * contain BIOS code or data. Map it read/write so
1456 * that the BIOS can write to it. (Memory from 0 to
1457 * the physical end of the kernel is mapped read-only
1458 * to begin with and then parts of it are remapped.
1459 * The parts that aren't remapped form holes that
1460 * remain read-only and are unused by the kernel.
1461 * The base memory area is below the physical end of
1462 * the kernel and right now forms a read-only hole.
1463 * The part of it from PAGE_SIZE to
1464 * (trunc_page(biosbasemem * 1024) - 1) will be
1465 * remapped and used by the kernel later.)
1466 *
1467 * This code is similar to the code used in
1468 * pmap_mapdev, but since no memory needs to be
1469 * allocated we simply change the mapping.
1470 */
1471 for (pa = trunc_page(basemem * 1024);
1472 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1473 pte = vtopte(pa + KERNBASE);
984263bc
MD
1474 *pte = pa | PG_RW | PG_V;
1475 }
1476
1477 /*
1478 * if basemem != 640, map pages r/w into vm86 page table so
1479 * that the bios can scribble on it.
1480 */
b5b32410 1481 pte = vm86paddr;
984263bc
MD
1482 for (i = basemem / 4; i < 160; i++)
1483 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1484
1485int15e820:
1486 /*
1487 * map page 1 R/W into the kernel page table so we can use it
1488 * as a buffer. The kernel will unmap this page later.
1489 */
b5b32410 1490 pte = vtopte(KERNBASE + (1 << PAGE_SHIFT));
984263bc
MD
1491 *pte = (1 << PAGE_SHIFT) | PG_RW | PG_V;
1492
1493 /*
1494 * get memory map with INT 15:E820
1495 */
1496#define SMAPSIZ sizeof(*smap)
1497#define SMAP_SIG 0x534D4150 /* 'SMAP' */
1498
1499 vmc.npages = 0;
1500 smap = (void *)vm86_addpage(&vmc, 1, KERNBASE + (1 << PAGE_SHIFT));
1501 vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
1502
1503 physmap_idx = 0;
1504 vmf.vmf_ebx = 0;
1505 do {
1506 vmf.vmf_eax = 0xE820;
1507 vmf.vmf_edx = SMAP_SIG;
1508 vmf.vmf_ecx = SMAPSIZ;
1509 i = vm86_datacall(0x15, &vmf, &vmc);
1510 if (i || vmf.vmf_eax != SMAP_SIG)
1511 break;
1512 if (boothowto & RB_VERBOSE)
26be20a0 1513 kprintf("SMAP type=%02x base=%08x %08x len=%08x %08x\n",
984263bc
MD
1514 smap->type,
1515 *(u_int32_t *)((char *)&smap->base + 4),
1516 (u_int32_t)smap->base,
1517 *(u_int32_t *)((char *)&smap->length + 4),
1518 (u_int32_t)smap->length);
1519
1520 if (smap->type != 0x01)
1521 goto next_run;
1522
1523 if (smap->length == 0)
1524 goto next_run;
1525
1bda0d3d
MD
1526 Realmem += smap->length;
1527
1528 if (smap->base >= 0xffffffffLLU) {
9c3db322 1529 kprintf("%ju MB of memory above 4GB ignored\n",
1bda0d3d 1530 (uintmax_t)(smap->length / 1024 / 1024));
984263bc
MD
1531 goto next_run;
1532 }
1533
1534 for (i = 0; i <= physmap_idx; i += 2) {
1535 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD
1536 if (boothowto & RB_VERBOSE) {
1537 kprintf("Overlapping or non-montonic "
1538 "memory region, ignoring "
1539 "second region\n");
1540 }
1541 Realmem -= smap->length;
984263bc
MD
1542 goto next_run;
1543 }
1544 }
1545
1546 if (smap->base == physmap[physmap_idx + 1]) {
1547 physmap[physmap_idx + 1] += smap->length;
1548 goto next_run;
1549 }
1550
1551 physmap_idx += 2;
ff1a75a1 1552 if (physmap_idx == PHYSMAP_ENTRIES*2) {
1bda0d3d
MD
1553 kprintf("Too many segments in the physical "
1554 "address map, giving up\n");
984263bc
MD
1555 break;
1556 }
1557 physmap[physmap_idx] = smap->base;
1558 physmap[physmap_idx + 1] = smap->base + smap->length;
1559next_run:
6b08710e 1560 ; /* fix GCC3.x warning */
984263bc
MD
1561 } while (vmf.vmf_ebx != 0);
1562
1563 /*
1564 * Perform "base memory" related probes & setup based on SMAP
1565 */
1566 if (basemem == 0) {
1567 for (i = 0; i <= physmap_idx; i += 2) {
1568 if (physmap[i] == 0x00000000) {
1569 basemem = physmap[i + 1] / 1024;
1570 break;
1571 }
1572 }
1573
1574 if (basemem == 0) {
1575 basemem = 640;
1576 }
1577
1578 if (basemem > 640) {
1bda0d3d
MD
1579 kprintf("Preposterous BIOS basemem of %uK, "
1580 "truncating to 640K\n", basemem);
984263bc
MD
1581 basemem = 640;
1582 }
1583
1584 for (pa = trunc_page(basemem * 1024);
1585 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1586 pte = vtopte(pa + KERNBASE);
984263bc
MD
1587 *pte = pa | PG_RW | PG_V;
1588 }
1589
b5b32410 1590 pte = vm86paddr;
984263bc
MD
1591 for (i = basemem / 4; i < 160; i++)
1592 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1593 }
1594
1595 if (physmap[1] != 0)
1596 goto physmap_done;
1597
1598 /*
1599 * If we failed above, try memory map with INT 15:E801
1600 */
1601 vmf.vmf_ax = 0xE801;
1602 if (vm86_intcall(0x15, &vmf) == 0) {
1603 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1604 } else {
1605#if 0
1606 vmf.vmf_ah = 0x88;
1607 vm86_intcall(0x15, &vmf);
1608 extmem = vmf.vmf_ax;
1609#else
1610 /*
1611 * Prefer the RTC value for extended memory.
1612 */
1613 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1614#endif
1615 }
1616
1617 /*
1618 * Special hack for chipsets that still remap the 384k hole when
1619 * there's 16MB of memory - this really confuses people that
1620 * are trying to use bus mastering ISA controllers with the
1621 * "16MB limit"; they only have 16MB, but the remapping puts
1622 * them beyond the limit.
1623 *
1624 * If extended memory is between 15-16MB (16-17MB phys address range),
1625 * chop it to 15MB.
1626 */
1627 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1628 extmem = 15 * 1024;
1629
1630 physmap[0] = 0;
1631 physmap[1] = basemem * 1024;
1632 physmap_idx = 2;
1633 physmap[physmap_idx] = 0x100000;
1634 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1635
1636physmap_done:
1637 /*
1638 * Now, physmap contains a map of physical memory.
1639 */
1640
1641#ifdef SMP
17a9f566 1642 /* make hole for AP bootstrap code YYY */
c0c5de70 1643 physmap[1] = mp_bootaddress(physmap[1]);
984263bc 1644
1876681a
SZ
1645 /* Save EBDA address, if any */
1646 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1647 ebda_addr <<= 4;
984263bc
MD
1648#endif
1649
1650 /*
1651 * Maxmem isn't the "maximum memory", it's one larger than the
1652 * highest page of the physical address space. It should be
1653 * called something like "Maxphyspage". We may adjust this
1654 * based on ``hw.physmem'' and the results of the memory test.
1655 */
1656 Maxmem = atop(physmap[physmap_idx + 1]);
1657
1658#ifdef MAXMEM
1659 Maxmem = MAXMEM / 4;
1660#endif
1661
555da584
MD
1662 if (kgetenv_quad("hw.physmem", &maxmem))
1663 Maxmem = atop(maxmem);
984263bc
MD
1664
1665 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1666 (boothowto & RB_VERBOSE))
26be20a0 1667 kprintf("Physical memory use set to %lluK\n", Maxmem * 4);
984263bc
MD
1668
1669 /*
1670 * If Maxmem has been increased beyond what the system has detected,
1671 * extend the last memory segment to the new limit.
1672 */
1673 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1674 physmap[physmap_idx + 1] = ptoa(Maxmem);
1675
1676 /* call pmap initialization to make new kernel address space */
1677 pmap_bootstrap(first, 0);
1678
1679 /*
1680 * Size up each available chunk of physical memory.
1681 */
1682 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1683 pa_indx = 0;
b24cd69c 1684 da_indx = 1;
984263bc
MD
1685 phys_avail[pa_indx++] = physmap[0];
1686 phys_avail[pa_indx] = physmap[0];
b24cd69c
AH
1687 dump_avail[da_indx] = physmap[0];
1688
b5b32410 1689 pte = CMAP1;
984263bc
MD
1690
1691 /*
28abdbbb
HS
1692 * Get dcons buffer address
1693 */
bc01a404
MD
1694 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1695 kgetenv_quad("dcons.size", &dcons_size) == 0)
28abdbbb
HS
1696 dcons_addr = 0;
1697
1698 /*
984263bc
MD
1699 * physmap is in bytes, so when converting to page boundaries,
1700 * round up the start address and round down the end address.
1701 */
1702 for (i = 0; i <= physmap_idx; i += 2) {
1703 vm_offset_t end;
1704
1705 end = ptoa(Maxmem);
1706 if (physmap[i + 1] < end)
1707 end = trunc_page(physmap[i + 1]);
1708 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
b24cd69c 1709 int tmp, page_bad, full;
984263bc
MD
1710#if 0
1711 int *ptr = 0;
1712#else
1713 int *ptr = (int *)CADDR1;
1714#endif
b24cd69c 1715 full = FALSE;
984263bc
MD
1716
1717 /*
1718 * block out kernel memory as not available.
1719 */
1720 if (pa >= 0x100000 && pa < first)
b24cd69c 1721 goto do_dump_avail;
984263bc 1722
28abdbbb
HS
1723 /*
1724 * block out dcons buffer
1725 */
1726 if (dcons_addr > 0
1727 && pa >= trunc_page(dcons_addr)
1728 && pa < dcons_addr + dcons_size)
b24cd69c 1729 goto do_dump_avail;
28abdbbb 1730
984263bc
MD
1731 page_bad = FALSE;
1732
1733 /*
1734 * map page into kernel: valid, read/write,non-cacheable
1735 */
1736 *pte = pa | PG_V | PG_RW | PG_N;
0f7a3396 1737 cpu_invltlb();
984263bc
MD
1738
1739 tmp = *(int *)ptr;
1740 /*
1741 * Test for alternating 1's and 0's
1742 */
1743 *(volatile int *)ptr = 0xaaaaaaaa;
1744 if (*(volatile int *)ptr != 0xaaaaaaaa) {
1745 page_bad = TRUE;
1746 }
1747 /*
1748 * Test for alternating 0's and 1's
1749 */
1750 *(volatile int *)ptr = 0x55555555;
1751 if (*(volatile int *)ptr != 0x55555555) {
1752 page_bad = TRUE;
1753 }
1754 /*
1755 * Test for all 1's
1756 */
1757 *(volatile int *)ptr = 0xffffffff;
1758 if (*(volatile int *)ptr != 0xffffffff) {
1759 page_bad = TRUE;
1760 }
1761 /*
1762 * Test for all 0's
1763 */
1764 *(volatile int *)ptr = 0x0;
1765 if (*(volatile int *)ptr != 0x0) {
1766 page_bad = TRUE;
1767 }
1768 /*
1769 * Restore original value.
1770 */
1771 *(int *)ptr = tmp;
1772
1773 /*
1774 * Adjust array of valid/good pages.
1775 */
1776 if (page_bad == TRUE) {
1777 continue;
1778 }
1779 /*
1780 * If this good page is a continuation of the
1781 * previous set of good pages, then just increase
1782 * the end pointer. Otherwise start a new chunk.
1783 * Note that "end" points one higher than end,
1784 * making the range >= start and < end.
1785 * If we're also doing a speculative memory
1786 * test and we at or past the end, bump up Maxmem
1787 * so that we keep going. The first bad page
1788 * will terminate the loop.
1789 */
1790 if (phys_avail[pa_indx] == pa) {
1791 phys_avail[pa_indx] += PAGE_SIZE;
1792 } else {
1793 pa_indx++;
ff1a75a1 1794 if (pa_indx >= PHYSMAP_ENTRIES*2) {
26be20a0 1795 kprintf("Too many holes in the physical address space, giving up\n");
984263bc 1796 pa_indx--;
b24cd69c
AH
1797 full = TRUE;
1798 goto do_dump_avail;
984263bc
MD
1799 }
1800 phys_avail[pa_indx++] = pa; /* start */
1801 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1802 }
1803 physmem++;
b24cd69c
AH
1804do_dump_avail:
1805 if (dump_avail[da_indx] == pa) {
1806 dump_avail[da_indx] += PAGE_SIZE;
1807 } else {
1808 da_indx++;
1809 if (da_indx >= PHYSMAP_ENTRIES*2) {
1810 da_indx--;
1811 goto do_next;
1812 }
1813 dump_avail[da_indx++] = pa; /* start */
1814 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1815 }
1816do_next:
1817 if (full)
1818 break;
1819
984263bc
MD
1820 }
1821 }
1822 *pte = 0;
0f7a3396 1823 cpu_invltlb();
984263bc
MD
1824
1825 /*
1826 * XXX
1827 * The last chunk must contain at least one page plus the message
1828 * buffer to avoid complicating other code (message buffer address
1829 * calculation, etc.).
1830 */
1831 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1832 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) {
1833 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1834 phys_avail[pa_indx--] = 0;
1835 phys_avail[pa_indx--] = 0;
1836 }
1837
1838 Maxmem = atop(phys_avail[pa_indx]);
1839
1840 /* Trim off space for the message buffer. */
1841 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE);
1842
1843 avail_end = phys_avail[pa_indx];
1844}
1845
79b62055
MN
1846#ifdef SMP
1847int apic_io_enable = 1; /* Enabled by default */
1848TUNABLE_INT("hw.apic_io_enable", &apic_io_enable);
1849extern struct machintr_abi MachIntrABI_APIC;
1850#endif
1851
1852extern struct machintr_abi MachIntrABI_ICU;
1853struct machintr_abi MachIntrABI;
1854
f7bc9806
MD
1855/*
1856 * IDT VECTORS:
1857 * 0 Divide by zero
1858 * 1 Debug
1859 * 2 NMI
1860 * 3 BreakPoint
1861 * 4 OverFlow
1862 * 5 Bound-Range
1863 * 6 Invalid OpCode
1864 * 7 Device Not Available (x87)
1865 * 8 Double-Fault
1866 * 9 Coprocessor Segment overrun (unsupported, reserved)
1867 * 10 Invalid-TSS
1868 * 11 Segment not present
1869 * 12 Stack
1870 * 13 General Protection
1871 * 14 Page Fault
1872 * 15 Reserved
1873 * 16 x87 FP Exception pending
1874 * 17 Alignment Check
1875 * 18 Machine Check
1876 * 19 SIMD floating point
1877 * 20-31 reserved
1878 * 32-255 INTn/external sources
1879 */
984263bc 1880void
17a9f566 1881init386(int first)
984263bc
MD
1882{
1883 struct gate_descriptor *gdp;
1884 int gsel_tss, metadata_missing, off, x;
85100692 1885 struct mdglobaldata *gd;
984263bc
MD
1886
1887 /*
1888 * Prevent lowering of the ipl if we call tsleep() early.
1889 */
85100692 1890 gd = &CPU_prvspace[0].mdglobaldata;
8a8d5d85 1891 bzero(gd, sizeof(*gd));
984263bc 1892
85100692 1893 gd->mi.gd_curthread = &thread0;
4e7c41c5 1894 thread0.td_gd = &gd->mi;
984263bc
MD
1895
1896 atdevbase = ISA_HOLE_START + KERNBASE;
1897
1898 metadata_missing = 0;
1899 if (bootinfo.bi_modulep) {
1900 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1901 preload_bootstrap_relocate(KERNBASE);
1902 } else {
1903 metadata_missing = 1;
1904 }
1905 if (bootinfo.bi_envp)
1906 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1907
c5cc06e3 1908 /*
79b62055
MN
1909 * Setup MachIntrABI
1910 * XXX: Where is the correct place for it?
1911 */
1912 MachIntrABI = MachIntrABI_ICU;
1913#ifdef SMP
1914 TUNABLE_INT_FETCH("hw.apic_io_enable", &apic_io_enable);
1915 if (apic_io_enable)
1916 MachIntrABI = MachIntrABI_APIC;
1917#endif
1918
1919 /*
b45759e1
MD
1920 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1921 * and ncpus_fit_mask remain 0.
c5cc06e3 1922 */
4e8e646b 1923 ncpus = 1;
c5cc06e3 1924 ncpus2 = 1;
b45759e1 1925 ncpus_fit = 1;
984263bc
MD
1926 /* Init basic tunables, hz etc */
1927 init_param1();
1928
1929 /*
1930 * make gdt memory segments, the code segment goes up to end of the
1931 * page with etext in it, the data segment goes to the end of
1932 * the address space
1933 */
1934 /*
1935 * XXX text protection is temporarily (?) disabled. The limit was
1936 * i386_btop(round_page(etext)) - 1.
1937 */
1938 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1939 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
17a9f566 1940
984263bc
MD
1941 gdt_segs[GPRIV_SEL].ssd_limit =
1942 atop(sizeof(struct privatespace) - 1);
8ad65e08 1943 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[0];
984263bc 1944 gdt_segs[GPROC0_SEL].ssd_base =
85100692 1945 (int) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
17a9f566 1946
85100692 1947 gd->mi.gd_prvspace = &CPU_prvspace[0];
17a9f566 1948
84b592ba
MD
1949 /*
1950 * Note: on both UP and SMP curthread must be set non-NULL
1951 * early in the boot sequence because the system assumes
1952 * that 'curthread' is never NULL.
1953 */
984263bc
MD
1954
1955 for (x = 0; x < NGDT; x++) {
1956#ifdef BDE_DEBUGGER
1957 /* avoid overwriting db entries with APM ones */
1958 if (x >= GAPMCODE32_SEL && x <= GAPMDATA_SEL)
1959 continue;
1960#endif
1961 ssdtosd(&gdt_segs[x], &gdt[x].sd);
1962 }
1963
1964 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1965 r_gdt.rd_base = (int) gdt;
1966 lgdt(&r_gdt);
1967
73e4f7b9
MD
1968 mi_gdinit(&gd->mi, 0);
1969 cpu_gdinit(gd, 0);
6bf59cd2 1970 mi_proc0init(&gd->mi, proc0paddr);
e43a034f 1971 safepri = TDPRI_MAX;
73e4f7b9 1972
984263bc
MD
1973 /* make ldt memory segments */
1974 /*
88181b08 1975 * XXX - VM_MAX_USER_ADDRESS is an end address, not a max. And it
984263bc
MD
1976 * should be spelled ...MAX_USER...
1977 */
88181b08
MD
1978 ldt_segs[LUCODE_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
1979 ldt_segs[LUDATA_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
984263bc
MD
1980 for (x = 0; x < sizeof ldt_segs / sizeof ldt_segs[0]; x++)
1981 ssdtosd(&ldt_segs[x], &ldt[x].sd);
1982
1983 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
1984 lldt(_default_ldt);
17a9f566 1985 gd->gd_currentldt = _default_ldt;
8a8d5d85
MD
1986 /* spinlocks and the BGL */
1987 init_locks();
984263bc 1988
2f839e54
MD
1989 /*
1990 * Setup the hardware exception table. Most exceptions use
1991 * SDT_SYS386TGT, known as a 'trap gate'. Trap gates leave
1992 * interrupts enabled. VM page faults use SDT_SYS386IGT, known as
1993 * an 'interrupt trap gate', which disables interrupts on entry,
1994 * in order to be able to poll the appropriate CRn register to
1995 * determine the fault address.
1996 */
f7bc9806
MD
1997 for (x = 0; x < NIDT; x++) {
1998#ifdef DEBUG_INTERRUPTS
1999 setidt(x, Xrsvdary[x], SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2000#else
2001 setidt(x, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2002#endif
2003 }
984263bc
MD
2004 setidt(0, &IDTVEC(div), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2005 setidt(1, &IDTVEC(dbg), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2006 setidt(2, &IDTVEC(nmi), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2007 setidt(3, &IDTVEC(bpt), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2008 setidt(4, &IDTVEC(ofl), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2009 setidt(5, &IDTVEC(bnd), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2010 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2011 setidt(7, &IDTVEC(dna), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2012 setidt(8, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, SEL_KPL));
2013 setidt(9, &IDTVEC(fpusegm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2014 setidt(10, &IDTVEC(tss), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2015 setidt(11, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2016 setidt(12, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2017 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2018 setidt(14, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
f7bc9806 2019 setidt(15, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc
MD
2020 setidt(16, &IDTVEC(fpu), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2021 setidt(17, &IDTVEC(align), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2022 setidt(18, &IDTVEC(mchk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2023 setidt(19, &IDTVEC(xmm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2024 setidt(0x80, &IDTVEC(int0x80_syscall),
2025 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2026
2027 r_idt.rd_limit = sizeof(idt0) - 1;
2028 r_idt.rd_base = (int) idt;
2029 lidt(&r_idt);
2030
2031 /*
2032 * Initialize the console before we print anything out.
2033 */
2034 cninit();
2035
2036 if (metadata_missing)
26be20a0 2037 kprintf("WARNING: loader(8) metadata is missing!\n");
984263bc 2038
984263bc
MD
2039#if NISA >0
2040 isa_defaultirq();
2041#endif
2042 rand_initialize();
2043
2044#ifdef DDB
2045 kdb_init();
2046 if (boothowto & RB_KDB)
2047 Debugger("Boot flags requested debugger");
2048#endif
2049
2050 finishidentcpu(); /* Final stage of CPU initialization */
2051 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2052 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2053 initializecpu(); /* Initialize CPU registers */
2054
b7c628e4
MD
2055 /*
2056 * make an initial tss so cpu can get interrupt stack on syscall!
2057 * The 16 bytes is to save room for a VM86 context.
2058 */
17a9f566
MD
2059 gd->gd_common_tss.tss_esp0 = (int) thread0.td_pcb - 16;
2060 gd->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL) ;
984263bc 2061 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
17a9f566
MD
2062 gd->gd_tss_gdt = &gdt[GPROC0_SEL].sd;
2063 gd->gd_common_tssd = *gd->gd_tss_gdt;
85100692 2064 gd->gd_common_tss.tss_ioopt = (sizeof gd->gd_common_tss) << 16;
984263bc
MD
2065 ltr(gsel_tss);
2066
2067 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
2068 dblfault_tss.tss_esp2 = (int) &dblfault_stack[sizeof(dblfault_stack)];
2069 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
2070 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
2071 dblfault_tss.tss_cr3 = (int)IdlePTD;
2072 dblfault_tss.tss_eip = (int) dblfault_handler;
2073 dblfault_tss.tss_eflags = PSL_KERNEL;
2074 dblfault_tss.tss_ds = dblfault_tss.tss_es =
2075 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
2076 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
2077 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
2078 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
2079
2080 vm86_initialize();
2081 getmemsize(first);
2082 init_param2(physmem);
2083
2084 /* now running on new page tables, configured,and u/iom is accessible */
2085
2086 /* Map the message buffer. */
2087 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2088 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2089
2090 msgbufinit(msgbufp, MSGBUF_SIZE);
2091
2092 /* make a call gate to reenter kernel with */
2093 gdp = &ldt[LSYS5CALLS_SEL].gd;
2094
2095 x = (int) &IDTVEC(syscall);
2096 gdp->gd_looffset = x++;
2097 gdp->gd_selector = GSEL(GCODE_SEL,SEL_KPL);
2098 gdp->gd_stkcpy = 1;
2099 gdp->gd_type = SDT_SYS386CGT;
2100 gdp->gd_dpl = SEL_UPL;
2101 gdp->gd_p = 1;
2102 gdp->gd_hioffset = ((int) &IDTVEC(syscall)) >>16;
2103
2104 /* XXX does this work? */
2105 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
2106 ldt[LSOL26CALLS_SEL] = ldt[LSYS5CALLS_SEL];
2107
2108 /* transfer to user mode */
2109
2110 _ucodesel = LSEL(LUCODE_SEL, SEL_UPL);
2111 _udatasel = LSEL(LUDATA_SEL, SEL_UPL);
2112
2113 /* setup proc 0's pcb */
b7c628e4
MD
2114 thread0.td_pcb->pcb_flags = 0;
2115 thread0.td_pcb->pcb_cr3 = (int)IdlePTD; /* should already be setup */
b7c628e4 2116 thread0.td_pcb->pcb_ext = 0;
08f2f1bb 2117 lwp0.lwp_md.md_regs = &proc0_tf;
984263bc
MD
2118}
2119
8ad65e08 2120/*
17a9f566
MD
2121 * Initialize machine-dependant portions of the global data structure.
2122 * Note that the global data area and cpu0's idlestack in the private
2123 * data space were allocated in locore.
ef0fdad1
MD
2124 *
2125 * Note: the idlethread's cpl is 0
73e4f7b9
MD
2126 *
2127 * WARNING! Called from early boot, 'mycpu' may not work yet.
8ad65e08
MD
2128 */
2129void
85100692 2130cpu_gdinit(struct mdglobaldata *gd, int cpu)
8ad65e08 2131{
7d0bac62 2132 if (cpu)
a2a5ad0d 2133 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
17a9f566 2134
f470d0c8
MD
2135 lwkt_init_thread(&gd->mi.gd_idlethread,
2136 gd->mi.gd_prvspace->idlestack,
d3d32139 2137 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 2138 0, &gd->mi);
a2a5ad0d
MD
2139 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2140 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2141 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2142 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
8ad65e08
MD
2143}
2144
0cd275af
MD
2145int
2146is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2147{
2148 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2149 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2150 return (TRUE);
2151 }
2152 return (FALSE);
2153}
2154
12e4aaff
MD
2155struct globaldata *
2156globaldata_find(int cpu)
2157{
2158 KKASSERT(cpu >= 0 && cpu < ncpus);
2159 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2160}
2161
984263bc
MD
2162#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2163static void f00f_hack(void *unused);
ba39e2e0 2164SYSINIT(f00f_hack, SI_BOOT2_BIOS, SI_ORDER_ANY, f00f_hack, NULL);
984263bc
MD
2165
2166static void
17a9f566
MD
2167f00f_hack(void *unused)
2168{
984263bc 2169 struct gate_descriptor *new_idt;
984263bc
MD
2170 vm_offset_t tmp;
2171
2172 if (!has_f00f_bug)
2173 return;
2174
26be20a0 2175 kprintf("Intel Pentium detected, installing workaround for F00F bug\n");
984263bc
MD
2176
2177 r_idt.rd_limit = sizeof(idt0) - 1;
2178
e4846942 2179 tmp = kmem_alloc(&kernel_map, PAGE_SIZE * 2);
984263bc
MD
2180 if (tmp == 0)
2181 panic("kmem_alloc returned 0");
2182 if (((unsigned int)tmp & (PAGE_SIZE-1)) != 0)
2183 panic("kmem_alloc returned non-page-aligned memory");
2184 /* Put the first seven entries in the lower page */
2185 new_idt = (struct gate_descriptor*)(tmp + PAGE_SIZE - (7*8));
2186 bcopy(idt, new_idt, sizeof(idt0));
2187 r_idt.rd_base = (int)new_idt;
2188 lidt(&r_idt);
2189 idt = new_idt;
e4846942 2190 if (vm_map_protect(&kernel_map, tmp, tmp + PAGE_SIZE,
984263bc
MD
2191 VM_PROT_READ, FALSE) != KERN_SUCCESS)
2192 panic("vm_map_protect failed");
2193 return;
2194}
2195#endif /* defined(I586_CPU) && !NO_F00F_HACK */
2196
2197int
08f2f1bb 2198ptrace_set_pc(struct lwp *lp, unsigned long addr)
984263bc 2199{
08f2f1bb 2200 lp->lwp_md.md_regs->tf_eip = addr;
984263bc
MD
2201 return (0);
2202}
2203
2204int
e9182c58 2205ptrace_single_step(struct lwp *lp)
984263bc 2206{
e9182c58 2207 lp->lwp_md.md_regs->tf_eflags |= PSL_T;
984263bc
MD
2208 return (0);
2209}
2210
f123d5a1 2211int
e9182c58 2212fill_regs(struct lwp *lp, struct reg *regs)
984263bc 2213{
984263bc
MD
2214 struct trapframe *tp;
2215
e9182c58 2216 tp = lp->lwp_md.md_regs;
4e7c41c5 2217 regs->r_gs = tp->tf_gs;
984263bc
MD
2218 regs->r_fs = tp->tf_fs;
2219 regs->r_es = tp->tf_es;
2220 regs->r_ds = tp->tf_ds;
2221 regs->r_edi = tp->tf_edi;
2222 regs->r_esi = tp->tf_esi;
2223 regs->r_ebp = tp->tf_ebp;
2224 regs->r_ebx = tp->tf_ebx;
2225 regs->r_edx = tp->tf_edx;
2226 regs->r_ecx = tp->tf_ecx;
2227 regs->r_eax = tp->tf_eax;
2228 regs->r_eip = tp->tf_eip;
2229 regs->r_cs = tp->tf_cs;
2230 regs->r_eflags = tp->tf_eflags;
2231 regs->r_esp = tp->tf_esp;
2232 regs->r_ss = tp->tf_ss;
984263bc
MD
2233 return (0);
2234}
2235
2236int
e9182c58 2237set_regs(struct lwp *lp, struct reg *regs)
984263bc 2238{
984263bc
MD
2239 struct trapframe *tp;
2240
e9182c58 2241 tp = lp->lwp_md.md_regs;
984263bc
MD
2242 if (!EFL_SECURE(regs->r_eflags, tp->tf_eflags) ||
2243 !CS_SECURE(regs->r_cs))
2244 return (EINVAL);
4e7c41c5 2245 tp->tf_gs = regs->r_gs;
984263bc
MD
2246 tp->tf_fs = regs->r_fs;
2247 tp->tf_es = regs->r_es;
2248 tp->tf_ds = regs->r_ds;
2249 tp->tf_edi = regs->r_edi;
2250 tp->tf_esi = regs->r_esi;
2251 tp->tf_ebp = regs->r_ebp;
2252 tp->tf_ebx = regs->r_ebx;
2253 tp->tf_edx = regs->r_edx;
2254 tp->tf_ecx = regs->r_ecx;
2255 tp->tf_eax = regs->r_eax;
2256 tp->tf_eip = regs->r_eip;
2257 tp->tf_cs = regs->r_cs;
2258 tp->tf_eflags = regs->r_eflags;
2259 tp->tf_esp = regs->r_esp;
2260 tp->tf_ss = regs->r_ss;
984263bc
MD
2261 return (0);
2262}
2263
642a6e88 2264#ifndef CPU_DISABLE_SSE
984263bc 2265static void
f123d5a1 2266fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
984263bc 2267{
c9faf524
RG
2268 struct env87 *penv_87 = &sv_87->sv_env;
2269 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2270 int i;
2271
2272 /* FPU control/status */
2273 penv_87->en_cw = penv_xmm->en_cw;
2274 penv_87->en_sw = penv_xmm->en_sw;
2275 penv_87->en_tw = penv_xmm->en_tw;
2276 penv_87->en_fip = penv_xmm->en_fip;
2277 penv_87->en_fcs = penv_xmm->en_fcs;
2278 penv_87->en_opcode = penv_xmm->en_opcode;
2279 penv_87->en_foo = penv_xmm->en_foo;
2280 penv_87->en_fos = penv_xmm->en_fos;
2281
2282 /* FPU registers */
2283 for (i = 0; i < 8; ++i)
2284 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2285
2286 sv_87->sv_ex_sw = sv_xmm->sv_ex_sw;
2287}
2288
2289static void
f123d5a1 2290set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
984263bc 2291{
c9faf524
RG
2292 struct env87 *penv_87 = &sv_87->sv_env;
2293 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2294 int i;
2295
2296 /* FPU control/status */
2297 penv_xmm->en_cw = penv_87->en_cw;
2298 penv_xmm->en_sw = penv_87->en_sw;
2299 penv_xmm->en_tw = penv_87->en_tw;
2300 penv_xmm->en_fip = penv_87->en_fip;
2301 penv_xmm->en_fcs = penv_87->en_fcs;
2302 penv_xmm->en_opcode = penv_87->en_opcode;
2303 penv_xmm->en_foo = penv_87->en_foo;
2304 penv_xmm->en_fos = penv_87->en_fos;
2305
2306 /* FPU registers */
2307 for (i = 0; i < 8; ++i)
2308 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2309
2310 sv_xmm->sv_ex_sw = sv_87->sv_ex_sw;
2311}
642a6e88 2312#endif /* CPU_DISABLE_SSE */
984263bc
MD
2313
2314int
e9182c58 2315fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2316{
642a6e88 2317#ifndef CPU_DISABLE_SSE
984263bc 2318 if (cpu_fxsr) {
e9182c58
SZ
2319 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2320 (struct save87 *)fpregs);
984263bc
MD
2321 return (0);
2322 }
642a6e88 2323#endif /* CPU_DISABLE_SSE */
e9182c58 2324 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
984263bc
MD
2325 return (0);
2326}
2327
2328int
e9182c58 2329set_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2330{
642a6e88 2331#ifndef CPU_DISABLE_SSE
984263bc
MD
2332 if (cpu_fxsr) {
2333 set_fpregs_xmm((struct save87 *)fpregs,
e9182c58 2334 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
984263bc
MD
2335 return (0);
2336 }
642a6e88 2337#endif /* CPU_DISABLE_SSE */
e9182c58 2338 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
984263bc
MD
2339 return (0);
2340}
2341
2342int
e9182c58 2343fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2344{
e9182c58 2345 if (lp == NULL) {
984263bc
MD
2346 dbregs->dr0 = rdr0();
2347 dbregs->dr1 = rdr1();
2348 dbregs->dr2 = rdr2();
2349 dbregs->dr3 = rdr3();
2350 dbregs->dr4 = rdr4();
2351 dbregs->dr5 = rdr5();
2352 dbregs->dr6 = rdr6();
2353 dbregs->dr7 = rdr7();
e9182c58
SZ
2354 } else {
2355 struct pcb *pcb;
2356
2357 pcb = lp->lwp_thread->td_pcb;
984263bc
MD
2358 dbregs->dr0 = pcb->pcb_dr0;
2359 dbregs->dr1 = pcb->pcb_dr1;
2360 dbregs->dr2 = pcb->pcb_dr2;
2361 dbregs->dr3 = pcb->pcb_dr3;
2362 dbregs->dr4 = 0;
2363 dbregs->dr5 = 0;
2364 dbregs->dr6 = pcb->pcb_dr6;
2365 dbregs->dr7 = pcb->pcb_dr7;
2366 }
2367 return (0);
2368}
2369
2370int
e9182c58 2371set_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2372{
e9182c58 2373 if (lp == NULL) {
984263bc
MD
2374 load_dr0(dbregs->dr0);
2375 load_dr1(dbregs->dr1);
2376 load_dr2(dbregs->dr2);
2377 load_dr3(dbregs->dr3);
2378 load_dr4(dbregs->dr4);
2379 load_dr5(dbregs->dr5);
2380 load_dr6(dbregs->dr6);
2381 load_dr7(dbregs->dr7);
e9182c58
SZ
2382 } else {
2383 struct pcb *pcb;
2384 struct ucred *ucred;
2385 int i;
2386 uint32_t mask1, mask2;
2387
984263bc
MD
2388 /*
2389 * Don't let an illegal value for dr7 get set. Specifically,
2390 * check for undefined settings. Setting these bit patterns
2391 * result in undefined behaviour and can lead to an unexpected
2392 * TRCTRAP.
2393 */
2394 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 8;
2395 i++, mask1 <<= 2, mask2 <<= 2)
2396 if ((dbregs->dr7 & mask1) == mask2)
2397 return (EINVAL);
2398
e9182c58
SZ
2399 pcb = lp->lwp_thread->td_pcb;
2400 ucred = lp->lwp_proc->p_ucred;
2401
984263bc
MD
2402 /*
2403 * Don't let a process set a breakpoint that is not within the
2404 * process's address space. If a process could do this, it
2405 * could halt the system by setting a breakpoint in the kernel
2406 * (if ddb was enabled). Thus, we need to check to make sure
2407 * that no breakpoints are being enabled for addresses outside
2408 * process's address space, unless, perhaps, we were called by
2409 * uid 0.
2410 *
2411 * XXX - what about when the watched area of the user's
2412 * address space is written into from within the kernel
2413 * ... wouldn't that still cause a breakpoint to be generated
2414 * from within kernel mode?
2415 */
e9182c58 2416
895c1f85 2417 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
984263bc
MD
2418 if (dbregs->dr7 & 0x3) {
2419 /* dr0 is enabled */
88181b08 2420 if (dbregs->dr0 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2421 return (EINVAL);
2422 }
e9182c58 2423
984263bc
MD
2424 if (dbregs->dr7 & (0x3<<2)) {
2425 /* dr1 is enabled */
88181b08 2426 if (dbregs->dr1 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2427 return (EINVAL);
2428 }
e9182c58 2429
984263bc
MD
2430 if (dbregs->dr7 & (0x3<<4)) {
2431 /* dr2 is enabled */
88181b08 2432 if (dbregs->dr2 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2433 return (EINVAL);
2434 }
e9182c58 2435
984263bc
MD
2436 if (dbregs->dr7 & (0x3<<6)) {
2437 /* dr3 is enabled */
88181b08 2438 if (dbregs->dr3 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2439 return (EINVAL);
2440 }
2441 }
e9182c58 2442
984263bc
MD
2443 pcb->pcb_dr0 = dbregs->dr0;
2444 pcb->pcb_dr1 = dbregs->dr1;
2445 pcb->pcb_dr2 = dbregs->dr2;
2446 pcb->pcb_dr3 = dbregs->dr3;
2447 pcb->pcb_dr6 = dbregs->dr6;
2448 pcb->pcb_dr7 = dbregs->dr7;
e9182c58 2449
984263bc
MD
2450 pcb->pcb_flags |= PCB_DBREGS;
2451 }
2452
2453 return (0);
2454}
2455
2456/*
2457 * Return > 0 if a hardware breakpoint has been hit, and the
2458 * breakpoint was in user space. Return 0, otherwise.
2459 */
2460int
2461user_dbreg_trap(void)
2462{
2463 u_int32_t dr7, dr6; /* debug registers dr6 and dr7 */
2464 u_int32_t bp; /* breakpoint bits extracted from dr6 */
2465 int nbp; /* number of breakpoints that triggered */
2466 caddr_t addr[4]; /* breakpoint addresses */
2467 int i;
2468
2469 dr7 = rdr7();
2470 if ((dr7 & 0x000000ff) == 0) {
2471 /*
2472 * all GE and LE bits in the dr7 register are zero,
2473 * thus the trap couldn't have been caused by the
2474 * hardware debug registers
2475 */
2476 return 0;
2477 }
2478
2479 nbp = 0;
2480 dr6 = rdr6();
2481 bp = dr6 & 0x0000000f;
2482
2483 if (!bp) {
2484 /*
2485 * None of the breakpoint bits are set meaning this
2486 * trap was not caused by any of the debug registers
2487 */
2488 return 0;
2489 }
2490
2491 /*
2492 * at least one of the breakpoints were hit, check to see
2493 * which ones and if any of them are user space addresses
2494 */
2495
2496 if (bp & 0x01) {
2497 addr[nbp++] = (caddr_t)rdr0();
2498 }
2499 if (bp & 0x02) {
2500 addr[nbp++] = (caddr_t)rdr1();
2501 }
2502 if (bp & 0x04) {
2503 addr[nbp++] = (caddr_t)rdr2();
2504 }
2505 if (bp & 0x08) {
2506 addr[nbp++] = (caddr_t)rdr3();
2507 }
2508
2509 for (i=0; i<nbp; i++) {
2510 if (addr[i] <
88181b08 2511 (caddr_t)VM_MAX_USER_ADDRESS) {
984263bc
MD
2512 /*
2513 * addr[i] is in user space
2514 */
2515 return nbp;
2516 }
2517 }
2518
2519 /*
2520 * None of the breakpoints are in user space.
2521 */
2522 return 0;
2523}
2524
2525
2526#ifndef DDB
2527void
2528Debugger(const char *msg)
2529{
26be20a0 2530 kprintf("Debugger(\"%s\") called.\n", msg);
984263bc
MD
2531}
2532#endif /* no DDB */
2533
984263bc
MD
2534#ifdef DDB
2535
2536/*
2537 * Provide inb() and outb() as functions. They are normally only
2538 * available as macros calling inlined functions, thus cannot be
2539 * called inside DDB.
2540 *
2541 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2542 */
2543
2544#undef inb
2545#undef outb
2546
2547/* silence compiler warnings */
2548u_char inb(u_int);
2549void outb(u_int, u_char);
2550
2551u_char
2552inb(u_int port)
2553{
2554 u_char data;
2555 /*
2556 * We use %%dx and not %1 here because i/o is done at %dx and not at
2557 * %edx, while gcc generates inferior code (movw instead of movl)
2558 * if we tell it to load (u_short) port.
2559 */
2560 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2561 return (data);
2562}
2563
2564void
2565outb(u_int port, u_char data)
2566{
2567 u_char al;
2568 /*
2569 * Use an unnecessary assignment to help gcc's register allocator.
2570 * This make a large difference for gcc-1.40 and a tiny difference
2571 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2572 * best results. gcc-2.6.0 can't handle this.
2573 */
2574 al = data;
2575 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2576}
2577
2578#endif /* DDB */
8a8d5d85
MD
2579
2580
2581
2582#include "opt_cpu.h"
8a8d5d85
MD
2583
2584
2585/*
2586 * initialize all the SMP locks
2587 */
2588
97359a5b 2589/* critical region when masking or unmasking interupts */
b1af91cb 2590struct spinlock_deprecated imen_spinlock;
8a8d5d85 2591
8a8d5d85 2592/* critical region for old style disable_intr/enable_intr */
b1af91cb 2593struct spinlock_deprecated mpintr_spinlock;
8a8d5d85
MD
2594
2595/* critical region around INTR() routines */
b1af91cb 2596struct spinlock_deprecated intr_spinlock;
8a8d5d85
MD
2597
2598/* lock region used by kernel profiling */
b1af91cb 2599struct spinlock_deprecated mcount_spinlock;
8a8d5d85
MD
2600
2601/* locks com (tty) data/hardware accesses: a FASTINTR() */
b1af91cb 2602struct spinlock_deprecated com_spinlock;
8a8d5d85 2603
8a8d5d85 2604/* lock regions around the clock hardware */
b1af91cb 2605struct spinlock_deprecated clock_spinlock;
8a8d5d85
MD
2606
2607/* lock around the MP rendezvous */
b1af91cb 2608struct spinlock_deprecated smp_rv_spinlock;
8a8d5d85
MD
2609
2610static void
2611init_locks(void)
2612{
2613 /*
2614 * mp_lock = 0; BSP already owns the MP lock
2615 */
2616 /*
2617 * Get the initial mp_lock with a count of 1 for the BSP.
2618 * This uses a LOGICAL cpu ID, ie BSP == 0.
2619 */
2620#ifdef SMP
2621 cpu_get_initial_mplock();
2622#endif
41a01a4d 2623 /* DEPRECATED */
8a8d5d85 2624 spin_lock_init(&mcount_spinlock);
8a8d5d85
MD
2625 spin_lock_init(&intr_spinlock);
2626 spin_lock_init(&mpintr_spinlock);
2627 spin_lock_init(&imen_spinlock);
2628 spin_lock_init(&smp_rv_spinlock);
2629 spin_lock_init(&com_spinlock);
2630 spin_lock_init(&clock_spinlock);
41a01a4d
MD
2631
2632 /* our token pool needs to work early */
2633 lwkt_token_pool_init();
8a8d5d85 2634}