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i386 - Get completely rid of APIC_IO
[dragonfly.git] / sys / platform / pc32 / i386 / mp_machdep.c
CommitLineData
984263bc
MD		 1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
c0c5de70 26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
984263bc
MD		 27 */
28
29#include "opt_cpu.h"
984263bc 30
984263bc
MD		 31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
984263bc
MD		 34#include <sys/sysctl.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
984263bc 37#include <sys/cons.h> /* cngetc() */
37e7efec 38#include <sys/machintr.h>
984263bc
MD		 39
40#include <vm/vm.h>
41#include <vm/vm_param.h>
42#include <vm/pmap.h>
43#include <vm/vm_kern.h>
44#include <vm/vm_extern.h>
984263bc
MD		 45#include <sys/lock.h>
46#include <vm/vm_map.h>
47#include <sys/user.h>
48#ifdef GPROF
49#include <sys/gmon.h>
50#endif
984263bc 51
684a93c4
MD		 52#include <sys/mplock2.h>
53
984263bc 54#include <machine/smp.h>
a9295349 55#include <machine_base/apic/apicreg.h>
984263bc
MD		 56#include <machine/atomic.h>
57#include <machine/cpufunc.h>
90e8a35b 58#include <machine/cputypes.h>
a9295349 59#include <machine_base/apic/mpapic.h>
984263bc
MD		 60#include <machine/psl.h>
61#include <machine/segments.h>
984263bc
MD		 62#include <machine/tss.h>
63#include <machine/specialreg.h>
64#include <machine/globaldata.h>
65
984263bc 66#include <machine/md_var.h> /* setidt() */
a9295349
MD		 67#include <machine_base/icu/icu.h> /* IPIs */
68#include <machine_base/isa/intr_machdep.h> /* IPIs */
984263bc 69
1439c090
MD		 70#define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71
984263bc
MD		 72#define WARMBOOT_TARGET 0
73#define WARMBOOT_OFF (KERNBASE + 0x0467)
74#define WARMBOOT_SEG (KERNBASE + 0x0469)
75
984263bc 76#define BIOS_BASE (0xf0000)
1df86978 77#define BIOS_BASE2 (0xe0000)
984263bc 78#define BIOS_SIZE (0x10000)
984263bc
MD		 79#define BIOS_COUNT (BIOS_SIZE/4)
80
81#define CMOS_REG (0x70)
82#define CMOS_DATA (0x71)
83#define BIOS_RESET (0x0f)
84#define BIOS_WARM (0x0a)
85
86#define PROCENTRY_FLAG_EN 0x01
87#define PROCENTRY_FLAG_BP 0x02
88#define IOAPICENTRY_FLAG_EN 0x01
89
90
91/* MP Floating Pointer Structure */
92typedef struct MPFPS {
93 char signature[4];
981bebd1 94 u_int32_t pap;
984263bc
MD		 95 u_char length;
96 u_char spec_rev;
97 u_char checksum;
98 u_char mpfb1;
99 u_char mpfb2;
100 u_char mpfb3;
101 u_char mpfb4;
102 u_char mpfb5;
103} *mpfps_t;
104
105/* MP Configuration Table Header */
106typedef struct MPCTH {
107 char signature[4];
108 u_short base_table_length;
109 u_char spec_rev;
110 u_char checksum;
111 u_char oem_id[8];
112 u_char product_id[12];
113 void *oem_table_pointer;
114 u_short oem_table_size;
115 u_short entry_count;
116 void *apic_address;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
119 u_char reserved;
120} *mpcth_t;
121
122
123typedef struct PROCENTRY {
124 u_char type;
125 u_char apic_id;
126 u_char apic_version;
127 u_char cpu_flags;
128 u_long cpu_signature;
129 u_long feature_flags;
130 u_long reserved1;
131 u_long reserved2;
132} *proc_entry_ptr;
133
134typedef struct BUSENTRY {
135 u_char type;
136 u_char bus_id;
137 char bus_type[6];
138} *bus_entry_ptr;
139
140typedef struct IOAPICENTRY {
141 u_char type;
142 u_char apic_id;
143 u_char apic_version;
144 u_char apic_flags;
145 void *apic_address;
146} *io_apic_entry_ptr;
147
148typedef struct INTENTRY {
149 u_char type;
150 u_char int_type;
151 u_short int_flags;
152 u_char src_bus_id;
153 u_char src_bus_irq;
154 u_char dst_apic_id;
155 u_char dst_apic_int;
156} *int_entry_ptr;
157
158/* descriptions of MP basetable entries */
159typedef struct BASETABLE_ENTRY {
160 u_char type;
161 u_char length;
162 char name[16];
163} basetable_entry;
164
981bebd1
SZ		 165struct mptable_pos {
166 mpfps_t mp_fps;
167 mpcth_t mp_cth;
168 vm_size_t mp_cth_mapsz;
169};
170
fa058384
SZ		 171typedef int (*mptable_iter_func)(void *, const void *, int);
172
984263bc
MD		 173/*
174 * this code MUST be enabled here and in mpboot.s.
175 * it follows the very early stages of AP boot by placing values in CMOS ram.
176 * it NORMALLY will never be needed and thus the primitive method for enabling.
177 *
984263bc 178 */
7d34994c 179#if defined(CHECK_POINTS)
984263bc
MD		 180#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
181#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
182
183#define CHECK_INIT(D); \
184 CHECK_WRITE(0x34, (D)); \
185 CHECK_WRITE(0x35, (D)); \
186 CHECK_WRITE(0x36, (D)); \
187 CHECK_WRITE(0x37, (D)); \
188 CHECK_WRITE(0x38, (D)); \
189 CHECK_WRITE(0x39, (D));
190
191#define CHECK_PRINT(S); \
26be20a0 192 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
984263bc
MD		 193 (S), \
194 CHECK_READ(0x34), \
195 CHECK_READ(0x35), \
196 CHECK_READ(0x36), \
197 CHECK_READ(0x37), \
198 CHECK_READ(0x38), \
199 CHECK_READ(0x39));
200
201#else /* CHECK_POINTS */
202
203#define CHECK_INIT(D)
204#define CHECK_PRINT(S)
205
206#endif /* CHECK_POINTS */
207
208/*
209 * Values to send to the POST hardware.
210 */
211#define MP_BOOTADDRESS_POST 0x10
212#define MP_PROBE_POST 0x11
213#define MPTABLE_PASS1_POST 0x12
214
215#define MP_START_POST 0x13
216#define MP_ENABLE_POST 0x14
217#define MPTABLE_PASS2_POST 0x15
218
219#define START_ALL_APS_POST 0x16
220#define INSTALL_AP_TRAMP_POST 0x17
221#define START_AP_POST 0x18
222
223#define MP_ANNOUNCE_POST 0x19
224
984263bc
MD		 225/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
226int current_postcode;
227
228/** XXX FIXME: what system files declare these??? */
229extern struct region_descriptor r_gdt, r_idt;
230
984263bc 231int mp_naps; /* # of Applications processors */
79b62055 232#ifdef SMP /* APIC-IO */
4f6a8b30 233static int mp_nbusses; /* # of busses */
984263bc 234int mp_napics; /* # of IO APICs */
984263bc 235vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
97359a5b
MD		 236u_int32_t *io_apic_versions;
237#endif
984263bc
MD		 238extern int nkpt;
239
240u_int32_t cpu_apic_versions[MAXCPU];
374133e3 241int64_t tsc0_offset;
0b698dca 242extern int64_t tsc_offsets[];
984263bc 243
1876681a
SZ		 244extern u_long ebda_addr;
245
79b62055 246#ifdef SMP /* APIC-IO */
8a8d5d85 247struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
97359a5b 248#endif
984263bc 249
984263bc
MD		 250/*
251 * APIC ID logical/physical mapping structures.
252 * We oversize these to simplify boot-time config.
253 */
254int cpu_num_to_apic_id[NAPICID];
79b62055 255#ifdef SMP /* APIC-IO */
984263bc 256int io_num_to_apic_id[NAPICID];
97359a5b 257#endif
984263bc
MD		 258int apic_id_to_logical[NAPICID];
259
984263bc
MD		 260/* AP uses this during bootstrap. Do not staticize. */
261char *bootSTK;
262static int bootAP;
263
264/* Hotwire a 0->4MB V==P mapping */
265extern pt_entry_t *KPTphys;
266
f13b5eec
MD		 267/*
268 * SMP page table page. Setup by locore to point to a page table
269 * page from which we allocate per-cpu privatespace areas io_apics,
270 * and so forth.
271 */
272
273#define IO_MAPPING_START_INDEX \
274 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
275
984263bc 276extern pt_entry_t *SMPpt;
f13b5eec 277static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
984263bc
MD		 278
279struct pcb stoppcbs[MAXCPU];
280
fa058384
SZ		 281static basetable_entry basetable_entry_types[] =
282{
283 {0, 20, "Processor"},
284 {1, 8, "Bus"},
285 {2, 8, "I/O APIC"},
286 {3, 8, "I/O INT"},
287 {4, 8, "Local INT"}
288};
289
984263bc
MD		 290/*
291 * Local data and functions.
292 */
293
984263bc
MD		 294static u_int boot_address;
295static u_int base_memory;
41a01a4d 296static int mp_finish;
984263bc 297
984263bc
MD		 298static void mp_enable(u_int boot_addr);
299
fa058384
SZ		 300static int mptable_iterate_entries(const mpcth_t,
301 mptable_iter_func, void *);
cb00b5c4 302static int mptable_probe(void);
34e6fa63 303static int mptable_search(void);
fa058384 304static int mptable_check(vm_paddr_t);
3aba8f73 305static int mptable_search_sig(u_int32_t target, int count);
44c36320 306static int mptable_hyperthread_fixup(u_int, int);
79b62055 307#ifdef SMP /* APIC-IO */
981bebd1 308static void mptable_pass1(struct mptable_pos *);
390b18b0 309static void mptable_pass2(struct mptable_pos *);
3aba8f73
SZ		 310static void mptable_default(int type);
311static void mptable_fix(void);
29bb1d92 312#endif
fa058384 313static int mptable_map(struct mptable_pos *, vm_paddr_t);
981bebd1 314static void mptable_unmap(struct mptable_pos *);
a0eaef71 315static void mptable_imcr(struct mptable_pos *);
3aba8f73 316
281d9482
SZ		 317static int mptable_lapic_probe(struct lapic_enumerator *);
318static void mptable_lapic_enumerate(struct lapic_enumerator *);
319static void mptable_lapic_default(void);
320
79b62055 321#ifdef SMP /* APIC-IO */
984263bc 322static void setup_apic_irq_mapping(void);
97359a5b
MD		 323static int apic_int_is_bus_type(int intr, int bus_type);
324#endif
984263bc
MD		 325static int start_all_aps(u_int boot_addr);
326static void install_ap_tramp(u_int boot_addr);
bb467734
MD		 327static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
328static int smitest(void);
984263bc 329
41a01a4d 330static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
0f7a3396
MD		 331cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
332SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
333
984263bc
MD		 334/*
335 * Calculate usable address in base memory for AP trampoline code.
336 */
337u_int
338mp_bootaddress(u_int basemem)
339{
340 POSTCODE(MP_BOOTADDRESS_POST);
341
c0c5de70 342 base_memory = basemem;
984263bc
MD		 343
344 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
345 if ((base_memory - boot_address) < bootMP_size)
346 boot_address -= 4096; /* not enough, lower by 4k */
347
348 return boot_address;
349}
350
351
34e6fa63
SZ		 352static int
353mptable_probe(void)
354{
355 int mpfps_paddr;
356
357 mpfps_paddr = mptable_search();
358 if (mptable_check(mpfps_paddr))
359 return 0;
360
361 return mpfps_paddr;
362}
363
984263bc
MD		 364/*
365 * Look for an Intel MP spec table (ie, SMP capable hardware).
366 */
cb00b5c4 367static int
34e6fa63 368mptable_search(void)
984263bc
MD		 369{
370 int x;
984263bc 371 u_int32_t target;
f13b5eec
MD		 372
373 /*
374 * Make sure our SMPpt[] page table is big enough to hold all the
375 * mappings we need.
376 */
377 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
984263bc
MD		 378
379 POSTCODE(MP_PROBE_POST);
380
381 /* see if EBDA exists */
1876681a 382 if (ebda_addr != 0) {
984263bc 383 /* search first 1K of EBDA */
1876681a 384 target = (u_int32_t)ebda_addr;
3aba8f73 385 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
aeb48299 386 return x;
984263bc
MD		 387 } else {
388 /* last 1K of base memory, effective 'top of base' passed in */
aeb48299 389 target = (u_int32_t)(base_memory - 0x400);
3aba8f73 390 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
aeb48299 391 return x;
984263bc
MD		 392 }
393
394 /* search the BIOS */
aeb48299 395 target = (u_int32_t)BIOS_BASE;
3aba8f73 396 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
aeb48299 397 return x;
984263bc 398
1df86978
SZ		 399 /* search the extended BIOS */
400 target = (u_int32_t)BIOS_BASE2;
401 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
402 return x;
403
984263bc 404 /* nothing found */
984263bc 405 return 0;
984263bc
MD		 406}
407
fa058384
SZ		 408struct mptable_check_cbarg {
409 int cpu_count;
410 int found_bsp;
411};
412
413static int
414mptable_check_callback(void *xarg, const void *pos, int type)
415{
416 const struct PROCENTRY *ent;
417 struct mptable_check_cbarg *arg = xarg;
418
419 if (type != 0)
420 return 0;
421 ent = pos;
422
423 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
424 return 0;
425 arg->cpu_count++;
426
427 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
428 if (arg->found_bsp) {
429 kprintf("more than one BSP in base MP table\n");
430 return EINVAL;
431 }
432 arg->found_bsp = 1;
433 }
434 return 0;
435}
436
437static int
438mptable_check(vm_paddr_t mpfps_paddr)
439{
440 struct mptable_pos mpt;
441 struct mptable_check_cbarg arg;
442 mpcth_t cth;
443 int error;
444
445 if (mpfps_paddr == 0)
446 return EOPNOTSUPP;
447
448 error = mptable_map(&mpt, mpfps_paddr);
449 if (error)
450 return error;
451
452 if (mpt.mp_fps->mpfb1 != 0)
453 goto done;
454
455 error = EINVAL;
456
457 cth = mpt.mp_cth;
458 if (cth == NULL)
459 goto done;
460 if (cth->apic_address == 0)
461 goto done;
462
463 bzero(&arg, sizeof(arg));
464 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
465 if (!error) {
466 if (arg.cpu_count == 0) {
467 kprintf("MP table contains no processor entries\n");
468 error = EINVAL;
469 } else if (!arg.found_bsp) {
470 kprintf("MP table does not contains BSP entry\n");
471 error = EINVAL;
472 }
473 }
474done:
475 mptable_unmap(&mpt);
476 return error;
477}
478
479static int
480mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
481{
482 int count, total_size;
483 const void *position;
484
485 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
486 total_size = cth->base_table_length - sizeof(struct MPCTH);
487 position = (const uint8_t *)cth + sizeof(struct MPCTH);
488 count = cth->entry_count;
489
490 while (count--) {
491 int type, error;
492
493 KKASSERT(total_size >= 0);
494 if (total_size == 0) {
495 kprintf("invalid base MP table, "
496 "entry count and length mismatch\n");
497 return EINVAL;
498 }
499
500 type = *(const uint8_t *)position;
501 switch (type) {
502 case 0: /* processor_entry */
503 case 1: /* bus_entry */
504 case 2: /* io_apic_entry */
505 case 3: /* int_entry */
506 case 4: /* int_entry */
507 break;
508 default:
509 kprintf("unknown base MP table entry type %d\n", type);
510 return EINVAL;
511 }
512
513 if (total_size < basetable_entry_types[type].length) {
514 kprintf("invalid base MP table length, "
515 "does not contain all entries\n");
516 return EINVAL;
517 }
518 total_size -= basetable_entry_types[type].length;
519
520 error = func(arg, position, type);
521 if (error)
522 return error;
523
524 position = (const uint8_t *)position +
525 basetable_entry_types[type].length;
526 }
527 return 0;
528}
529
984263bc
MD		 530
531/*
532 * Startup the SMP processors.
533 */
534void
535mp_start(void)
536{
537 POSTCODE(MP_START_POST);
50bc991e 538 mp_enable(boot_address);
984263bc
MD		 539}
540
541
542/*
543 * Print various information about the SMP system hardware and setup.
544 */
545void
546mp_announce(void)
547{
548 int x;
549
550 POSTCODE(MP_ANNOUNCE_POST);
551
26be20a0
SW		 552 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
553 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
8629c4ea 554 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
984263bc 555 for (x = 1; x <= mp_naps; ++x) {
26be20a0 556 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
8629c4ea 557 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
984263bc
MD		 558 }
559
79b62055 560if (apic_io_enable) {
984263bc 561 for (x = 0; x < mp_napics; ++x) {
26be20a0
SW		 562 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
563 kprintf(", version: 0x%08x", io_apic_versions[x]);
d557216f 564 kprintf(", at 0x%08lx\n", io_apic_address[x]);
984263bc 565 }
79b62055 566} else {
26be20a0 567 kprintf(" Warning: APIC I/O disabled\n");
79b62055 568}
984263bc
MD		 569}
570
571/*
572 * AP cpu's call this to sync up protected mode.
7160572f
MD		 573 *
574 * WARNING! We must ensure that the cpu is sufficiently initialized to
575 * be able to use to the FP for our optimized bzero/bcopy code before
576 * we enter more mainstream C code.
a44bdeec
MD		 577 *
578 * WARNING! %fs is not set up on entry. This routine sets up %fs.
984263bc
MD		 579 */
580void
581init_secondary(void)
582{
583 int gsel_tss;
584 int x, myid = bootAP;
585 u_int cr0;
8a8d5d85 586 struct mdglobaldata *md;
0f7a3396 587 struct privatespace *ps;
984263bc 588
0f7a3396
MD		 589 ps = &CPU_prvspace[myid];
590
591 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
984263bc 592 gdt_segs[GPROC0_SEL].ssd_base =
0f7a3396
MD		 593 (int) &ps->mdglobaldata.gd_common_tss;
594 ps->mdglobaldata.mi.gd_prvspace = ps;
984263bc
MD		 595
596 for (x = 0; x < NGDT; x++) {
597 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
598 }
599
600 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
601 r_gdt.rd_base = (int) &gdt[myid * NGDT];
602 lgdt(&r_gdt); /* does magic intra-segment return */
603
604 lidt(&r_idt);
605
606 lldt(_default_ldt);
7b95be2a 607 mdcpu->gd_currentldt = _default_ldt;
984263bc
MD		 608
609 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
610 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
8a8d5d85 611
0f7a3396 612 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
8a8d5d85
MD		 613
614 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
615 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
616 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
617 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
618 md->gd_common_tssd = *md->gd_tss_gdt;
984263bc
MD		 619 ltr(gsel_tss);
620
621 /*
622 * Set to a known state:
623 * Set by mpboot.s: CR0_PG, CR0_PE
624 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
625 */
626 cr0 = rcr0();
627 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
628 load_cr0(cr0);
7160572f 629 pmap_set_opt(); /* PSE/4MB pages, etc */
984263bc 630
7160572f
MD		 631 /* set up CPU registers and state */
632 cpu_setregs();
633
634 /* set up FPU state on the AP */
635 npxinit(__INITIAL_NPXCW__);
636
637 /* set up SSE registers */
638 enable_sse();
984263bc
MD		 639}
640
984263bc
MD		 641/*******************************************************************
642 * local functions and data
643 */
644
645/*
646 * start the SMP system
647 */
648static void
649mp_enable(u_int boot_addr)
650{
984263bc
MD		 651 int apic;
652 u_int ux;
981bebd1 653 vm_paddr_t mpfps_paddr;
f65c10b6 654 struct mptable_pos mpt;
984263bc
MD		 655
656 POSTCODE(MP_ENABLE_POST);
657
281d9482 658 lapic_config();
984263bc 659
f65c10b6
SZ		 660 mpfps_paddr = mptable_probe();
661 if (mpfps_paddr) {
662 mptable_map(&mpt, mpfps_paddr);
663 mptable_imcr(&mpt);
664 mptable_unmap(&mpt);
665 }
79b62055 666if (apic_io_enable) {
984263bc 667
f65c10b6 668 if (!mpfps_paddr)
79b62055 669 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
f65c10b6
SZ		 670
671 mptable_map(&mpt, mpfps_paddr);
672
673 /*
674 * Examine the MP table for needed info
675 */
676 mptable_pass1(&mpt);
677 mptable_pass2(&mpt);
678
679 mptable_unmap(&mpt);
680
681 /* Post scan cleanup */
682 mptable_fix();
683
97359a5b
MD		 684 setup_apic_irq_mapping();
685
984263bc
MD		 686 /* fill the LOGICAL io_apic_versions table */
687 for (apic = 0; apic < mp_napics; ++apic) {
688 ux = io_apic_read(apic, IOAPIC_VER);
689 io_apic_versions[apic] = ux;
690 io_apic_set_id(apic, IO_TO_ID(apic));
691 }
692
693 /* program each IO APIC in the system */
694 for (apic = 0; apic < mp_napics; ++apic)
695 if (io_apic_setup(apic) < 0)
696 panic("IO APIC setup failure");
697
79b62055 698}
97359a5b
MD		 699
700 /*
701 * These are required for SMP operation
702 */
703
984263bc
MD		 704 /* install a 'Spurious INTerrupt' vector */
705 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
706 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
707
708 /* install an inter-CPU IPI for TLB invalidation */
709 setidt(XINVLTLB_OFFSET, Xinvltlb,
710 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
711
96728c05
MD		 712 /* install an inter-CPU IPI for IPIQ messaging */
713 setidt(XIPIQ_OFFSET, Xipiq,
714 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
78ea5a2a
SZ		 715
716 /* install a timer vector */
717 setidt(XTIMER_OFFSET, Xtimer,
718 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc 719
984263bc
MD		 720 /* install an inter-CPU IPI for CPU stop/restart */
721 setidt(XCPUSTOP_OFFSET, Xcpustop,
722 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
723
984263bc
MD		 724 /* start each Application Processor */
725 start_all_aps(boot_addr);
726}
727
728
729/*
730 * look for the MP spec signature
731 */
732
733/* string defined by the Intel MP Spec as identifying the MP table */
734#define MP_SIG 0x5f504d5f /* _MP_ */
735#define NEXT(X) ((X) += 4)
736static int
3aba8f73 737mptable_search_sig(u_int32_t target, int count)
984263bc 738{
0f85efa2
SZ		 739 vm_size_t map_size;
740 u_int32_t *addr;
741 int x, ret;
984263bc 742
aeb48299
SZ		 743 KKASSERT(target != 0);
744
0f85efa2
SZ		 745 map_size = count * sizeof(u_int32_t);
746 addr = pmap_mapdev((vm_paddr_t)target, map_size);
984263bc 747
aeb48299 748 ret = 0;
0f85efa2
SZ		 749 for (x = 0; x < count; NEXT(x)) {
750 if (addr[x] == MP_SIG) {
751 /* make array index a byte index */
752 ret = target + (x * sizeof(u_int32_t));
753 break;
754 }
755 }
aeb48299 756
0f85efa2
SZ		 757 pmap_unmapdev((vm_offset_t)addr, map_size);
758 return ret;
984263bc
MD		 759}
760
761
984263bc
MD		 762typedef struct BUSDATA {
763 u_char bus_id;
764 enum busTypes bus_type;
765} bus_datum;
766
767typedef struct INTDATA {
768 u_char int_type;
769 u_short int_flags;
770 u_char src_bus_id;
771 u_char src_bus_irq;
772 u_char dst_apic_id;
773 u_char dst_apic_int;
774 u_char int_vector;
775} io_int, local_int;
776
777typedef struct BUSTYPENAME {
778 u_char type;
779 char name[7];
780} bus_type_name;
781
782static bus_type_name bus_type_table[] =
783{
784 {CBUS, "CBUS"},
785 {CBUSII, "CBUSII"},
786 {EISA, "EISA"},
787 {MCA, "MCA"},
788 {UNKNOWN_BUSTYPE, "---"},
789 {ISA, "ISA"},
790 {MCA, "MCA"},
791 {UNKNOWN_BUSTYPE, "---"},
792 {UNKNOWN_BUSTYPE, "---"},
793 {UNKNOWN_BUSTYPE, "---"},
794 {UNKNOWN_BUSTYPE, "---"},
795 {UNKNOWN_BUSTYPE, "---"},
796 {PCI, "PCI"},
797 {UNKNOWN_BUSTYPE, "---"},
798 {UNKNOWN_BUSTYPE, "---"},
799 {UNKNOWN_BUSTYPE, "---"},
800 {UNKNOWN_BUSTYPE, "---"},
801 {XPRESS, "XPRESS"},
802 {UNKNOWN_BUSTYPE, "---"}
803};
804/* from MP spec v1.4, table 5-1 */
805static int default_data[7][5] =
806{
807/* nbus, id0, type0, id1, type1 */
808 {1, 0, ISA, 255, 255},
809 {1, 0, EISA, 255, 255},
810 {1, 0, EISA, 255, 255},
811 {1, 0, MCA, 255, 255},
812 {2, 0, ISA, 1, PCI},
813 {2, 0, EISA, 1, PCI},
814 {2, 0, MCA, 1, PCI}
815};
816
817
818/* the bus data */
819static bus_datum *bus_data;
820
821/* the IO INT data, one entry per possible APIC INTerrupt */
822static io_int *io_apic_ints;
984263bc 823static int nintrs;
4f6a8b30 824
a0873f07 825static int processor_entry (const struct PROCENTRY *entry, int cpu);
c4717d5c
SZ		 826static int bus_entry (const struct BUSENTRY *entry, int bus);
827static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
828static int int_entry (const struct INTENTRY *entry, int intr);
3ae0cd58 829static int lookup_bus_type (char *name);
8658b5be
SZ		 830
831static int
832mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
833{
834 const struct IOAPICENTRY *ioapic_ent;
835
836 switch (type) {
837 case 1: /* bus_entry */
838 ++mp_nbusses;
839 break;
840
841 case 2: /* io_apic_entry */
842 ioapic_ent = pos;
843 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
844 io_apic_address[mp_napics++] =
845 (vm_offset_t)ioapic_ent->apic_address;
846 }
847 break;
848
849 case 3: /* int_entry */
850 ++nintrs;
851 break;
852 }
853 return 0;
854}
855
984263bc
MD		 856/*
857 * 1st pass on motherboard's Intel MP specification table.
858 *
984263bc 859 * determines:
984263bc 860 * io_apic_address[N]
984263bc
MD		 861 * mp_nbusses
862 * mp_napics
863 * nintrs
864 */
865static void
981bebd1 866mptable_pass1(struct mptable_pos *mpt)
984263bc 867{
981bebd1 868 mpfps_t fps;
8658b5be 869 int x;
984263bc
MD		 870
871 POSTCODE(MPTABLE_PASS1_POST);
872
981bebd1
SZ		 873 fps = mpt->mp_fps;
874 KKASSERT(fps != NULL);
f9c3b04f 875
984263bc 876 /* clear various tables */
8658b5be 877 for (x = 0; x < NAPICID; ++x)
984263bc 878 io_apic_address[x] = ~0; /* IO APIC address table */
984263bc 879
4f6a8b30 880 mp_nbusses = 0;
984263bc
MD		 881 mp_napics = 0;
882 nintrs = 0;
984263bc
MD		 883
884 /* check for use of 'default' configuration */
981bebd1 885 if (fps->mpfb1 != 0) {
984263bc 886 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
4f6a8b30 887 mp_nbusses = default_data[fps->mpfb1 - 1][0];
984263bc
MD		 888 mp_napics = 1;
889 nintrs = 16;
8658b5be
SZ		 890 } else {
891 int error;
892
893 error = mptable_iterate_entries(mpt->mp_cth,
894 mptable_ioapic_pass1_callback, NULL);
895 if (error)
896 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
984263bc 897 }
984263bc
MD		 898}
899
c4717d5c
SZ		 900struct mptable_ioapic2_cbarg {
901 int bus;
902 int apic;
903 int intr;
904};
905
906static int
907mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
908{
909 struct mptable_ioapic2_cbarg *arg = xarg;
910
911 switch (type) {
912 case 1:
913 if (bus_entry(pos, arg->bus))
914 ++arg->bus;
915 break;
916
917 case 2:
918 if (io_apic_entry(pos, arg->apic))
919 ++arg->apic;
920 break;
921
922 case 3:
923 if (int_entry(pos, arg->intr))
924 ++arg->intr;
925 break;
926 }
927 return 0;
928}
929
984263bc
MD		 930/*
931 * 2nd pass on motherboard's Intel MP specification table.
932 *
933 * sets:
984263bc 934 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
984263bc
MD		 935 * IO_TO_ID(N), logical IO to APIC ID table
936 * bus_data[N]
937 * io_apic_ints[N]
938 */
390b18b0 939static void
981bebd1 940mptable_pass2(struct mptable_pos *mpt)
984263bc 941{
c4717d5c 942 struct mptable_ioapic2_cbarg arg;
981bebd1 943 mpfps_t fps;
c4717d5c 944 int error, x;
984263bc
MD		 945
946 POSTCODE(MPTABLE_PASS2_POST);
947
981bebd1
SZ		 948 fps = mpt->mp_fps;
949 KKASSERT(fps != NULL);
950
984263bc
MD		 951 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
952 M_DEVBUF, M_WAITOK);
953 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
e7b4468c 954 M_DEVBUF, M_WAITOK | M_ZERO);
1439c090 955 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
984263bc
MD		 956 M_DEVBUF, M_WAITOK);
957 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
958 M_DEVBUF, M_WAITOK);
959
c4717d5c
SZ		 960 for (x = 0; x < mp_napics; x++)
961 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
984263bc
MD		 962
963 /* clear various tables */
964 for (x = 0; x < NAPICID; ++x) {
97359a5b 965 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
984263bc
MD		 966 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
967 }
968
969 /* clear bus data table */
970 for (x = 0; x < mp_nbusses; ++x)
971 bus_data[x].bus_id = 0xff;
972
973 /* clear IO APIC INT table */
974 for (x = 0; x < (nintrs + 1); ++x) {
975 io_apic_ints[x].int_type = 0xff;
976 io_apic_ints[x].int_vector = 0xff;
977 }
978
984263bc 979 /* check for use of 'default' configuration */
390b18b0
SZ		 980 if (fps->mpfb1 != 0) {
981 mptable_default(fps->mpfb1);
982 return;
983 }
984263bc 984
c4717d5c
SZ		 985 bzero(&arg, sizeof(arg));
986 error = mptable_iterate_entries(mpt->mp_cth,
987 mptable_ioapic_pass2_callback, &arg);
988 if (error)
989 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
984263bc
MD		 990}
991
984263bc
MD		 992/*
993 * Check if we should perform a hyperthreading "fix-up" to
994 * enumerate any logical CPU's that aren't already listed
995 * in the table.
996 *
997 * XXX: We assume that all of the physical CPUs in the
998 * system have the same number of logical CPUs.
999 *
1000 * XXX: We assume that APIC ID's are allocated such that
1001 * the APIC ID's for a physical processor are aligned
1002 * with the number of logical CPU's in the processor.
1003 */
44c36320
SZ		 1004static int
1005mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
984263bc 1006{
44c36320 1007 int i, id, lcpus_max, logical_cpus;
984263bc 1008
984263bc 1009 if ((cpu_feature & CPUID_HTT) == 0)
44c36320 1010 return 0;
7ea07fd2
SZ		 1011
1012 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1013 if (lcpus_max <= 1)
44c36320 1014 return 0;
984263bc 1015
90e8a35b 1016 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
7ea07fd2
SZ		 1017 /*
1018 * INSTRUCTION SET REFERENCE, A-M (#253666)
1019 * Page 3-181, Table 3-20
1020 * "The nearest power-of-2 integer that is not smaller
1021 * than EBX[23:16] is the number of unique initial APIC
1022 * IDs reserved for addressing different logical
1023 * processors in a physical package."
1024 */
1025 for (i = 0; ; ++i) {
1026 if ((1 << i) >= lcpus_max) {
1027 lcpus_max = 1 << i;
1028 break;
1029 }
1030 }
1031 }
1032
44c36320
SZ		 1033 KKASSERT(cpu_count != 0);
1034 if (cpu_count == lcpus_max) {
7ea07fd2 1035 /* We have nothing to fix */
44c36320
SZ		 1036 return 0;
1037 } else if (cpu_count == 1) {
7ea07fd2
SZ		 1038 /* XXX this may be incorrect */
1039 logical_cpus = lcpus_max;
1040 } else {
1041 int cur, prev, dist;
1042
1043 /*
1044 * Calculate the distances between two nearest
1045 * APIC IDs. If all such distances are same,
1046 * then it is the number of missing cpus that
1047 * we are going to fill later.
1048 */
1049 dist = cur = prev = -1;
1050 for (id = 0; id < MAXCPU; ++id) {
1051 if ((id_mask & 1 << id) == 0)
1052 continue;
1053
1054 cur = id;
1055 if (prev >= 0) {
1056 int new_dist = cur - prev;
1057
1058 if (dist < 0)
1059 dist = new_dist;
1060
1061 /*
1062 * Make sure that all distances
1063 * between two nearest APIC IDs
1064 * are same.
1065 */
1066 if (dist != new_dist)
44c36320 1067 return 0;
7ea07fd2
SZ		 1068 }
1069 prev = cur;
1070 }
1071 if (dist == 1)
44c36320 1072 return 0;
7ea07fd2
SZ		 1073
1074 /* Must be power of 2 */
1075 if (dist & (dist - 1))
44c36320 1076 return 0;
7ea07fd2
SZ		 1077
1078 /* Can't exceed CPU package capacity */
1079 if (dist > lcpus_max)
1080 logical_cpus = lcpus_max;
1081 else
1082 logical_cpus = dist;
1083 }
1084
984263bc
MD		 1085 /*
1086 * For each APIC ID of a CPU that is set in the mask,
1087 * scan the other candidate APIC ID's for this
1088 * physical processor. If any of those ID's are
1089 * already in the table, then kill the fixup.
1090 */
7ea07fd2 1091 for (id = 0; id < MAXCPU; id++) {
984263bc
MD		 1092 if ((id_mask & 1 << id) == 0)
1093 continue;
1094 /* First, make sure we are on a logical_cpus boundary. */
1095 if (id % logical_cpus != 0)
44c36320 1096 return 0;
984263bc
MD		 1097 for (i = id + 1; i < id + logical_cpus; i++)
1098 if ((id_mask & 1 << i) != 0)
44c36320 1099 return 0;
984263bc 1100 }
44c36320 1101 return logical_cpus;
984263bc 1102}
984263bc 1103
fa058384 1104static int
981bebd1
SZ		 1105mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1106{
1107 mpfps_t fps = NULL;
1108 mpcth_t cth = NULL;
1109 vm_size_t cth_mapsz = 0;
1110
fa058384
SZ		 1111 bzero(mpt, sizeof(*mpt));
1112
981bebd1
SZ		 1113 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1114 if (fps->pap != 0) {
1115 /*
1116 * Map configuration table header to get
1117 * the base table size
1118 */
1119 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1120 cth_mapsz = cth->base_table_length;
1121 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1122
fa058384
SZ		 1123 if (cth_mapsz < sizeof(*cth)) {
1124 kprintf("invalid base MP table length %d\n",
1125 (int)cth_mapsz);
1126 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1127 return EINVAL;
1128 }
1129
981bebd1
SZ		 1130 /*
1131 * Map the base table
1132 */
1133 cth = pmap_mapdev(fps->pap, cth_mapsz);
1134 }
1135
1136 mpt->mp_fps = fps;
1137 mpt->mp_cth = cth;
1138 mpt->mp_cth_mapsz = cth_mapsz;
fa058384
SZ		 1139
1140 return 0;
981bebd1
SZ		 1141}
1142
1143static void
1144mptable_unmap(struct mptable_pos *mpt)
1145{
1146 if (mpt->mp_cth != NULL) {
1147 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1148 mpt->mp_cth = NULL;
1149 mpt->mp_cth_mapsz = 0;
1150 }
1151 if (mpt->mp_fps != NULL) {
1152 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1153 mpt->mp_fps = NULL;
1154 }
1155}
1156
984263bc
MD		 1157void
1158assign_apic_irq(int apic, int intpin, int irq)
1159{
1160 int x;
1161
1162 if (int_to_apicintpin[irq].ioapic != -1)
1163 panic("assign_apic_irq: inconsistent table");
1164
1165 int_to_apicintpin[irq].ioapic = apic;
1166 int_to_apicintpin[irq].int_pin = intpin;
1167 int_to_apicintpin[irq].apic_address = ioapic[apic];
1168 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1169
1170 for (x = 0; x < nintrs; x++) {
1171 if ((io_apic_ints[x].int_type == 0 ||
1172 io_apic_ints[x].int_type == 3) &&
1173 io_apic_ints[x].int_vector == 0xff &&
1174 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1175 io_apic_ints[x].dst_apic_int == intpin)
1176 io_apic_ints[x].int_vector = irq;
1177 }
1178}
1179
1180void
1181revoke_apic_irq(int irq)
1182{
1183 int x;
1184 int oldapic;
1185 int oldintpin;
1186
1187 if (int_to_apicintpin[irq].ioapic == -1)
1188 panic("revoke_apic_irq: inconsistent table");
1189
1190 oldapic = int_to_apicintpin[irq].ioapic;
1191 oldintpin = int_to_apicintpin[irq].int_pin;
1192
1193 int_to_apicintpin[irq].ioapic = -1;
1194 int_to_apicintpin[irq].int_pin = 0;
1195 int_to_apicintpin[irq].apic_address = NULL;
1196 int_to_apicintpin[irq].redirindex = 0;
1197
1198 for (x = 0; x < nintrs; x++) {
1199 if ((io_apic_ints[x].int_type == 0 ||
1200 io_apic_ints[x].int_type == 3) &&
1201 io_apic_ints[x].int_vector != 0xff &&
1202 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1203 io_apic_ints[x].dst_apic_int == oldintpin)
1204 io_apic_ints[x].int_vector = 0xff;
1205 }
1206}
1207
1439c090
MD		 1208/*
1209 * Allocate an IRQ
1210 */
984263bc
MD		 1211static void
1212allocate_apic_irq(int intr)
1213{
1214 int apic;
1215 int intpin;
1216 int irq;
1217
1218 if (io_apic_ints[intr].int_vector != 0xff)
1219 return; /* Interrupt handler already assigned */
1220
1221 if (io_apic_ints[intr].int_type != 0 &&
1222 (io_apic_ints[intr].int_type != 3 ||
1223 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1224 io_apic_ints[intr].dst_apic_int == 0)))
1225 return; /* Not INT or ExtInt on != (0, 0) */
1226
1227 irq = 0;
1228 while (irq < APIC_INTMAPSIZE &&
1229 int_to_apicintpin[irq].ioapic != -1)
1230 irq++;
1231
1232 if (irq >= APIC_INTMAPSIZE)
1233 return; /* No free interrupt handlers */
1234
1235 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1236 intpin = io_apic_ints[intr].dst_apic_int;
1237
1238 assign_apic_irq(apic, intpin, irq);
4612bd39 1239 io_apic_setup_intpin(apic, intpin);
984263bc
MD		 1240}
1241
1242
1243static void
1244swap_apic_id(int apic, int oldid, int newid)
1245{
1246 int x;
1247 int oapic;
1248
1249
1250 if (oldid == newid)
1251 return; /* Nothing to do */
1252
26be20a0 1253 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
984263bc
MD		 1254 apic, oldid, newid);
1255
1256 /* Swap physical APIC IDs in interrupt entries */
1257 for (x = 0; x < nintrs; x++) {
1258 if (io_apic_ints[x].dst_apic_id == oldid)
1259 io_apic_ints[x].dst_apic_id = newid;
1260 else if (io_apic_ints[x].dst_apic_id == newid)
1261 io_apic_ints[x].dst_apic_id = oldid;
1262 }
1263
1264 /* Swap physical APIC IDs in IO_TO_ID mappings */
1265 for (oapic = 0; oapic < mp_napics; oapic++)
1266 if (IO_TO_ID(oapic) == newid)
1267 break;
1268
1269 if (oapic < mp_napics) {
26be20a0 1270 kprintf("Changing APIC ID for IO APIC #%d from "
984263bc
MD		 1271 "%d to %d in MP table\n",
1272 oapic, newid, oldid);
1273 IO_TO_ID(oapic) = oldid;
1274 }
1275 IO_TO_ID(apic) = newid;
1276}
1277
1278
1279static void
1280fix_id_to_io_mapping(void)
1281{
1282 int x;
1283
1284 for (x = 0; x < NAPICID; x++)
1285 ID_TO_IO(x) = -1;
1286
1287 for (x = 0; x <= mp_naps; x++)
1288 if (CPU_TO_ID(x) < NAPICID)
1289 ID_TO_IO(CPU_TO_ID(x)) = x;
1290
1291 for (x = 0; x < mp_napics; x++)
1292 if (IO_TO_ID(x) < NAPICID)
1293 ID_TO_IO(IO_TO_ID(x)) = x;
1294}
1295
1296
1297static int
1298first_free_apic_id(void)
1299{
1300 int freeid, x;
1301
1302 for (freeid = 0; freeid < NAPICID; freeid++) {
1303 for (x = 0; x <= mp_naps; x++)
1304 if (CPU_TO_ID(x) == freeid)
1305 break;
1306 if (x <= mp_naps)
1307 continue;
1308 for (x = 0; x < mp_napics; x++)
1309 if (IO_TO_ID(x) == freeid)
1310 break;
1311 if (x < mp_napics)
1312 continue;
1313 return freeid;
1314 }
1315 return freeid;
1316}
1317
1318
1319static int
1320io_apic_id_acceptable(int apic, int id)
1321{
1322 int cpu; /* Logical CPU number */
1323 int oapic; /* Logical IO APIC number for other IO APIC */
1324
1325 if (id >= NAPICID)
1326 return 0; /* Out of range */
1327
1328 for (cpu = 0; cpu <= mp_naps; cpu++)
1329 if (CPU_TO_ID(cpu) == id)
1330 return 0; /* Conflict with CPU */
1331
1332 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1333 if (IO_TO_ID(oapic) == id)
1334 return 0; /* Conflict with other APIC */
1335
1336 return 1; /* ID is acceptable for IO APIC */
1337}
1338
1439c090
MD		 1339static
1340io_int *
1341io_apic_find_int_entry(int apic, int pin)
1342{
1343 int x;
1344
1345 /* search each of the possible INTerrupt sources */
1346 for (x = 0; x < nintrs; ++x) {
1347 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1348 (pin == io_apic_ints[x].dst_apic_int))
1349 return (&io_apic_ints[x]);
1350 }
1351 return NULL;
1352}
1353
984263bc
MD		 1354/*
1355 * parse an Intel MP specification table
1356 */
1357static void
3aba8f73 1358mptable_fix(void)
984263bc 1359{
4f6a8b30 1360 int x;
984263bc 1361 int id;
984263bc
MD		 1362 int apic; /* IO APIC unit number */
1363 int freeid; /* Free physical APIC ID */
1364 int physid; /* Current physical IO APIC ID */
1439c090 1365 io_int *io14;
97359a5b
MD		 1366 int bus_0 = 0; /* Stop GCC warning */
1367 int bus_pci = 0; /* Stop GCC warning */
1368 int num_pci_bus;
984263bc
MD		 1369
1370 /*
1371 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1372 * did it wrong. The MP spec says that when more than 1 PCI bus
1373 * exists the BIOS must begin with bus entries for the PCI bus and use
1374 * actual PCI bus numbering. This implies that when only 1 PCI bus
1375 * exists the BIOS can choose to ignore this ordering, and indeed many
1376 * MP motherboards do ignore it. This causes a problem when the PCI
1377 * sub-system makes requests of the MP sub-system based on PCI bus
1378 * numbers. So here we look for the situation and renumber the
1379 * busses and associated INTs in an effort to "make it right".
1380 */
1381
1382 /* find bus 0, PCI bus, count the number of PCI busses */
1383 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1384 if (bus_data[x].bus_id == 0) {
1385 bus_0 = x;
1386 }
1387 if (bus_data[x].bus_type == PCI) {
1388 ++num_pci_bus;
1389 bus_pci = x;
1390 }
1391 }
1392 /*
1393 * bus_0 == slot of bus with ID of 0
1394 * bus_pci == slot of last PCI bus encountered
1395 */
1396
1397 /* check the 1 PCI bus case for sanity */
1398 /* if it is number 0 all is well */
1399 if (num_pci_bus == 1 &&
1400 bus_data[bus_pci].bus_id != 0) {
1401
1402 /* mis-numbered, swap with whichever bus uses slot 0 */
1403
1404 /* swap the bus entry types */
1405 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1406 bus_data[bus_0].bus_type = PCI;
1407
1408 /* swap each relavant INTerrupt entry */
1409 id = bus_data[bus_pci].bus_id;
1410 for (x = 0; x < nintrs; ++x) {
1411 if (io_apic_ints[x].src_bus_id == id) {
1412 io_apic_ints[x].src_bus_id = 0;
1413 }
1414 else if (io_apic_ints[x].src_bus_id == 0) {
1415 io_apic_ints[x].src_bus_id = id;
1416 }
1417 }
1418 }
1419
1420 /* Assign IO APIC IDs.
1421 *
1422 * First try the existing ID. If a conflict is detected, try
1423 * the ID in the MP table. If a conflict is still detected, find
1424 * a free id.
1425 *
1426 * We cannot use the ID_TO_IO table before all conflicts has been
1427 * resolved and the table has been corrected.
1428 */
1429 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1430
1431 /* First try to use the value set by the BIOS */
1432 physid = io_apic_get_id(apic);
1433 if (io_apic_id_acceptable(apic, physid)) {
1434 if (IO_TO_ID(apic) != physid)
1435 swap_apic_id(apic, IO_TO_ID(apic), physid);
1436 continue;
1437 }
1438
1439 /* Then check if the value in the MP table is acceptable */
1440 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1441 continue;
1442
1443 /* Last resort, find a free APIC ID and use it */
1444 freeid = first_free_apic_id();
1445 if (freeid >= NAPICID)
1446 panic("No free physical APIC IDs found");
1447
1448 if (io_apic_id_acceptable(apic, freeid)) {
1449 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1450 continue;
1451 }
1452 panic("Free physical APIC ID not usable");
1453 }
1454 fix_id_to_io_mapping();
1455
1456 /* detect and fix broken Compaq MP table */
1457 if (apic_int_type(0, 0) == -1) {
26be20a0 1458 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
984263bc
MD		 1459 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1460 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1461 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1462 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1463 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1464 nintrs++;
ad12f88c 1465 } else if (apic_int_type(0, 0) == 0) {
26be20a0 1466 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
ad12f88c
HP		 1467 for (x = 0; x < nintrs; ++x)
1468 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1469 (0 == io_apic_ints[x].dst_apic_int)) {
1470 io_apic_ints[x].int_type = 3;
1471 io_apic_ints[x].int_vector = 0xff;
1472 break;
1473 }
984263bc 1474 }
1439c090
MD		 1475
1476 /*
1477 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1478 * controllers universally come in pairs. If IRQ 14 is specified
1479 * as an ISA interrupt, then IRQ 15 had better be too.
1480 *
1481 * [ Shuttle XPC / AMD Athlon X2 ]
1482 * The MPTable is missing an entry for IRQ 15. Note that the
1483 * ACPI table has an entry for both 14 and 15.
1484 */
1485 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
26be20a0 1486 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1439c090
MD		 1487 io14 = io_apic_find_int_entry(0, 14);
1488 io_apic_ints[nintrs] = *io14;
1489 io_apic_ints[nintrs].src_bus_irq = 15;
1490 io_apic_ints[nintrs].dst_apic_int = 15;
1491 nintrs++;
1492 }
984263bc
MD		 1493}
1494
984263bc
MD		 1495/* Assign low level interrupt handlers */
1496static void
1497setup_apic_irq_mapping(void)
1498{
1499 int x;
1500 int int_vector;
1501
1502 /* Clear array */
1503 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1504 int_to_apicintpin[x].ioapic = -1;
1505 int_to_apicintpin[x].int_pin = 0;
1506 int_to_apicintpin[x].apic_address = NULL;
1507 int_to_apicintpin[x].redirindex = 0;
ea689d1c
SZ		 1508
1509 /* Default to masked */
1510 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
984263bc
MD		 1511 }
1512
1513 /* First assign ISA/EISA interrupts */
1514 for (x = 0; x < nintrs; x++) {
1515 int_vector = io_apic_ints[x].src_bus_irq;
1516 if (int_vector < APIC_INTMAPSIZE &&
1517 io_apic_ints[x].int_vector == 0xff &&
1518 int_to_apicintpin[int_vector].ioapic == -1 &&
1519 (apic_int_is_bus_type(x, ISA) ||
1520 apic_int_is_bus_type(x, EISA)) &&
1521 io_apic_ints[x].int_type == 0) {
1522 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1523 io_apic_ints[x].dst_apic_int,
1524 int_vector);
1525 }
1526 }
1527
1528 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1529 for (x = 0; x < nintrs; x++) {
1530 if (io_apic_ints[x].dst_apic_int == 0 &&
1531 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1532 io_apic_ints[x].int_vector == 0xff &&
1533 int_to_apicintpin[0].ioapic == -1 &&
1534 io_apic_ints[x].int_type == 3) {
1535 assign_apic_irq(0, 0, 0);
1536 break;
1537 }
1538 }
4612bd39 1539 /* PCI interrupt assignment is deferred */
984263bc
MD		 1540}
1541
a9112655
SZ		 1542void
1543mp_set_cpuids(int cpu_id, int apic_id)
1544{
1545 CPU_TO_ID(cpu_id) = apic_id;
1546 ID_TO_CPU(apic_id) = cpu_id;
1547}
1548
984263bc 1549static int
a0873f07 1550processor_entry(const struct PROCENTRY *entry, int cpu)
984263bc 1551{
bd8aa7e2
SZ		 1552 KKASSERT(cpu > 0);
1553
984263bc
MD		 1554 /* check for usability */
1555 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1556 return 0;
1557
984263bc
MD		 1558 /* check for BSP flag */
1559 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
a9112655 1560 mp_set_cpuids(0, entry->apic_id);
984263bc
MD		 1561 return 0; /* its already been counted */
1562 }
1563
1564 /* add another AP to list, if less than max number of CPUs */
1565 else if (cpu < MAXCPU) {
a9112655 1566 mp_set_cpuids(cpu, entry->apic_id);
984263bc
MD		 1567 return 1;
1568 }
1569
1570 return 0;
1571}
1572
984263bc 1573static int
c4717d5c 1574bus_entry(const struct BUSENTRY *entry, int bus)
984263bc
MD		 1575{
1576 int x;
1577 char c, name[8];
1578
1579 /* encode the name into an index */
1580 for (x = 0; x < 6; ++x) {
1581 if ((c = entry->bus_type[x]) == ' ')
1582 break;
1583 name[x] = c;
1584 }
1585 name[x] = '\0';
1586
1587 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1588 panic("unknown bus type: '%s'", name);
1589
1590 bus_data[bus].bus_id = entry->bus_id;
1591 bus_data[bus].bus_type = x;
1592
1593 return 1;
1594}
1595
984263bc 1596static int
c4717d5c 1597io_apic_entry(const struct IOAPICENTRY *entry, int apic)
984263bc
MD		 1598{
1599 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1600 return 0;
1601
1602 IO_TO_ID(apic) = entry->apic_id;
c163176b 1603 ID_TO_IO(entry->apic_id) = apic;
984263bc
MD		 1604
1605 return 1;
1606}
1607
984263bc
MD		 1608static int
1609lookup_bus_type(char *name)
1610{
1611 int x;
1612
1613 for (x = 0; x < MAX_BUSTYPE; ++x)
1614 if (strcmp(bus_type_table[x].name, name) == 0)
1615 return bus_type_table[x].type;
1616
1617 return UNKNOWN_BUSTYPE;
1618}
1619
984263bc 1620static int
c4717d5c 1621int_entry(const struct INTENTRY *entry, int intr)
984263bc
MD		 1622{
1623 int apic;
1624
1625 io_apic_ints[intr].int_type = entry->int_type;
1626 io_apic_ints[intr].int_flags = entry->int_flags;
1627 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1628 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1629 if (entry->dst_apic_id == 255) {
1630 /* This signal goes to all IO APICS. Select an IO APIC
1631 with sufficient number of interrupt pins */
1632 for (apic = 0; apic < mp_napics; apic++)
1633 if (((io_apic_read(apic, IOAPIC_VER) &
1634 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1635 entry->dst_apic_int)
1636 break;
1637 if (apic < mp_napics)
1638 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1639 else
1640 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1641 } else
1642 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1643 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1644
1645 return 1;
1646}
1647
984263bc
MD		 1648static int
1649apic_int_is_bus_type(int intr, int bus_type)
1650{
1651 int bus;
1652
1653 for (bus = 0; bus < mp_nbusses; ++bus)
1654 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1655 && ((int) bus_data[bus].bus_type == bus_type))
1656 return 1;
1657
1658 return 0;
1659}
1660
984263bc
MD		 1661/*
1662 * Given a traditional ISA INT mask, return an APIC mask.
1663 */
1664u_int
1665isa_apic_mask(u_int isa_mask)
1666{
1667 int isa_irq;
1668 int apic_pin;
1669
1670#if defined(SKIP_IRQ15_REDIRECT)
1671 if (isa_mask == (1 << 15)) {
26be20a0 1672 kprintf("skipping ISA IRQ15 redirect\n");
984263bc
MD		 1673 return isa_mask;
1674 }
1675#endif /* SKIP_IRQ15_REDIRECT */
1676
1677 isa_irq = ffs(isa_mask); /* find its bit position */
1678 if (isa_irq == 0) /* doesn't exist */
1679 return 0;
1680 --isa_irq; /* make it zero based */
1681
1682 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1683 if (apic_pin == -1)
1684 return 0;
1685
1686 return (1 << apic_pin); /* convert pin# to a mask */
1687}
1688
984263bc
MD		 1689/*
1690 * Determine which APIC pin an ISA/EISA INT is attached to.
1691 */
1692#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1693#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1694#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1695#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1696
1697#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1698int
1699isa_apic_irq(int isa_irq)
1700{
1701 int intr;
1702
1703 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1704 if (INTTYPE(intr) == 0) { /* standard INT */
1705 if (SRCBUSIRQ(intr) == isa_irq) {
1706 if (apic_int_is_bus_type(intr, ISA) ||
1707 apic_int_is_bus_type(intr, EISA)) {
1708 if (INTIRQ(intr) == 0xff)
1709 return -1; /* unassigned */
1710 return INTIRQ(intr); /* found */
1711 }
1712 }
1713 }
1714 }
1715 return -1; /* NOT found */
1716}
1717
1718
1719/*
1720 * Determine which APIC pin a PCI INT is attached to.
1721 */
1722#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1723#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1724#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1725int
1726pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1727{
1728 int intr;
1729
1730 --pciInt; /* zero based */
1731
1439c090 1732 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
984263bc
MD		 1733 if ((INTTYPE(intr) == 0) /* standard INT */
1734 && (SRCBUSID(intr) == pciBus)
1735 && (SRCBUSDEVICE(intr) == pciDevice)
1439c090 1736 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
984263bc 1737 if (apic_int_is_bus_type(intr, PCI)) {
4612bd39
AP		 1738 if (INTIRQ(intr) == 0xff)
1739 allocate_apic_irq(intr);
1740 if (INTIRQ(intr) == 0xff)
984263bc
MD		 1741 return -1; /* unassigned */
1742 return INTIRQ(intr); /* exact match */
1743 }
1439c090
MD		 1744 }
1745 }
984263bc
MD		 1746
1747 return -1; /* NOT found */
1748}
1749
1750int
1751next_apic_irq(int irq)
1752{
1753 int intr, ointr;
1754 int bus, bustype;
1755
1756 bus = 0;
1757 bustype = 0;
1758 for (intr = 0; intr < nintrs; intr++) {
1759 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1760 continue;
1761 bus = SRCBUSID(intr);
1762 bustype = apic_bus_type(bus);
1763 if (bustype != ISA &&
1764 bustype != EISA &&
1765 bustype != PCI)
1766 continue;
1767 break;
1768 }
1769 if (intr >= nintrs) {
1770 return -1;
1771 }
1772 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1773 if (INTTYPE(ointr) != 0)
1774 continue;
1775 if (bus != SRCBUSID(ointr))
1776 continue;
1777 if (bustype == PCI) {
1778 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1779 continue;
1780 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1781 continue;
1782 }
1783 if (bustype == ISA || bustype == EISA) {
1784 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1785 continue;
1786 }
1787 if (INTPIN(intr) == INTPIN(ointr))
1788 continue;
1789 break;
1790 }
1791 if (ointr >= nintrs) {
1792 return -1;
1793 }
1794 return INTIRQ(ointr);
1795}
1796#undef SRCBUSLINE
1797#undef SRCBUSDEVICE
1798#undef SRCBUSID
1799#undef SRCBUSIRQ
1800
1801#undef INTPIN
1802#undef INTIRQ
1803#undef INTAPIC
1804#undef INTTYPE
1805
984263bc
MD		 1806/*
1807 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1808 *
1809 * XXX FIXME:
1810 * Exactly what this means is unclear at this point. It is a solution
1811 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1812 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1813 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1814 * option.
1815 */
1816int
1817undirect_isa_irq(int rirq)
1818{
1819#if defined(READY)
1820 if (bootverbose)
26be20a0 1821 kprintf("Freeing redirected ISA irq %d.\n", rirq);
984263bc 1822 /** FIXME: tickle the MB redirector chip */
c044141b 1823 return /* XXX */;
984263bc
MD		 1824#else
1825 if (bootverbose)
26be20a0 1826 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
984263bc
MD		 1827 return 0;
1828#endif /* READY */
1829}
1830
1831
1832/*
1833 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1834 */
1835int
1836undirect_pci_irq(int rirq)
1837{
1838#if defined(READY)
1839 if (bootverbose)
26be20a0 1840 kprintf("Freeing redirected PCI irq %d.\n", rirq);
984263bc
MD		 1841
1842 /** FIXME: tickle the MB redirector chip */
c044141b 1843 return /* XXX */;
984263bc
MD		 1844#else
1845 if (bootverbose)
26be20a0 1846 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
984263bc
MD		 1847 rirq);
1848 return 0;
1849#endif /* READY */
1850}
1851
1852
1853/*
1854 * given a bus ID, return:
1855 * the bus type if found
1856 * -1 if NOT found
1857 */
1858int
1859apic_bus_type(int id)
1860{
1861 int x;
1862
1863 for (x = 0; x < mp_nbusses; ++x)
1864 if (bus_data[x].bus_id == id)
1865 return bus_data[x].bus_type;
1866
1867 return -1;
1868}
1869
984263bc
MD		 1870/*
1871 * given a LOGICAL APIC# and pin#, return:
1872 * the associated src bus ID if found
1873 * -1 if NOT found
1874 */
1875int
1876apic_src_bus_id(int apic, int pin)
1877{
1878 int x;
1879
1880 /* search each of the possible INTerrupt sources */
1881 for (x = 0; x < nintrs; ++x)
1882 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1883 (pin == io_apic_ints[x].dst_apic_int))
1884 return (io_apic_ints[x].src_bus_id);
1885
1886 return -1; /* NOT found */
1887}
1888
984263bc
MD		 1889/*
1890 * given a LOGICAL APIC# and pin#, return:
1891 * the associated src bus IRQ if found
1892 * -1 if NOT found
1893 */
1894int
1895apic_src_bus_irq(int apic, int pin)
1896{
1897 int x;
1898
1899 for (x = 0; x < nintrs; x++)
1900 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1901 (pin == io_apic_ints[x].dst_apic_int))
1902 return (io_apic_ints[x].src_bus_irq);
1903
1904 return -1; /* NOT found */
1905}
1906
1907
1908/*
1909 * given a LOGICAL APIC# and pin#, return:
1910 * the associated INTerrupt type if found
1911 * -1 if NOT found
1912 */
1913int
1914apic_int_type(int apic, int pin)
1915{
1916 int x;
1917
1918 /* search each of the possible INTerrupt sources */
1439c090 1919 for (x = 0; x < nintrs; ++x) {
984263bc
MD		 1920 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1921 (pin == io_apic_ints[x].dst_apic_int))
1922 return (io_apic_ints[x].int_type);
1439c090 1923 }
984263bc
MD		 1924 return -1; /* NOT found */
1925}
1926
1439c090
MD		 1927/*
1928 * Return the IRQ associated with an APIC pin
1929 */
984263bc
MD		 1930int
1931apic_irq(int apic, int pin)
1932{
1933 int x;
1934 int res;
1935
1439c090 1936 for (x = 0; x < nintrs; ++x) {
984263bc
MD		 1937 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1938 (pin == io_apic_ints[x].dst_apic_int)) {
1939 res = io_apic_ints[x].int_vector;
1940 if (res == 0xff)
1941 return -1;
1942 if (apic != int_to_apicintpin[res].ioapic)
1439c090 1943 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
984263bc
MD		 1944 if (pin != int_to_apicintpin[res].int_pin)
1945 panic("apic_irq inconsistent table (2)");
1946 return res;
1947 }
1439c090 1948 }
984263bc
MD		 1949 return -1;
1950}
1951
1952
1953/*
1954 * given a LOGICAL APIC# and pin#, return:
1955 * the associated trigger mode if found
1956 * -1 if NOT found
1957 */
1958int
1959apic_trigger(int apic, int pin)
1960{
1961 int x;
1962
1963 /* search each of the possible INTerrupt sources */
1964 for (x = 0; x < nintrs; ++x)
1965 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1966 (pin == io_apic_ints[x].dst_apic_int))
1967 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1968
1969 return -1; /* NOT found */
1970}
1971
1972
1973/*
1974 * given a LOGICAL APIC# and pin#, return:
1975 * the associated 'active' level if found
1976 * -1 if NOT found
1977 */
1978int
1979apic_polarity(int apic, int pin)
1980{
1981 int x;
1982
1983 /* search each of the possible INTerrupt sources */
1984 for (x = 0; x < nintrs; ++x)
1985 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1986 (pin == io_apic_ints[x].dst_apic_int))
1987 return (io_apic_ints[x].int_flags & 0x03);
1988
1989 return -1; /* NOT found */
1990}
1991
984263bc
MD		 1992/*
1993 * set data according to MP defaults
1994 * FIXME: probably not complete yet...
1995 */
1996static void
3aba8f73 1997mptable_default(int type)
984263bc 1998{
984263bc
MD		 1999 int io_apic_id;
2000 int pin;
984263bc
MD		 2001
2002#if 0
26be20a0 2003 kprintf(" MP default config type: %d\n", type);
984263bc
MD		 2004 switch (type) {
2005 case 1:
26be20a0 2006 kprintf(" bus: ISA, APIC: 82489DX\n");
984263bc
MD		 2007 break;
2008 case 2:
26be20a0 2009 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD		 2010 break;
2011 case 3:
26be20a0 2012 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD		 2013 break;
2014 case 4:
26be20a0 2015 kprintf(" bus: MCA, APIC: 82489DX\n");
984263bc
MD		 2016 break;
2017 case 5:
26be20a0 2018 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
984263bc
MD		 2019 break;
2020 case 6:
26be20a0 2021 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
984263bc
MD		 2022 break;
2023 case 7:
26be20a0 2024 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
984263bc
MD		 2025 break;
2026 default:
26be20a0 2027 kprintf(" future type\n");
984263bc
MD		 2028 break;
2029 /* NOTREACHED */
2030 }
2031#endif /* 0 */
2032
984263bc
MD		 2033 /* one and only IO APIC */
2034 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2035
2036 /*
2037 * sanity check, refer to MP spec section 3.6.6, last paragraph
2038 * necessary as some hardware isn't properly setting up the IO APIC
2039 */
2040#if defined(REALLY_ANAL_IOAPICID_VALUE)
2041 if (io_apic_id != 2) {
2042#else
2043 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2044#endif /* REALLY_ANAL_IOAPICID_VALUE */
2045 io_apic_set_id(0, 2);
2046 io_apic_id = 2;
2047 }
2048 IO_TO_ID(0) = io_apic_id;
2049 ID_TO_IO(io_apic_id) = 0;
984263bc
MD		 2050
2051 /* fill out bus entries */
2052 switch (type) {
2053 case 1:
2054 case 2:
2055 case 3:
2056 case 4:
2057 case 5:
2058 case 6:
2059 case 7:
2060 bus_data[0].bus_id = default_data[type - 1][1];
2061 bus_data[0].bus_type = default_data[type - 1][2];
2062 bus_data[1].bus_id = default_data[type - 1][3];
2063 bus_data[1].bus_type = default_data[type - 1][4];
2064 break;
2065
2066 /* case 4: case 7: MCA NOT supported */
2067 default: /* illegal/reserved */
2068 panic("BAD default MP config: %d", type);
2069 /* NOTREACHED */
2070 }
2071
984263bc
MD		 2072 /* general cases from MP v1.4, table 5-2 */
2073 for (pin = 0; pin < 16; ++pin) {
2074 io_apic_ints[pin].int_type = 0;
2075 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2076 io_apic_ints[pin].src_bus_id = 0;
2077 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2078 io_apic_ints[pin].dst_apic_id = io_apic_id;
2079 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2080 }
2081
2082 /* special cases from MP v1.4, table 5-2 */
2083 if (type == 2) {
2084 io_apic_ints[2].int_type = 0xff; /* N/C */
2085 io_apic_ints[13].int_type = 0xff; /* N/C */
2086#if !defined(APIC_MIXED_MODE)
2087 /** FIXME: ??? */
2088 panic("sorry, can't support type 2 default yet");
2089#endif /* APIC_MIXED_MODE */
2090 }
2091 else
2092 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2093
2094 if (type == 7)
2095 io_apic_ints[0].int_type = 0xff; /* N/C */
2096 else
2097 io_apic_ints[0].int_type = 3; /* vectored 8259 */
984263bc
MD		 2098}
2099
984263bc 2100/*
f13b5eec
MD		 2101 * Map a physical memory address representing I/O into KVA. The I/O
2102 * block is assumed not to cross a page boundary.
2103 */
2104void *
2105permanent_io_mapping(vm_paddr_t pa)
2106{
2107 vm_offset_t vaddr;
2108 int pgeflag;
2109 int i;
2110
2111 KKASSERT(pa < 0x100000000LL);
2112
2113 pgeflag = 0; /* not used for SMP yet */
2114
2115 /*
2116 * If the requested physical address has already been incidently
2117 * mapped, just use the existing mapping. Otherwise create a new
2118 * mapping.
2119 */
2120 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2121 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2122 ((vm_offset_t)pa & PG_FRAME)) {
2123 break;
2124 }
2125 }
2126 if (i == SMPpt_alloc_index) {
2127 if (i == NPTEPG - 2) {
2128 panic("permanent_io_mapping: We ran out of space"
2129 " in SMPpt[]!");
2130 }
5277b9f6 2131 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
f13b5eec
MD		 2132 ((vm_offset_t)pa & PG_FRAME));
2133 ++SMPpt_alloc_index;
2134 }
2135 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2136 ((vm_offset_t)pa & PAGE_MASK);
2137 return ((void *)vaddr);
2138}
2139
2140/*
984263bc
MD		 2141 * start each AP in our list
2142 */
2143static int
2144start_all_aps(u_int boot_addr)
2145{
b45759e1
MD		 2146 int x, i, pg;
2147 int shift;
bb467734
MD		 2148 int smicount;
2149 int smibest;
2150 int smilast;
984263bc
MD		 2151 u_char mpbiosreason;
2152 u_long mpbioswarmvec;
8a8d5d85 2153 struct mdglobaldata *gd;
0f7a3396 2154 struct privatespace *ps;
984263bc
MD		 2155 char *stack;
2156 uintptr_t kptbase;
2157
2158 POSTCODE(START_ALL_APS_POST);
2159
b52c8db0
SZ		 2160 /* Initialize BSP's local APIC */
2161 apic_initialize(TRUE);
984263bc
MD		 2162
2163 /* install the AP 1st level boot code */
2164 install_ap_tramp(boot_addr);
2165
2166
2167 /* save the current value of the warm-start vector */
2168 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
984263bc
MD		 2169 outb(CMOS_REG, BIOS_RESET);
2170 mpbiosreason = inb(CMOS_DATA);
984263bc 2171
bb467734
MD		 2172 /* setup a vector to our boot code */
2173 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2174 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2175 outb(CMOS_REG, BIOS_RESET);
2176 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2177
2178 /*
2179 * If we have a TSC we can figure out the SMI interrupt rate.
2180 * The SMI does not necessarily use a constant rate. Spend
2181 * up to 250ms trying to figure it out.
2182 */
2183 smibest = 0;
2184 if (cpu_feature & CPUID_TSC) {
2185 set_apic_timer(275000);
2186 smilast = read_apic_timer();
2187 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2188 smicount = smitest();
2189 if (smibest == 0 || smilast - smicount < smibest)
2190 smibest = smilast - smicount;
2191 smilast = smicount;
2192 }
2193 if (smibest > 250000)
2194 smibest = 0;
2195 if (smibest) {
2196 smibest = smibest * (int64_t)1000000 /
2197 get_apic_timer_frequency();
2198 }
2199 }
2200 if (smibest)
2201 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2202 1000000 / smibest, smibest);
2203
2204
984263bc
MD		 2205 /* set up temporary P==V mapping for AP boot */
2206 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2207 kptbase = (uintptr_t)(void *)KPTphys;
a44bdeec 2208 for (x = 0; x < NKPT; x++) {
984263bc
MD		 2209 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2210 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
a44bdeec 2211 }
0f7a3396 2212 cpu_invltlb();
984263bc
MD		 2213
2214 /* start each AP */
2215 for (x = 1; x <= mp_naps; ++x) {
2216
2217 /* This is a bit verbose, it will go away soon. */
2218
2219 /* first page of AP's private space */
2220 pg = x * i386_btop(sizeof(struct privatespace));
2221
81c04d07 2222 /* allocate new private data page(s) */
e4846942 2223 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
81c04d07 2224 MDGLOBALDATA_BASEALLOC_SIZE);
984263bc 2225 /* wire it into the private page table page */
81c04d07
MD		 2226 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2227 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2228 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2229 }
2230 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2231
2232 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2233 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2234 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2235 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
984263bc
MD		 2236
2237 /* allocate and set up an idle stack data page */
e4846942 2238 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
8a8d5d85 2239 for (i = 0; i < UPAGES; i++) {
81c04d07 2240 SMPpt[pg + 4 + i] = (pt_entry_t)
b5b32410 2241 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
8a8d5d85 2242 }
984263bc 2243
8a8d5d85
MD		 2244 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2245 bzero(gd, sizeof(*gd));
0f7a3396 2246 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
8a8d5d85 2247
984263bc 2248 /* prime data page for it to use */
8a8d5d85 2249 mi_gdinit(&gd->mi, x);
8ad65e08 2250 cpu_gdinit(gd, x);
81c04d07
MD		 2251 gd->gd_CMAP1 = &SMPpt[pg + 0];
2252 gd->gd_CMAP2 = &SMPpt[pg + 1];
2253 gd->gd_CMAP3 = &SMPpt[pg + 2];
2254 gd->gd_PMAP1 = &SMPpt[pg + 3];
0f7a3396
MD		 2255 gd->gd_CADDR1 = ps->CPAGE1;
2256 gd->gd_CADDR2 = ps->CPAGE2;
2257 gd->gd_CADDR3 = ps->CPAGE3;
2258 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
9388fcaa
MD		 2259
2260 /*
2261 * Per-cpu pmap for get_ptbase().
2262 */
2263 gd->gd_GDADDR1= (unsigned *)
2264 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2265 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2266
e4846942 2267 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
96728c05 2268 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
984263bc 2269
8a8d5d85
MD		 2270 /*
2271 * Setup the AP boot stack
2272 */
0f7a3396 2273 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
984263bc
MD		 2274 bootAP = x;
2275
2276 /* attempt to start the Application Processor */
2277 CHECK_INIT(99); /* setup checkpoints */
bb467734 2278 if (!start_ap(gd, boot_addr, smibest)) {
26be20a0 2279 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
984263bc
MD		 2280 CHECK_PRINT("trace"); /* show checkpoints */
2281 /* better panic as the AP may be running loose */
26be20a0 2282 kprintf("panic y/n? [y] ");
984263bc
MD		 2283 if (cngetc() != 'n')
2284 panic("bye-bye");
2285 }
2286 CHECK_PRINT("trace"); /* show checkpoints */
2287
2288 /* record its version info */
2289 cpu_apic_versions[x] = cpu_apic_versions[0];
984263bc
MD		 2290 }
2291
0f7a3396
MD		 2292 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2293 ncpus = x;
2294
b45759e1
MD		 2295 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2296 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2297 ;
2298 --shift;
2299 ncpus2_shift = shift;
2300 ncpus2 = 1 << shift;
90100055
JH		 2301 ncpus2_mask = ncpus2 - 1;
2302
b45759e1
MD		 2303 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2304 if ((1 << shift) < ncpus)
2305 ++shift;
2306 ncpus_fit = 1 << shift;
2307 ncpus_fit_mask = ncpus_fit - 1;
2308
984263bc 2309 /* build our map of 'other' CPUs */
0f7a3396 2310 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
e4846942 2311 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
96728c05 2312 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
984263bc
MD		 2313
2314 /* fill in our (BSP) APIC version */
2315 cpu_apic_versions[0] = lapic.version;
2316
2317 /* restore the warmstart vector */
2318 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
984263bc
MD		 2319 outb(CMOS_REG, BIOS_RESET);
2320 outb(CMOS_DATA, mpbiosreason);
984263bc
MD		 2321
2322 /*
8a8d5d85
MD		 2323 * NOTE! The idlestack for the BSP was setup by locore. Finish
2324 * up, clean out the P==V mapping we did earlier.
984263bc 2325 */
984263bc
MD		 2326 for (x = 0; x < NKPT; x++)
2327 PTD[x] = 0;
2328 pmap_set_opt();
2329
2330 /* number of APs actually started */
8a8d5d85 2331 return ncpus - 1;
984263bc
MD		 2332}
2333
984263bc
MD		 2334/*
2335 * load the 1st level AP boot code into base memory.
2336 */
2337
2338/* targets for relocation */
2339extern void bigJump(void);
2340extern void bootCodeSeg(void);
2341extern void bootDataSeg(void);
2342extern void MPentry(void);
2343extern u_int MP_GDT;
2344extern u_int mp_gdtbase;
2345
2346static void
2347install_ap_tramp(u_int boot_addr)
2348{
2349 int x;
2350 int size = *(int *) ((u_long) & bootMP_size);
2351 u_char *src = (u_char *) ((u_long) bootMP);
2352 u_char *dst = (u_char *) boot_addr + KERNBASE;
2353 u_int boot_base = (u_int) bootMP;
2354 u_int8_t *dst8;
2355 u_int16_t *dst16;
2356 u_int32_t *dst32;
2357
2358 POSTCODE(INSTALL_AP_TRAMP_POST);
2359
2360 for (x = 0; x < size; ++x)
2361 *dst++ = *src++;
2362
2363 /*
2364 * modify addresses in code we just moved to basemem. unfortunately we
2365 * need fairly detailed info about mpboot.s for this to work. changes
2366 * to mpboot.s might require changes here.
2367 */
2368
2369 /* boot code is located in KERNEL space */
2370 dst = (u_char *) boot_addr + KERNBASE;
2371
2372 /* modify the lgdt arg */
2373 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2374 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2375
2376 /* modify the ljmp target for MPentry() */
2377 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2378 *dst32 = ((u_int) MPentry - KERNBASE);
2379
2380 /* modify the target for boot code segment */
2381 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2382 dst8 = (u_int8_t *) (dst16 + 1);
2383 *dst16 = (u_int) boot_addr & 0xffff;
2384 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2385
2386 /* modify the target for boot data segment */
2387 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2388 dst8 = (u_int8_t *) (dst16 + 1);
2389 *dst16 = (u_int) boot_addr & 0xffff;
2390 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2391}
2392
2393
2394/*
bb467734 2395 * This function starts the AP (application processor) identified
984263bc
MD		 2396 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2397 * to accomplish this. This is necessary because of the nuances
2398 * of the different hardware we might encounter. It ain't pretty,
2399 * but it seems to work.
a108bf71
MD		 2400 *
2401 * NOTE: eventually an AP gets to ap_init(), which is called just
2402 * before the AP goes into the LWKT scheduler's idle loop.
984263bc
MD		 2403 */
2404static int
bb467734 2405start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
984263bc
MD		 2406{
2407 int physical_cpu;
2408 int vector;
984263bc
MD		 2409 u_long icr_lo, icr_hi;
2410
2411 POSTCODE(START_AP_POST);
2412
2413 /* get the PHYSICAL APIC ID# */
0f7a3396 2414 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
984263bc
MD		 2415
2416 /* calculate the vector */
2417 vector = (boot_addr >> 12) & 0xff;
2418
bb467734
MD		 2419 /* We don't want anything interfering */
2420 cpu_disable_intr();
2421
8a8d5d85
MD		 2422 /* Make sure the target cpu sees everything */
2423 wbinvd();
984263bc
MD		 2424
2425 /*
bb467734
MD		 2426 * Try to detect when a SMI has occurred, wait up to 200ms.
2427 *
2428 * If a SMI occurs during an AP reset but before we issue
2429 * the STARTUP command, the AP may brick. To work around
2430 * this problem we hold off doing the AP startup until
2431 * after we have detected the SMI. Hopefully another SMI
2432 * will not occur before we finish the AP startup.
2433 *
2434 * Retries don't seem to help. SMIs have a window of opportunity
2435 * and if USB->legacy keyboard emulation is enabled in the BIOS
2436 * the interrupt rate can be quite high.
2437 *
2438 * NOTE: Don't worry about the L1 cache load, it might bloat
2439 * ldelta a little but ndelta will be so huge when the SMI
2440 * occurs the detection logic will still work fine.
2441 */
2442 if (smibest) {
2443 set_apic_timer(200000);
2444 smitest();
2445 }
2446
2447 /*
984263bc
MD		 2448 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2449 * and running the target CPU. OR this INIT IPI might be latched (P5
2450 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2451 * ignored.
bb467734
MD		 2452 *
2453 * see apic/apicreg.h for icr bit definitions.
2454 *
2455 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
984263bc
MD		 2456 */
2457
bb467734
MD		 2458 /*
2459 * Setup the address for the target AP. We can setup
2460 * icr_hi once and then just trigger operations with
2461 * icr_lo.
2462 */
984263bc
MD		 2463 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2464 icr_hi |= (physical_cpu << 24);
bb467734 2465 icr_lo = lapic.icr_lo & 0xfff00000;
984263bc
MD		 2466 lapic.icr_hi = icr_hi;
2467
bb467734
MD		 2468 /*
2469 * Do an INIT IPI: assert RESET
2470 *
2471 * Use edge triggered mode to assert INIT
2472 */
984263bc 2473 lapic.icr_lo = icr_lo | 0x0000c500;
984263bc
MD		 2474 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2475 /* spin */ ;
2476
bb467734
MD		 2477 /*
2478 * The spec calls for a 10ms delay but we may have to use a
2479 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2480 * interrupt. We have other loops here too and dividing by 2
2481 * doesn't seem to be enough even after subtracting 350us,
2482 * so we divide by 4.
2483 *
2484 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2485 * interrupt was detected we use the full 10ms.
2486 */
2487 if (smibest == 0)
2488 u_sleep(10000);
2489 else if (smibest < 150 * 4 + 350)
2490 u_sleep(150);
2491 else if ((smibest - 350) / 4 < 10000)
2492 u_sleep((smibest - 350) / 4);
2493 else
2494 u_sleep(10000);
984263bc 2495
bb467734
MD		 2496 /*
2497 * Do an INIT IPI: deassert RESET
2498 *
2499 * Use level triggered mode to deassert. It is unclear
2500 * why we need to do this.
2501 */
2502 lapic.icr_lo = icr_lo | 0x00008500;
984263bc
MD		 2503 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2504 /* spin */ ;
bb467734 2505 u_sleep(150); /* wait 150us */
984263bc
MD		 2506
2507 /*
bb467734 2508 * Next we do a STARTUP IPI: the previous INIT IPI might still be
984263bc
MD		 2509 * latched, (P5 bug) this 1st STARTUP would then terminate
2510 * immediately, and the previously started INIT IPI would continue. OR
2511 * the previous INIT IPI has already run. and this STARTUP IPI will
2512 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2513 * will run.
2514 */
984263bc
MD		 2515 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2516 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2517 /* spin */ ;
2518 u_sleep(200); /* wait ~200uS */
2519
2520 /*
bb467734 2521 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
984263bc
MD		 2522 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2523 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2524 * recognized after hardware RESET or INIT IPI.
2525 */
984263bc
MD		 2526 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2527 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2528 /* spin */ ;
bb467734
MD		 2529
2530 /* Resume normal operation */
2531 cpu_enable_intr();
984263bc 2532
8a8d5d85 2533 /* wait for it to start, see ap_init() */
984263bc 2534 set_apic_timer(5000000);/* == 5 seconds */
8a8d5d85 2535 while (read_apic_timer()) {
0f7a3396 2536 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
984263bc 2537 return 1; /* return SUCCESS */
8a8d5d85 2538 }
bb467734 2539
984263bc
MD		 2540 return 0; /* return FAILURE */
2541}
2542
bb467734
MD		 2543static
2544int
2545smitest(void)
2546{
2547 int64_t ltsc;
2548 int64_t ntsc;
2549 int64_t ldelta;
2550 int64_t ndelta;
2551 int count;
2552
2553 ldelta = 0;
2554 ndelta = 0;
2555 while (read_apic_timer()) {
2556 ltsc = rdtsc();
2557 for (count = 0; count < 100; ++count)
2558 ntsc = rdtsc(); /* force loop to occur */
2559 if (ldelta) {
2560 ndelta = ntsc - ltsc;
2561 if (ldelta > ndelta)
2562 ldelta = ndelta;
2563 if (ndelta > ldelta * 2)
2564 break;
2565 } else {
2566 ldelta = ntsc - ltsc;
2567 }
2568 }
2569 return(read_apic_timer());
2570}
984263bc
MD		 2571
2572/*
0f7a3396 2573 * Lazy flush the TLB on all other CPU's. DEPRECATED.
984263bc 2574 *
0f7a3396
MD		 2575 * If for some reason we were unable to start all cpus we cannot safely
2576 * use broadcast IPIs.
984263bc
MD		 2577 */
2578void
2579smp_invltlb(void)
2580{
97359a5b 2581#ifdef SMP
0f7a3396 2582 if (smp_startup_mask == smp_active_mask) {
984263bc 2583 all_but_self_ipi(XINVLTLB_OFFSET);
0f7a3396
MD		 2584 } else {
2585 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2586 APIC_DELMODE_FIXED);
2587 }
97359a5b 2588#endif
984263bc
MD		 2589}
2590
984263bc
MD		 2591/*
2592 * When called the executing CPU will send an IPI to all other CPUs
2593 * requesting that they halt execution.
2594 *
2595 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2596 *
2597 * - Signals all CPUs in map to stop.
2598 * - Waits for each to stop.
2599 *
2600 * Returns:
2601 * -1: error
2602 * 0: NA
2603 * 1: ok
2604 *
2605 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2606 * from executing at same time.
2607 */
2608int
2609stop_cpus(u_int map)
2610{
0f7a3396 2611 map &= smp_active_mask;
984263bc
MD		 2612
2613 /* send the Xcpustop IPI to all CPUs in map */
2614 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2615
2616 while ((stopped_cpus & map) != map)
2617 /* spin */ ;
2618
2619 return 1;
2620}
2621
2622
2623/*
2624 * Called by a CPU to restart stopped CPUs.
2625 *
2626 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2627 *
2628 * - Signals all CPUs in map to restart.
2629 * - Waits for each to restart.
2630 *
2631 * Returns:
2632 * -1: error
2633 * 0: NA
2634 * 1: ok
2635 */
2636int
2637restart_cpus(u_int map)
2638{
0f7a3396
MD		 2639 /* signal other cpus to restart */
2640 started_cpus = map & smp_active_mask;
984263bc
MD		 2641
2642 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2643 /* spin */ ;
2644
2645 return 1;
2646}
2647
984263bc 2648/*
8a8d5d85
MD		 2649 * This is called once the mpboot code has gotten us properly relocated
2650 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2651 * and when it returns the scheduler will call the real cpu_idle() main
2652 * loop for the idlethread. Interrupts are disabled on entry and should
2653 * remain disabled at return.
984263bc 2654 */
984263bc 2655void
8a8d5d85 2656ap_init(void)
984263bc
MD		 2657{
2658 u_int apic_id;
2659
8a8d5d85 2660 /*
0f7a3396
MD		 2661 * Adjust smp_startup_mask to signal the BSP that we have started
2662 * up successfully. Note that we do not yet hold the BGL. The BSP
2663 * is waiting for our signal.
2664 *
2665 * We can't set our bit in smp_active_mask yet because we are holding
2666 * interrupts physically disabled and remote cpus could deadlock
2667 * trying to send us an IPI.
8a8d5d85 2668 */
0f7a3396 2669 smp_startup_mask |= 1 << mycpu->gd_cpuid;
35238fa5 2670 cpu_mfence();
8a8d5d85
MD		 2671
2672 /*
41a01a4d
MD		 2673 * Interlock for finalization. Wait until mp_finish is non-zero,
2674 * then get the MP lock.
2675 *
2676 * Note: We are in a critical section.
2677 *
2678 * Note: We have to synchronize td_mpcount to our desired MP state
2679 * before calling cpu_try_mplock().
2680 *
2681 * Note: we are the idle thread, we can only spin.
2682 *
35238fa5
MD		 2683 * Note: The load fence is memory volatile and prevents the compiler
2684 * from improperly caching mp_finish, and the cpu from improperly
2685 * caching it.
8a8d5d85 2686 */
41a01a4d 2687 while (mp_finish == 0)
35238fa5 2688 cpu_lfence();
d9ebdce5 2689 ++curthread->td_mpcount;
8a8d5d85
MD		 2690 while (cpu_try_mplock() == 0)
2691 ;
2692
374133e3
MD		 2693 if (cpu_feature & CPUID_TSC) {
2694 /*
2695 * The BSP is constantly updating tsc0_offset, figure out the
2696 * relative difference to synchronize ktrdump.
2697 */
2698 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2699 }
2700
984263bc
MD		 2701 /* BSP may have changed PTD while we're waiting for the lock */
2702 cpu_invltlb();
2703
984263bc
MD		 2704#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2705 lidt(&r_idt);
2706#endif
2707
2708 /* Build our map of 'other' CPUs. */
0f7a3396 2709 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
984263bc 2710
26be20a0 2711 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
984263bc 2712
984263bc
MD		 2713 /* A quick check from sanity claus */
2714 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
8a8d5d85 2715 if (mycpu->gd_cpuid != apic_id) {
26be20a0
SW		 2716 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2717 kprintf("SMP: apic_id = %d\n", apic_id);
2718 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
984263bc
MD		 2719 panic("cpuid mismatch! boom!!");
2720 }
2721
b52c8db0
SZ		 2722 /* Initialize AP's local APIC for irq's */
2723 apic_initialize(FALSE);
984263bc
MD		 2724
2725 /* Set memory range attributes for this CPU to match the BSP */
2726 mem_range_AP_init();
2727
a2a5ad0d 2728 /*
4c9f5a7f
MD		 2729 * Once we go active we must process any IPIQ messages that may
2730 * have been queued, because no actual IPI will occur until we
2731 * set our bit in the smp_active_mask. If we don't the IPI
2732 * message interlock could be left set which would also prevent
2733 * further IPIs.
2734 *
8a8d5d85
MD		 2735 * The idle loop doesn't expect the BGL to be held and while
2736 * lwkt_switch() normally cleans things up this is a special case
2737 * because we returning almost directly into the idle loop.
41a01a4d
MD		 2738 *
2739 * The idle thread is never placed on the runq, make sure
4c9f5a7f 2740 * nothing we've done put it there.
8a8d5d85 2741 */
96728c05 2742 KKASSERT(curthread->td_mpcount == 1);
41a01a4d 2743 smp_active_mask |= 1 << mycpu->gd_cpuid;
d19f6edf
MD		 2744
2745 /*
2746 * Enable interrupts here. idle_restore will also do it, but
2747 * doing it here lets us clean up any strays that got posted to
2748 * the CPU during the AP boot while we are still in a critical
2749 * section.
2750 */
2751 __asm __volatile("sti; pause; pause"::);
2752 mdcpu->gd_fpending = 0;
d19f6edf 2753
4a19580d 2754 initclocks_pcpu(); /* clock interrupts (via IPIs) */
4c9f5a7f 2755 lwkt_process_ipiq();
d19f6edf
MD		 2756
2757 /*
2758 * Releasing the mp lock lets the BSP finish up the SMP init
2759 */
96728c05 2760 rel_mplock();
41a01a4d 2761 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
984263bc
MD		 2762}
2763
41a01a4d
MD		 2764/*
2765 * Get SMP fully working before we start initializing devices.
2766 */
2767static
2768void
2769ap_finish(void)
2770{
2771 mp_finish = 1;
2772 if (bootverbose)
26be20a0 2773 kprintf("Finish MP startup\n");
374133e3
MD		 2774 if (cpu_feature & CPUID_TSC)
2775 tsc0_offset = rdtsc();
2776 tsc_offsets[0] = 0;
41a01a4d 2777 rel_mplock();
374133e3 2778 while (smp_active_mask != smp_startup_mask) {
35238fa5 2779 cpu_lfence();
374133e3
MD		 2780 if (cpu_feature & CPUID_TSC)
2781 tsc0_offset = rdtsc();
2782 }
4da43e1f 2783 while (try_mplock() == 0)
41a01a4d
MD		 2784 ;
2785 if (bootverbose)
26be20a0 2786 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
41a01a4d
MD		 2787}
2788
ba39e2e0 2789SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
41a01a4d 2790
96728c05
MD		 2791void
2792cpu_send_ipiq(int dcpu)
2793{
41a01a4d
MD		 2794 if ((1 << dcpu) & smp_active_mask)
2795 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
96728c05 2796}
41a01a4d
MD		 2797
2798#if 0 /* single_apic_ipi_passive() not working yet */
2799/*
2800 * Returns 0 on failure, 1 on success
2801 */
2802int
2803cpu_send_ipiq_passive(int dcpu)
2804{
2805 int r = 0;
2806 if ((1 << dcpu) & smp_active_mask) {
2807 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2808 APIC_DELMODE_FIXED);
2809 }
2810 return(r);
2811}
2812#endif
2813
a0873f07
SZ		 2814struct mptable_lapic_cbarg1 {
2815 int cpu_count;
44c36320
SZ		 2816 int ht_fixup;
2817 u_int ht_apicid_mask;
a0873f07
SZ		 2818};
2819
2820static int
2821mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2822{
2823 const struct PROCENTRY *ent;
2824 struct mptable_lapic_cbarg1 *arg = xarg;
2825
2826 if (type != 0)
2827 return 0;
2828 ent = pos;
2829
2830 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2831 return 0;
2832
2833 arg->cpu_count++;
44c36320
SZ		 2834 if (ent->apic_id < 32) {
2835 arg->ht_apicid_mask |= 1 << ent->apic_id;
2836 } else if (arg->ht_fixup) {
2837 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2838 arg->ht_fixup = 0;
2839 }
a0873f07
SZ		 2840 return 0;
2841}
2842
2843struct mptable_lapic_cbarg2 {
2844 int cpu;
44c36320 2845 int logical_cpus;
a0873f07
SZ		 2846 int found_bsp;
2847};
2848
2849static int
2850mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2851{
2852 const struct PROCENTRY *ent;
2853 struct mptable_lapic_cbarg2 *arg = xarg;
2854
2855 if (type != 0)
2856 return 0;
2857 ent = pos;
2858
2859 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2860 KKASSERT(!arg->found_bsp);
2861 arg->found_bsp = 1;
2862 }
2863
2864 if (processor_entry(ent, arg->cpu))
2865 arg->cpu++;
2866
44c36320 2867 if (arg->logical_cpus) {
a0873f07
SZ		 2868 struct PROCENTRY proc;
2869 int i;
2870
2871 /*
2872 * Create fake mptable processor entries
2873 * and feed them to processor_entry() to
2874 * enumerate the logical CPUs.
2875 */
2876 bzero(&proc, sizeof(proc));
2877 proc.type = 0;
2878 proc.cpu_flags = PROCENTRY_FLAG_EN;
2879 proc.apic_id = ent->apic_id;
2880
44c36320 2881 for (i = 1; i < arg->logical_cpus; i++) {
a0873f07
SZ		 2882 proc.apic_id++;
2883 processor_entry(&proc, arg->cpu);
a0873f07
SZ		 2884 arg->cpu++;
2885 }
2886 }
2887 return 0;
2888}
2889
322abba7 2890static void
281d9482
SZ		 2891mptable_imcr(struct mptable_pos *mpt)
2892{
2893 /* record whether PIC or virtual-wire mode */
2894 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2895 mpt->mp_fps->mpfb2 & 0x80);
2896}
2897
2898struct mptable_lapic_enumerator {
2899 struct lapic_enumerator enumerator;
2900 vm_paddr_t mpfps_paddr;
2901};
2902
2903static void
322abba7
SZ		 2904mptable_lapic_default(void)
2905{
2906 int ap_apicid, bsp_apicid;
2907
2908 mp_naps = 1; /* exclude BSP */
2909
2910 /* Map local apic before the id field is accessed */
84cc808b 2911 lapic_map(DEFAULT_APIC_BASE);
322abba7
SZ		 2912
2913 bsp_apicid = APIC_ID(lapic.id);
2914 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2915
2916 /* BSP */
2917 mp_set_cpuids(0, bsp_apicid);
2918 /* one and only AP */
2919 mp_set_cpuids(1, ap_apicid);
2920}
2921
a0873f07
SZ		 2922/*
2923 * Configure:
a0873f07 2924 * mp_naps
d787e80c 2925 * ID_TO_CPU(N), APIC ID to logical CPU table
a0873f07
SZ		 2926 * CPU_TO_ID(N), logical CPU to APIC ID table
2927 */
2928static void
281d9482 2929mptable_lapic_enumerate(struct lapic_enumerator *e)
a0873f07 2930{
281d9482 2931 struct mptable_pos mpt;
322abba7
SZ		 2932 struct mptable_lapic_cbarg1 arg1;
2933 struct mptable_lapic_cbarg2 arg2;
2934 mpcth_t cth;
44c36320 2935 int error, logical_cpus = 0;
5a16ccc3 2936 vm_offset_t lapic_addr;
281d9482
SZ		 2937 vm_paddr_t mpfps_paddr;
2938
2939 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
2940 KKASSERT(mpfps_paddr != 0);
a0873f07 2941
281d9482
SZ		 2942 error = mptable_map(&mpt, mpfps_paddr);
2943 if (error)
2944 panic("mptable_lapic_enumerate mptable_map failed\n");
2945
2946 KKASSERT(mpt.mp_fps != NULL);
a0873f07 2947
322abba7
SZ		 2948 /*
2949 * Check for use of 'default' configuration
2950 */
281d9482 2951 if (mpt.mp_fps->mpfb1 != 0) {
322abba7 2952 mptable_lapic_default();
281d9482 2953 mptable_unmap(&mpt);
322abba7
SZ		 2954 return;
2955 }
a0873f07 2956
281d9482 2957 cth = mpt.mp_cth;
322abba7 2958 KKASSERT(cth != NULL);
a0873f07 2959
322abba7
SZ		 2960 /* Save local apic address */
2961 lapic_addr = (vm_offset_t)cth->apic_address;
2962 KKASSERT(lapic_addr != 0);
a0873f07 2963
322abba7
SZ		 2964 /*
2965 * Find out how many CPUs do we have
2966 */
2967 bzero(&arg1, sizeof(arg1));
44c36320
SZ		 2968 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2969
322abba7
SZ		 2970 error = mptable_iterate_entries(cth,
2971 mptable_lapic_pass1_callback, &arg1);
2972 if (error)
2973 panic("mptable_iterate_entries(lapic_pass1) failed\n");
322abba7 2974 KKASSERT(arg1.cpu_count != 0);
a0873f07 2975
322abba7 2976 /* See if we need to fixup HT logical CPUs. */
44c36320
SZ		 2977 if (arg1.ht_fixup) {
2978 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2979 arg1.cpu_count);
2980 if (logical_cpus != 0)
2981 arg1.cpu_count *= logical_cpus;
2982 }
2983 mp_naps = arg1.cpu_count;
a0873f07 2984
44c36320 2985 /* Qualify the numbers again, after possible HT fixup */
322abba7
SZ		 2986 if (mp_naps > MAXCPU) {
2987 kprintf("Warning: only using %d of %d available CPUs!\n",
2988 MAXCPU, mp_naps);
2989 mp_naps = MAXCPU;
a0873f07
SZ		 2990 }
2991
322abba7 2992 --mp_naps; /* subtract the BSP */
a0873f07 2993
322abba7
SZ		 2994 /*
2995 * Link logical CPU id to local apic id
2996 */
2997 bzero(&arg2, sizeof(arg2));
2998 arg2.cpu = 1;
44c36320 2999 arg2.logical_cpus = logical_cpus;
a0873f07 3000
322abba7
SZ		 3001 error = mptable_iterate_entries(cth,
3002 mptable_lapic_pass2_callback, &arg2);
3003 if (error)
3004 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3005 KKASSERT(arg2.found_bsp);
a0873f07 3006
322abba7 3007 /* Map local apic */
84cc808b 3008 lapic_map(lapic_addr);
281d9482
SZ		 3009
3010 mptable_unmap(&mpt);
3011}
3012
3013static int
3014mptable_lapic_probe(struct lapic_enumerator *e)
3015{
3016 vm_paddr_t mpfps_paddr;
3017
3018 mpfps_paddr = mptable_probe();
3019 if (mpfps_paddr == 0)
3020 return ENXIO;
3021
3022 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3023 return 0;
a0873f07 3024}
5a16ccc3 3025
281d9482
SZ		 3026static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3027 .enumerator = {
3028 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3029 .lapic_probe = mptable_lapic_probe,
3030 .lapic_enumerate = mptable_lapic_enumerate
3031 }
3032};
3033
5a16ccc3 3034static void
281d9482 3035mptable_apic_register(void)
a0eaef71 3036{
281d9482 3037 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
a0eaef71 3038}
281d9482 3039SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);
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