i386 - Get completely rid of APIC_IO
[dragonfly.git] / sys / platform / pc32 / isa / clock.c
CommitLineData
984263bc
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1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 */
39
40/*
41 * Routines to handle clock hardware.
42 */
43
44/*
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
47 *
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
49 */
50
1f2de5d4 51#include "use_apm.h"
984263bc 52#include "opt_clock.h"
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53
54#include <sys/param.h>
55#include <sys/systm.h>
13194089 56#include <sys/eventhandler.h>
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57#include <sys/time.h>
58#include <sys/kernel.h>
e126caf1 59#include <sys/bus.h>
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60#ifndef SMP
61#include <sys/lock.h>
62#endif
63#include <sys/sysctl.h>
64#include <sys/cons.h>
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65#include <sys/systimer.h>
66#include <sys/globaldata.h>
67#include <sys/thread2.h>
68#include <sys/systimer.h>
37e7efec 69#include <sys/machintr.h>
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70
71#include <machine/clock.h>
72#ifdef CLK_CALIBRATION_LOOP
73#endif
74#include <machine/cputypes.h>
75#include <machine/frame.h>
76#include <machine/ipl.h>
77#include <machine/limits.h>
78#include <machine/md_var.h>
79#include <machine/psl.h>
984263bc 80#include <machine/segments.h>
984263bc 81#include <machine/smp.h>
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82#include <machine/specialreg.h>
83
a9295349 84#include <machine_base/icu/icu.h>
21ce0dfa 85#include <bus/isa/isa.h>
1f2de5d4 86#include <bus/isa/rtc.h>
a9295349 87#include <machine_base/isa/timerreg.h>
984263bc 88
a9295349 89#include <machine_base/isa/intr_machdep.h>
984263bc 90
79b62055 91#ifdef SMP /* APIC-IO */
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92/* The interrupt triggered by the 8254 (timer) chip */
93int apic_8254_intr;
3ae0cd58 94static void setup_8254_mixed_mode (void);
984263bc 95#endif
88c4d2f6 96static void i8254_restore(void);
e63ac55d 97static void resettodr_on_shutdown(void *arg __unused);
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98
99/*
100 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
101 * can use a simple formula for leap years.
102 */
103#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
104#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
105
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106#ifndef TIMER_FREQ
107#define TIMER_FREQ 1193182
108#endif
984263bc 109
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110static uint8_t i8254_walltimer_sel;
111static uint16_t i8254_walltimer_cntr;
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112
113int adjkerntz; /* local offset from GMT in seconds */
984263bc 114int disable_rtc_set; /* disable resettodr() if != 0 */
88c4d2f6 115int statclock_disable = 1; /* we don't use the statclock right now */
8b3ec75a 116int tsc_present;
374133e3 117int64_t tsc_frequency;
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118int tsc_is_broken;
119int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
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120int timer0_running;
121enum tstate { RELEASED, ACQUIRED };
122enum tstate timer0_state;
123enum tstate timer1_state;
124enum tstate timer2_state;
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125
126static int beeping = 0;
984263bc 127static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
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128static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
129static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
e63ac55d 130static int rtc_loaded;
984263bc 131
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132static int i8254_cputimer_div;
133
ef612539 134static int i8254_nointr;
e87376d9
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135static int i8254_intr_disable = 0;
136TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
137
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138static struct callout sysbeepstop_ch;
139
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140static sysclock_t i8254_cputimer_count(void);
141static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
142static void i8254_cputimer_destruct(struct cputimer *cputimer);
143
144static struct cputimer i8254_cputimer = {
d8fdd978 145 SLIST_ENTRY_INITIALIZER,
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146 "i8254",
147 CPUTIMER_PRI_8254,
148 0,
149 i8254_cputimer_count,
150 cputimer_default_fromhz,
151 cputimer_default_fromus,
152 i8254_cputimer_construct,
153 i8254_cputimer_destruct,
154 TIMER_FREQ,
5ee041ae 155 0, 0, 0
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156};
157
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158static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
159static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
160static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
161
162static struct cputimer_intr i8254_cputimer_intr = {
163 .freq = TIMER_FREQ,
164 .reload = i8254_intr_reload,
165 .enable = cputimer_intr_default_enable,
166 .config = i8254_intr_config,
167 .restart = cputimer_intr_default_restart,
168 .pmfixup = cputimer_intr_default_pmfixup,
169 .initclock = i8254_intr_initclock,
170 .next = SLIST_ENTRY_INITIALIZER,
171 .name = "i8254",
172 .type = CPUTIMER_INTR_8254,
173 .prio = CPUTIMER_INTR_PRIO_8254,
174 .caps = CPUTIMER_INTR_CAP_PS
175};
176
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177/*
178 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
179 * counting as of this interrupt. We use timer1 in free-running mode (not
180 * generating any interrupts) as our main counter. Each cpu has timeouts
181 * pending.
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182 *
183 * This code is INTR_MPSAFE and may be called without the BGL held.
88c4d2f6 184 */
984263bc 185static void
477d3c1c 186clkintr(void *dummy, void *frame_arg)
984263bc 187{
ec4812b0 188 static sysclock_t sysclock_count; /* NOTE! Must be static */
88c4d2f6 189 struct globaldata *gd = mycpu;
b8a98473 190#ifdef SMP
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191 struct globaldata *gscan;
192 int n;
b8a98473 193#endif
9a47427a 194
b505872f 195 /*
88c4d2f6 196 * SWSTROBE mode is a one-shot, the timer is no longer running
b505872f 197 */
88c4d2f6 198 timer0_running = 0;
b505872f 199
88c4d2f6 200 /*
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201 * XXX the dispatcher needs work. right now we call systimer_intr()
202 * directly or via IPI for any cpu with systimers queued, which is
ec4812b0 203 * usually *ALL* of them. We need to use the LAPIC timer for this.
88c4d2f6 204 */
ec4812b0 205 sysclock_count = sys_cputimer->count();
b8a98473 206#ifdef SMP
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207 for (n = 0; n < ncpus; ++n) {
208 gscan = globaldata_find(n);
774fc796 209 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
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210 continue;
211 if (gscan != gd) {
b8a98473 212 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
ec4812b0 213 &sysclock_count, 0);
88c4d2f6 214 } else {
ec4812b0 215 systimer_intr(&sysclock_count, 0, frame_arg);
88c4d2f6 216 }
984263bc 217 }
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218#else
219 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
ec4812b0 220 systimer_intr(&sysclock_count, 0, frame_arg);
b8a98473 221#endif
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222}
223
88c4d2f6 224
984263bc 225/*
88c4d2f6 226 * NOTE! not MP safe.
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227 */
228int
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229acquire_timer2(int mode)
230{
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231 if (timer2_state != RELEASED)
232 return (-1);
233 timer2_state = ACQUIRED;
234
235 /*
236 * This access to the timer registers is as atomic as possible
237 * because it is a single instruction. We could do better if we
88c4d2f6 238 * knew the rate.
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239 */
240 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
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241 return (0);
242}
243
244int
09e6e929 245release_timer2(void)
984263bc 246{
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247 if (timer2_state != ACQUIRED)
248 return (-1);
984263bc 249 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
88c4d2f6 250 timer2_state = RELEASED;
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251 return (0);
252}
253
254/*
255 * This routine receives statistical clock interrupts from the RTC.
256 * As explained above, these occur at 128 interrupts per second.
257 * When profiling, we receive interrupts at a rate of 1024 Hz.
258 *
259 * This does not actually add as much overhead as it sounds, because
260 * when the statistical clock is active, the hardclock driver no longer
261 * needs to keep (inaccurate) statistics on its own. This decouples
262 * statistics gathering from scheduling interrupts.
263 *
264 * The RTC chip requires that we read status register C (RTC_INTR)
265 * to acknowledge an interrupt, before it will generate the next one.
266 * Under high interrupt load, rtcintr() can be indefinitely delayed and
267 * the clock can tick immediately after the read from RTC_INTR. In this
268 * case, the mc146818A interrupt signal will not drop for long enough
269 * to register with the 8259 PIC. If an interrupt is missed, the stat
270 * clock will halt, considerably degrading system performance. This is
271 * why we use 'while' rather than a more straightforward 'if' below.
272 * Stat clock ticks can still be lost, causing minor loss of accuracy
273 * in the statistics, but the stat clock will no longer stop.
274 */
275static void
477d3c1c 276rtcintr(void *dummy, void *frame)
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277{
278 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
88c4d2f6 279 ;
477d3c1c 280 /* statclock(frame); no longer used */
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281}
282
283#include "opt_ddb.h"
284#ifdef DDB
285#include <ddb/ddb.h>
286
287DB_SHOW_COMMAND(rtc, rtc)
288{
26be20a0 289 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
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290 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
291 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
292 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
293}
294#endif /* DDB */
295
88c4d2f6 296/*
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297 * Return the current cpu timer count as a 32 bit integer.
298 */
044ee7c4 299static
88c4d2f6 300sysclock_t
044ee7c4 301i8254_cputimer_count(void)
88c4d2f6 302{
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303 static __uint16_t cputimer_last;
304 __uint16_t count;
305 sysclock_t ret;
984263bc 306
88c4d2f6 307 clock_lock();
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308 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
309 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
310 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
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311 count = -count; /* -> countup */
312 if (count < cputimer_last) /* rollover */
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313 i8254_cputimer.base += 0x00010000;
314 ret = i8254_cputimer.base | count;
88c4d2f6 315 cputimer_last = count;
8a8d5d85 316 clock_unlock();
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317 return(ret);
318}
319
320/*
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321 * This function is called whenever the system timebase changes, allowing
322 * us to calculate what is needed to convert a system timebase tick
323 * into an 8254 tick for the interrupt timer. If we can convert to a
324 * simple shift, multiplication, or division, we do so. Otherwise 64
325 * bit arithmatic is required every time the interrupt timer is reloaded.
326 */
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327static void
328i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
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329{
330 int freq;
331 int div;
332
333 /*
334 * Will a simple divide do the trick?
335 */
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336 div = (timer->freq + (cti->freq / 2)) / cti->freq;
337 freq = cti->freq * div;
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338
339 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
340 i8254_cputimer_div = div;
341 else
342 i8254_cputimer_div = 0;
343}
344
345/*
88c4d2f6
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346 * Reload for the next timeout. It is possible for the reload value
347 * to be 0 or negative, indicating that an immediate timer interrupt
348 * is desired. For now make the minimum 2 ticks.
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349 *
350 * We may have to convert from the system timebase to the 8254 timebase.
88c4d2f6 351 */
c5c70fac 352static void
ef612539 353i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
88c4d2f6
MD
354{
355 __uint16_t count;
356
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357 if (i8254_cputimer_div)
358 reload /= i8254_cputimer_div;
359 else
ef612539 360 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
5ee041ae 361
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362 if ((int)reload < 2)
363 reload = 2;
364
365 clock_lock();
366 if (timer0_running) {
367 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
368 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
369 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
370 if (reload < count) {
371 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
372 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
373 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
374 }
375 } else {
376 timer0_running = 1;
377 if (reload > 0xFFFF)
378 reload = 0; /* full count */
379 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
380 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
381 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
382 }
383 clock_unlock();
984263bc
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384}
385
386/*
dbcd0c9b
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387 * DELAY(usec) - Spin for the specified number of microseconds.
388 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
389 * but do a thread switch in the loop
390 *
88c4d2f6 391 * Relies on timer 1 counting down from (cputimer_freq / hz)
984263bc
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392 * Note: timer had better have been programmed before this is first used!
393 */
dbcd0c9b
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394static void
395DODELAY(int n, int doswitch)
984263bc
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396{
397 int delta, prev_tick, tick, ticks_left;
398
399#ifdef DELAYDEBUG
400 int getit_calls = 1;
401 int n1;
402 static int state = 0;
403
404 if (state == 0) {
405 state = 1;
406 for (n1 = 1; n1 <= 10000000; n1 *= 10)
407 DELAY(n1);
408 state = 2;
409 }
410 if (state == 1)
26be20a0 411 kprintf("DELAY(%d)...", n);
984263bc
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412#endif
413 /*
414 * Guard against the timer being uninitialized if we are called
415 * early for console i/o.
416 */
88c4d2f6
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417 if (timer0_state == RELEASED)
418 i8254_restore();
984263bc
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419
420 /*
421 * Read the counter first, so that the rest of the setup overhead is
1636ba19
MD
422 * counted. Then calculate the number of hardware timer ticks
423 * required, rounding up to be sure we delay at least the requested
424 * number of microseconds.
984263bc 425 */
044ee7c4 426 prev_tick = sys_cputimer->count();
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427 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
428 1000000;
429
984263bc 430 /*
1636ba19 431 * Loop until done.
984263bc 432 */
984263bc 433 while (ticks_left > 0) {
044ee7c4 434 tick = sys_cputimer->count();
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435#ifdef DELAYDEBUG
436 ++getit_calls;
437#endif
88c4d2f6 438 delta = tick - prev_tick;
984263bc 439 prev_tick = tick;
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440 if (delta < 0)
441 delta = 0;
984263bc 442 ticks_left -= delta;
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443 if (doswitch && ticks_left > 0)
444 lwkt_switch();
c5724852 445 cpu_pause();
984263bc
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446 }
447#ifdef DELAYDEBUG
448 if (state == 1)
26be20a0 449 kprintf(" %d calls to getit() at %d usec each\n",
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450 getit_calls, (n + 5) / getit_calls);
451#endif
452}
453
77912481
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454/*
455 * DELAY() never switches
456 */
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457void
458DELAY(int n)
459{
460 DODELAY(n, 0);
461}
462
77912481
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463/*
464 * DRIVERSLEEP() does not switch if called with a spinlock held or
465 * from a hard interrupt.
466 */
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467void
468DRIVERSLEEP(int usec)
469{
470 globaldata_t gd = mycpu;
471
8f165b8c 472 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) {
dbcd0c9b
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473 DODELAY(usec, 0);
474 } else {
475 DODELAY(usec, 1);
476 }
477}
478
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479static void
480sysbeepstop(void *chan)
481{
482 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
984263bc 483 beeping = 0;
88c4d2f6 484 release_timer2();
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485}
486
487int
488sysbeep(int pitch, int period)
489{
984263bc 490 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
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491 return(-1);
492 /*
493 * Nobody else is using timer2, we do not need the clock lock
494 */
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495 outb(TIMER_CNTR2, pitch);
496 outb(TIMER_CNTR2, (pitch>>8));
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497 if (!beeping) {
498 /* enable counter2 output to speaker */
499 outb(IO_PPI, inb(IO_PPI) | 3);
500 beeping = period;
b02bbab0 501 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
984263bc 502 }
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503 return (0);
504}
505
506/*
507 * RTC support routines
508 */
509
510int
09e6e929 511rtcin(int reg)
984263bc 512{
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513 u_char val;
514
9acd5bbb 515 crit_enter();
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516 outb(IO_RTC, reg);
517 inb(0x84);
518 val = inb(IO_RTC + 1);
519 inb(0x84);
9acd5bbb 520 crit_exit();
984263bc
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521 return (val);
522}
523
524static __inline void
525writertc(u_char reg, u_char val)
526{
9acd5bbb 527 crit_enter();
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528 inb(0x84);
529 outb(IO_RTC, reg);
530 inb(0x84);
531 outb(IO_RTC + 1, val);
532 inb(0x84); /* XXX work around wrong order in rtcin() */
9acd5bbb 533 crit_exit();
984263bc
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534}
535
536static __inline int
537readrtc(int port)
538{
539 return(bcd2bin(rtcin(port)));
540}
541
542static u_int
543calibrate_clocks(void)
544{
545 u_int64_t old_tsc;
546 u_int count, prev_count, tot_count;
547 int sec, start_sec, timeout;
548
549 if (bootverbose)
26be20a0 550 kprintf("Calibrating clock(s) ... ");
984263bc
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551 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
552 goto fail;
553 timeout = 100000000;
554
555 /* Read the mc146818A seconds counter. */
556 for (;;) {
557 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
558 sec = rtcin(RTC_SEC);
559 break;
560 }
561 if (--timeout == 0)
562 goto fail;
563 }
564
565 /* Wait for the mC146818A seconds counter to change. */
566 start_sec = sec;
567 for (;;) {
568 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
569 sec = rtcin(RTC_SEC);
570 if (sec != start_sec)
571 break;
572 }
573 if (--timeout == 0)
574 goto fail;
575 }
576
577 /* Start keeping track of the i8254 counter. */
044ee7c4 578 prev_count = sys_cputimer->count();
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579 tot_count = 0;
580
581 if (tsc_present)
582 old_tsc = rdtsc();
583 else
584 old_tsc = 0; /* shut up gcc */
585
586 /*
587 * Wait for the mc146818A seconds counter to change. Read the i8254
588 * counter for each iteration since this is convenient and only
589 * costs a few usec of inaccuracy. The timing of the final reads
590 * of the counters almost matches the timing of the initial reads,
591 * so the main cause of inaccuracy is the varying latency from
592 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
593 * rtcin(RTC_SEC) that returns a changed seconds count. The
594 * maximum inaccuracy from this cause is < 10 usec on 486's.
595 */
596 start_sec = sec;
597 for (;;) {
598 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
599 sec = rtcin(RTC_SEC);
044ee7c4 600 count = sys_cputimer->count();
88c4d2f6 601 tot_count += (int)(count - prev_count);
984263bc
MD
602 prev_count = count;
603 if (sec != start_sec)
604 break;
605 if (--timeout == 0)
606 goto fail;
607 }
608
609 /*
610 * Read the cpu cycle counter. The timing considerations are
611 * similar to those for the i8254 clock.
612 */
374133e3
MD
613 if (tsc_present) {
614 tsc_frequency = rdtsc() - old_tsc;
374133e3 615 }
984263bc 616
c17827b4 617 if (tsc_present)
870b0161 618 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
26be20a0 619 kprintf("i8254 clock: %u Hz\n", tot_count);
984263bc
MD
620 return (tot_count);
621
622fail:
26be20a0 623 kprintf("failed, using default i8254 clock of %u Hz\n",
044ee7c4
MD
624 i8254_cputimer.freq);
625 return (i8254_cputimer.freq);
984263bc
MD
626}
627
628static void
629i8254_restore(void)
630{
88c4d2f6 631 timer0_state = ACQUIRED;
e54beab0 632
044ee7c4
MD
633 clock_lock();
634
635 /*
636 * Timer0 is our fine-grained variable clock interrupt
637 */
638 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
639 outb(TIMER_CNTR0, 2); /* lsb */
640 outb(TIMER_CNTR0, 0); /* msb */
ee31250e 641 clock_unlock();
044ee7c4 642
ef612539
SZ
643 if (!i8254_nointr) {
644 cputimer_intr_register(&i8254_cputimer_intr);
645 cputimer_intr_select(&i8254_cputimer_intr, 0);
646 }
647
044ee7c4
MD
648 /*
649 * Timer1 or timer2 is our free-running clock, but only if another
650 * has not been selected.
651 */
5ee041ae
MD
652 cputimer_register(&i8254_cputimer);
653 cputimer_select(&i8254_cputimer, 0);
044ee7c4
MD
654}
655
656static void
657i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
658{
659 int which;
660
661 /*
662 * Should we use timer 1 or timer 2 ?
663 */
664 which = 0;
665 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
666 if (which != 1 && which != 2)
667 which = 2;
668
669 switch(which) {
670 case 1:
671 timer->name = "i8254_timer1";
672 timer->type = CPUTIMER_8254_SEL1;
e54beab0
JS
673 i8254_walltimer_sel = TIMER_SEL1;
674 i8254_walltimer_cntr = TIMER_CNTR1;
675 timer1_state = ACQUIRED;
044ee7c4
MD
676 break;
677 case 2:
678 timer->name = "i8254_timer2";
679 timer->type = CPUTIMER_8254_SEL2;
e54beab0
JS
680 i8254_walltimer_sel = TIMER_SEL2;
681 i8254_walltimer_cntr = TIMER_CNTR2;
682 timer2_state = ACQUIRED;
044ee7c4 683 break;
e54beab0 684 }
044ee7c4
MD
685
686 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
687
ee31250e 688 clock_lock();
e54beab0
JS
689 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
690 outb(i8254_walltimer_cntr, 0); /* lsb */
691 outb(i8254_walltimer_cntr, 0); /* msb */
88c4d2f6 692 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
ee31250e 693 clock_unlock();
044ee7c4
MD
694}
695
696static void
697i8254_cputimer_destruct(struct cputimer *timer)
698{
699 switch(timer->type) {
700 case CPUTIMER_8254_SEL1:
701 timer1_state = RELEASED;
702 break;
703 case CPUTIMER_8254_SEL2:
704 timer2_state = RELEASED;
705 break;
706 default:
707 break;
708 }
709 timer->type = 0;
984263bc
MD
710}
711
712static void
713rtc_restore(void)
714{
984263bc
MD
715 /* Restore all of the RTC's "status" (actually, control) registers. */
716 writertc(RTC_STATUSB, RTCSB_24HR);
717 writertc(RTC_STATUSA, rtc_statusa);
718 writertc(RTC_STATUSB, rtc_statusb);
719}
720
721/*
0284027e 722 * Restore all the timers.
984263bc 723 *
0d1dffdf
MD
724 * This function is called to resynchronize our core timekeeping after a
725 * long halt, e.g. from apm_default_resume() and friends. It is also
726 * called if after a BIOS call we have detected munging of the 8254.
727 * It is necessary because cputimer_count() counter's delta may have grown
728 * too large for nanouptime() and friends to handle, or (in the case of 8254
729 * munging) might cause the SYSTIMER code to prematurely trigger.
984263bc
MD
730 */
731void
732timer_restore(void)
733{
0284027e 734 crit_enter();
984263bc
MD
735 i8254_restore(); /* restore timer_freq and hz */
736 rtc_restore(); /* reenable RTC interrupts */
0284027e 737 crit_exit();
984263bc
MD
738}
739
740/*
741 * Initialize 8254 timer 0 early so that it can be used in DELAY().
984263bc
MD
742 */
743void
09e6e929 744startrtclock(void)
984263bc
MD
745{
746 u_int delta, freq;
747
88c4d2f6
MD
748 /*
749 * Can we use the TSC?
750 */
984263bc
MD
751 if (cpu_feature & CPUID_TSC)
752 tsc_present = 1;
753 else
754 tsc_present = 0;
755
88c4d2f6
MD
756 /*
757 * Initial RTC state, don't do anything unexpected
758 */
984263bc
MD
759 writertc(RTC_STATUSA, rtc_statusa);
760 writertc(RTC_STATUSB, RTCSB_24HR);
761
88c4d2f6
MD
762 /*
763 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
764 * generate an interrupt, which we will ignore for now.
765 *
766 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
767 * (so it counts a full 2^16 and repeats). We will use this timer
768 * for our counting.
769 */
770 i8254_restore();
984263bc
MD
771 freq = calibrate_clocks();
772#ifdef CLK_CALIBRATION_LOOP
773 if (bootverbose) {
26be20a0 774 kprintf(
984263bc
MD
775 "Press a key on the console to abort clock calibration\n");
776 while (cncheckc() == -1)
777 calibrate_clocks();
778 }
779#endif
780
781 /*
782 * Use the calibrated i8254 frequency if it seems reasonable.
783 * Otherwise use the default, and don't use the calibrated i586
784 * frequency.
785 */
044ee7c4
MD
786 delta = freq > i8254_cputimer.freq ?
787 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
788 if (delta < i8254_cputimer.freq / 100) {
984263bc
MD
789#ifndef CLK_USE_I8254_CALIBRATION
790 if (bootverbose)
26be20a0 791 kprintf(
984263bc 792"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
044ee7c4 793 freq = i8254_cputimer.freq;
984263bc 794#endif
ef612539
SZ
795 /*
796 * NOTE:
797 * Interrupt timer's freq must be adjusted
798 * before we change the cuptimer's frequency.
799 */
800 i8254_cputimer_intr.freq = freq;
5ee041ae 801 cputimer_set_frequency(&i8254_cputimer, freq);
984263bc
MD
802 } else {
803 if (bootverbose)
26be20a0 804 kprintf(
984263bc 805 "%d Hz differs from default of %d Hz by more than 1%%\n",
044ee7c4 806 freq, i8254_cputimer.freq);
374133e3 807 tsc_frequency = 0;
984263bc
MD
808 }
809
984263bc 810#ifndef CLK_USE_TSC_CALIBRATION
870b0161 811 if (tsc_frequency != 0) {
984263bc 812 if (bootverbose)
26be20a0 813 kprintf(
984263bc 814"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
374133e3 815 tsc_frequency = 0;
984263bc
MD
816 }
817#endif
374133e3 818 if (tsc_present && tsc_frequency == 0) {
984263bc
MD
819 /*
820 * Calibration of the i586 clock relative to the mc146818A
821 * clock failed. Do a less accurate calibration relative
822 * to the i8254 clock.
823 */
824 u_int64_t old_tsc = rdtsc();
825
826 DELAY(1000000);
374133e3 827 tsc_frequency = rdtsc() - old_tsc;
984263bc 828#ifdef CLK_USE_TSC_CALIBRATION
870b0161
MD
829 if (bootverbose) {
830 kprintf("TSC clock: %llu Hz (Method B)\n",
831 tsc_frequency);
832 }
984263bc
MD
833#endif
834 }
835
87e2fa7e 836 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
13194089 837
984263bc
MD
838#if !defined(SMP)
839 /*
840 * We can not use the TSC in SMP mode, until we figure out a
841 * cheap (impossible), reliable and precise (yeah right!) way
842 * to synchronize the TSCs of all the CPUs.
843 * Curse Intel for leaving the counter out of the I/O APIC.
844 */
845
846#if NAPM > 0
847 /*
848 * We can not use the TSC if we support APM. Precise timekeeping
849 * on an APM'ed machine is at best a fools pursuit, since
850 * any and all of the time spent in various SMM code can't
851 * be reliably accounted for. Reading the RTC is your only
852 * source of reliable time info. The i8254 looses too of course
853 * but we need to have some kind of time...
854 * We don't know at this point whether APM is going to be used
855 * or not, nor when it might be activated. Play it safe.
856 */
857 return;
858#endif /* NAPM > 0 */
859
984263bc
MD
860#endif /* !defined(SMP) */
861}
862
863/*
e63ac55d
MD
864 * Sync the time of day back to the RTC on shutdown, but only if
865 * we have already loaded it and have not crashed.
866 */
867static void
868resettodr_on_shutdown(void *arg __unused)
869{
870 if (rtc_loaded && panicstr == NULL) {
871 resettodr();
872 }
873}
874
875/*
984263bc
MD
876 * Initialize the time of day register, based on the time base which is, e.g.
877 * from a filesystem.
878 */
879void
880inittodr(time_t base)
881{
882 unsigned long sec, days;
984263bc 883 int year, month;
88c4d2f6 884 int y, m;
984263bc
MD
885 struct timespec ts;
886
887 if (base) {
984263bc
MD
888 ts.tv_sec = base;
889 ts.tv_nsec = 0;
88c4d2f6 890 set_timeofday(&ts);
984263bc
MD
891 }
892
893 /* Look if we have a RTC present and the time is valid */
894 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
895 goto wrong_time;
896
897 /* wait for time update to complete */
898 /* If RTCSA_TUP is zero, we have at least 244us before next update */
88c4d2f6 899 crit_enter();
984263bc 900 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
88c4d2f6
MD
901 crit_exit();
902 crit_enter();
984263bc
MD
903 }
904
905 days = 0;
906#ifdef USE_RTC_CENTURY
907 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
908#else
909 year = readrtc(RTC_YEAR) + 1900;
910 if (year < 1970)
911 year += 100;
912#endif
913 if (year < 1970) {
88c4d2f6 914 crit_exit();
984263bc
MD
915 goto wrong_time;
916 }
917 month = readrtc(RTC_MONTH);
918 for (m = 1; m < month; m++)
919 days += daysinmonth[m-1];
920 if ((month > 2) && LEAPYEAR(year))
921 days ++;
922 days += readrtc(RTC_DAY) - 1;
984263bc
MD
923 for (y = 1970; y < year; y++)
924 days += DAYSPERYEAR + LEAPYEAR(y);
925 sec = ((( days * 24 +
926 readrtc(RTC_HRS)) * 60 +
927 readrtc(RTC_MIN)) * 60 +
928 readrtc(RTC_SEC));
929 /* sec now contains the number of seconds, since Jan 1 1970,
930 in the local time zone */
931
932 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
933
934 y = time_second - sec;
935 if (y <= -2 || y >= 2) {
936 /* badly off, adjust it */
937 ts.tv_sec = sec;
938 ts.tv_nsec = 0;
88c4d2f6 939 set_timeofday(&ts);
984263bc 940 }
e63ac55d 941 rtc_loaded = 1;
88c4d2f6 942 crit_exit();
984263bc
MD
943 return;
944
945wrong_time:
26be20a0
SW
946 kprintf("Invalid time in real time clock.\n");
947 kprintf("Check and reset the date immediately!\n");
984263bc
MD
948}
949
950/*
951 * Write system time back to RTC
952 */
953void
09e6e929 954resettodr(void)
984263bc 955{
2f70966e
MD
956 struct timeval tv;
957 unsigned long tm;
958 int m;
959 int y;
984263bc
MD
960
961 if (disable_rtc_set)
962 return;
963
2f70966e
MD
964 microtime(&tv);
965 tm = tv.tv_sec;
984263bc 966
88c4d2f6 967 crit_enter();
984263bc
MD
968 /* Disable RTC updates and interrupts. */
969 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
970
971 /* Calculate local time to put in RTC */
972
973 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
974
975 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
976 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
977 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
978
979 /* We have now the days since 01-01-1970 in tm */
980 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
981 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
982 tm >= m;
983 y++, m = DAYSPERYEAR + LEAPYEAR(y))
984 tm -= m;
985
986 /* Now we have the years in y and the day-of-the-year in tm */
987 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
988#ifdef USE_RTC_CENTURY
989 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
990#endif
991 for (m = 0; ; m++) {
992 int ml;
993
994 ml = daysinmonth[m];
995 if (m == 1 && LEAPYEAR(y))
996 ml++;
997 if (tm < ml)
998 break;
999 tm -= ml;
1000 }
1001
1002 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
1003 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
1004
1005 /* Reenable RTC updates and interrupts. */
1006 writertc(RTC_STATUSB, rtc_statusb);
88c4d2f6 1007 crit_exit();
984263bc
MD
1008}
1009
1010
1011/*
88c4d2f6
MD
1012 * Start both clocks running. DragonFly note: the stat clock is no longer
1013 * used. Instead, 8254 based systimers are used for all major clock
1014 * interrupts. statclock_disable is set by default.
984263bc 1015 */
ef612539
SZ
1016static void
1017i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
984263bc 1018{
38015462 1019 int diag;
79b62055 1020#ifdef SMP /* APIC-IO */
984263bc 1021 int apic_8254_trial;
477d3c1c 1022 void *clkdesc;
79b62055 1023#endif
984263bc 1024
38015462
SZ
1025 callout_init(&sysbeepstop_ch);
1026
ef612539
SZ
1027 if (!selected && i8254_intr_disable) {
1028 i8254_nointr = 1; /* don't try to register again */
1029 cputimer_intr_deregister(cti);
e87376d9 1030 return;
ef612539 1031 }
e87376d9 1032
38015462
SZ
1033 if (statclock_disable) {
1034 /*
1035 * The stat interrupt mask is different without the
1036 * statistics clock. Also, don't set the interrupt
1037 * flag which would normally cause the RTC to generate
1038 * interrupts.
1039 */
1040 rtc_statusb = RTCSB_24HR;
1041 } else {
1042 /* Setting stathz to nonzero early helps avoid races. */
1043 stathz = RTC_NOPROFRATE;
1044 profhz = RTC_PROFRATE;
1045 }
1046
984263bc 1047 /* Finish initializing 8253 timer 0. */
79b62055
MN
1048#ifdef SMP /* APIC-IO */
1049if (apic_io_enable) {
984263bc
MD
1050 apic_8254_intr = isa_apic_irq(0);
1051 apic_8254_trial = 0;
1052 if (apic_8254_intr >= 0 ) {
1053 if (apic_int_type(0, 0) == 3)
1054 apic_8254_trial = 1;
1055 } else {
1056 /* look for ExtInt on pin 0 */
1057 if (apic_int_type(0, 0) == 3) {
1058 apic_8254_intr = apic_irq(0, 0);
1059 setup_8254_mixed_mode();
1060 } else
1061 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1062 }
1063
9d522d14
MD
1064 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk",
1065 NULL,
f8a09be1 1066 INTR_EXCL | INTR_CLOCK |
8b3ec75a
MD
1067 INTR_NOPOLL | INTR_MPSAFE |
1068 INTR_NOENTROPY);
37e7efec 1069 machintr_intren(apic_8254_intr);
79b62055
MN
1070} else {
1071#endif
38015462 1072 register_int(0, clkintr, NULL, "clk", NULL,
f8a09be1 1073 INTR_EXCL | INTR_CLOCK |
38015462
SZ
1074 INTR_NOPOLL | INTR_MPSAFE |
1075 INTR_NOENTROPY);
1076 machintr_intren(ICU_IRQ0);
79b62055
MN
1077#ifdef SMP /* APIC-IO */
1078}
1079#endif
38015462
SZ
1080
1081 /* Initialize RTC. */
1082 writertc(RTC_STATUSA, rtc_statusa);
1083 writertc(RTC_STATUSB, RTCSB_24HR);
1084
1085 if (statclock_disable == 0) {
1086 diag = rtcin(RTC_DIAG);
1087 if (diag != 0)
1088 kprintf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
984263bc 1089
79b62055
MN
1090#ifdef SMP /* APIC-IO */
1091if (apic_io_enable) {
38015462
SZ
1092 if (isa_apic_irq(8) != 8)
1093 panic("APIC RTC != 8");
79b62055
MN
1094}
1095#endif
38015462
SZ
1096
1097 register_int(8, (inthand2_t *)rtcintr, NULL, "rtc", NULL,
f8a09be1 1098 INTR_EXCL | INTR_CLOCK | INTR_NOPOLL |
38015462
SZ
1099 INTR_NOENTROPY);
1100 machintr_intren(8);
1101
1102 writertc(RTC_STATUSB, rtc_statusb);
1103 }
1104
79b62055
MN
1105#ifdef SMP /* APIC-IO */
1106if (apic_io_enable) {
984263bc 1107 if (apic_8254_trial) {
88c4d2f6 1108 sysclock_t base;
477d3c1c
MD
1109 long lastcnt;
1110
c5c70fac
SZ
1111 /*
1112 * Following code assumes the 8254 is the cpu timer,
1113 * so make sure it is.
1114 */
1115 KKASSERT(sys_cputimer == &i8254_cputimer);
ef612539 1116 KKASSERT(cti == &i8254_cputimer_intr);
c5c70fac 1117
477d3c1c 1118 lastcnt = get_interrupt_counter(apic_8254_intr);
88c4d2f6
MD
1119
1120 /*
c5c70fac
SZ
1121 * Force an 8254 Timer0 interrupt and wait 1/100s for
1122 * it to happen, then see if we got it.
88c4d2f6 1123 */
26be20a0 1124 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
ef612539 1125 i8254_intr_reload(cti, 2);
044ee7c4
MD
1126 base = sys_cputimer->count();
1127 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
984263bc 1128 ; /* nothing */
477d3c1c 1129 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) {
984263bc
MD
1130 /*
1131 * The MP table is broken.
1132 * The 8254 was not connected to the specified pin
1133 * on the IO APIC.
1134 * Workaround: Limited variant of mixed mode.
1135 */
37e7efec 1136 machintr_intrdis(apic_8254_intr);
9d522d14 1137 unregister_int(clkdesc);
26be20a0 1138 kprintf("APIC_IO: Broken MP table detected: "
984263bc
MD
1139 "8254 is not connected to "
1140 "IOAPIC #%d intpin %d\n",
1141 int_to_apicintpin[apic_8254_intr].ioapic,
1142 int_to_apicintpin[apic_8254_intr].int_pin);
1143 /*
1144 * Revoke current ISA IRQ 0 assignment and
1145 * configure a fallback interrupt routing from
1146 * the 8254 Timer via the 8259 PIC to the
1147 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1148 * We reuse the low level interrupt handler number.
1149 */
1150 if (apic_irq(0, 0) < 0) {
1151 revoke_apic_irq(apic_8254_intr);
1152 assign_apic_irq(0, 0, apic_8254_intr);
1153 }
1154 apic_8254_intr = apic_irq(0, 0);
1155 setup_8254_mixed_mode();
9d522d14
MD
1156 register_int(apic_8254_intr, clkintr, NULL, "clk",
1157 NULL,
f8a09be1 1158 INTR_EXCL | INTR_CLOCK |
8b3ec75a
MD
1159 INTR_NOPOLL | INTR_MPSAFE |
1160 INTR_NOENTROPY);
37e7efec 1161 machintr_intren(apic_8254_intr);
984263bc 1162 }
984263bc
MD
1163 }
1164 if (apic_int_type(0, 0) != 3 ||
1165 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
88c4d2f6 1166 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
26be20a0 1167 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
984263bc
MD
1168 int_to_apicintpin[apic_8254_intr].ioapic,
1169 int_to_apicintpin[apic_8254_intr].int_pin);
88c4d2f6 1170 } else {
26be20a0 1171 kprintf("APIC_IO: "
984263bc 1172 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
88c4d2f6 1173 }
79b62055 1174}
38015462 1175#endif
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1176}
1177
79b62055 1178#ifdef SMP /* APIC-IO */
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1179
1180static void
09e6e929 1181setup_8254_mixed_mode(void)
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1182{
1183 /*
1184 * Allow 8254 timer to INTerrupt 8259:
1185 * re-initialize master 8259:
1186 * reset; prog 4 bytes, single ICU, edge triggered
1187 */
1188 outb(IO_ICU1, 0x13);
97359a5b 1189 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
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1190 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1191 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1192 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1193
1194 /* program IO APIC for type 3 INT on INT0 */
1195 if (ext_int_setup(0, 0) < 0)
1196 panic("8254 redirect via APIC pin0 impossible!");
1197}
1198#endif
1199
1200void
1201setstatclockrate(int newhz)
1202{
1203 if (newhz == RTC_PROFRATE)
1204 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1205 else
1206 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1207 writertc(RTC_STATUSA, rtc_statusa);
1208}
1209
88c4d2f6 1210#if 0
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1211static unsigned
1212tsc_get_timecount(struct timecounter *tc)
1213{
1214 return (rdtsc());
1215}
88c4d2f6 1216#endif
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1217
1218#ifdef KERN_TIMESTAMP
1219#define KERN_TIMESTAMP_SIZE 16384
1220static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1221SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1222 sizeof(tsc), "LU", "Kernel timestamps");
1223void
1224_TSTMP(u_int32_t x)
1225{
1226 static int i;
1227
1228 tsc[i] = (u_int32_t)rdtsc();
1229 tsc[i+1] = x;
1230 i = i + 2;
1231 if (i >= KERN_TIMESTAMP_SIZE)
1232 i = 0;
1233 tsc[i] = 0; /* mark last entry */
1234}
6b08710e 1235#endif /* KERN_TIMESTAMP */
984263bc 1236
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1237/*
1238 *
1239 */
1240
1241static int
1242hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1243{
1244 sysclock_t count;
1245 __uint64_t tscval;
1246 char buf[32];
1247
1248 crit_enter();
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1249 if (sys_cputimer == &i8254_cputimer)
1250 count = sys_cputimer->count();
1251 else
1252 count = 0;
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1253 if (tsc_present)
1254 tscval = rdtsc();
1255 else
1256 tscval = 0;
1257 crit_exit();
f8c7a42d 1258 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
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1259 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1260}
1261
1262SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
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1263SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1264 "frequency");
c17827b4 1265SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
044ee7c4 1266 0, 0, hw_i8254_timestamp, "A", "");
c17827b4 1267
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1268SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1269 &tsc_present, 0, "TSC Available");
1270SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1271 &tsc_frequency, 0, "TSC Frequency");
1272