Commit | Line | Data |
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06f5be02 MD |
1 | /* |
2 | * Copyright (c) 2005 The DragonFly Project. All rights reserved. | |
10ff1029 MD |
3 | * Copyright (c) 1996, by Steve Passe. All rights reserved. |
4 | * Copyright (c) 1991 The Regents of the University of California. | |
5 | * All rights reserved. | |
06f5be02 MD |
6 | * |
7 | * This code is derived from software contributed to The DragonFly Project | |
8 | * by Matthew Dillon <dillon@backplane.com> | |
10ff1029 MD |
9 | * |
10 | * This code is derived from software contributed to Berkeley by | |
11 | * William Jolitz. | |
06f5be02 MD |
12 | * |
13 | * Redistribution and use in source and binary forms, with or without | |
14 | * modification, are permitted provided that the following conditions | |
15 | * are met: | |
16 | * | |
17 | * 1. Redistributions of source code must retain the above copyright | |
18 | * notice, this list of conditions and the following disclaimer. | |
19 | * 2. Redistributions in binary form must reproduce the above copyright | |
20 | * notice, this list of conditions and the following disclaimer in | |
21 | * the documentation and/or other materials provided with the | |
22 | * distribution. | |
23 | * 3. Neither the name of The DragonFly Project nor the names of its | |
24 | * contributors may be used to endorse or promote products derived | |
25 | * from this software without specific, prior written permission. | |
26 | * | |
27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
28 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | |
30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | |
31 | * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
32 | * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, | |
33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED | |
35 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | |
37 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
38 | * SUCH DAMAGE. | |
37e7efec MD |
39 | */ |
40 | ||
41 | #include <sys/param.h> | |
42 | #include <sys/systm.h> | |
43 | #include <sys/kernel.h> | |
44 | #include <sys/machintr.h> | |
10ff1029 MD |
45 | #include <sys/interrupt.h> |
46 | #include <sys/bus.h> | |
0f3e19b1 | 47 | #include <sys/rman.h> |
9dba15ae | 48 | #include <sys/thread2.h> |
0b692e79 | 49 | |
37e7efec | 50 | #include <machine/smp.h> |
10ff1029 MD |
51 | #include <machine/segments.h> |
52 | #include <machine/md_var.h> | |
87cf6827 | 53 | #include <machine/intr_machdep.h> |
0b692e79 | 54 | #include <machine/globaldata.h> |
be98308a | 55 | #include <machine/msi_var.h> |
0b692e79 | 56 | |
58587c23 | 57 | #include <machine_base/isa/isa_intr.h> |
4298586a | 58 | #include <machine_base/icu/icu.h> |
6b809ec7 | 59 | #include <machine_base/icu/icu_var.h> |
4298586a | 60 | #include <machine_base/apic/ioapic.h> |
929c940f | 61 | #include <machine_base/apic/ioapic_abi.h> |
77f86d14 | 62 | #include <machine_base/apic/ioapic_ipl.h> |
1e7aaefa | 63 | #include <machine_base/apic/apicreg.h> |
37e7efec | 64 | |
5db2f26e | 65 | #include <dev/acpica/acpi_sci_var.h> |
9dba15ae | 66 | |
b2150df1 SZ |
67 | #define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS |
68 | ||
10ff1029 | 69 | extern inthand_t |
9e0e3f85 SZ |
70 | IDTVEC(ioapic_intr0), |
71 | IDTVEC(ioapic_intr1), | |
72 | IDTVEC(ioapic_intr2), | |
73 | IDTVEC(ioapic_intr3), | |
74 | IDTVEC(ioapic_intr4), | |
75 | IDTVEC(ioapic_intr5), | |
76 | IDTVEC(ioapic_intr6), | |
77 | IDTVEC(ioapic_intr7), | |
78 | IDTVEC(ioapic_intr8), | |
79 | IDTVEC(ioapic_intr9), | |
80 | IDTVEC(ioapic_intr10), | |
81 | IDTVEC(ioapic_intr11), | |
82 | IDTVEC(ioapic_intr12), | |
83 | IDTVEC(ioapic_intr13), | |
84 | IDTVEC(ioapic_intr14), | |
85 | IDTVEC(ioapic_intr15), | |
86 | IDTVEC(ioapic_intr16), | |
87 | IDTVEC(ioapic_intr17), | |
88 | IDTVEC(ioapic_intr18), | |
89 | IDTVEC(ioapic_intr19), | |
90 | IDTVEC(ioapic_intr20), | |
91 | IDTVEC(ioapic_intr21), | |
92 | IDTVEC(ioapic_intr22), | |
93 | IDTVEC(ioapic_intr23), | |
94 | IDTVEC(ioapic_intr24), | |
95 | IDTVEC(ioapic_intr25), | |
96 | IDTVEC(ioapic_intr26), | |
97 | IDTVEC(ioapic_intr27), | |
98 | IDTVEC(ioapic_intr28), | |
99 | IDTVEC(ioapic_intr29), | |
100 | IDTVEC(ioapic_intr30), | |
101 | IDTVEC(ioapic_intr31), | |
102 | IDTVEC(ioapic_intr32), | |
103 | IDTVEC(ioapic_intr33), | |
104 | IDTVEC(ioapic_intr34), | |
105 | IDTVEC(ioapic_intr35), | |
106 | IDTVEC(ioapic_intr36), | |
107 | IDTVEC(ioapic_intr37), | |
108 | IDTVEC(ioapic_intr38), | |
109 | IDTVEC(ioapic_intr39), | |
110 | IDTVEC(ioapic_intr40), | |
111 | IDTVEC(ioapic_intr41), | |
112 | IDTVEC(ioapic_intr42), | |
113 | IDTVEC(ioapic_intr43), | |
114 | IDTVEC(ioapic_intr44), | |
115 | IDTVEC(ioapic_intr45), | |
116 | IDTVEC(ioapic_intr46), | |
117 | IDTVEC(ioapic_intr47), | |
118 | IDTVEC(ioapic_intr48), | |
119 | IDTVEC(ioapic_intr49), | |
120 | IDTVEC(ioapic_intr50), | |
121 | IDTVEC(ioapic_intr51), | |
122 | IDTVEC(ioapic_intr52), | |
123 | IDTVEC(ioapic_intr53), | |
124 | IDTVEC(ioapic_intr54), | |
125 | IDTVEC(ioapic_intr55), | |
126 | IDTVEC(ioapic_intr56), | |
127 | IDTVEC(ioapic_intr57), | |
128 | IDTVEC(ioapic_intr58), | |
129 | IDTVEC(ioapic_intr59), | |
130 | IDTVEC(ioapic_intr60), | |
131 | IDTVEC(ioapic_intr61), | |
132 | IDTVEC(ioapic_intr62), | |
133 | IDTVEC(ioapic_intr63), | |
134 | IDTVEC(ioapic_intr64), | |
135 | IDTVEC(ioapic_intr65), | |
136 | IDTVEC(ioapic_intr66), | |
137 | IDTVEC(ioapic_intr67), | |
138 | IDTVEC(ioapic_intr68), | |
139 | IDTVEC(ioapic_intr69), | |
140 | IDTVEC(ioapic_intr70), | |
141 | IDTVEC(ioapic_intr71), | |
142 | IDTVEC(ioapic_intr72), | |
143 | IDTVEC(ioapic_intr73), | |
144 | IDTVEC(ioapic_intr74), | |
145 | IDTVEC(ioapic_intr75), | |
146 | IDTVEC(ioapic_intr76), | |
147 | IDTVEC(ioapic_intr77), | |
148 | IDTVEC(ioapic_intr78), | |
149 | IDTVEC(ioapic_intr79), | |
150 | IDTVEC(ioapic_intr80), | |
151 | IDTVEC(ioapic_intr81), | |
152 | IDTVEC(ioapic_intr82), | |
153 | IDTVEC(ioapic_intr83), | |
154 | IDTVEC(ioapic_intr84), | |
155 | IDTVEC(ioapic_intr85), | |
156 | IDTVEC(ioapic_intr86), | |
157 | IDTVEC(ioapic_intr87), | |
158 | IDTVEC(ioapic_intr88), | |
159 | IDTVEC(ioapic_intr89), | |
160 | IDTVEC(ioapic_intr90), | |
161 | IDTVEC(ioapic_intr91), | |
162 | IDTVEC(ioapic_intr92), | |
163 | IDTVEC(ioapic_intr93), | |
164 | IDTVEC(ioapic_intr94), | |
165 | IDTVEC(ioapic_intr95), | |
166 | IDTVEC(ioapic_intr96), | |
167 | IDTVEC(ioapic_intr97), | |
168 | IDTVEC(ioapic_intr98), | |
169 | IDTVEC(ioapic_intr99), | |
170 | IDTVEC(ioapic_intr100), | |
171 | IDTVEC(ioapic_intr101), | |
172 | IDTVEC(ioapic_intr102), | |
173 | IDTVEC(ioapic_intr103), | |
174 | IDTVEC(ioapic_intr104), | |
175 | IDTVEC(ioapic_intr105), | |
176 | IDTVEC(ioapic_intr106), | |
177 | IDTVEC(ioapic_intr107), | |
178 | IDTVEC(ioapic_intr108), | |
179 | IDTVEC(ioapic_intr109), | |
180 | IDTVEC(ioapic_intr110), | |
181 | IDTVEC(ioapic_intr111), | |
182 | IDTVEC(ioapic_intr112), | |
183 | IDTVEC(ioapic_intr113), | |
184 | IDTVEC(ioapic_intr114), | |
185 | IDTVEC(ioapic_intr115), | |
186 | IDTVEC(ioapic_intr116), | |
187 | IDTVEC(ioapic_intr117), | |
188 | IDTVEC(ioapic_intr118), | |
189 | IDTVEC(ioapic_intr119), | |
190 | IDTVEC(ioapic_intr120), | |
191 | IDTVEC(ioapic_intr121), | |
192 | IDTVEC(ioapic_intr122), | |
193 | IDTVEC(ioapic_intr123), | |
194 | IDTVEC(ioapic_intr124), | |
195 | IDTVEC(ioapic_intr125), | |
196 | IDTVEC(ioapic_intr126), | |
197 | IDTVEC(ioapic_intr127), | |
198 | IDTVEC(ioapic_intr128), | |
199 | IDTVEC(ioapic_intr129), | |
200 | IDTVEC(ioapic_intr130), | |
201 | IDTVEC(ioapic_intr131), | |
202 | IDTVEC(ioapic_intr132), | |
203 | IDTVEC(ioapic_intr133), | |
204 | IDTVEC(ioapic_intr134), | |
205 | IDTVEC(ioapic_intr135), | |
206 | IDTVEC(ioapic_intr136), | |
207 | IDTVEC(ioapic_intr137), | |
208 | IDTVEC(ioapic_intr138), | |
209 | IDTVEC(ioapic_intr139), | |
210 | IDTVEC(ioapic_intr140), | |
211 | IDTVEC(ioapic_intr141), | |
212 | IDTVEC(ioapic_intr142), | |
213 | IDTVEC(ioapic_intr143), | |
214 | IDTVEC(ioapic_intr144), | |
215 | IDTVEC(ioapic_intr145), | |
216 | IDTVEC(ioapic_intr146), | |
217 | IDTVEC(ioapic_intr147), | |
218 | IDTVEC(ioapic_intr148), | |
219 | IDTVEC(ioapic_intr149), | |
220 | IDTVEC(ioapic_intr150), | |
221 | IDTVEC(ioapic_intr151), | |
222 | IDTVEC(ioapic_intr152), | |
223 | IDTVEC(ioapic_intr153), | |
224 | IDTVEC(ioapic_intr154), | |
225 | IDTVEC(ioapic_intr155), | |
226 | IDTVEC(ioapic_intr156), | |
227 | IDTVEC(ioapic_intr157), | |
228 | IDTVEC(ioapic_intr158), | |
229 | IDTVEC(ioapic_intr159), | |
230 | IDTVEC(ioapic_intr160), | |
231 | IDTVEC(ioapic_intr161), | |
232 | IDTVEC(ioapic_intr162), | |
233 | IDTVEC(ioapic_intr163), | |
234 | IDTVEC(ioapic_intr164), | |
235 | IDTVEC(ioapic_intr165), | |
236 | IDTVEC(ioapic_intr166), | |
237 | IDTVEC(ioapic_intr167), | |
238 | IDTVEC(ioapic_intr168), | |
239 | IDTVEC(ioapic_intr169), | |
240 | IDTVEC(ioapic_intr170), | |
241 | IDTVEC(ioapic_intr171), | |
242 | IDTVEC(ioapic_intr172), | |
243 | IDTVEC(ioapic_intr173), | |
244 | IDTVEC(ioapic_intr174), | |
245 | IDTVEC(ioapic_intr175), | |
246 | IDTVEC(ioapic_intr176), | |
247 | IDTVEC(ioapic_intr177), | |
248 | IDTVEC(ioapic_intr178), | |
249 | IDTVEC(ioapic_intr179), | |
250 | IDTVEC(ioapic_intr180), | |
251 | IDTVEC(ioapic_intr181), | |
252 | IDTVEC(ioapic_intr182), | |
253 | IDTVEC(ioapic_intr183), | |
254 | IDTVEC(ioapic_intr184), | |
255 | IDTVEC(ioapic_intr185), | |
256 | IDTVEC(ioapic_intr186), | |
257 | IDTVEC(ioapic_intr187), | |
258 | IDTVEC(ioapic_intr188), | |
259 | IDTVEC(ioapic_intr189), | |
260 | IDTVEC(ioapic_intr190), | |
261 | IDTVEC(ioapic_intr191); | |
262 | ||
263 | static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = { | |
264 | &IDTVEC(ioapic_intr0), | |
265 | &IDTVEC(ioapic_intr1), | |
266 | &IDTVEC(ioapic_intr2), | |
267 | &IDTVEC(ioapic_intr3), | |
268 | &IDTVEC(ioapic_intr4), | |
269 | &IDTVEC(ioapic_intr5), | |
270 | &IDTVEC(ioapic_intr6), | |
271 | &IDTVEC(ioapic_intr7), | |
272 | &IDTVEC(ioapic_intr8), | |
273 | &IDTVEC(ioapic_intr9), | |
274 | &IDTVEC(ioapic_intr10), | |
275 | &IDTVEC(ioapic_intr11), | |
276 | &IDTVEC(ioapic_intr12), | |
277 | &IDTVEC(ioapic_intr13), | |
278 | &IDTVEC(ioapic_intr14), | |
279 | &IDTVEC(ioapic_intr15), | |
280 | &IDTVEC(ioapic_intr16), | |
281 | &IDTVEC(ioapic_intr17), | |
282 | &IDTVEC(ioapic_intr18), | |
283 | &IDTVEC(ioapic_intr19), | |
284 | &IDTVEC(ioapic_intr20), | |
285 | &IDTVEC(ioapic_intr21), | |
286 | &IDTVEC(ioapic_intr22), | |
287 | &IDTVEC(ioapic_intr23), | |
288 | &IDTVEC(ioapic_intr24), | |
289 | &IDTVEC(ioapic_intr25), | |
290 | &IDTVEC(ioapic_intr26), | |
291 | &IDTVEC(ioapic_intr27), | |
292 | &IDTVEC(ioapic_intr28), | |
293 | &IDTVEC(ioapic_intr29), | |
294 | &IDTVEC(ioapic_intr30), | |
295 | &IDTVEC(ioapic_intr31), | |
296 | &IDTVEC(ioapic_intr32), | |
297 | &IDTVEC(ioapic_intr33), | |
298 | &IDTVEC(ioapic_intr34), | |
299 | &IDTVEC(ioapic_intr35), | |
300 | &IDTVEC(ioapic_intr36), | |
301 | &IDTVEC(ioapic_intr37), | |
302 | &IDTVEC(ioapic_intr38), | |
303 | &IDTVEC(ioapic_intr39), | |
304 | &IDTVEC(ioapic_intr40), | |
305 | &IDTVEC(ioapic_intr41), | |
306 | &IDTVEC(ioapic_intr42), | |
307 | &IDTVEC(ioapic_intr43), | |
308 | &IDTVEC(ioapic_intr44), | |
309 | &IDTVEC(ioapic_intr45), | |
310 | &IDTVEC(ioapic_intr46), | |
311 | &IDTVEC(ioapic_intr47), | |
312 | &IDTVEC(ioapic_intr48), | |
313 | &IDTVEC(ioapic_intr49), | |
314 | &IDTVEC(ioapic_intr50), | |
315 | &IDTVEC(ioapic_intr51), | |
316 | &IDTVEC(ioapic_intr52), | |
317 | &IDTVEC(ioapic_intr53), | |
318 | &IDTVEC(ioapic_intr54), | |
319 | &IDTVEC(ioapic_intr55), | |
320 | &IDTVEC(ioapic_intr56), | |
321 | &IDTVEC(ioapic_intr57), | |
322 | &IDTVEC(ioapic_intr58), | |
323 | &IDTVEC(ioapic_intr59), | |
324 | &IDTVEC(ioapic_intr60), | |
325 | &IDTVEC(ioapic_intr61), | |
326 | &IDTVEC(ioapic_intr62), | |
327 | &IDTVEC(ioapic_intr63), | |
328 | &IDTVEC(ioapic_intr64), | |
329 | &IDTVEC(ioapic_intr65), | |
330 | &IDTVEC(ioapic_intr66), | |
331 | &IDTVEC(ioapic_intr67), | |
332 | &IDTVEC(ioapic_intr68), | |
333 | &IDTVEC(ioapic_intr69), | |
334 | &IDTVEC(ioapic_intr70), | |
335 | &IDTVEC(ioapic_intr71), | |
336 | &IDTVEC(ioapic_intr72), | |
337 | &IDTVEC(ioapic_intr73), | |
338 | &IDTVEC(ioapic_intr74), | |
339 | &IDTVEC(ioapic_intr75), | |
340 | &IDTVEC(ioapic_intr76), | |
341 | &IDTVEC(ioapic_intr77), | |
342 | &IDTVEC(ioapic_intr78), | |
343 | &IDTVEC(ioapic_intr79), | |
344 | &IDTVEC(ioapic_intr80), | |
345 | &IDTVEC(ioapic_intr81), | |
346 | &IDTVEC(ioapic_intr82), | |
347 | &IDTVEC(ioapic_intr83), | |
348 | &IDTVEC(ioapic_intr84), | |
349 | &IDTVEC(ioapic_intr85), | |
350 | &IDTVEC(ioapic_intr86), | |
351 | &IDTVEC(ioapic_intr87), | |
352 | &IDTVEC(ioapic_intr88), | |
353 | &IDTVEC(ioapic_intr89), | |
354 | &IDTVEC(ioapic_intr90), | |
355 | &IDTVEC(ioapic_intr91), | |
356 | &IDTVEC(ioapic_intr92), | |
357 | &IDTVEC(ioapic_intr93), | |
358 | &IDTVEC(ioapic_intr94), | |
359 | &IDTVEC(ioapic_intr95), | |
360 | &IDTVEC(ioapic_intr96), | |
361 | &IDTVEC(ioapic_intr97), | |
362 | &IDTVEC(ioapic_intr98), | |
363 | &IDTVEC(ioapic_intr99), | |
364 | &IDTVEC(ioapic_intr100), | |
365 | &IDTVEC(ioapic_intr101), | |
366 | &IDTVEC(ioapic_intr102), | |
367 | &IDTVEC(ioapic_intr103), | |
368 | &IDTVEC(ioapic_intr104), | |
369 | &IDTVEC(ioapic_intr105), | |
370 | &IDTVEC(ioapic_intr106), | |
371 | &IDTVEC(ioapic_intr107), | |
372 | &IDTVEC(ioapic_intr108), | |
373 | &IDTVEC(ioapic_intr109), | |
374 | &IDTVEC(ioapic_intr110), | |
375 | &IDTVEC(ioapic_intr111), | |
376 | &IDTVEC(ioapic_intr112), | |
377 | &IDTVEC(ioapic_intr113), | |
378 | &IDTVEC(ioapic_intr114), | |
379 | &IDTVEC(ioapic_intr115), | |
380 | &IDTVEC(ioapic_intr116), | |
381 | &IDTVEC(ioapic_intr117), | |
382 | &IDTVEC(ioapic_intr118), | |
383 | &IDTVEC(ioapic_intr119), | |
384 | &IDTVEC(ioapic_intr120), | |
385 | &IDTVEC(ioapic_intr121), | |
386 | &IDTVEC(ioapic_intr122), | |
387 | &IDTVEC(ioapic_intr123), | |
388 | &IDTVEC(ioapic_intr124), | |
389 | &IDTVEC(ioapic_intr125), | |
390 | &IDTVEC(ioapic_intr126), | |
391 | &IDTVEC(ioapic_intr127), | |
392 | &IDTVEC(ioapic_intr128), | |
393 | &IDTVEC(ioapic_intr129), | |
394 | &IDTVEC(ioapic_intr130), | |
395 | &IDTVEC(ioapic_intr131), | |
396 | &IDTVEC(ioapic_intr132), | |
397 | &IDTVEC(ioapic_intr133), | |
398 | &IDTVEC(ioapic_intr134), | |
399 | &IDTVEC(ioapic_intr135), | |
400 | &IDTVEC(ioapic_intr136), | |
401 | &IDTVEC(ioapic_intr137), | |
402 | &IDTVEC(ioapic_intr138), | |
403 | &IDTVEC(ioapic_intr139), | |
404 | &IDTVEC(ioapic_intr140), | |
405 | &IDTVEC(ioapic_intr141), | |
406 | &IDTVEC(ioapic_intr142), | |
407 | &IDTVEC(ioapic_intr143), | |
408 | &IDTVEC(ioapic_intr144), | |
409 | &IDTVEC(ioapic_intr145), | |
410 | &IDTVEC(ioapic_intr146), | |
411 | &IDTVEC(ioapic_intr147), | |
412 | &IDTVEC(ioapic_intr148), | |
413 | &IDTVEC(ioapic_intr149), | |
414 | &IDTVEC(ioapic_intr150), | |
415 | &IDTVEC(ioapic_intr151), | |
416 | &IDTVEC(ioapic_intr152), | |
417 | &IDTVEC(ioapic_intr153), | |
418 | &IDTVEC(ioapic_intr154), | |
419 | &IDTVEC(ioapic_intr155), | |
420 | &IDTVEC(ioapic_intr156), | |
421 | &IDTVEC(ioapic_intr157), | |
422 | &IDTVEC(ioapic_intr158), | |
423 | &IDTVEC(ioapic_intr159), | |
424 | &IDTVEC(ioapic_intr160), | |
425 | &IDTVEC(ioapic_intr161), | |
426 | &IDTVEC(ioapic_intr162), | |
427 | &IDTVEC(ioapic_intr163), | |
428 | &IDTVEC(ioapic_intr164), | |
429 | &IDTVEC(ioapic_intr165), | |
430 | &IDTVEC(ioapic_intr166), | |
431 | &IDTVEC(ioapic_intr167), | |
432 | &IDTVEC(ioapic_intr168), | |
433 | &IDTVEC(ioapic_intr169), | |
434 | &IDTVEC(ioapic_intr170), | |
435 | &IDTVEC(ioapic_intr171), | |
436 | &IDTVEC(ioapic_intr172), | |
437 | &IDTVEC(ioapic_intr173), | |
438 | &IDTVEC(ioapic_intr174), | |
439 | &IDTVEC(ioapic_intr175), | |
440 | &IDTVEC(ioapic_intr176), | |
441 | &IDTVEC(ioapic_intr177), | |
442 | &IDTVEC(ioapic_intr178), | |
443 | &IDTVEC(ioapic_intr179), | |
444 | &IDTVEC(ioapic_intr180), | |
445 | &IDTVEC(ioapic_intr181), | |
446 | &IDTVEC(ioapic_intr182), | |
447 | &IDTVEC(ioapic_intr183), | |
448 | &IDTVEC(ioapic_intr184), | |
449 | &IDTVEC(ioapic_intr185), | |
450 | &IDTVEC(ioapic_intr186), | |
451 | &IDTVEC(ioapic_intr187), | |
452 | &IDTVEC(ioapic_intr188), | |
453 | &IDTVEC(ioapic_intr189), | |
454 | &IDTVEC(ioapic_intr190), | |
455 | &IDTVEC(ioapic_intr191) | |
c571da4a | 456 | }; |
10ff1029 | 457 | |
474ba684 SZ |
458 | #define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET) |
459 | ||
a3dd9120 SZ |
460 | static struct ioapic_irqmap { |
461 | int im_type; /* IOAPIC_IMT_ */ | |
462 | enum intr_trigger im_trig; | |
f6915355 | 463 | enum intr_polarity im_pola; |
a3dd9120 | 464 | int im_gsi; |
be98308a | 465 | int im_msi_base; |
d1ae7328 | 466 | uint32_t im_flags; /* IOAPIC_IMF_ */ |
2e62e7a5 | 467 | } ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS]; |
a3dd9120 | 468 | |
be98308a SZ |
469 | static struct lwkt_token ioapic_irqmap_tok = |
470 | LWKT_TOKEN_INITIALIZER(ioapic_irqmap_token); | |
471 | ||
a3dd9120 SZ |
472 | #define IOAPIC_IMT_UNUSED 0 |
473 | #define IOAPIC_IMT_RESERVED 1 | |
2a32da90 | 474 | #define IOAPIC_IMT_LEGACY 2 |
474ba684 | 475 | #define IOAPIC_IMT_SYSCALL 3 |
be98308a SZ |
476 | #define IOAPIC_IMT_SHADOW 4 |
477 | #define IOAPIC_IMT_MSI 5 | |
6bf6f751 | 478 | #define IOAPIC_IMT_MSIX 6 |
a3dd9120 | 479 | |
0f3e19b1 | 480 | #define IOAPIC_IMT_ISHWI(map) ((map)->im_type != IOAPIC_IMT_RESERVED && \ |
be98308a SZ |
481 | (map)->im_type != IOAPIC_IMT_SYSCALL && \ |
482 | (map)->im_type != IOAPIC_IMT_SHADOW) | |
0f3e19b1 | 483 | |
d1ae7328 SZ |
484 | #define IOAPIC_IMF_CONF 0x1 |
485 | ||
9e0e3f85 SZ |
486 | extern void IOAPIC_INTREN(int); |
487 | extern void IOAPIC_INTRDIS(int); | |
488 | ||
1d903de5 SZ |
489 | extern int imcr_present; |
490 | ||
35b2edcb SZ |
491 | static void ioapic_abi_intr_enable(int); |
492 | static void ioapic_abi_intr_disable(int); | |
f416026e SZ |
493 | static void ioapic_abi_intr_setup(int, int); |
494 | static void ioapic_abi_intr_teardown(int); | |
bec969af SZ |
495 | |
496 | static void ioapic_abi_legacy_intr_config(int, | |
780a6eec | 497 | enum intr_trigger, enum intr_polarity); |
bec969af | 498 | static int ioapic_abi_legacy_intr_cpuid(int); |
86d692fe SZ |
499 | static int ioapic_abi_legacy_intr_find(int, |
500 | enum intr_trigger, enum intr_polarity); | |
501 | static int ioapic_abi_legacy_intr_find_bygsi(int, | |
502 | enum intr_trigger, enum intr_polarity); | |
35b2edcb | 503 | |
be98308a SZ |
504 | static int ioapic_abi_msi_alloc(int [], int, int); |
505 | static void ioapic_abi_msi_release(const int [], int, int); | |
506 | static void ioapic_abi_msi_map(int, uint64_t *, uint32_t *, int); | |
6bf6f751 SZ |
507 | static int ioapic_abi_msix_alloc(int *, int); |
508 | static void ioapic_abi_msix_release(int, int); | |
509 | ||
510 | static int ioapic_abi_msi_alloc_intern(int, const char *, | |
511 | int [], int, int); | |
512 | static void ioapic_abi_msi_release_intern(int, const char *, | |
513 | const int [], int, int); | |
be98308a | 514 | |
780a6eec SZ |
515 | static void ioapic_abi_finalize(void); |
516 | static void ioapic_abi_cleanup(void); | |
517 | static void ioapic_abi_setdefault(void); | |
518 | static void ioapic_abi_stabilize(void); | |
519 | static void ioapic_abi_initmap(void); | |
0f3e19b1 | 520 | static void ioapic_abi_rman_setup(struct rman *); |
9e0e3f85 | 521 | |
9dba15ae | 522 | static int ioapic_abi_gsi_cpuid(int, int); |
0a83ab6f | 523 | static int ioapic_find_unused_irqmap(int); |
9dba15ae | 524 | |
9e0e3f85 SZ |
525 | struct machintr_abi MachIntrABI_IOAPIC = { |
526 | MACHINTR_IOAPIC, | |
35b2edcb SZ |
527 | |
528 | .intr_disable = ioapic_abi_intr_disable, | |
529 | .intr_enable = ioapic_abi_intr_enable, | |
f416026e SZ |
530 | .intr_setup = ioapic_abi_intr_setup, |
531 | .intr_teardown = ioapic_abi_intr_teardown, | |
bec969af SZ |
532 | |
533 | .legacy_intr_config = ioapic_abi_legacy_intr_config, | |
534 | .legacy_intr_cpuid = ioapic_abi_legacy_intr_cpuid, | |
86d692fe SZ |
535 | .legacy_intr_find = ioapic_abi_legacy_intr_find, |
536 | .legacy_intr_find_bygsi = ioapic_abi_legacy_intr_find_bygsi, | |
35b2edcb | 537 | |
be98308a SZ |
538 | .msi_alloc = ioapic_abi_msi_alloc, |
539 | .msi_release = ioapic_abi_msi_release, | |
540 | .msi_map = ioapic_abi_msi_map, | |
6bf6f751 SZ |
541 | .msix_alloc = ioapic_abi_msix_alloc, |
542 | .msix_release = ioapic_abi_msix_release, | |
be98308a | 543 | |
780a6eec SZ |
544 | .finalize = ioapic_abi_finalize, |
545 | .cleanup = ioapic_abi_cleanup, | |
546 | .setdefault = ioapic_abi_setdefault, | |
547 | .stabilize = ioapic_abi_stabilize, | |
0f3e19b1 SZ |
548 | .initmap = ioapic_abi_initmap, |
549 | .rman_setup = ioapic_abi_rman_setup | |
37e7efec MD |
550 | }; |
551 | ||
6b809ec7 | 552 | static int ioapic_abi_extint_irq = -1; |
2a32da90 | 553 | static int ioapic_abi_legacy_irq_max; |
cae71b2c | 554 | static int ioapic_abi_gsi_balance; |
be98308a | 555 | static int ioapic_abi_msi_start; /* NOTE: for testing only */ |
6b809ec7 | 556 | |
7a54dec9 | 557 | struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS]; |
fa6eddaf SZ |
558 | |
559 | static void | |
35b2edcb | 560 | ioapic_abi_intr_enable(int irq) |
fa6eddaf | 561 | { |
5157c933 SZ |
562 | const struct ioapic_irqmap *map; |
563 | ||
564 | KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS, | |
ed20d0e3 | 565 | ("ioapic enable, invalid irq %d", irq)); |
5157c933 SZ |
566 | |
567 | map = &ioapic_irqmaps[mycpuid][irq]; | |
568 | KASSERT(IOAPIC_IMT_ISHWI(map), | |
ed20d0e3 | 569 | ("ioapic enable, not hwi irq %d, type %d, cpu%d", |
5157c933 | 570 | irq, map->im_type, mycpuid)); |
2a32da90 | 571 | if (map->im_type != IOAPIC_IMT_LEGACY) |
fa6eddaf | 572 | return; |
5157c933 | 573 | |
fa6eddaf SZ |
574 | IOAPIC_INTREN(irq); |
575 | } | |
576 | ||
577 | static void | |
35b2edcb | 578 | ioapic_abi_intr_disable(int irq) |
fa6eddaf | 579 | { |
5157c933 SZ |
580 | const struct ioapic_irqmap *map; |
581 | ||
582 | KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS, | |
ed20d0e3 | 583 | ("ioapic disable, invalid irq %d", irq)); |
5157c933 SZ |
584 | |
585 | map = &ioapic_irqmaps[mycpuid][irq]; | |
586 | KASSERT(IOAPIC_IMT_ISHWI(map), | |
ed20d0e3 | 587 | ("ioapic disable, not hwi irq %d, type %d, cpu%d", |
5157c933 | 588 | irq, map->im_type, mycpuid)); |
2a32da90 | 589 | if (map->im_type != IOAPIC_IMT_LEGACY) |
fa6eddaf | 590 | return; |
5157c933 | 591 | |
fa6eddaf SZ |
592 | IOAPIC_INTRDIS(irq); |
593 | } | |
594 | ||
37e7efec | 595 | static void |
780a6eec | 596 | ioapic_abi_finalize(void) |
37e7efec | 597 | { |
e0918665 | 598 | KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC); |
f45bfca0 | 599 | KKASSERT(ioapic_enable); |
10db3cc6 | 600 | |
54e1df6b SZ |
601 | /* |
602 | * If an IMCR is present, program bit 0 to disconnect the 8259 | |
e0918665 | 603 | * from the BSP. |
54e1df6b | 604 | */ |
9d758cc4 | 605 | if (imcr_present) { |
54e1df6b SZ |
606 | outb(0x22, 0x70); /* select IMCR */ |
607 | outb(0x23, 0x01); /* disconnect 8259 */ | |
608 | } | |
37e7efec MD |
609 | } |
610 | ||
0b692e79 MD |
611 | /* |
612 | * This routine is called after physical interrupts are enabled but before | |
613 | * the critical section is released. We need to clean out any interrupts | |
614 | * that had already been posted to the cpu. | |
615 | */ | |
616 | static void | |
780a6eec | 617 | ioapic_abi_cleanup(void) |
0b692e79 | 618 | { |
c263294b | 619 | bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); |
0b692e79 MD |
620 | } |
621 | ||
7bf5fa56 SZ |
622 | /* Must never be called */ |
623 | static void | |
780a6eec | 624 | ioapic_abi_stabilize(void) |
7bf5fa56 | 625 | { |
ed20d0e3 | 626 | panic("ioapic_stabilize() is called"); |
7bf5fa56 SZ |
627 | } |
628 | ||
f416026e SZ |
629 | static void |
630 | ioapic_abi_intr_setup(int intr, int flags) | |
10ff1029 | 631 | { |
ba66d506 | 632 | const struct ioapic_irqmap *map; |
f416026e | 633 | int vector, select; |
54e1df6b SZ |
634 | uint32_t value; |
635 | u_long ef; | |
10ff1029 | 636 | |
ba66d506 | 637 | KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, |
ed20d0e3 | 638 | ("ioapic setup, invalid irq %d", intr)); |
ba66d506 SZ |
639 | |
640 | map = &ioapic_irqmaps[mycpuid][intr]; | |
641 | KASSERT(IOAPIC_IMT_ISHWI(map), | |
642 | ("ioapic setup, not hwi irq %d, type %d, cpu%d", | |
643 | intr, map->im_type, mycpuid)); | |
2a32da90 | 644 | if (map->im_type != IOAPIC_IMT_LEGACY) |
ba66d506 | 645 | return; |
ba66d506 SZ |
646 | |
647 | KASSERT(ioapic_irqs[intr].io_addr != NULL, | |
ed20d0e3 | 648 | ("ioapic setup, no GSI information, irq %d", intr)); |
f416026e SZ |
649 | |
650 | ef = read_eflags(); | |
651 | cpu_disable_intr(); | |
652 | ||
653 | vector = IDT_OFFSET + intr; | |
f416026e SZ |
654 | |
655 | /* | |
656 | * Now reprogram the vector in the IO APIC. In order to avoid | |
657 | * losing an EOI for a level interrupt, which is vector based, | |
658 | * make sure that the IO APIC is programmed for edge-triggering | |
659 | * first, then reprogrammed with the new vector. This should | |
660 | * clear the IRR bit. | |
661 | */ | |
662 | imen_lock(); | |
663 | ||
664 | select = ioapic_irqs[intr].io_idx; | |
665 | value = ioapic_read(ioapic_irqs[intr].io_addr, select); | |
666 | value |= IOART_INTMSET; | |
667 | ||
668 | ioapic_write(ioapic_irqs[intr].io_addr, select, | |
669 | (value & ~APIC_TRIGMOD_MASK)); | |
670 | ioapic_write(ioapic_irqs[intr].io_addr, select, | |
671 | (value & ~IOART_INTVEC) | vector); | |
672 | ||
673 | imen_unlock(); | |
674 | ||
eaeca813 | 675 | IOAPIC_INTREN(intr); |
f416026e SZ |
676 | |
677 | write_eflags(ef); | |
678 | } | |
679 | ||
680 | static void | |
681 | ioapic_abi_intr_teardown(int intr) | |
682 | { | |
ba66d506 | 683 | const struct ioapic_irqmap *map; |
f416026e SZ |
684 | int vector, select; |
685 | uint32_t value; | |
686 | u_long ef; | |
10ff1029 | 687 | |
ba66d506 | 688 | KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, |
ed20d0e3 | 689 | ("ioapic teardown, invalid irq %d", intr)); |
ba66d506 SZ |
690 | |
691 | map = &ioapic_irqmaps[mycpuid][intr]; | |
692 | KASSERT(IOAPIC_IMT_ISHWI(map), | |
693 | ("ioapic teardown, not hwi irq %d, type %d, cpu%d", | |
694 | intr, map->im_type, mycpuid)); | |
2a32da90 | 695 | if (map->im_type != IOAPIC_IMT_LEGACY) |
ba66d506 | 696 | return; |
ba66d506 SZ |
697 | |
698 | KASSERT(ioapic_irqs[intr].io_addr != NULL, | |
ed20d0e3 | 699 | ("ioapic teardown, no GSI information, irq %d", intr)); |
7a54dec9 | 700 | |
54e1df6b SZ |
701 | ef = read_eflags(); |
702 | cpu_disable_intr(); | |
10ff1029 | 703 | |
f416026e SZ |
704 | /* |
705 | * Teardown an interrupt vector. The vector should already be | |
706 | * installed in the cpu's IDT, but make sure. | |
707 | */ | |
eaeca813 | 708 | IOAPIC_INTRDIS(intr); |
35408d22 | 709 | |
f416026e | 710 | vector = IDT_OFFSET + intr; |
f416026e SZ |
711 | |
712 | /* | |
713 | * In order to avoid losing an EOI for a level interrupt, which | |
714 | * is vector based, make sure that the IO APIC is programmed for | |
715 | * edge-triggering first, then reprogrammed with the new vector. | |
716 | * This should clear the IRR bit. | |
717 | */ | |
718 | imen_lock(); | |
719 | ||
720 | select = ioapic_irqs[intr].io_idx; | |
721 | value = ioapic_read(ioapic_irqs[intr].io_addr, select); | |
722 | ||
723 | ioapic_write(ioapic_irqs[intr].io_addr, select, | |
724 | (value & ~APIC_TRIGMOD_MASK)); | |
725 | ioapic_write(ioapic_irqs[intr].io_addr, select, | |
726 | (value & ~IOART_INTVEC) | vector); | |
727 | ||
728 | imen_unlock(); | |
10ff1029 | 729 | |
54e1df6b | 730 | write_eflags(ef); |
54e1df6b | 731 | } |
06f5be02 | 732 | |
10db3cc6 | 733 | static void |
780a6eec | 734 | ioapic_abi_setdefault(void) |
10db3cc6 SZ |
735 | { |
736 | int intr; | |
737 | ||
9e0e3f85 | 738 | for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) { |
474ba684 | 739 | if (intr == IOAPIC_HWI_SYSCALL) |
10db3cc6 | 740 | continue; |
9e0e3f85 | 741 | setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYS386IGT, |
10db3cc6 SZ |
742 | SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); |
743 | } | |
744 | } | |
745 | ||
a3dd9120 | 746 | static void |
780a6eec | 747 | ioapic_abi_initmap(void) |
a3dd9120 | 748 | { |
2e62e7a5 | 749 | int cpu; |
a3dd9120 | 750 | |
cae71b2c SZ |
751 | kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance); |
752 | ||
be98308a SZ |
753 | kgetenv_int("hw.ioapic.msi_start", &ioapic_abi_msi_start); |
754 | ioapic_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */ | |
755 | ||
2e62e7a5 SZ |
756 | /* |
757 | * NOTE: ncpus is not ready yet | |
758 | */ | |
759 | for (cpu = 0; cpu < MAXCPU; ++cpu) { | |
760 | int i; | |
761 | ||
be98308a | 762 | for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) { |
2e62e7a5 | 763 | ioapic_irqmaps[cpu][i].im_gsi = -1; |
be98308a SZ |
764 | ioapic_irqmaps[cpu][i].im_msi_base = -1; |
765 | } | |
2e62e7a5 SZ |
766 | ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type = |
767 | IOAPIC_IMT_SYSCALL; | |
768 | } | |
a3dd9120 SZ |
769 | } |
770 | ||
0a83ab6f SZ |
771 | static int |
772 | ioapic_find_unused_irqmap(int gsi) | |
773 | { | |
774 | int cpuid, i; | |
775 | ||
776 | cpuid = ioapic_abi_gsi_cpuid(-1, gsi); | |
777 | ||
778 | for (i = ISA_IRQ_CNT; i < IOAPIC_HWI_VECTORS; ++i) { | |
779 | if (i == acpi_sci_irqno()) | |
780 | continue; | |
781 | if (ioapic_irqmaps[cpuid][i].im_type == IOAPIC_IMT_UNUSED) | |
782 | return i; | |
783 | } | |
784 | return -1; | |
785 | } | |
786 | ||
929c940f | 787 | void |
027bbbfe | 788 | ioapic_set_legacy_irqmap(int irq, int gsi, enum intr_trigger trig, |
929c940f SZ |
789 | enum intr_polarity pola) |
790 | { | |
7a54dec9 | 791 | struct ioapic_irqinfo *info; |
929c940f SZ |
792 | struct ioapic_irqmap *map; |
793 | void *ioaddr; | |
9dba15ae | 794 | int pin, cpuid; |
929c940f SZ |
795 | |
796 | KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL); | |
797 | KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW); | |
929c940f | 798 | |
0a83ab6f SZ |
799 | KKASSERT(irq >= 0); |
800 | if (irq >= IOAPIC_HWI_VECTORS) { | |
801 | /* | |
802 | * Some BIOSes seem to assume that all 256 IDT vectors | |
803 | * could be used, while we limit the available IDT | |
804 | * vectors to 192; find an unused IRQ for this GSI. | |
805 | */ | |
806 | irq = ioapic_find_unused_irqmap(gsi); | |
807 | if (irq < 0) { | |
644285c0 SZ |
808 | kprintf("failed to find unused irq for gsi %d, " |
809 | "overflow\n", gsi); | |
0a83ab6f SZ |
810 | return; |
811 | } | |
812 | } | |
813 | KKASSERT(irq < IOAPIC_HWI_VECTORS); | |
814 | ||
2e62e7a5 | 815 | cpuid = ioapic_abi_gsi_cpuid(irq, gsi); |
2e62e7a5 | 816 | map = &ioapic_irqmaps[cpuid][irq]; |
929c940f | 817 | |
644285c0 SZ |
818 | if (map->im_type != IOAPIC_IMT_UNUSED) { |
819 | /* | |
820 | * There are so many IOAPICs, that 1:1 mapping | |
821 | * of GSI and IRQ hits SYSCALL entry. | |
822 | */ | |
823 | irq = ioapic_find_unused_irqmap(gsi); | |
824 | if (irq < 0) { | |
825 | kprintf("failed to find unused irq for gsi %d, " | |
826 | "conflict\n", gsi); | |
827 | return; | |
828 | } | |
829 | KKASSERT(irq < IOAPIC_HWI_VECTORS); | |
830 | ||
831 | cpuid = ioapic_abi_gsi_cpuid(irq, gsi); | |
832 | map = &ioapic_irqmaps[cpuid][irq]; | |
833 | } | |
834 | ||
835 | if (irq > ioapic_abi_legacy_irq_max) | |
836 | ioapic_abi_legacy_irq_max = irq; | |
837 | ||
929c940f | 838 | KKASSERT(map->im_type == IOAPIC_IMT_UNUSED); |
2a32da90 | 839 | map->im_type = IOAPIC_IMT_LEGACY; |
929c940f SZ |
840 | |
841 | map->im_gsi = gsi; | |
842 | map->im_trig = trig; | |
843 | map->im_pola = pola; | |
844 | ||
845 | if (bootverbose) { | |
4ecd5d4d SZ |
846 | kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n", |
847 | irq, map->im_gsi, | |
848 | intr_str_trigger(map->im_trig), | |
849 | intr_str_polarity(map->im_pola)); | |
929c940f SZ |
850 | } |
851 | ||
d1ae7328 SZ |
852 | pin = ioapic_gsi_pin(map->im_gsi); |
853 | ioaddr = ioapic_gsi_ioaddr(map->im_gsi); | |
929c940f | 854 | |
7a54dec9 | 855 | info = &ioapic_irqs[irq]; |
929c940f | 856 | |
7bceaa10 SZ |
857 | imen_lock(); |
858 | ||
7a54dec9 SZ |
859 | info->io_addr = ioaddr; |
860 | info->io_idx = IOAPIC_REDTBL + (2 * pin); | |
861 | info->io_flags = IOAPIC_IRQI_FLAG_MASKED; | |
d1ae7328 | 862 | if (map->im_trig == INTR_TRIGGER_LEVEL) |
7a54dec9 | 863 | info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL; |
d1ae7328 SZ |
864 | |
865 | ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq, | |
9dba15ae | 866 | map->im_trig, map->im_pola, cpuid); |
7bceaa10 SZ |
867 | |
868 | imen_unlock(); | |
d1ae7328 SZ |
869 | } |
870 | ||
4a913811 | 871 | void |
027bbbfe | 872 | ioapic_fixup_legacy_irqmaps(void) |
4a913811 | 873 | { |
2e62e7a5 SZ |
874 | int cpu; |
875 | ||
2a32da90 SZ |
876 | ioapic_abi_legacy_irq_max += 1; |
877 | if (bootverbose) { | |
878 | kprintf("IOAPIC: legacy irq max %d\n", | |
879 | ioapic_abi_legacy_irq_max); | |
880 | } | |
1973dfbc | 881 | |
2e62e7a5 SZ |
882 | for (cpu = 0; cpu < ncpus; ++cpu) { |
883 | int i; | |
4a913811 | 884 | |
2a32da90 | 885 | for (i = 0; i < ioapic_abi_legacy_irq_max; ++i) { |
2e62e7a5 | 886 | struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i]; |
4a913811 | 887 | |
2e62e7a5 SZ |
888 | if (map->im_type == IOAPIC_IMT_UNUSED) { |
889 | map->im_type = IOAPIC_IMT_RESERVED; | |
890 | if (bootverbose) { | |
891 | kprintf("IOAPIC: " | |
892 | "cpu%d irq %d reserved\n", cpu, i); | |
893 | } | |
894 | } | |
4a913811 SZ |
895 | } |
896 | } | |
897 | } | |
898 | ||
86d692fe SZ |
899 | static int |
900 | ioapic_abi_legacy_intr_find_bygsi(int gsi, enum intr_trigger trig, | |
027bbbfe | 901 | enum intr_polarity pola) |
e90e7ac4 | 902 | { |
2e62e7a5 | 903 | int cpu; |
e90e7ac4 | 904 | |
86d692fe SZ |
905 | #ifdef INVARIANTS |
906 | if (trig == INTR_TRIGGER_CONFORM) { | |
907 | KKASSERT(pola == INTR_POLARITY_CONFORM); | |
908 | } else { | |
909 | KKASSERT(trig == INTR_TRIGGER_EDGE || | |
910 | trig == INTR_TRIGGER_LEVEL); | |
911 | KKASSERT(pola == INTR_POLARITY_HIGH || | |
912 | pola == INTR_POLARITY_LOW); | |
913 | } | |
914 | #endif | |
e90e7ac4 | 915 | |
2e62e7a5 SZ |
916 | for (cpu = 0; cpu < ncpus; ++cpu) { |
917 | int irq; | |
e90e7ac4 | 918 | |
2a32da90 | 919 | for (irq = 0; irq < ioapic_abi_legacy_irq_max; ++irq) { |
2e62e7a5 SZ |
920 | const struct ioapic_irqmap *map = |
921 | &ioapic_irqmaps[cpu][irq]; | |
e90e7ac4 | 922 | |
2e62e7a5 | 923 | if (map->im_gsi == gsi) { |
2a32da90 | 924 | KKASSERT(map->im_type == IOAPIC_IMT_LEGACY); |
2e62e7a5 | 925 | |
86d692fe SZ |
926 | if ((map->im_flags & IOAPIC_IMF_CONF) && |
927 | trig != INTR_TRIGGER_CONFORM && | |
928 | pola != INTR_POLARITY_CONFORM) { | |
2e62e7a5 SZ |
929 | if (map->im_trig != trig || |
930 | map->im_pola != pola) | |
931 | return -1; | |
932 | } | |
933 | return irq; | |
e90e7ac4 | 934 | } |
e90e7ac4 SZ |
935 | } |
936 | } | |
937 | return -1; | |
938 | } | |
939 | ||
86d692fe SZ |
940 | static int |
941 | ioapic_abi_legacy_intr_find(int irq, enum intr_trigger trig, | |
027bbbfe | 942 | enum intr_polarity pola) |
e90e7ac4 | 943 | { |
2e62e7a5 | 944 | int cpu; |
e90e7ac4 | 945 | |
86d692fe SZ |
946 | #ifdef INVARIANTS |
947 | if (trig == INTR_TRIGGER_CONFORM) { | |
948 | KKASSERT(pola == INTR_POLARITY_CONFORM); | |
949 | } else { | |
950 | KKASSERT(trig == INTR_TRIGGER_EDGE || | |
951 | trig == INTR_TRIGGER_LEVEL); | |
952 | KKASSERT(pola == INTR_POLARITY_HIGH || | |
953 | pola == INTR_POLARITY_LOW); | |
954 | } | |
955 | #endif | |
e90e7ac4 | 956 | |
2a32da90 | 957 | if (irq < 0 || irq >= ioapic_abi_legacy_irq_max) |
e90e7ac4 | 958 | return -1; |
e90e7ac4 | 959 | |
2e62e7a5 SZ |
960 | for (cpu = 0; cpu < ncpus; ++cpu) { |
961 | const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq]; | |
e90e7ac4 | 962 | |
2a32da90 | 963 | if (map->im_type == IOAPIC_IMT_LEGACY) { |
86d692fe SZ |
964 | if ((map->im_flags & IOAPIC_IMF_CONF) && |
965 | trig != INTR_TRIGGER_CONFORM && | |
966 | pola != INTR_POLARITY_CONFORM) { | |
2e62e7a5 SZ |
967 | if (map->im_trig != trig || |
968 | map->im_pola != pola) | |
969 | return -1; | |
970 | } | |
971 | return irq; | |
972 | } | |
e90e7ac4 | 973 | } |
2e62e7a5 | 974 | return -1; |
e90e7ac4 SZ |
975 | } |
976 | ||
d1ae7328 | 977 | static void |
bec969af SZ |
978 | ioapic_abi_legacy_intr_config(int irq, enum intr_trigger trig, |
979 | enum intr_polarity pola) | |
d1ae7328 | 980 | { |
7a54dec9 | 981 | struct ioapic_irqinfo *info; |
2e62e7a5 | 982 | struct ioapic_irqmap *map = NULL; |
d1ae7328 | 983 | void *ioaddr; |
9dba15ae | 984 | int pin, cpuid; |
d1ae7328 | 985 | |
d1ae7328 SZ |
986 | KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL); |
987 | KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW); | |
d1ae7328 | 988 | |
2a32da90 | 989 | KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max); |
2e62e7a5 SZ |
990 | for (cpuid = 0; cpuid < ncpus; ++cpuid) { |
991 | map = &ioapic_irqmaps[cpuid][irq]; | |
2a32da90 | 992 | if (map->im_type == IOAPIC_IMT_LEGACY) |
2e62e7a5 SZ |
993 | break; |
994 | } | |
995 | KKASSERT(cpuid < ncpus); | |
d1ae7328 | 996 | |
7962296e | 997 | #ifdef notyet |
d1ae7328 SZ |
998 | if (map->im_flags & IOAPIC_IMF_CONF) { |
999 | if (trig != map->im_trig) { | |
ed20d0e3 | 1000 | panic("ioapic_intr_config: trig %s -> %s", |
4ecd5d4d SZ |
1001 | intr_str_trigger(map->im_trig), |
1002 | intr_str_trigger(trig)); | |
d1ae7328 SZ |
1003 | } |
1004 | if (pola != map->im_pola) { | |
ed20d0e3 | 1005 | panic("ioapic_intr_config: pola %s -> %s", |
4ecd5d4d SZ |
1006 | intr_str_polarity(map->im_pola), |
1007 | intr_str_polarity(pola)); | |
d1ae7328 SZ |
1008 | } |
1009 | return; | |
1010 | } | |
7962296e | 1011 | #endif |
d1ae7328 SZ |
1012 | map->im_flags |= IOAPIC_IMF_CONF; |
1013 | ||
1014 | if (trig == map->im_trig && pola == map->im_pola) | |
1015 | return; | |
1016 | ||
1017 | if (bootverbose) { | |
4ecd5d4d SZ |
1018 | kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n", |
1019 | irq, map->im_gsi, | |
1020 | intr_str_trigger(map->im_trig), | |
1021 | intr_str_polarity(map->im_pola), | |
1022 | intr_str_trigger(trig), | |
1023 | intr_str_polarity(pola)); | |
d1ae7328 | 1024 | } |
d1ae7328 SZ |
1025 | map->im_trig = trig; |
1026 | map->im_pola = pola; | |
1027 | ||
1028 | pin = ioapic_gsi_pin(map->im_gsi); | |
1029 | ioaddr = ioapic_gsi_ioaddr(map->im_gsi); | |
1030 | ||
7a54dec9 | 1031 | info = &ioapic_irqs[irq]; |
d1ae7328 | 1032 | |
7bceaa10 SZ |
1033 | imen_lock(); |
1034 | ||
7a54dec9 | 1035 | info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL; |
d1ae7328 | 1036 | if (map->im_trig == INTR_TRIGGER_LEVEL) |
7a54dec9 | 1037 | info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL; |
929c940f | 1038 | |
ecec8ddc | 1039 | ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq, |
9dba15ae | 1040 | map->im_trig, map->im_pola, cpuid); |
7bceaa10 SZ |
1041 | |
1042 | imen_unlock(); | |
929c940f SZ |
1043 | } |
1044 | ||
6b809ec7 | 1045 | int |
027bbbfe | 1046 | ioapic_conf_legacy_extint(int irq) |
6b809ec7 | 1047 | { |
7a54dec9 | 1048 | struct ioapic_irqinfo *info; |
6b809ec7 SZ |
1049 | struct ioapic_irqmap *map; |
1050 | void *ioaddr; | |
1051 | int pin, error, vec; | |
1052 | ||
9dba15ae SZ |
1053 | /* XXX only irq0 is allowed */ |
1054 | KKASSERT(irq == 0); | |
1055 | ||
6b809ec7 SZ |
1056 | vec = IDT_OFFSET + irq; |
1057 | ||
1058 | if (ioapic_abi_extint_irq == irq) | |
1059 | return 0; | |
1060 | else if (ioapic_abi_extint_irq >= 0) | |
1061 | return EEXIST; | |
1062 | ||
1063 | error = icu_ioapic_extint(irq, vec); | |
1064 | if (error) | |
1065 | return error; | |
1066 | ||
2e62e7a5 SZ |
1067 | /* ExtINT is always targeted to cpu0 */ |
1068 | map = &ioapic_irqmaps[0][irq]; | |
6b809ec7 SZ |
1069 | |
1070 | KKASSERT(map->im_type == IOAPIC_IMT_RESERVED || | |
2a32da90 SZ |
1071 | map->im_type == IOAPIC_IMT_LEGACY); |
1072 | if (map->im_type == IOAPIC_IMT_LEGACY) { | |
6b809ec7 SZ |
1073 | if (map->im_flags & IOAPIC_IMF_CONF) |
1074 | return EEXIST; | |
1075 | } | |
1076 | ioapic_abi_extint_irq = irq; | |
1077 | ||
2a32da90 | 1078 | map->im_type = IOAPIC_IMT_LEGACY; |
6b809ec7 SZ |
1079 | map->im_trig = INTR_TRIGGER_EDGE; |
1080 | map->im_pola = INTR_POLARITY_HIGH; | |
1081 | map->im_flags = IOAPIC_IMF_CONF; | |
1082 | ||
1083 | map->im_gsi = ioapic_extpin_gsi(); | |
1084 | KKASSERT(map->im_gsi >= 0); | |
1085 | ||
1086 | if (bootverbose) { | |
4ecd5d4d SZ |
1087 | kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n", |
1088 | irq, map->im_gsi, | |
1089 | intr_str_trigger(map->im_trig), | |
1090 | intr_str_polarity(map->im_pola)); | |
6b809ec7 SZ |
1091 | } |
1092 | ||
1093 | pin = ioapic_gsi_pin(map->im_gsi); | |
1094 | ioaddr = ioapic_gsi_ioaddr(map->im_gsi); | |
1095 | ||
7a54dec9 | 1096 | info = &ioapic_irqs[irq]; |
6b809ec7 SZ |
1097 | |
1098 | imen_lock(); | |
1099 | ||
7a54dec9 SZ |
1100 | info->io_addr = ioaddr; |
1101 | info->io_idx = IOAPIC_REDTBL + (2 * pin); | |
1102 | info->io_flags = IOAPIC_IRQI_FLAG_MASKED; | |
6b809ec7 SZ |
1103 | |
1104 | ioapic_extpin_setup(ioaddr, pin, vec); | |
1105 | ||
1106 | imen_unlock(); | |
1107 | ||
1108 | return 0; | |
1109 | } | |
a05c798c SZ |
1110 | |
1111 | static int | |
bec969af | 1112 | ioapic_abi_legacy_intr_cpuid(int irq) |
a05c798c | 1113 | { |
2e62e7a5 SZ |
1114 | const struct ioapic_irqmap *map = NULL; |
1115 | int cpuid; | |
9dba15ae | 1116 | |
2a32da90 | 1117 | KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max); |
9dba15ae | 1118 | |
2e62e7a5 SZ |
1119 | for (cpuid = 0; cpuid < ncpus; ++cpuid) { |
1120 | map = &ioapic_irqmaps[cpuid][irq]; | |
2a32da90 | 1121 | if (map->im_type == IOAPIC_IMT_LEGACY) |
2e62e7a5 | 1122 | return cpuid; |
9dba15ae SZ |
1123 | } |
1124 | ||
2e62e7a5 SZ |
1125 | /* XXX some drivers tries to peek at reserved IRQs */ |
1126 | for (cpuid = 0; cpuid < ncpus; ++cpuid) { | |
1127 | map = &ioapic_irqmaps[cpuid][irq]; | |
1128 | KKASSERT(map->im_type == IOAPIC_IMT_RESERVED); | |
1129 | } | |
1130 | return 0; | |
9dba15ae SZ |
1131 | } |
1132 | ||
1133 | static int | |
1134 | ioapic_abi_gsi_cpuid(int irq, int gsi) | |
1135 | { | |
1136 | char envpath[32]; | |
1137 | int cpuid = -1; | |
1138 | ||
1139 | KKASSERT(gsi >= 0); | |
1140 | ||
1141 | if (irq == 0 || gsi == 0) { | |
0a83ab6f | 1142 | KKASSERT(irq >= 0); |
c80b6136 SZ |
1143 | if (bootverbose) { |
1144 | kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n", | |
1145 | irq, gsi); | |
1146 | } | |
9dba15ae SZ |
1147 | return 0; |
1148 | } | |
1149 | ||
0a83ab6f | 1150 | if (irq >= 0 && irq == acpi_sci_irqno()) { |
c80b6136 SZ |
1151 | if (bootverbose) { |
1152 | kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n", | |
1153 | irq, gsi); | |
1154 | } | |
9dba15ae SZ |
1155 | return 0; |
1156 | } | |
1157 | ||
1158 | ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi); | |
1159 | kgetenv_int(envpath, &cpuid); | |
1160 | ||
1161 | if (cpuid < 0) { | |
b18d6a13 | 1162 | if (!ioapic_abi_gsi_balance) { |
0a83ab6f | 1163 | if (irq >= 0 && bootverbose) { |
b18d6a13 SZ |
1164 | kprintf("IOAPIC: irq %d, gsi %d -> cpu0 " |
1165 | "(fixed)\n", irq, gsi); | |
1166 | } | |
1167 | return 0; | |
1168 | } | |
1169 | ||
9dba15ae | 1170 | cpuid = gsi % ncpus; |
0a83ab6f | 1171 | if (irq >= 0 && bootverbose) { |
c80b6136 SZ |
1172 | kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n", |
1173 | irq, gsi, cpuid); | |
1174 | } | |
9dba15ae SZ |
1175 | } else if (cpuid >= ncpus) { |
1176 | cpuid = ncpus - 1; | |
0a83ab6f | 1177 | if (irq >= 0 && bootverbose) { |
c80b6136 SZ |
1178 | kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n", |
1179 | irq, gsi, cpuid); | |
1180 | } | |
9dba15ae | 1181 | } else { |
0a83ab6f | 1182 | if (irq >= 0 && bootverbose) { |
c80b6136 SZ |
1183 | kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n", |
1184 | irq, gsi, cpuid); | |
1185 | } | |
9dba15ae SZ |
1186 | } |
1187 | return cpuid; | |
a05c798c | 1188 | } |
0f3e19b1 SZ |
1189 | |
1190 | static void | |
1191 | ioapic_abi_rman_setup(struct rman *rm) | |
1192 | { | |
1193 | int start, end, i; | |
1194 | ||
1195 | KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU, | |
1196 | ("invalid rman cpuid %d", rm->rm_cpuid)); | |
1197 | ||
1198 | start = end = -1; | |
1199 | for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) { | |
1200 | const struct ioapic_irqmap *map = | |
1201 | &ioapic_irqmaps[rm->rm_cpuid][i]; | |
1202 | ||
1203 | if (start < 0) { | |
1204 | if (IOAPIC_IMT_ISHWI(map)) | |
1205 | start = end = i; | |
1206 | } else { | |
1207 | if (IOAPIC_IMT_ISHWI(map)) { | |
1208 | end = i; | |
1209 | } else { | |
1210 | KKASSERT(end >= 0); | |
1211 | if (bootverbose) { | |
1212 | kprintf("IOAPIC: rman cpu%d %d - %d\n", | |
1213 | rm->rm_cpuid, start, end); | |
1214 | } | |
1215 | if (rman_manage_region(rm, start, end)) { | |
1216 | panic("rman_manage_region" | |
1217 | "(cpu%d %d - %d)", rm->rm_cpuid, | |
1218 | start, end); | |
1219 | } | |
1220 | start = end = -1; | |
1221 | } | |
1222 | } | |
1223 | } | |
1224 | if (start >= 0) { | |
1225 | KKASSERT(end >= 0); | |
1226 | if (bootverbose) { | |
1227 | kprintf("IOAPIC: rman cpu%d %d - %d\n", | |
1228 | rm->rm_cpuid, start, end); | |
1229 | } | |
1230 | if (rman_manage_region(rm, start, end)) { | |
1231 | panic("rman_manage_region(cpu%d %d - %d)", | |
1232 | rm->rm_cpuid, start, end); | |
1233 | } | |
1234 | } | |
1235 | } | |
be98308a SZ |
1236 | |
1237 | static int | |
6bf6f751 SZ |
1238 | ioapic_abi_msi_alloc_intern(int type, const char *desc, |
1239 | int intrs[], int count, int cpuid) | |
be98308a SZ |
1240 | { |
1241 | int i, error; | |
1242 | ||
1243 | KASSERT(cpuid >= 0 && cpuid < ncpus, | |
1244 | ("invalid cpuid %d", cpuid)); | |
1245 | ||
ed20d0e3 | 1246 | KASSERT(count > 0 && count <= 32, ("invalid count %d", count)); |
be98308a | 1247 | KASSERT((count & (count - 1)) == 0, |
ed20d0e3 | 1248 | ("count %d is not power of 2", count)); |
be98308a SZ |
1249 | |
1250 | lwkt_gettoken(&ioapic_irqmap_tok); | |
1251 | ||
1252 | /* | |
1253 | * NOTE: | |
1254 | * Since IDT_OFFSET is 32, which is the maximum valid 'count', | |
1255 | * we do not need to find out the first properly aligned | |
1256 | * interrupt vector. | |
1257 | */ | |
1258 | ||
1259 | error = EMSGSIZE; | |
1260 | for (i = ioapic_abi_msi_start; i < IOAPIC_HWI_VECTORS; i += count) { | |
1261 | int j; | |
1262 | ||
1263 | if (ioapic_irqmaps[cpuid][i].im_type != IOAPIC_IMT_UNUSED) | |
1264 | continue; | |
1265 | ||
1266 | for (j = 1; j < count; ++j) { | |
1267 | if (ioapic_irqmaps[cpuid][i + j].im_type != | |
1268 | IOAPIC_IMT_UNUSED) | |
1269 | break; | |
1270 | } | |
1271 | if (j != count) | |
1272 | continue; | |
1273 | ||
1274 | for (j = 0; j < count; ++j) { | |
1275 | int intr = i + j, cpu; | |
1276 | ||
1277 | for (cpu = 0; cpu < ncpus; ++cpu) { | |
1278 | struct ioapic_irqmap *map; | |
1279 | ||
1280 | map = &ioapic_irqmaps[cpu][intr]; | |
1281 | KASSERT(map->im_msi_base < 0, | |
ed20d0e3 | 1282 | ("intr %d cpu%d, stale %s-base %d", |
6bf6f751 | 1283 | intr, cpu, desc, map->im_msi_base)); |
be98308a | 1284 | KASSERT(map->im_type == IOAPIC_IMT_UNUSED, |
ed20d0e3 | 1285 | ("intr %d cpu%d, already allocated", |
be98308a SZ |
1286 | intr, cpu)); |
1287 | ||
1288 | if (cpu == cpuid) { | |
6bf6f751 | 1289 | map->im_type = type; |
be98308a SZ |
1290 | map->im_msi_base = i; |
1291 | } else { | |
1292 | map->im_type = IOAPIC_IMT_SHADOW; | |
1293 | } | |
1294 | } | |
1295 | ||
1296 | intrs[j] = intr; | |
1297 | msi_setup(intr); | |
1298 | ||
1299 | if (bootverbose) { | |
6bf6f751 SZ |
1300 | kprintf("alloc %s intr %d on cpu%d\n", |
1301 | desc, intr, cpuid); | |
be98308a SZ |
1302 | } |
1303 | } | |
1304 | error = 0; | |
1305 | break; | |
1306 | } | |
1307 | ||
1308 | lwkt_reltoken(&ioapic_irqmap_tok); | |
1309 | ||
1310 | return error; | |
1311 | } | |
1312 | ||
1313 | static void | |
6bf6f751 SZ |
1314 | ioapic_abi_msi_release_intern(int type, const char *desc, |
1315 | const int intrs[], int count, int cpuid) | |
be98308a SZ |
1316 | { |
1317 | int i, msi_base = -1, intr_next = -1, mask; | |
1318 | ||
1319 | KASSERT(cpuid >= 0 && cpuid < ncpus, | |
1320 | ("invalid cpuid %d", cpuid)); | |
1321 | ||
ed20d0e3 | 1322 | KASSERT(count > 0 && count <= 32, ("invalid count %d", count)); |
be98308a SZ |
1323 | |
1324 | mask = count - 1; | |
ed20d0e3 | 1325 | KASSERT((count & mask) == 0, ("count %d is not power of 2", count)); |
be98308a SZ |
1326 | |
1327 | lwkt_gettoken(&ioapic_irqmap_tok); | |
1328 | ||
1329 | for (i = 0; i < count; ++i) { | |
1330 | int intr = intrs[i], cpu; | |
1331 | ||
1332 | KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, | |
ed20d0e3 | 1333 | ("invalid intr %d", intr)); |
be98308a SZ |
1334 | |
1335 | for (cpu = 0; cpu < ncpus; ++cpu) { | |
1336 | struct ioapic_irqmap *map; | |
1337 | ||
1338 | map = &ioapic_irqmaps[cpu][intr]; | |
1339 | ||
1340 | if (cpu == cpuid) { | |
6bf6f751 | 1341 | KASSERT(map->im_type == type, |
ed20d0e3 SW |
1342 | ("trying to release non-%s intr %d cpu%d, " |
1343 | "type %d", desc, intr, cpu, | |
6bf6f751 | 1344 | map->im_type)); |
be98308a SZ |
1345 | KASSERT(map->im_msi_base >= 0 && |
1346 | map->im_msi_base <= intr, | |
ed20d0e3 | 1347 | ("intr %d cpu%d, invalid %s-base %d", |
6bf6f751 | 1348 | intr, cpu, desc, map->im_msi_base)); |
be98308a | 1349 | KASSERT((map->im_msi_base & mask) == 0, |
6bf6f751 | 1350 | ("intr %d cpu%d, %s-base %d is " |
ed20d0e3 | 1351 | "not properly aligned %d", |
6bf6f751 | 1352 | intr, cpu, desc, map->im_msi_base, count)); |
be98308a SZ |
1353 | |
1354 | if (msi_base < 0) { | |
1355 | msi_base = map->im_msi_base; | |
1356 | } else { | |
1357 | KASSERT(map->im_msi_base == msi_base, | |
1358 | ("intr %d cpu%d, " | |
6bf6f751 | 1359 | "inconsistent %s-base, " |
ed20d0e3 | 1360 | "was %d, now %d", |
6bf6f751 | 1361 | intr, cpu, desc, |
be98308a SZ |
1362 | msi_base, map->im_msi_base)); |
1363 | } | |
1364 | map->im_msi_base = -1; | |
1365 | } else { | |
1366 | KASSERT(map->im_type == IOAPIC_IMT_SHADOW, | |
ed20d0e3 SW |
1367 | ("trying to release non-%ssh intr %d cpu%d, " |
1368 | "type %d", desc, intr, cpu, | |
6bf6f751 | 1369 | map->im_type)); |
be98308a | 1370 | KASSERT(map->im_msi_base < 0, |
ed20d0e3 | 1371 | ("intr %d cpu%d, invalid %ssh-base %d", |
6bf6f751 | 1372 | intr, cpu, desc, map->im_msi_base)); |
be98308a SZ |
1373 | } |
1374 | map->im_type = IOAPIC_IMT_UNUSED; | |
1375 | } | |
1376 | ||
1377 | if (intr_next < intr) | |
1378 | intr_next = intr; | |
1379 | ||
6bf6f751 SZ |
1380 | if (bootverbose) { |
1381 | kprintf("release %s intr %d on cpu%d\n", | |
1382 | desc, intr, cpuid); | |
1383 | } | |
be98308a SZ |
1384 | } |
1385 | ||
1386 | KKASSERT(intr_next > 0); | |
1387 | KKASSERT(msi_base >= 0); | |
1388 | ||
1389 | ++intr_next; | |
1390 | if (intr_next < IOAPIC_HWI_VECTORS) { | |
1391 | int cpu; | |
1392 | ||
1393 | for (cpu = 0; cpu < ncpus; ++cpu) { | |
1394 | const struct ioapic_irqmap *map = | |
1395 | &ioapic_irqmaps[cpu][intr_next]; | |
1396 | ||
6bf6f751 | 1397 | if (map->im_type == type) { |
be98308a | 1398 | KASSERT(map->im_msi_base != msi_base, |
ed20d0e3 | 1399 | ("more than %d %s was allocated", |
6bf6f751 | 1400 | count, desc)); |
be98308a SZ |
1401 | } |
1402 | } | |
1403 | } | |
1404 | ||
1405 | lwkt_reltoken(&ioapic_irqmap_tok); | |
1406 | } | |
1407 | ||
6bf6f751 SZ |
1408 | static int |
1409 | ioapic_abi_msi_alloc(int intrs[], int count, int cpuid) | |
1410 | { | |
1411 | return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSI, "MSI", | |
1412 | intrs, count, cpuid); | |
1413 | } | |
1414 | ||
1415 | static void | |
1416 | ioapic_abi_msi_release(const int intrs[], int count, int cpuid) | |
1417 | { | |
1418 | ioapic_abi_msi_release_intern(IOAPIC_IMT_MSI, "MSI", | |
1419 | intrs, count, cpuid); | |
1420 | } | |
1421 | ||
1422 | static int | |
1423 | ioapic_abi_msix_alloc(int *intr, int cpuid) | |
1424 | { | |
1425 | return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSIX, "MSI-X", | |
1426 | intr, 1, cpuid); | |
1427 | } | |
1428 | ||
1429 | static void | |
1430 | ioapic_abi_msix_release(int intr, int cpuid) | |
1431 | { | |
1432 | ioapic_abi_msi_release_intern(IOAPIC_IMT_MSIX, "MSI-X", | |
1433 | &intr, 1, cpuid); | |
1434 | } | |
1435 | ||
be98308a SZ |
1436 | static void |
1437 | ioapic_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid) | |
1438 | { | |
1439 | const struct ioapic_irqmap *map; | |
1440 | ||
1441 | KASSERT(cpuid >= 0 && cpuid < ncpus, | |
1442 | ("invalid cpuid %d", cpuid)); | |
1443 | ||
1444 | KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, | |
ed20d0e3 | 1445 | ("invalid intr %d", intr)); |
be98308a SZ |
1446 | |
1447 | lwkt_gettoken(&ioapic_irqmap_tok); | |
1448 | ||
1449 | map = &ioapic_irqmaps[cpuid][intr]; | |
6bf6f751 SZ |
1450 | KASSERT(map->im_type == IOAPIC_IMT_MSI || |
1451 | map->im_type == IOAPIC_IMT_MSIX, | |
ed20d0e3 | 1452 | ("trying to map non-MSI/MSI-X intr %d, type %d", intr, map->im_type)); |
be98308a | 1453 | KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, |
ed20d0e3 | 1454 | ("intr %d, invalid %s-base %d", intr, |
6bf6f751 SZ |
1455 | map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X", |
1456 | map->im_msi_base)); | |
be98308a SZ |
1457 | |
1458 | msi_map(map->im_msi_base, addr, data, cpuid); | |
1459 | ||
6bf6f751 SZ |
1460 | if (bootverbose) { |
1461 | kprintf("map %s intr %d on cpu%d\n", | |
1462 | map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X", | |
1463 | intr, cpuid); | |
1464 | } | |
be98308a SZ |
1465 | |
1466 | lwkt_reltoken(&ioapic_irqmap_tok); | |
1467 | } |