| 1 | /* |
| 2 | * Copyright (c) 1997, 1998, 1999 |
| 3 | * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * 1. Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * 2. Redistributions in binary form must reproduce the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer in the |
| 12 | * documentation and/or other materials provided with the distribution. |
| 13 | * 3. All advertising materials mentioning features or use of this software |
| 14 | * must display the following acknowledgement: |
| 15 | * This product includes software developed by Bill Paul. |
| 16 | * 4. Neither the name of the author nor the names of any co-contributors |
| 17 | * may be used to endorse or promote products derived from this software |
| 18 | * without specific prior written permission. |
| 19 | * |
| 20 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
| 21 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 23 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
| 24 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 30 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 31 | * |
| 32 | * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ |
| 33 | * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.56.2.1 2008/08/05 11:30:33 sephe Exp $ |
| 34 | */ |
| 35 | |
| 36 | /* |
| 37 | * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 |
| 38 | * series chips and several workalikes including the following: |
| 39 | * |
| 40 | * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) |
| 41 | * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) |
| 42 | * Lite-On 82c168/82c169 PNIC (www.litecom.com) |
| 43 | * ASIX Electronics AX88140A (www.asix.com.tw) |
| 44 | * ASIX Electronics AX88141 (www.asix.com.tw) |
| 45 | * ADMtek AL981 (www.admtek.com.tw) |
| 46 | * ADMtek AN985 (www.admtek.com.tw) |
| 47 | * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 |
| 48 | * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) |
| 49 | * Accton EN1217 (www.accton.com) |
| 50 | * Xircom X3201 (www.xircom.com) |
| 51 | * Conexant LANfinity (www.conexant.com) |
| 52 | * |
| 53 | * Datasheets for the 21143 are available at developer.intel.com. |
| 54 | * Datasheets for the clone parts can be found at their respective sites. |
| 55 | * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) |
| 56 | * The PNIC II is essentially a Macronix 98715A chip; the only difference |
| 57 | * worth noting is that its multicast hash table is only 128 bits wide |
| 58 | * instead of 512. |
| 59 | * |
| 60 | * Written by Bill Paul <wpaul@ee.columbia.edu> |
| 61 | * Electrical Engineering Department |
| 62 | * Columbia University, New York City |
| 63 | */ |
| 64 | |
| 65 | /* |
| 66 | * The Intel 21143 is the successor to the DEC 21140. It is basically |
| 67 | * the same as the 21140 but with a few new features. The 21143 supports |
| 68 | * three kinds of media attachments: |
| 69 | * |
| 70 | * o MII port, for 10Mbps and 100Mbps support and NWAY |
| 71 | * autonegotiation provided by an external PHY. |
| 72 | * o SYM port, for symbol mode 100Mbps support. |
| 73 | * o 10baseT port. |
| 74 | * o AUI/BNC port. |
| 75 | * |
| 76 | * The 100Mbps SYM port and 10baseT port can be used together in |
| 77 | * combination with the internal NWAY support to create a 10/100 |
| 78 | * autosensing configuration. |
| 79 | * |
| 80 | * Note that not all tulip workalikes are handled in this driver: we only |
| 81 | * deal with those which are relatively well behaved. The Winbond is |
| 82 | * handled separately due to its different register offsets and the |
| 83 | * special handling needed for its various bugs. The PNIC is handled |
| 84 | * here, but I'm not thrilled about it. |
| 85 | * |
| 86 | * All of the workalike chips use some form of MII transceiver support |
| 87 | * with the exception of the Macronix chips, which also have a SYM port. |
| 88 | * The ASIX AX88140A is also documented to have a SYM port, but all |
| 89 | * the cards I've seen use an MII transceiver, probably because the |
| 90 | * AX88140A doesn't support internal NWAY. |
| 91 | */ |
| 92 | |
| 93 | #include "opt_polling.h" |
| 94 | |
| 95 | #include <sys/param.h> |
| 96 | #include <sys/systm.h> |
| 97 | #include <sys/sockio.h> |
| 98 | #include <sys/mbuf.h> |
| 99 | #include <sys/malloc.h> |
| 100 | #include <sys/kernel.h> |
| 101 | #include <sys/interrupt.h> |
| 102 | #include <sys/socket.h> |
| 103 | #include <sys/sysctl.h> |
| 104 | #include <sys/bus.h> |
| 105 | #include <sys/rman.h> |
| 106 | #include <sys/thread2.h> |
| 107 | |
| 108 | #include <net/if.h> |
| 109 | #include <net/ifq_var.h> |
| 110 | #include <net/if_arp.h> |
| 111 | #include <net/ethernet.h> |
| 112 | #include <net/if_dl.h> |
| 113 | #include <net/if_media.h> |
| 114 | #include <net/if_types.h> |
| 115 | #include <net/vlan/if_vlan_var.h> |
| 116 | |
| 117 | #include <net/bpf.h> |
| 118 | |
| 119 | #include <vm/vm.h> /* for vtophys */ |
| 120 | #include <vm/pmap.h> /* for vtophys */ |
| 121 | |
| 122 | #include "../mii_layer/mii.h" |
| 123 | #include "../mii_layer/miivar.h" |
| 124 | |
| 125 | #include <bus/pci/pcireg.h> |
| 126 | #include <bus/pci/pcivar.h> |
| 127 | |
| 128 | #define DC_USEIOSPACE |
| 129 | |
| 130 | #include "if_dcreg.h" |
| 131 | |
| 132 | /* "controller miibus0" required. See GENERIC if you get errors here. */ |
| 133 | #include "miibus_if.h" |
| 134 | |
| 135 | /* |
| 136 | * Various supported device vendors/types and their names. |
| 137 | */ |
| 138 | static const struct dc_type dc_devs[] = { |
| 139 | { DC_VENDORID_DEC, DC_DEVICEID_21143, |
| 140 | "Intel 21143 10/100BaseTX" }, |
| 141 | { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, |
| 142 | "Davicom DM9009 10/100BaseTX" }, |
| 143 | { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, |
| 144 | "Davicom DM9100 10/100BaseTX" }, |
| 145 | { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, |
| 146 | "Davicom DM9102 10/100BaseTX" }, |
| 147 | { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, |
| 148 | "Davicom DM9102A 10/100BaseTX" }, |
| 149 | { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, |
| 150 | "ADMtek AL981 10/100BaseTX" }, |
| 151 | { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, |
| 152 | "ADMtek AN985 10/100BaseTX" }, |
| 153 | { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, |
| 154 | "Netgear FA511 10/100BaseTX" }, |
| 155 | { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, |
| 156 | "ADMtek ADM9511 10/100BaseTX" }, |
| 157 | { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, |
| 158 | "ADMtek ADM9513 10/100BaseTX" }, |
| 159 | { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, |
| 160 | "ASIX AX88140A 10/100BaseTX" }, |
| 161 | { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, |
| 162 | "ASIX AX88141 10/100BaseTX" }, |
| 163 | { DC_VENDORID_MX, DC_DEVICEID_98713, |
| 164 | "Macronix 98713 10/100BaseTX" }, |
| 165 | { DC_VENDORID_MX, DC_DEVICEID_98713, |
| 166 | "Macronix 98713A 10/100BaseTX" }, |
| 167 | { DC_VENDORID_CP, DC_DEVICEID_98713_CP, |
| 168 | "Compex RL100-TX 10/100BaseTX" }, |
| 169 | { DC_VENDORID_CP, DC_DEVICEID_98713_CP, |
| 170 | "Compex RL100-TX 10/100BaseTX" }, |
| 171 | { DC_VENDORID_MX, DC_DEVICEID_987x5, |
| 172 | "Macronix 98715/98715A 10/100BaseTX" }, |
| 173 | { DC_VENDORID_MX, DC_DEVICEID_987x5, |
| 174 | "Macronix 98715AEC-C 10/100BaseTX" }, |
| 175 | { DC_VENDORID_MX, DC_DEVICEID_987x5, |
| 176 | "Macronix 98725 10/100BaseTX" }, |
| 177 | { DC_VENDORID_MX, DC_DEVICEID_98727, |
| 178 | "Macronix 98727/98732 10/100BaseTX" }, |
| 179 | { DC_VENDORID_LO, DC_DEVICEID_82C115, |
| 180 | "LC82C115 PNIC II 10/100BaseTX" }, |
| 181 | { DC_VENDORID_LO, DC_DEVICEID_82C168, |
| 182 | "82c168 PNIC 10/100BaseTX" }, |
| 183 | { DC_VENDORID_LO, DC_DEVICEID_82C168, |
| 184 | "82c169 PNIC 10/100BaseTX" }, |
| 185 | { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, |
| 186 | "Accton EN1217 10/100BaseTX" }, |
| 187 | { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, |
| 188 | "Accton EN2242 MiniPCI 10/100BaseTX" }, |
| 189 | { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, |
| 190 | "Xircom X3201 10/100BaseTX" }, |
| 191 | { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, |
| 192 | "Conexant LANfinity MiniPCI 10/100BaseTX" }, |
| 193 | { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, |
| 194 | "3Com OfficeConnect 10/100B" }, |
| 195 | { 0, 0, NULL } |
| 196 | }; |
| 197 | |
| 198 | static int dc_probe (device_t); |
| 199 | static int dc_attach (device_t); |
| 200 | static int dc_detach (device_t); |
| 201 | static int dc_suspend (device_t); |
| 202 | static int dc_resume (device_t); |
| 203 | static void dc_acpi (device_t); |
| 204 | static const struct dc_type *dc_devtype (device_t); |
| 205 | static int dc_newbuf (struct dc_softc *, int, struct mbuf *); |
| 206 | static int dc_encap (struct dc_softc *, struct mbuf *, |
| 207 | u_int32_t *); |
| 208 | static void dc_pnic_rx_bug_war (struct dc_softc *, int); |
| 209 | static int dc_rx_resync (struct dc_softc *); |
| 210 | static void dc_rxeof (struct dc_softc *); |
| 211 | static void dc_txeof (struct dc_softc *); |
| 212 | static void dc_tick (void *); |
| 213 | static void dc_tx_underrun (struct dc_softc *); |
| 214 | static void dc_intr (void *); |
| 215 | static void dc_start (struct ifnet *); |
| 216 | static int dc_ioctl (struct ifnet *, u_long, caddr_t, |
| 217 | struct ucred *); |
| 218 | #ifdef DEVICE_POLLING |
| 219 | static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd, |
| 220 | int count); |
| 221 | #endif |
| 222 | static void dc_init (void *); |
| 223 | static void dc_stop (struct dc_softc *); |
| 224 | static void dc_watchdog (struct ifnet *); |
| 225 | static void dc_shutdown (device_t); |
| 226 | static int dc_ifmedia_upd (struct ifnet *); |
| 227 | static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); |
| 228 | |
| 229 | static void dc_delay (struct dc_softc *); |
| 230 | static void dc_eeprom_idle (struct dc_softc *); |
| 231 | static void dc_eeprom_putbyte (struct dc_softc *, int); |
| 232 | static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); |
| 233 | static void dc_eeprom_getword_pnic |
| 234 | (struct dc_softc *, int, u_int16_t *); |
| 235 | static void dc_eeprom_getword_xircom |
| 236 | (struct dc_softc *, int, u_int16_t *); |
| 237 | static void dc_eeprom_width (struct dc_softc *); |
| 238 | static void dc_read_eeprom (struct dc_softc *, caddr_t, int, |
| 239 | int, int); |
| 240 | |
| 241 | static void dc_mii_writebit (struct dc_softc *, int); |
| 242 | static int dc_mii_readbit (struct dc_softc *); |
| 243 | static void dc_mii_sync (struct dc_softc *); |
| 244 | static void dc_mii_send (struct dc_softc *, u_int32_t, int); |
| 245 | static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); |
| 246 | static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); |
| 247 | static int dc_miibus_readreg (device_t, int, int); |
| 248 | static int dc_miibus_writereg (device_t, int, int, int); |
| 249 | static void dc_miibus_statchg (device_t); |
| 250 | static void dc_miibus_mediainit (device_t); |
| 251 | |
| 252 | static u_int32_t dc_crc_mask (struct dc_softc *); |
| 253 | static void dc_setcfg (struct dc_softc *, int); |
| 254 | static void dc_setfilt_21143 (struct dc_softc *); |
| 255 | static void dc_setfilt_asix (struct dc_softc *); |
| 256 | static void dc_setfilt_admtek (struct dc_softc *); |
| 257 | static void dc_setfilt_xircom (struct dc_softc *); |
| 258 | |
| 259 | static void dc_setfilt (struct dc_softc *); |
| 260 | |
| 261 | static void dc_reset (struct dc_softc *); |
| 262 | static int dc_list_rx_init (struct dc_softc *); |
| 263 | static int dc_list_tx_init (struct dc_softc *); |
| 264 | |
| 265 | static void dc_read_srom (struct dc_softc *, int); |
| 266 | static void dc_parse_21143_srom (struct dc_softc *); |
| 267 | static void dc_decode_leaf_sia (struct dc_softc *, |
| 268 | struct dc_eblock_sia *); |
| 269 | static void dc_decode_leaf_mii (struct dc_softc *, |
| 270 | struct dc_eblock_mii *); |
| 271 | static void dc_decode_leaf_sym (struct dc_softc *, |
| 272 | struct dc_eblock_sym *); |
| 273 | static void dc_apply_fixup (struct dc_softc *, int); |
| 274 | static uint32_t dc_mchash_xircom(struct dc_softc *, const uint8_t *); |
| 275 | |
| 276 | #ifdef DC_USEIOSPACE |
| 277 | #define DC_RES SYS_RES_IOPORT |
| 278 | #define DC_RID DC_PCI_CFBIO |
| 279 | #else |
| 280 | #define DC_RES SYS_RES_MEMORY |
| 281 | #define DC_RID DC_PCI_CFBMA |
| 282 | #endif |
| 283 | |
| 284 | static device_method_t dc_methods[] = { |
| 285 | /* Device interface */ |
| 286 | DEVMETHOD(device_probe, dc_probe), |
| 287 | DEVMETHOD(device_attach, dc_attach), |
| 288 | DEVMETHOD(device_detach, dc_detach), |
| 289 | DEVMETHOD(device_suspend, dc_suspend), |
| 290 | DEVMETHOD(device_resume, dc_resume), |
| 291 | DEVMETHOD(device_shutdown, dc_shutdown), |
| 292 | |
| 293 | /* bus interface */ |
| 294 | DEVMETHOD(bus_print_child, bus_generic_print_child), |
| 295 | DEVMETHOD(bus_driver_added, bus_generic_driver_added), |
| 296 | |
| 297 | /* MII interface */ |
| 298 | DEVMETHOD(miibus_readreg, dc_miibus_readreg), |
| 299 | DEVMETHOD(miibus_writereg, dc_miibus_writereg), |
| 300 | DEVMETHOD(miibus_statchg, dc_miibus_statchg), |
| 301 | DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), |
| 302 | |
| 303 | { 0, 0 } |
| 304 | }; |
| 305 | |
| 306 | static driver_t dc_driver = { |
| 307 | "dc", |
| 308 | dc_methods, |
| 309 | sizeof(struct dc_softc) |
| 310 | }; |
| 311 | |
| 312 | static devclass_t dc_devclass; |
| 313 | |
| 314 | #ifdef __i386__ |
| 315 | static int dc_quick=1; |
| 316 | SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, |
| 317 | &dc_quick,0,"do not mdevget in dc driver"); |
| 318 | #endif |
| 319 | |
| 320 | DECLARE_DUMMY_MODULE(if_dc); |
| 321 | DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); |
| 322 | DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); |
| 323 | DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); |
| 324 | |
| 325 | #define DC_SETBIT(sc, reg, x) \ |
| 326 | CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) |
| 327 | |
| 328 | #define DC_CLRBIT(sc, reg, x) \ |
| 329 | CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) |
| 330 | |
| 331 | #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) |
| 332 | #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) |
| 333 | |
| 334 | static void |
| 335 | dc_delay(struct dc_softc *sc) |
| 336 | { |
| 337 | int idx; |
| 338 | |
| 339 | for (idx = (300 / 33) + 1; idx > 0; idx--) |
| 340 | CSR_READ_4(sc, DC_BUSCTL); |
| 341 | } |
| 342 | |
| 343 | static void |
| 344 | dc_eeprom_width(struct dc_softc *sc) |
| 345 | { |
| 346 | int i; |
| 347 | |
| 348 | /* Force EEPROM to idle state. */ |
| 349 | dc_eeprom_idle(sc); |
| 350 | |
| 351 | /* Enter EEPROM access mode. */ |
| 352 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); |
| 353 | dc_delay(sc); |
| 354 | DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); |
| 355 | dc_delay(sc); |
| 356 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 357 | dc_delay(sc); |
| 358 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); |
| 359 | dc_delay(sc); |
| 360 | |
| 361 | for (i = 3; i--;) { |
| 362 | if (6 & (1 << i)) |
| 363 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); |
| 364 | else |
| 365 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); |
| 366 | dc_delay(sc); |
| 367 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 368 | dc_delay(sc); |
| 369 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 370 | dc_delay(sc); |
| 371 | } |
| 372 | |
| 373 | for (i = 1; i <= 12; i++) { |
| 374 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 375 | dc_delay(sc); |
| 376 | if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { |
| 377 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 378 | dc_delay(sc); |
| 379 | break; |
| 380 | } |
| 381 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 382 | dc_delay(sc); |
| 383 | } |
| 384 | |
| 385 | /* Turn off EEPROM access mode. */ |
| 386 | dc_eeprom_idle(sc); |
| 387 | |
| 388 | if (i < 4 || i > 12) |
| 389 | sc->dc_romwidth = 6; |
| 390 | else |
| 391 | sc->dc_romwidth = i; |
| 392 | |
| 393 | /* Enter EEPROM access mode. */ |
| 394 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); |
| 395 | dc_delay(sc); |
| 396 | DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); |
| 397 | dc_delay(sc); |
| 398 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 399 | dc_delay(sc); |
| 400 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); |
| 401 | dc_delay(sc); |
| 402 | |
| 403 | /* Turn off EEPROM access mode. */ |
| 404 | dc_eeprom_idle(sc); |
| 405 | } |
| 406 | |
| 407 | static void |
| 408 | dc_eeprom_idle(struct dc_softc *sc) |
| 409 | { |
| 410 | int i; |
| 411 | |
| 412 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); |
| 413 | dc_delay(sc); |
| 414 | DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); |
| 415 | dc_delay(sc); |
| 416 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 417 | dc_delay(sc); |
| 418 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); |
| 419 | dc_delay(sc); |
| 420 | |
| 421 | for (i = 0; i < 25; i++) { |
| 422 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 423 | dc_delay(sc); |
| 424 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 425 | dc_delay(sc); |
| 426 | } |
| 427 | |
| 428 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 429 | dc_delay(sc); |
| 430 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); |
| 431 | dc_delay(sc); |
| 432 | CSR_WRITE_4(sc, DC_SIO, 0x00000000); |
| 433 | |
| 434 | return; |
| 435 | } |
| 436 | |
| 437 | /* |
| 438 | * Send a read command and address to the EEPROM, check for ACK. |
| 439 | */ |
| 440 | static void |
| 441 | dc_eeprom_putbyte(struct dc_softc *sc, int addr) |
| 442 | { |
| 443 | int d, i; |
| 444 | |
| 445 | d = DC_EECMD_READ >> 6; |
| 446 | for (i = 3; i--; ) { |
| 447 | if (d & (1 << i)) |
| 448 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); |
| 449 | else |
| 450 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); |
| 451 | dc_delay(sc); |
| 452 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 453 | dc_delay(sc); |
| 454 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 455 | dc_delay(sc); |
| 456 | } |
| 457 | |
| 458 | /* |
| 459 | * Feed in each bit and strobe the clock. |
| 460 | */ |
| 461 | for (i = sc->dc_romwidth; i--;) { |
| 462 | if (addr & (1 << i)) { |
| 463 | SIO_SET(DC_SIO_EE_DATAIN); |
| 464 | } else { |
| 465 | SIO_CLR(DC_SIO_EE_DATAIN); |
| 466 | } |
| 467 | dc_delay(sc); |
| 468 | SIO_SET(DC_SIO_EE_CLK); |
| 469 | dc_delay(sc); |
| 470 | SIO_CLR(DC_SIO_EE_CLK); |
| 471 | dc_delay(sc); |
| 472 | } |
| 473 | |
| 474 | return; |
| 475 | } |
| 476 | |
| 477 | /* |
| 478 | * Read a word of data stored in the EEPROM at address 'addr.' |
| 479 | * The PNIC 82c168/82c169 has its own non-standard way to read |
| 480 | * the EEPROM. |
| 481 | */ |
| 482 | static void |
| 483 | dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) |
| 484 | { |
| 485 | int i; |
| 486 | u_int32_t r; |
| 487 | |
| 488 | CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); |
| 489 | |
| 490 | for (i = 0; i < DC_TIMEOUT; i++) { |
| 491 | DELAY(1); |
| 492 | r = CSR_READ_4(sc, DC_SIO); |
| 493 | if (!(r & DC_PN_SIOCTL_BUSY)) { |
| 494 | *dest = (u_int16_t)(r & 0xFFFF); |
| 495 | return; |
| 496 | } |
| 497 | } |
| 498 | |
| 499 | return; |
| 500 | } |
| 501 | |
| 502 | /* |
| 503 | * Read a word of data stored in the EEPROM at address 'addr.' |
| 504 | * The Xircom X3201 has its own non-standard way to read |
| 505 | * the EEPROM, too. |
| 506 | */ |
| 507 | static void |
| 508 | dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) |
| 509 | { |
| 510 | SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); |
| 511 | |
| 512 | addr *= 2; |
| 513 | CSR_WRITE_4(sc, DC_ROM, addr | 0x160); |
| 514 | *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; |
| 515 | addr += 1; |
| 516 | CSR_WRITE_4(sc, DC_ROM, addr | 0x160); |
| 517 | *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; |
| 518 | |
| 519 | SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); |
| 520 | } |
| 521 | |
| 522 | /* |
| 523 | * Read a word of data stored in the EEPROM at address 'addr.' |
| 524 | */ |
| 525 | static void |
| 526 | dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) |
| 527 | { |
| 528 | int i; |
| 529 | u_int16_t word = 0; |
| 530 | |
| 531 | /* Force EEPROM to idle state. */ |
| 532 | dc_eeprom_idle(sc); |
| 533 | |
| 534 | /* Enter EEPROM access mode. */ |
| 535 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); |
| 536 | dc_delay(sc); |
| 537 | DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); |
| 538 | dc_delay(sc); |
| 539 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
| 540 | dc_delay(sc); |
| 541 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); |
| 542 | dc_delay(sc); |
| 543 | |
| 544 | /* |
| 545 | * Send address of word we want to read. |
| 546 | */ |
| 547 | dc_eeprom_putbyte(sc, addr); |
| 548 | |
| 549 | /* |
| 550 | * Start reading bits from EEPROM. |
| 551 | */ |
| 552 | for (i = 0x8000; i; i >>= 1) { |
| 553 | SIO_SET(DC_SIO_EE_CLK); |
| 554 | dc_delay(sc); |
| 555 | if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) |
| 556 | word |= i; |
| 557 | dc_delay(sc); |
| 558 | SIO_CLR(DC_SIO_EE_CLK); |
| 559 | dc_delay(sc); |
| 560 | } |
| 561 | |
| 562 | /* Turn off EEPROM access mode. */ |
| 563 | dc_eeprom_idle(sc); |
| 564 | |
| 565 | *dest = word; |
| 566 | |
| 567 | return; |
| 568 | } |
| 569 | |
| 570 | /* |
| 571 | * Read a sequence of words from the EEPROM. |
| 572 | */ |
| 573 | static void |
| 574 | dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) |
| 575 | { |
| 576 | int i; |
| 577 | u_int16_t word = 0, *ptr; |
| 578 | |
| 579 | for (i = 0; i < cnt; i++) { |
| 580 | if (DC_IS_PNIC(sc)) |
| 581 | dc_eeprom_getword_pnic(sc, off + i, &word); |
| 582 | else if (DC_IS_XIRCOM(sc)) |
| 583 | dc_eeprom_getword_xircom(sc, off + i, &word); |
| 584 | else |
| 585 | dc_eeprom_getword(sc, off + i, &word); |
| 586 | ptr = (u_int16_t *)(dest + (i * 2)); |
| 587 | if (swap) |
| 588 | *ptr = ntohs(word); |
| 589 | else |
| 590 | *ptr = word; |
| 591 | } |
| 592 | |
| 593 | return; |
| 594 | } |
| 595 | |
| 596 | /* |
| 597 | * The following two routines are taken from the Macronix 98713 |
| 598 | * Application Notes pp.19-21. |
| 599 | */ |
| 600 | /* |
| 601 | * Write a bit to the MII bus. |
| 602 | */ |
| 603 | static void |
| 604 | dc_mii_writebit(struct dc_softc *sc, int bit) |
| 605 | { |
| 606 | if (bit) |
| 607 | CSR_WRITE_4(sc, DC_SIO, |
| 608 | DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); |
| 609 | else |
| 610 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); |
| 611 | |
| 612 | DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); |
| 613 | DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); |
| 614 | |
| 615 | return; |
| 616 | } |
| 617 | |
| 618 | /* |
| 619 | * Read a bit from the MII bus. |
| 620 | */ |
| 621 | static int |
| 622 | dc_mii_readbit(struct dc_softc *sc) |
| 623 | { |
| 624 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); |
| 625 | CSR_READ_4(sc, DC_SIO); |
| 626 | DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); |
| 627 | DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); |
| 628 | if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) |
| 629 | return(1); |
| 630 | |
| 631 | return(0); |
| 632 | } |
| 633 | |
| 634 | /* |
| 635 | * Sync the PHYs by setting data bit and strobing the clock 32 times. |
| 636 | */ |
| 637 | static void |
| 638 | dc_mii_sync(struct dc_softc *sc) |
| 639 | { |
| 640 | int i; |
| 641 | |
| 642 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); |
| 643 | |
| 644 | for (i = 0; i < 32; i++) |
| 645 | dc_mii_writebit(sc, 1); |
| 646 | |
| 647 | return; |
| 648 | } |
| 649 | |
| 650 | /* |
| 651 | * Clock a series of bits through the MII. |
| 652 | */ |
| 653 | static void |
| 654 | dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) |
| 655 | { |
| 656 | int i; |
| 657 | |
| 658 | for (i = (0x1 << (cnt - 1)); i; i >>= 1) |
| 659 | dc_mii_writebit(sc, bits & i); |
| 660 | } |
| 661 | |
| 662 | /* |
| 663 | * Read an PHY register through the MII. |
| 664 | */ |
| 665 | static int |
| 666 | dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) |
| 667 | { |
| 668 | int ack, i; |
| 669 | |
| 670 | /* |
| 671 | * Set up frame for RX. |
| 672 | */ |
| 673 | frame->mii_stdelim = DC_MII_STARTDELIM; |
| 674 | frame->mii_opcode = DC_MII_READOP; |
| 675 | frame->mii_turnaround = 0; |
| 676 | frame->mii_data = 0; |
| 677 | |
| 678 | /* |
| 679 | * Sync the PHYs. |
| 680 | */ |
| 681 | dc_mii_sync(sc); |
| 682 | |
| 683 | /* |
| 684 | * Send command/address info. |
| 685 | */ |
| 686 | dc_mii_send(sc, frame->mii_stdelim, 2); |
| 687 | dc_mii_send(sc, frame->mii_opcode, 2); |
| 688 | dc_mii_send(sc, frame->mii_phyaddr, 5); |
| 689 | dc_mii_send(sc, frame->mii_regaddr, 5); |
| 690 | |
| 691 | #ifdef notdef |
| 692 | /* Idle bit */ |
| 693 | dc_mii_writebit(sc, 1); |
| 694 | dc_mii_writebit(sc, 0); |
| 695 | #endif |
| 696 | |
| 697 | /* Check for ack */ |
| 698 | ack = dc_mii_readbit(sc); |
| 699 | |
| 700 | /* |
| 701 | * Now try reading data bits. If the ack failed, we still |
| 702 | * need to clock through 16 cycles to keep the PHY(s) in sync. |
| 703 | */ |
| 704 | if (ack) { |
| 705 | for(i = 0; i < 16; i++) { |
| 706 | dc_mii_readbit(sc); |
| 707 | } |
| 708 | goto fail; |
| 709 | } |
| 710 | |
| 711 | for (i = 0x8000; i; i >>= 1) { |
| 712 | if (!ack) { |
| 713 | if (dc_mii_readbit(sc)) |
| 714 | frame->mii_data |= i; |
| 715 | } |
| 716 | } |
| 717 | |
| 718 | fail: |
| 719 | |
| 720 | dc_mii_writebit(sc, 0); |
| 721 | dc_mii_writebit(sc, 0); |
| 722 | |
| 723 | if (ack) |
| 724 | return(1); |
| 725 | return(0); |
| 726 | } |
| 727 | |
| 728 | /* |
| 729 | * Write to a PHY register through the MII. |
| 730 | */ |
| 731 | static int |
| 732 | dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) |
| 733 | { |
| 734 | /* |
| 735 | * Set up frame for TX. |
| 736 | */ |
| 737 | |
| 738 | frame->mii_stdelim = DC_MII_STARTDELIM; |
| 739 | frame->mii_opcode = DC_MII_WRITEOP; |
| 740 | frame->mii_turnaround = DC_MII_TURNAROUND; |
| 741 | |
| 742 | /* |
| 743 | * Sync the PHYs. |
| 744 | */ |
| 745 | dc_mii_sync(sc); |
| 746 | |
| 747 | dc_mii_send(sc, frame->mii_stdelim, 2); |
| 748 | dc_mii_send(sc, frame->mii_opcode, 2); |
| 749 | dc_mii_send(sc, frame->mii_phyaddr, 5); |
| 750 | dc_mii_send(sc, frame->mii_regaddr, 5); |
| 751 | dc_mii_send(sc, frame->mii_turnaround, 2); |
| 752 | dc_mii_send(sc, frame->mii_data, 16); |
| 753 | |
| 754 | /* Idle bit. */ |
| 755 | dc_mii_writebit(sc, 0); |
| 756 | dc_mii_writebit(sc, 0); |
| 757 | |
| 758 | return(0); |
| 759 | } |
| 760 | |
| 761 | static int |
| 762 | dc_miibus_readreg(device_t dev, int phy, int reg) |
| 763 | { |
| 764 | struct dc_mii_frame frame; |
| 765 | struct dc_softc *sc; |
| 766 | int i, rval, phy_reg = 0; |
| 767 | |
| 768 | sc = device_get_softc(dev); |
| 769 | bzero((char *)&frame, sizeof(frame)); |
| 770 | |
| 771 | /* |
| 772 | * Note: both the AL981 and AN985 have internal PHYs, |
| 773 | * however the AL981 provides direct access to the PHY |
| 774 | * registers while the AN985 uses a serial MII interface. |
| 775 | * The AN985's MII interface is also buggy in that you |
| 776 | * can read from any MII address (0 to 31), but only address 1 |
| 777 | * behaves normally. To deal with both cases, we pretend |
| 778 | * that the PHY is at MII address 1. |
| 779 | */ |
| 780 | if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) |
| 781 | return(0); |
| 782 | |
| 783 | /* |
| 784 | * Note: the ukphy probes of the RS7112 report a PHY at |
| 785 | * MII address 0 (possibly HomePNA?) and 1 (ethernet) |
| 786 | * so we only respond to correct one. |
| 787 | */ |
| 788 | if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) |
| 789 | return(0); |
| 790 | |
| 791 | if (sc->dc_pmode != DC_PMODE_MII) { |
| 792 | if (phy == (MII_NPHY - 1)) { |
| 793 | switch(reg) { |
| 794 | case MII_BMSR: |
| 795 | /* |
| 796 | * Fake something to make the probe |
| 797 | * code think there's a PHY here. |
| 798 | */ |
| 799 | return(BMSR_MEDIAMASK); |
| 800 | break; |
| 801 | case MII_PHYIDR1: |
| 802 | if (DC_IS_PNIC(sc)) |
| 803 | return(DC_VENDORID_LO); |
| 804 | return(DC_VENDORID_DEC); |
| 805 | break; |
| 806 | case MII_PHYIDR2: |
| 807 | if (DC_IS_PNIC(sc)) |
| 808 | return(DC_DEVICEID_82C168); |
| 809 | return(DC_DEVICEID_21143); |
| 810 | break; |
| 811 | default: |
| 812 | return(0); |
| 813 | break; |
| 814 | } |
| 815 | } else |
| 816 | return(0); |
| 817 | } |
| 818 | |
| 819 | if (DC_IS_PNIC(sc)) { |
| 820 | CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | |
| 821 | (phy << 23) | (reg << 18)); |
| 822 | for (i = 0; i < DC_TIMEOUT; i++) { |
| 823 | DELAY(1); |
| 824 | rval = CSR_READ_4(sc, DC_PN_MII); |
| 825 | if (!(rval & DC_PN_MII_BUSY)) { |
| 826 | rval &= 0xFFFF; |
| 827 | return(rval == 0xFFFF ? 0 : rval); |
| 828 | } |
| 829 | } |
| 830 | return(0); |
| 831 | } |
| 832 | |
| 833 | if (DC_IS_COMET(sc)) { |
| 834 | switch(reg) { |
| 835 | case MII_BMCR: |
| 836 | phy_reg = DC_AL_BMCR; |
| 837 | break; |
| 838 | case MII_BMSR: |
| 839 | phy_reg = DC_AL_BMSR; |
| 840 | break; |
| 841 | case MII_PHYIDR1: |
| 842 | phy_reg = DC_AL_VENID; |
| 843 | break; |
| 844 | case MII_PHYIDR2: |
| 845 | phy_reg = DC_AL_DEVID; |
| 846 | break; |
| 847 | case MII_ANAR: |
| 848 | phy_reg = DC_AL_ANAR; |
| 849 | break; |
| 850 | case MII_ANLPAR: |
| 851 | phy_reg = DC_AL_LPAR; |
| 852 | break; |
| 853 | case MII_ANER: |
| 854 | phy_reg = DC_AL_ANER; |
| 855 | break; |
| 856 | default: |
| 857 | if_printf(&sc->arpcom.ac_if, |
| 858 | "phy_read: bad phy register %x\n", reg); |
| 859 | return(0); |
| 860 | break; |
| 861 | } |
| 862 | |
| 863 | rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; |
| 864 | |
| 865 | if (rval == 0xFFFF) |
| 866 | return(0); |
| 867 | return(rval); |
| 868 | } |
| 869 | |
| 870 | frame.mii_phyaddr = phy; |
| 871 | frame.mii_regaddr = reg; |
| 872 | if (sc->dc_type == DC_TYPE_98713) { |
| 873 | phy_reg = CSR_READ_4(sc, DC_NETCFG); |
| 874 | CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); |
| 875 | } |
| 876 | dc_mii_readreg(sc, &frame); |
| 877 | if (sc->dc_type == DC_TYPE_98713) |
| 878 | CSR_WRITE_4(sc, DC_NETCFG, phy_reg); |
| 879 | |
| 880 | return(frame.mii_data); |
| 881 | } |
| 882 | |
| 883 | static int |
| 884 | dc_miibus_writereg(device_t dev, int phy, int reg, int data) |
| 885 | { |
| 886 | struct dc_softc *sc; |
| 887 | struct dc_mii_frame frame; |
| 888 | int i, phy_reg = 0; |
| 889 | |
| 890 | sc = device_get_softc(dev); |
| 891 | bzero((char *)&frame, sizeof(frame)); |
| 892 | |
| 893 | if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) |
| 894 | return(0); |
| 895 | |
| 896 | if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) |
| 897 | return(0); |
| 898 | |
| 899 | if (DC_IS_PNIC(sc)) { |
| 900 | CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | |
| 901 | (phy << 23) | (reg << 10) | data); |
| 902 | for (i = 0; i < DC_TIMEOUT; i++) { |
| 903 | if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) |
| 904 | break; |
| 905 | } |
| 906 | return(0); |
| 907 | } |
| 908 | |
| 909 | if (DC_IS_COMET(sc)) { |
| 910 | switch(reg) { |
| 911 | case MII_BMCR: |
| 912 | phy_reg = DC_AL_BMCR; |
| 913 | break; |
| 914 | case MII_BMSR: |
| 915 | phy_reg = DC_AL_BMSR; |
| 916 | break; |
| 917 | case MII_PHYIDR1: |
| 918 | phy_reg = DC_AL_VENID; |
| 919 | break; |
| 920 | case MII_PHYIDR2: |
| 921 | phy_reg = DC_AL_DEVID; |
| 922 | break; |
| 923 | case MII_ANAR: |
| 924 | phy_reg = DC_AL_ANAR; |
| 925 | break; |
| 926 | case MII_ANLPAR: |
| 927 | phy_reg = DC_AL_LPAR; |
| 928 | break; |
| 929 | case MII_ANER: |
| 930 | phy_reg = DC_AL_ANER; |
| 931 | break; |
| 932 | default: |
| 933 | if_printf(&sc->arpcom.ac_if, |
| 934 | "phy_write: bad phy register %x\n", reg); |
| 935 | return(0); |
| 936 | break; |
| 937 | } |
| 938 | |
| 939 | CSR_WRITE_4(sc, phy_reg, data); |
| 940 | return(0); |
| 941 | } |
| 942 | |
| 943 | frame.mii_phyaddr = phy; |
| 944 | frame.mii_regaddr = reg; |
| 945 | frame.mii_data = data; |
| 946 | |
| 947 | if (sc->dc_type == DC_TYPE_98713) { |
| 948 | phy_reg = CSR_READ_4(sc, DC_NETCFG); |
| 949 | CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); |
| 950 | } |
| 951 | dc_mii_writereg(sc, &frame); |
| 952 | if (sc->dc_type == DC_TYPE_98713) |
| 953 | CSR_WRITE_4(sc, DC_NETCFG, phy_reg); |
| 954 | |
| 955 | return(0); |
| 956 | } |
| 957 | |
| 958 | static void |
| 959 | dc_miibus_statchg(device_t dev) |
| 960 | { |
| 961 | struct dc_softc *sc; |
| 962 | struct mii_data *mii; |
| 963 | struct ifmedia *ifm; |
| 964 | |
| 965 | sc = device_get_softc(dev); |
| 966 | if (DC_IS_ADMTEK(sc)) |
| 967 | return; |
| 968 | |
| 969 | mii = device_get_softc(sc->dc_miibus); |
| 970 | ifm = &mii->mii_media; |
| 971 | if (DC_IS_DAVICOM(sc) && |
| 972 | IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { |
| 973 | dc_setcfg(sc, ifm->ifm_media); |
| 974 | sc->dc_if_media = ifm->ifm_media; |
| 975 | } else { |
| 976 | dc_setcfg(sc, mii->mii_media_active); |
| 977 | sc->dc_if_media = mii->mii_media_active; |
| 978 | } |
| 979 | |
| 980 | return; |
| 981 | } |
| 982 | |
| 983 | /* |
| 984 | * Special support for DM9102A cards with HomePNA PHYs. Note: |
| 985 | * with the Davicom DM9102A/DM9801 eval board that I have, it seems |
| 986 | * to be impossible to talk to the management interface of the DM9801 |
| 987 | * PHY (its MDIO pin is not connected to anything). Consequently, |
| 988 | * the driver has to just 'know' about the additional mode and deal |
| 989 | * with it itself. *sigh* |
| 990 | */ |
| 991 | static void |
| 992 | dc_miibus_mediainit(device_t dev) |
| 993 | { |
| 994 | struct dc_softc *sc; |
| 995 | struct mii_data *mii; |
| 996 | struct ifmedia *ifm; |
| 997 | int rev; |
| 998 | |
| 999 | rev = pci_get_revid(dev); |
| 1000 | |
| 1001 | sc = device_get_softc(dev); |
| 1002 | mii = device_get_softc(sc->dc_miibus); |
| 1003 | ifm = &mii->mii_media; |
| 1004 | |
| 1005 | if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) |
| 1006 | ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); |
| 1007 | |
| 1008 | return; |
| 1009 | } |
| 1010 | |
| 1011 | #define DC_BITS_512 9 |
| 1012 | #define DC_BITS_128 7 |
| 1013 | #define DC_BITS_64 6 |
| 1014 | |
| 1015 | static u_int32_t |
| 1016 | dc_crc_mask(struct dc_softc *sc) |
| 1017 | { |
| 1018 | /* |
| 1019 | * The hash table on the PNIC II and the MX98715AEC-C/D/E |
| 1020 | * chips is only 128 bits wide. |
| 1021 | */ |
| 1022 | if (sc->dc_flags & DC_128BIT_HASH) |
| 1023 | return ((1 << DC_BITS_128) - 1); |
| 1024 | |
| 1025 | /* The hash table on the MX98715BEC is only 64 bits wide. */ |
| 1026 | if (sc->dc_flags & DC_64BIT_HASH) |
| 1027 | return ((1 << DC_BITS_64) - 1); |
| 1028 | |
| 1029 | return ((1 << DC_BITS_512) - 1); |
| 1030 | } |
| 1031 | |
| 1032 | /* |
| 1033 | * 21143-style RX filter setup routine. Filter programming is done by |
| 1034 | * downloading a special setup frame into the TX engine. 21143, Macronix, |
| 1035 | * PNIC, PNIC II and Davicom chips are programmed this way. |
| 1036 | * |
| 1037 | * We always program the chip using 'hash perfect' mode, i.e. one perfect |
| 1038 | * address (our node address) and a 512-bit hash filter for multicast |
| 1039 | * frames. We also sneak the broadcast address into the hash filter since |
| 1040 | * we need that too. |
| 1041 | */ |
| 1042 | void |
| 1043 | dc_setfilt_21143(struct dc_softc *sc) |
| 1044 | { |
| 1045 | struct dc_desc *sframe; |
| 1046 | u_int32_t h, crc_mask, *sp; |
| 1047 | struct ifmultiaddr *ifma; |
| 1048 | struct ifnet *ifp; |
| 1049 | int i; |
| 1050 | |
| 1051 | ifp = &sc->arpcom.ac_if; |
| 1052 | |
| 1053 | i = sc->dc_cdata.dc_tx_prod; |
| 1054 | DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); |
| 1055 | sc->dc_cdata.dc_tx_cnt++; |
| 1056 | sframe = &sc->dc_ldata->dc_tx_list[i]; |
| 1057 | sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; |
| 1058 | bzero((char *)sp, DC_SFRAME_LEN); |
| 1059 | |
| 1060 | sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); |
| 1061 | sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | |
| 1062 | DC_FILTER_HASHPERF | DC_TXCTL_FINT; |
| 1063 | |
| 1064 | sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; |
| 1065 | |
| 1066 | /* If we want promiscuous mode, set the allframes bit. */ |
| 1067 | if (ifp->if_flags & IFF_PROMISC) |
| 1068 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
| 1069 | else |
| 1070 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
| 1071 | |
| 1072 | if (ifp->if_flags & IFF_ALLMULTI) |
| 1073 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
| 1074 | else |
| 1075 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
| 1076 | |
| 1077 | crc_mask = dc_crc_mask(sc); |
| 1078 | LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { |
| 1079 | if (ifma->ifma_addr->sa_family != AF_LINK) |
| 1080 | continue; |
| 1081 | h = ether_crc32_le( |
| 1082 | LLADDR((struct sockaddr_dl *)ifma->ifma_addr), |
| 1083 | ETHER_ADDR_LEN) & crc_mask; |
| 1084 | sp[h >> 4] |= 1 << (h & 0xF); |
| 1085 | } |
| 1086 | |
| 1087 | if (ifp->if_flags & IFF_BROADCAST) { |
| 1088 | h = ether_crc32_le(ifp->if_broadcastaddr, |
| 1089 | ETHER_ADDR_LEN) & crc_mask; |
| 1090 | sp[h >> 4] |= 1 << (h & 0xF); |
| 1091 | } |
| 1092 | |
| 1093 | /* Set our MAC address */ |
| 1094 | sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; |
| 1095 | sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; |
| 1096 | sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; |
| 1097 | |
| 1098 | sframe->dc_status = DC_TXSTAT_OWN; |
| 1099 | CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); |
| 1100 | |
| 1101 | /* |
| 1102 | * The PNIC takes an exceedingly long time to process its |
| 1103 | * setup frame; wait 10ms after posting the setup frame |
| 1104 | * before proceeding, just so it has time to swallow its |
| 1105 | * medicine. |
| 1106 | */ |
| 1107 | DELAY(10000); |
| 1108 | |
| 1109 | ifp->if_timer = 5; |
| 1110 | |
| 1111 | return; |
| 1112 | } |
| 1113 | |
| 1114 | void |
| 1115 | dc_setfilt_admtek(struct dc_softc *sc) |
| 1116 | { |
| 1117 | struct ifnet *ifp; |
| 1118 | int h = 0; |
| 1119 | u_int32_t crc_mask; |
| 1120 | u_int32_t hashes[2] = { 0, 0 }; |
| 1121 | struct ifmultiaddr *ifma; |
| 1122 | |
| 1123 | ifp = &sc->arpcom.ac_if; |
| 1124 | |
| 1125 | /* Init our MAC address */ |
| 1126 | CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); |
| 1127 | CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); |
| 1128 | |
| 1129 | /* If we want promiscuous mode, set the allframes bit. */ |
| 1130 | if (ifp->if_flags & IFF_PROMISC) |
| 1131 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
| 1132 | else |
| 1133 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
| 1134 | |
| 1135 | if (ifp->if_flags & IFF_ALLMULTI) |
| 1136 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
| 1137 | else |
| 1138 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
| 1139 | |
| 1140 | /* first, zot all the existing hash bits */ |
| 1141 | CSR_WRITE_4(sc, DC_AL_MAR0, 0); |
| 1142 | CSR_WRITE_4(sc, DC_AL_MAR1, 0); |
| 1143 | |
| 1144 | /* |
| 1145 | * If we're already in promisc or allmulti mode, we |
| 1146 | * don't have to bother programming the multicast filter. |
| 1147 | */ |
| 1148 | if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) |
| 1149 | return; |
| 1150 | |
| 1151 | /* now program new ones */ |
| 1152 | if (DC_IS_CENTAUR(sc)) |
| 1153 | crc_mask = dc_crc_mask(sc); |
| 1154 | else |
| 1155 | crc_mask = 0x3f; |
| 1156 | LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { |
| 1157 | if (ifma->ifma_addr->sa_family != AF_LINK) |
| 1158 | continue; |
| 1159 | if (DC_IS_CENTAUR(sc)) { |
| 1160 | h = ether_crc32_le( |
| 1161 | LLADDR((struct sockaddr_dl *)ifma->ifma_addr), |
| 1162 | ETHER_ADDR_LEN) & crc_mask; |
| 1163 | } else { |
| 1164 | h = ether_crc32_be( |
| 1165 | LLADDR((struct sockaddr_dl *)ifma->ifma_addr), |
| 1166 | ETHER_ADDR_LEN); |
| 1167 | h = (h >> 26) & crc_mask; |
| 1168 | } |
| 1169 | if (h < 32) |
| 1170 | hashes[0] |= (1 << h); |
| 1171 | else |
| 1172 | hashes[1] |= (1 << (h - 32)); |
| 1173 | } |
| 1174 | |
| 1175 | CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); |
| 1176 | CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); |
| 1177 | |
| 1178 | return; |
| 1179 | } |
| 1180 | |
| 1181 | void |
| 1182 | dc_setfilt_asix(struct dc_softc *sc) |
| 1183 | { |
| 1184 | struct ifnet *ifp; |
| 1185 | int h = 0; |
| 1186 | u_int32_t hashes[2] = { 0, 0 }; |
| 1187 | struct ifmultiaddr *ifma; |
| 1188 | |
| 1189 | ifp = &sc->arpcom.ac_if; |
| 1190 | |
| 1191 | /* Init our MAC address */ |
| 1192 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); |
| 1193 | CSR_WRITE_4(sc, DC_AX_FILTDATA, |
| 1194 | *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); |
| 1195 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); |
| 1196 | CSR_WRITE_4(sc, DC_AX_FILTDATA, |
| 1197 | *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); |
| 1198 | |
| 1199 | /* If we want promiscuous mode, set the allframes bit. */ |
| 1200 | if (ifp->if_flags & IFF_PROMISC) |
| 1201 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
| 1202 | else |
| 1203 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
| 1204 | |
| 1205 | if (ifp->if_flags & IFF_ALLMULTI) |
| 1206 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
| 1207 | else |
| 1208 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
| 1209 | |
| 1210 | /* |
| 1211 | * The ASIX chip has a special bit to enable reception |
| 1212 | * of broadcast frames. |
| 1213 | */ |
| 1214 | if (ifp->if_flags & IFF_BROADCAST) |
| 1215 | DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); |
| 1216 | else |
| 1217 | DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); |
| 1218 | |
| 1219 | /* first, zot all the existing hash bits */ |
| 1220 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); |
| 1221 | CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); |
| 1222 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); |
| 1223 | CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); |
| 1224 | |
| 1225 | /* |
| 1226 | * If we're already in promisc or allmulti mode, we |
| 1227 | * don't have to bother programming the multicast filter. |
| 1228 | */ |
| 1229 | if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) |
| 1230 | return; |
| 1231 | |
| 1232 | /* now program new ones */ |
| 1233 | LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { |
| 1234 | if (ifma->ifma_addr->sa_family != AF_LINK) |
| 1235 | continue; |
| 1236 | h = ether_crc32_be( |
| 1237 | LLADDR((struct sockaddr_dl *)ifma->ifma_addr), |
| 1238 | ETHER_ADDR_LEN); |
| 1239 | h = (h >> 26) & 0x3f; |
| 1240 | if (h < 32) |
| 1241 | hashes[0] |= (1 << h); |
| 1242 | else |
| 1243 | hashes[1] |= (1 << (h - 32)); |
| 1244 | } |
| 1245 | |
| 1246 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); |
| 1247 | CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); |
| 1248 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); |
| 1249 | CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); |
| 1250 | |
| 1251 | return; |
| 1252 | } |
| 1253 | |
| 1254 | void |
| 1255 | dc_setfilt_xircom(struct dc_softc *sc) |
| 1256 | { |
| 1257 | struct dc_desc *sframe; |
| 1258 | u_int32_t h, *sp; |
| 1259 | struct ifmultiaddr *ifma; |
| 1260 | struct ifnet *ifp; |
| 1261 | int i; |
| 1262 | |
| 1263 | ifp = &sc->arpcom.ac_if; |
| 1264 | KASSERT(ifp->if_flags & IFF_RUNNING, |
| 1265 | ("%s is not running yet\n", ifp->if_xname)); |
| 1266 | |
| 1267 | DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); |
| 1268 | |
| 1269 | i = sc->dc_cdata.dc_tx_prod; |
| 1270 | DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); |
| 1271 | sc->dc_cdata.dc_tx_cnt++; |
| 1272 | sframe = &sc->dc_ldata->dc_tx_list[i]; |
| 1273 | sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; |
| 1274 | bzero(sp, DC_SFRAME_LEN); |
| 1275 | |
| 1276 | sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); |
| 1277 | sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | |
| 1278 | DC_FILTER_HASHPERF | DC_TXCTL_FINT; |
| 1279 | |
| 1280 | sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; |
| 1281 | |
| 1282 | /* If we want promiscuous mode, set the allframes bit. */ |
| 1283 | if (ifp->if_flags & IFF_PROMISC) |
| 1284 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
| 1285 | else |
| 1286 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
| 1287 | |
| 1288 | if (ifp->if_flags & IFF_ALLMULTI) |
| 1289 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
| 1290 | else |
| 1291 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
| 1292 | |
| 1293 | LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { |
| 1294 | if (ifma->ifma_addr->sa_family != AF_LINK) |
| 1295 | continue; |
| 1296 | h = dc_mchash_xircom(sc, |
| 1297 | LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); |
| 1298 | sp[h >> 4] |= 1 << (h & 0xF); |
| 1299 | } |
| 1300 | |
| 1301 | if (ifp->if_flags & IFF_BROADCAST) { |
| 1302 | h = dc_mchash_xircom(sc, (caddr_t)ðerbroadcastaddr); |
| 1303 | sp[h >> 4] |= 1 << (h & 0xF); |
| 1304 | } |
| 1305 | |
| 1306 | /* Set our MAC address */ |
| 1307 | sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; |
| 1308 | sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; |
| 1309 | sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; |
| 1310 | |
| 1311 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); |
| 1312 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); |
| 1313 | sframe->dc_status = DC_TXSTAT_OWN; |
| 1314 | CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); |
| 1315 | |
| 1316 | /* |
| 1317 | * wait some time... |
| 1318 | */ |
| 1319 | DELAY(1000); |
| 1320 | |
| 1321 | ifp->if_timer = 5; |
| 1322 | } |
| 1323 | |
| 1324 | static void |
| 1325 | dc_setfilt(struct dc_softc *sc) |
| 1326 | { |
| 1327 | if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || |
| 1328 | DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) |
| 1329 | dc_setfilt_21143(sc); |
| 1330 | |
| 1331 | if (DC_IS_ASIX(sc)) |
| 1332 | dc_setfilt_asix(sc); |
| 1333 | |
| 1334 | if (DC_IS_ADMTEK(sc)) |
| 1335 | dc_setfilt_admtek(sc); |
| 1336 | |
| 1337 | if (DC_IS_XIRCOM(sc)) |
| 1338 | dc_setfilt_xircom(sc); |
| 1339 | } |
| 1340 | |
| 1341 | /* |
| 1342 | * In order to fiddle with the |
| 1343 | * 'full-duplex' and '100Mbps' bits in the netconfig register, we |
| 1344 | * first have to put the transmit and/or receive logic in the idle state. |
| 1345 | */ |
| 1346 | static void |
| 1347 | dc_setcfg(struct dc_softc *sc, int media) |
| 1348 | { |
| 1349 | int i, restart = 0; |
| 1350 | u_int32_t isr; |
| 1351 | |
| 1352 | if (IFM_SUBTYPE(media) == IFM_NONE) |
| 1353 | return; |
| 1354 | |
| 1355 | if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { |
| 1356 | restart = 1; |
| 1357 | DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); |
| 1358 | |
| 1359 | for (i = 0; i < DC_TIMEOUT; i++) { |
| 1360 | isr = CSR_READ_4(sc, DC_ISR); |
| 1361 | if ((isr & DC_ISR_TX_IDLE) && |
| 1362 | ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || |
| 1363 | (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) |
| 1364 | break; |
| 1365 | DELAY(10); |
| 1366 | } |
| 1367 | |
| 1368 | if (i == DC_TIMEOUT) { |
| 1369 | if_printf(&sc->arpcom.ac_if, |
| 1370 | "failed to force tx and rx to idle state\n"); |
| 1371 | } |
| 1372 | } |
| 1373 | |
| 1374 | if (IFM_SUBTYPE(media) == IFM_100_TX) { |
| 1375 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); |
| 1376 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); |
| 1377 | if (sc->dc_pmode == DC_PMODE_MII) { |
| 1378 | int watchdogreg; |
| 1379 | |
| 1380 | if (DC_IS_INTEL(sc)) { |
| 1381 | /* there's a write enable bit here that reads as 1 */ |
| 1382 | watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); |
| 1383 | watchdogreg &= ~DC_WDOG_CTLWREN; |
| 1384 | watchdogreg |= DC_WDOG_JABBERDIS; |
| 1385 | CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); |
| 1386 | } else { |
| 1387 | DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); |
| 1388 | } |
| 1389 | DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| |
| 1390 | DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); |
| 1391 | if (sc->dc_type == DC_TYPE_98713) |
| 1392 | DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| |
| 1393 | DC_NETCFG_SCRAMBLER)); |
| 1394 | if (!DC_IS_DAVICOM(sc)) |
| 1395 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
| 1396 | DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); |
| 1397 | if (DC_IS_INTEL(sc)) |
| 1398 | dc_apply_fixup(sc, IFM_AUTO); |
| 1399 | } else { |
| 1400 | if (DC_IS_PNIC(sc)) { |
| 1401 | DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); |
| 1402 | DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); |
| 1403 | DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); |
| 1404 | } |
| 1405 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
| 1406 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); |
| 1407 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); |
| 1408 | if (DC_IS_INTEL(sc)) |
| 1409 | dc_apply_fixup(sc, |
| 1410 | (media & IFM_GMASK) == IFM_FDX ? |
| 1411 | IFM_100_TX|IFM_FDX : IFM_100_TX); |
| 1412 | } |
| 1413 | } |
| 1414 | |
| 1415 | if (IFM_SUBTYPE(media) == IFM_10_T) { |
| 1416 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); |
| 1417 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); |
| 1418 | if (sc->dc_pmode == DC_PMODE_MII) { |
| 1419 | int watchdogreg; |
| 1420 | |
| 1421 | /* there's a write enable bit here that reads as 1 */ |
| 1422 | if (DC_IS_INTEL(sc)) { |
| 1423 | watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); |
| 1424 | watchdogreg &= ~DC_WDOG_CTLWREN; |
| 1425 | watchdogreg |= DC_WDOG_JABBERDIS; |
| 1426 | CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); |
| 1427 | } else { |
| 1428 | DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); |
| 1429 | } |
| 1430 | DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| |
| 1431 | DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); |
| 1432 | if (sc->dc_type == DC_TYPE_98713) |
| 1433 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); |
| 1434 | if (!DC_IS_DAVICOM(sc)) |
| 1435 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
| 1436 | DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); |
| 1437 | if (DC_IS_INTEL(sc)) |
| 1438 | dc_apply_fixup(sc, IFM_AUTO); |
| 1439 | } else { |
| 1440 | if (DC_IS_PNIC(sc)) { |
| 1441 | DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); |
| 1442 | DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); |
| 1443 | DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); |
| 1444 | } |
| 1445 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
| 1446 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); |
| 1447 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); |
| 1448 | if (DC_IS_INTEL(sc)) { |
| 1449 | DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); |
| 1450 | DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); |
| 1451 | if ((media & IFM_GMASK) == IFM_FDX) |
| 1452 | DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); |
| 1453 | else |
| 1454 | DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); |
| 1455 | DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); |
| 1456 | DC_CLRBIT(sc, DC_10BTCTRL, |
| 1457 | DC_TCTL_AUTONEGENBL); |
| 1458 | dc_apply_fixup(sc, |
| 1459 | (media & IFM_GMASK) == IFM_FDX ? |
| 1460 | IFM_10_T|IFM_FDX : IFM_10_T); |
| 1461 | DELAY(20000); |
| 1462 | } |
| 1463 | } |
| 1464 | } |
| 1465 | |
| 1466 | /* |
| 1467 | * If this is a Davicom DM9102A card with a DM9801 HomePNA |
| 1468 | * PHY and we want HomePNA mode, set the portsel bit to turn |
| 1469 | * on the external MII port. |
| 1470 | */ |
| 1471 | if (DC_IS_DAVICOM(sc)) { |
| 1472 | if (IFM_SUBTYPE(media) == IFM_HPNA_1) { |
| 1473 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
| 1474 | sc->dc_link = 1; |
| 1475 | } else { |
| 1476 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
| 1477 | } |
| 1478 | } |
| 1479 | |
| 1480 | if ((media & IFM_GMASK) == IFM_FDX) { |
| 1481 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); |
| 1482 | if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) |
| 1483 | DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); |
| 1484 | } else { |
| 1485 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); |
| 1486 | if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) |
| 1487 | DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); |
| 1488 | } |
| 1489 | |
| 1490 | if (restart) |
| 1491 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); |
| 1492 | |
| 1493 | return; |
| 1494 | } |
| 1495 | |
| 1496 | static void |
| 1497 | dc_reset(struct dc_softc *sc) |
| 1498 | { |
| 1499 | int i; |
| 1500 | |
| 1501 | DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); |
| 1502 | |
| 1503 | for (i = 0; i < DC_TIMEOUT; i++) { |
| 1504 | DELAY(10); |
| 1505 | if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) |
| 1506 | break; |
| 1507 | } |
| 1508 | |
| 1509 | if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) || |
| 1510 | DC_IS_CONEXANT(sc)) { |
| 1511 | DELAY(10000); |
| 1512 | DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); |
| 1513 | i = 0; |
| 1514 | } |
| 1515 | |
| 1516 | if (i == DC_TIMEOUT) |
| 1517 | if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); |
| 1518 | |
| 1519 | /* Wait a little while for the chip to get its brains in order. */ |
| 1520 | DELAY(1000); |
| 1521 | |
| 1522 | CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
| 1523 | CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); |
| 1524 | CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); |
| 1525 | |
| 1526 | /* |
| 1527 | * Bring the SIA out of reset. In some cases, it looks |
| 1528 | * like failing to unreset the SIA soon enough gets it |
| 1529 | * into a state where it will never come out of reset |
| 1530 | * until we reset the whole chip again. |
| 1531 | */ |
| 1532 | if (DC_IS_INTEL(sc)) { |
| 1533 | DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); |
| 1534 | CSR_WRITE_4(sc, DC_10BTCTRL, 0); |
| 1535 | CSR_WRITE_4(sc, DC_WATCHDOG, 0); |
| 1536 | } |
| 1537 | |
| 1538 | return; |
| 1539 | } |
| 1540 | |
| 1541 | static const struct dc_type * |
| 1542 | dc_devtype(device_t dev) |
| 1543 | { |
| 1544 | const struct dc_type *t; |
| 1545 | u_int32_t rev; |
| 1546 | |
| 1547 | t = dc_devs; |
| 1548 | |
| 1549 | while(t->dc_name != NULL) { |
| 1550 | if ((pci_get_vendor(dev) == t->dc_vid) && |
| 1551 | (pci_get_device(dev) == t->dc_did)) { |
| 1552 | /* Check the PCI revision */ |
| 1553 | rev = pci_get_revid(dev); |
| 1554 | if (t->dc_did == DC_DEVICEID_98713 && |
| 1555 | rev >= DC_REVISION_98713A) |
| 1556 | t++; |
| 1557 | if (t->dc_did == DC_DEVICEID_98713_CP && |
| 1558 | rev >= DC_REVISION_98713A) |
| 1559 | t++; |
| 1560 | if (t->dc_did == DC_DEVICEID_987x5 && |
| 1561 | rev >= DC_REVISION_98715AEC_C) |
| 1562 | t++; |
| 1563 | if (t->dc_did == DC_DEVICEID_987x5 && |
| 1564 | rev >= DC_REVISION_98725) |
| 1565 | t++; |
| 1566 | if (t->dc_did == DC_DEVICEID_AX88140A && |
| 1567 | rev >= DC_REVISION_88141) |
| 1568 | t++; |
| 1569 | if (t->dc_did == DC_DEVICEID_82C168 && |
| 1570 | rev >= DC_REVISION_82C169) |
| 1571 | t++; |
| 1572 | if (t->dc_did == DC_DEVICEID_DM9102 && |
| 1573 | rev >= DC_REVISION_DM9102A) |
| 1574 | t++; |
| 1575 | return(t); |
| 1576 | } |
| 1577 | t++; |
| 1578 | } |
| 1579 | |
| 1580 | return(NULL); |
| 1581 | } |
| 1582 | |
| 1583 | /* |
| 1584 | * Probe for a 21143 or clone chip. Check the PCI vendor and device |
| 1585 | * IDs against our list and return a device name if we find a match. |
| 1586 | * We do a little bit of extra work to identify the exact type of |
| 1587 | * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, |
| 1588 | * but different revision IDs. The same is true for 98715/98715A |
| 1589 | * chips and the 98725, as well as the ASIX and ADMtek chips. In some |
| 1590 | * cases, the exact chip revision affects driver behavior. |
| 1591 | */ |
| 1592 | static int |
| 1593 | dc_probe(device_t dev) |
| 1594 | { |
| 1595 | const struct dc_type *t; |
| 1596 | |
| 1597 | t = dc_devtype(dev); |
| 1598 | if (t != NULL) { |
| 1599 | struct dc_softc *sc = device_get_softc(dev); |
| 1600 | |
| 1601 | /* Need this info to decide on a chip type. */ |
| 1602 | sc->dc_info = t; |
| 1603 | device_set_desc(dev, t->dc_name); |
| 1604 | return(0); |
| 1605 | } |
| 1606 | |
| 1607 | return(ENXIO); |
| 1608 | } |
| 1609 | |
| 1610 | static void |
| 1611 | dc_acpi(device_t dev) |
| 1612 | { |
| 1613 | if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { |
| 1614 | uint32_t iobase, membase, irq; |
| 1615 | struct dc_softc *sc; |
| 1616 | |
| 1617 | /* Save important PCI config data. */ |
| 1618 | iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); |
| 1619 | membase = pci_read_config(dev, DC_PCI_CFBMA, 4); |
| 1620 | irq = pci_read_config(dev, DC_PCI_CFIT, 4); |
| 1621 | |
| 1622 | sc = device_get_softc(dev); |
| 1623 | /* Reset the power state. */ |
| 1624 | if_printf(&sc->arpcom.ac_if, |
| 1625 | "chip is in D%d power mode " |
| 1626 | "-- setting to D0\n", pci_get_powerstate(dev)); |
| 1627 | pci_set_powerstate(dev, PCI_POWERSTATE_D0); |
| 1628 | |
| 1629 | /* Restore PCI config data. */ |
| 1630 | pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); |
| 1631 | pci_write_config(dev, DC_PCI_CFBMA, membase, 4); |
| 1632 | pci_write_config(dev, DC_PCI_CFIT, irq, 4); |
| 1633 | } |
| 1634 | } |
| 1635 | |
| 1636 | static void |
| 1637 | dc_apply_fixup(struct dc_softc *sc, int media) |
| 1638 | { |
| 1639 | struct dc_mediainfo *m; |
| 1640 | u_int8_t *p; |
| 1641 | int i; |
| 1642 | u_int32_t reg; |
| 1643 | |
| 1644 | m = sc->dc_mi; |
| 1645 | |
| 1646 | while (m != NULL) { |
| 1647 | if (m->dc_media == media) |
| 1648 | break; |
| 1649 | m = m->dc_next; |
| 1650 | } |
| 1651 | |
| 1652 | if (m == NULL) |
| 1653 | return; |
| 1654 | |
| 1655 | for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { |
| 1656 | reg = (p[0] | (p[1] << 8)) << 16; |
| 1657 | CSR_WRITE_4(sc, DC_WATCHDOG, reg); |
| 1658 | } |
| 1659 | |
| 1660 | for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { |
| 1661 | reg = (p[0] | (p[1] << 8)) << 16; |
| 1662 | CSR_WRITE_4(sc, DC_WATCHDOG, reg); |
| 1663 | } |
| 1664 | |
| 1665 | return; |
| 1666 | } |
| 1667 | |
| 1668 | static void |
| 1669 | dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) |
| 1670 | { |
| 1671 | struct dc_mediainfo *m; |
| 1672 | |
| 1673 | m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); |
| 1674 | switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){ |
| 1675 | case DC_SIA_CODE_10BT: |
| 1676 | m->dc_media = IFM_10_T; |
| 1677 | break; |
| 1678 | |
| 1679 | case DC_SIA_CODE_10BT_FDX: |
| 1680 | m->dc_media = IFM_10_T|IFM_FDX; |
| 1681 | break; |
| 1682 | |
| 1683 | case DC_SIA_CODE_10B2: |
| 1684 | m->dc_media = IFM_10_2; |
| 1685 | break; |
| 1686 | |
| 1687 | case DC_SIA_CODE_10B5: |
| 1688 | m->dc_media = IFM_10_5; |
| 1689 | break; |
| 1690 | } |
| 1691 | if (l->dc_sia_code & DC_SIA_CODE_EXT){ |
| 1692 | m->dc_gp_len = 2; |
| 1693 | m->dc_gp_ptr = |
| 1694 | (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; |
| 1695 | } else { |
| 1696 | m->dc_gp_len = 2; |
| 1697 | m->dc_gp_ptr = |
| 1698 | (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; |
| 1699 | } |
| 1700 | |
| 1701 | m->dc_next = sc->dc_mi; |
| 1702 | sc->dc_mi = m; |
| 1703 | |
| 1704 | sc->dc_pmode = DC_PMODE_SIA; |
| 1705 | |
| 1706 | return; |
| 1707 | } |
| 1708 | |
| 1709 | static void |
| 1710 | dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) |
| 1711 | { |
| 1712 | struct dc_mediainfo *m; |
| 1713 | |
| 1714 | m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); |
| 1715 | if (l->dc_sym_code == DC_SYM_CODE_100BT) |
| 1716 | m->dc_media = IFM_100_TX; |
| 1717 | |
| 1718 | if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) |
| 1719 | m->dc_media = IFM_100_TX|IFM_FDX; |
| 1720 | |
| 1721 | m->dc_gp_len = 2; |
| 1722 | m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; |
| 1723 | |
| 1724 | m->dc_next = sc->dc_mi; |
| 1725 | sc->dc_mi = m; |
| 1726 | |
| 1727 | sc->dc_pmode = DC_PMODE_SYM; |
| 1728 | |
| 1729 | return; |
| 1730 | } |
| 1731 | |
| 1732 | static void |
| 1733 | dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) |
| 1734 | { |
| 1735 | u_int8_t *p; |
| 1736 | struct dc_mediainfo *m; |
| 1737 | |
| 1738 | m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); |
| 1739 | /* We abuse IFM_AUTO to represent MII. */ |
| 1740 | m->dc_media = IFM_AUTO; |
| 1741 | m->dc_gp_len = l->dc_gpr_len; |
| 1742 | |
| 1743 | p = (u_int8_t *)l; |
| 1744 | p += sizeof(struct dc_eblock_mii); |
| 1745 | m->dc_gp_ptr = p; |
| 1746 | p += 2 * l->dc_gpr_len; |
| 1747 | m->dc_reset_len = *p; |
| 1748 | p++; |
| 1749 | m->dc_reset_ptr = p; |
| 1750 | |
| 1751 | m->dc_next = sc->dc_mi; |
| 1752 | sc->dc_mi = m; |
| 1753 | |
| 1754 | return; |
| 1755 | } |
| 1756 | |
| 1757 | static void |
| 1758 | dc_read_srom(struct dc_softc *sc, int bits) |
| 1759 | { |
| 1760 | int size; |
| 1761 | |
| 1762 | size = 2 << bits; |
| 1763 | sc->dc_srom = kmalloc(size, M_DEVBUF, M_INTWAIT); |
| 1764 | dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); |
| 1765 | } |
| 1766 | |
| 1767 | static void |
| 1768 | dc_parse_21143_srom(struct dc_softc *sc) |
| 1769 | { |
| 1770 | struct dc_leaf_hdr *lhdr; |
| 1771 | struct dc_eblock_hdr *hdr; |
| 1772 | int i, loff; |
| 1773 | char *ptr; |
| 1774 | int have_mii; |
| 1775 | |
| 1776 | have_mii = 0; |
| 1777 | loff = sc->dc_srom[27]; |
| 1778 | lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); |
| 1779 | |
| 1780 | ptr = (char *)lhdr; |
| 1781 | ptr += sizeof(struct dc_leaf_hdr) - 1; |
| 1782 | /* |
| 1783 | * Look if we got a MII media block. |
| 1784 | */ |
| 1785 | for (i = 0; i < lhdr->dc_mcnt; i++) { |
| 1786 | hdr = (struct dc_eblock_hdr *)ptr; |
| 1787 | if (hdr->dc_type == DC_EBLOCK_MII) |
| 1788 | have_mii++; |
| 1789 | |
| 1790 | ptr += (hdr->dc_len & 0x7F); |
| 1791 | ptr++; |
| 1792 | } |
| 1793 | |
| 1794 | /* |
| 1795 | * Do the same thing again. Only use SIA and SYM media |
| 1796 | * blocks if no MII media block is available. |
| 1797 | */ |
| 1798 | ptr = (char *)lhdr; |
| 1799 | ptr += sizeof(struct dc_leaf_hdr) - 1; |
| 1800 | for (i = 0; i < lhdr->dc_mcnt; i++) { |
| 1801 | hdr = (struct dc_eblock_hdr *)ptr; |
| 1802 | switch(hdr->dc_type) { |
| 1803 | case DC_EBLOCK_MII: |
| 1804 | dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); |
| 1805 | break; |
| 1806 | case DC_EBLOCK_SIA: |
| 1807 | if (! have_mii) |
| 1808 | dc_decode_leaf_sia(sc, |
| 1809 | (struct dc_eblock_sia *)hdr); |
| 1810 | break; |
| 1811 | case DC_EBLOCK_SYM: |
| 1812 | if (! have_mii) |
| 1813 | dc_decode_leaf_sym(sc, |
| 1814 | (struct dc_eblock_sym *)hdr); |
| 1815 | break; |
| 1816 | default: |
| 1817 | /* Don't care. Yet. */ |
| 1818 | break; |
| 1819 | } |
| 1820 | ptr += (hdr->dc_len & 0x7F); |
| 1821 | ptr++; |
| 1822 | } |
| 1823 | |
| 1824 | return; |
| 1825 | } |
| 1826 | |
| 1827 | /* |
| 1828 | * Attach the interface. Allocate softc structures, do ifmedia |
| 1829 | * setup and ethernet/BPF attach. |
| 1830 | */ |
| 1831 | static int |
| 1832 | dc_attach(device_t dev) |
| 1833 | { |
| 1834 | int tmp = 0; |
| 1835 | u_char eaddr[ETHER_ADDR_LEN]; |
| 1836 | u_int32_t command; |
| 1837 | struct dc_softc *sc; |
| 1838 | struct ifnet *ifp; |
| 1839 | u_int32_t revision; |
| 1840 | int error = 0, rid, mac_offset; |
| 1841 | uint8_t *mac; |
| 1842 | |
| 1843 | sc = device_get_softc(dev); |
| 1844 | callout_init(&sc->dc_stat_timer); |
| 1845 | |
| 1846 | ifp = &sc->arpcom.ac_if; |
| 1847 | if_initname(ifp, device_get_name(dev), device_get_unit(dev)); |
| 1848 | |
| 1849 | /* |
| 1850 | * Handle power management nonsense. |
| 1851 | */ |
| 1852 | dc_acpi(dev); |
| 1853 | |
| 1854 | /* |
| 1855 | * Map control/status registers. |
| 1856 | */ |
| 1857 | pci_enable_busmaster(dev); |
| 1858 | |
| 1859 | rid = DC_RID; |
| 1860 | sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); |
| 1861 | |
| 1862 | if (sc->dc_res == NULL) { |
| 1863 | device_printf(dev, "couldn't map ports/memory\n"); |
| 1864 | error = ENXIO; |
| 1865 | goto fail; |
| 1866 | } |
| 1867 | |
| 1868 | sc->dc_btag = rman_get_bustag(sc->dc_res); |
| 1869 | sc->dc_bhandle = rman_get_bushandle(sc->dc_res); |
| 1870 | |
| 1871 | /* Allocate interrupt */ |
| 1872 | rid = 0; |
| 1873 | sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, |
| 1874 | RF_SHAREABLE | RF_ACTIVE); |
| 1875 | |
| 1876 | if (sc->dc_irq == NULL) { |
| 1877 | device_printf(dev, "couldn't map interrupt\n"); |
| 1878 | error = ENXIO; |
| 1879 | goto fail; |
| 1880 | } |
| 1881 | |
| 1882 | revision = pci_get_revid(dev); |
| 1883 | |
| 1884 | /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ |
| 1885 | if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && |
| 1886 | sc->dc_info->dc_did != DC_DEVICEID_X3201) |
| 1887 | dc_eeprom_width(sc); |
| 1888 | |
| 1889 | switch(sc->dc_info->dc_did) { |
| 1890 | case DC_DEVICEID_21143: |
| 1891 | sc->dc_type = DC_TYPE_21143; |
| 1892 | sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; |
| 1893 | sc->dc_flags |= DC_REDUCED_MII_POLL; |
| 1894 | /* Save EEPROM contents so we can parse them later. */ |
| 1895 | dc_read_srom(sc, sc->dc_romwidth); |
| 1896 | break; |
| 1897 | case DC_DEVICEID_DM9009: |
| 1898 | case DC_DEVICEID_DM9100: |
| 1899 | case DC_DEVICEID_DM9102: |
| 1900 | sc->dc_type = DC_TYPE_DM9102; |
| 1901 | sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; |
| 1902 | sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; |
| 1903 | sc->dc_flags |= DC_TX_ALIGN; |
| 1904 | sc->dc_pmode = DC_PMODE_MII; |
| 1905 | /* Increase the latency timer value. */ |
| 1906 | command = pci_read_config(dev, DC_PCI_CFLT, 4); |
| 1907 | command &= 0xFFFF00FF; |
| 1908 | command |= 0x00008000; |
| 1909 | pci_write_config(dev, DC_PCI_CFLT, command, 4); |
| 1910 | break; |
| 1911 | case DC_DEVICEID_AL981: |
| 1912 | sc->dc_type = DC_TYPE_AL981; |
| 1913 | sc->dc_flags |= DC_TX_USE_TX_INTR; |
| 1914 | sc->dc_flags |= DC_TX_ADMTEK_WAR; |
| 1915 | sc->dc_pmode = DC_PMODE_MII; |
| 1916 | dc_read_srom(sc, sc->dc_romwidth); |
| 1917 | break; |
| 1918 | case DC_DEVICEID_AN985: |
| 1919 | case DC_DEVICEID_ADM9511: |
| 1920 | case DC_DEVICEID_ADM9513: |
| 1921 | case DC_DEVICEID_FA511: |
| 1922 | case DC_DEVICEID_EN2242: |
| 1923 | case DC_DEVICEID_3CSOHOB: |
| 1924 | sc->dc_type = DC_TYPE_AN985; |
| 1925 | sc->dc_flags |= DC_64BIT_HASH; |
| 1926 | sc->dc_flags |= DC_TX_USE_TX_INTR; |
| 1927 | sc->dc_flags |= DC_TX_ADMTEK_WAR; |
| 1928 | sc->dc_pmode = DC_PMODE_MII; |
| 1929 | break; |
| 1930 | case DC_DEVICEID_98713: |
| 1931 | case DC_DEVICEID_98713_CP: |
| 1932 | if (revision < DC_REVISION_98713A) { |
| 1933 | sc->dc_type = DC_TYPE_98713; |
| 1934 | } |
| 1935 | if (revision >= DC_REVISION_98713A) { |
| 1936 | sc->dc_type = DC_TYPE_98713A; |
| 1937 | sc->dc_flags |= DC_21143_NWAY; |
| 1938 | } |
| 1939 | sc->dc_flags |= DC_REDUCED_MII_POLL; |
| 1940 | sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; |
| 1941 | break; |
| 1942 | case DC_DEVICEID_987x5: |
| 1943 | case DC_DEVICEID_EN1217: |
| 1944 | /* |
| 1945 | * Macronix MX98715AEC-C/D/E parts have only a |
| 1946 | * 128-bit hash table. We need to deal with these |
| 1947 | * in the same manner as the PNIC II so that we |
| 1948 | * get the right number of bits out of the |
| 1949 | * CRC routine. |
| 1950 | */ |
| 1951 | if (revision >= DC_REVISION_98715AEC_C && |
| 1952 | revision < DC_REVISION_98725) |
| 1953 | sc->dc_flags |= DC_128BIT_HASH; |
| 1954 | sc->dc_type = DC_TYPE_987x5; |
| 1955 | sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; |
| 1956 | sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; |
| 1957 | break; |
| 1958 | case DC_DEVICEID_98727: |
| 1959 | sc->dc_type = DC_TYPE_987x5; |
| 1960 | sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; |
| 1961 | sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; |
| 1962 | break; |
| 1963 | case DC_DEVICEID_82C115: |
| 1964 | sc->dc_type = DC_TYPE_PNICII; |
| 1965 | sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; |
| 1966 | sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; |
| 1967 | break; |
| 1968 | case DC_DEVICEID_82C168: |
| 1969 | sc->dc_type = DC_TYPE_PNIC; |
| 1970 | sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; |
| 1971 | sc->dc_flags |= DC_PNIC_RX_BUG_WAR; |
| 1972 | sc->dc_pnic_rx_buf = kmalloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK); |
| 1973 | if (revision < DC_REVISION_82C169) |
| 1974 | sc->dc_pmode = DC_PMODE_SYM; |
| 1975 | break; |
| 1976 | case DC_DEVICEID_AX88140A: |
| 1977 | sc->dc_type = DC_TYPE_ASIX; |
| 1978 | sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; |
| 1979 | sc->dc_flags |= DC_REDUCED_MII_POLL; |
| 1980 | sc->dc_pmode = DC_PMODE_MII; |
| 1981 | break; |
| 1982 | case DC_DEVICEID_RS7112: |
| 1983 | sc->dc_type = DC_TYPE_CONEXANT; |
| 1984 | sc->dc_flags |= DC_TX_INTR_ALWAYS; |
| 1985 | sc->dc_flags |= DC_REDUCED_MII_POLL; |
| 1986 | sc->dc_pmode = DC_PMODE_MII; |
| 1987 | dc_read_srom(sc, sc->dc_romwidth); |
| 1988 | break; |
| 1989 | case DC_DEVICEID_X3201: |
| 1990 | sc->dc_type = DC_TYPE_XIRCOM; |
| 1991 | sc->dc_flags |= (DC_TX_INTR_ALWAYS | DC_TX_COALESCE | |
| 1992 | DC_TX_ALIGN); |
| 1993 | /* |
| 1994 | * We don't actually need to coalesce, but we're doing |
| 1995 | * it to obtain a double word aligned buffer. |
| 1996 | * The DC_TX_COALESCE flag is required. |
| 1997 | */ |
| 1998 | sc->dc_pmode = DC_PMODE_MII; |
| 1999 | break; |
| 2000 | default: |
| 2001 | device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); |
| 2002 | break; |
| 2003 | } |
| 2004 | |
| 2005 | /* Save the cache line size. */ |
| 2006 | if (DC_IS_DAVICOM(sc)) |
| 2007 | sc->dc_cachesize = 0; |
| 2008 | else |
| 2009 | sc->dc_cachesize = pci_read_config(dev, |
| 2010 | DC_PCI_CFLT, 4) & 0xFF; |
| 2011 | |
| 2012 | /* Reset the adapter. */ |
| 2013 | dc_reset(sc); |
| 2014 | |
| 2015 | /* Take 21143 out of snooze mode */ |
| 2016 | if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { |
| 2017 | command = pci_read_config(dev, DC_PCI_CFDD, 4); |
| 2018 | command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); |
| 2019 | pci_write_config(dev, DC_PCI_CFDD, command, 4); |
| 2020 | } |
| 2021 | |
| 2022 | /* |
| 2023 | * Try to learn something about the supported media. |
| 2024 | * We know that ASIX and ADMtek and Davicom devices |
| 2025 | * will *always* be using MII media, so that's a no-brainer. |
| 2026 | * The tricky ones are the Macronix/PNIC II and the |
| 2027 | * Intel 21143. |
| 2028 | */ |
| 2029 | if (DC_IS_INTEL(sc)) |
| 2030 | dc_parse_21143_srom(sc); |
| 2031 | else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { |
| 2032 | if (sc->dc_type == DC_TYPE_98713) |
| 2033 | sc->dc_pmode = DC_PMODE_MII; |
| 2034 | else |
| 2035 | sc->dc_pmode = DC_PMODE_SYM; |
| 2036 | } else if (!sc->dc_pmode) |
| 2037 | sc->dc_pmode = DC_PMODE_MII; |
| 2038 | |
| 2039 | /* |
| 2040 | * Get station address from the EEPROM. |
| 2041 | */ |
| 2042 | switch(sc->dc_type) { |
| 2043 | case DC_TYPE_98713: |
| 2044 | case DC_TYPE_98713A: |
| 2045 | case DC_TYPE_987x5: |
| 2046 | case DC_TYPE_PNICII: |
| 2047 | dc_read_eeprom(sc, (caddr_t)&mac_offset, |
| 2048 | (DC_EE_NODEADDR_OFFSET / 2), 1, 0); |
| 2049 | dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); |
| 2050 | break; |
| 2051 | case DC_TYPE_PNIC: |
| 2052 | dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); |
| 2053 | break; |
| 2054 | case DC_TYPE_DM9102: |
| 2055 | case DC_TYPE_21143: |
| 2056 | case DC_TYPE_ASIX: |
| 2057 | dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); |
| 2058 | break; |
| 2059 | case DC_TYPE_AL981: |
| 2060 | case DC_TYPE_AN985: |
| 2061 | *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0); |
| 2062 | *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1); |
| 2063 | break; |
| 2064 | case DC_TYPE_CONEXANT: |
| 2065 | bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); |
| 2066 | break; |
| 2067 | case DC_TYPE_XIRCOM: |
| 2068 | /* The MAC comes from the CIS */ |
| 2069 | mac = pci_get_ether(dev); |
| 2070 | if (!mac) { |
| 2071 | device_printf(dev, "No station address in CIS!\n"); |
| 2072 | error = ENXIO; |
| 2073 | goto fail; |
| 2074 | } |
| 2075 | bcopy(mac, eaddr, ETHER_ADDR_LEN); |
| 2076 | break; |
| 2077 | default: |
| 2078 | dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); |
| 2079 | break; |
| 2080 | } |
| 2081 | |
| 2082 | sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, |
| 2083 | M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); |
| 2084 | |
| 2085 | if (sc->dc_ldata == NULL) { |
| 2086 | device_printf(dev, "no memory for list buffers!\n"); |
| 2087 | error = ENXIO; |
| 2088 | goto fail; |
| 2089 | } |
| 2090 | |
| 2091 | ifp->if_softc = sc; |
| 2092 | ifp->if_mtu = ETHERMTU; |
| 2093 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
| 2094 | ifp->if_ioctl = dc_ioctl; |
| 2095 | ifp->if_start = dc_start; |
| 2096 | #ifdef DEVICE_POLLING |
| 2097 | ifp->if_poll = dc_poll; |
| 2098 | #endif |
| 2099 | ifp->if_watchdog = dc_watchdog; |
| 2100 | ifp->if_init = dc_init; |
| 2101 | ifp->if_baudrate = 10000000; |
| 2102 | ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1); |
| 2103 | ifq_set_ready(&ifp->if_snd); |
| 2104 | |
| 2105 | /* |
| 2106 | * Do MII setup. If this is a 21143, check for a PHY on the |
| 2107 | * MII bus after applying any necessary fixups to twiddle the |
| 2108 | * GPIO bits. If we don't end up finding a PHY, restore the |
| 2109 | * old selection (SIA only or SIA/SYM) and attach the dcphy |
| 2110 | * driver instead. |
| 2111 | */ |
| 2112 | if (DC_IS_INTEL(sc)) { |
| 2113 | dc_apply_fixup(sc, IFM_AUTO); |
| 2114 | tmp = sc->dc_pmode; |
| 2115 | sc->dc_pmode = DC_PMODE_MII; |
| 2116 | } |
| 2117 | |
| 2118 | /* |
| 2119 | * Setup General Purpose port mode and data so the tulip can talk |
| 2120 | * to the MII. This needs to be done before mii_phy_probe so that |
| 2121 | * we can actually see them. |
| 2122 | */ |
| 2123 | if (DC_IS_XIRCOM(sc)) { |
| 2124 | CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | |
| 2125 | DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); |
| 2126 | DELAY(10); |
| 2127 | CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | |
| 2128 | DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); |
| 2129 | DELAY(10); |
| 2130 | } |
| 2131 | |
| 2132 | error = mii_phy_probe(dev, &sc->dc_miibus, |
| 2133 | dc_ifmedia_upd, dc_ifmedia_sts); |
| 2134 | |
| 2135 | if (error && DC_IS_INTEL(sc)) { |
| 2136 | sc->dc_pmode = tmp; |
| 2137 | if (sc->dc_pmode != DC_PMODE_SIA) |
| 2138 | sc->dc_pmode = DC_PMODE_SYM; |
| 2139 | sc->dc_flags |= DC_21143_NWAY; |
| 2140 | mii_phy_probe(dev, &sc->dc_miibus, |
| 2141 | dc_ifmedia_upd, dc_ifmedia_sts); |
| 2142 | /* |
| 2143 | * For non-MII cards, we need to have the 21143 |
| 2144 | * drive the LEDs. Except there are some systems |
| 2145 | * like the NEC VersaPro NoteBook PC which have no |
| 2146 | * LEDs, and twiddling these bits has adverse effects |
| 2147 | * on them. (I.e. you suddenly can't get a link.) |
| 2148 | */ |
| 2149 | if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) |
| 2150 | sc->dc_flags |= DC_TULIP_LEDS; |
| 2151 | error = 0; |
| 2152 | } |
| 2153 | |
| 2154 | if (error) { |
| 2155 | device_printf(dev, "MII without any PHY!\n"); |
| 2156 | error = ENXIO; |
| 2157 | goto fail; |
| 2158 | } |
| 2159 | |
| 2160 | /* |
| 2161 | * Call MI attach routine. |
| 2162 | */ |
| 2163 | ether_ifattach(ifp, eaddr, NULL); |
| 2164 | |
| 2165 | if (DC_IS_ADMTEK(sc)) { |
| 2166 | /* |
| 2167 | * Set automatic TX underrun recovery for the ADMtek chips |
| 2168 | */ |
| 2169 | DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); |
| 2170 | } |
| 2171 | |
| 2172 | /* |
| 2173 | * Tell the upper layer(s) we support long frames. |
| 2174 | */ |
| 2175 | ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); |
| 2176 | |
| 2177 | error = bus_setup_intr(dev, sc->dc_irq, INTR_NETSAFE, |
| 2178 | dc_intr, sc, &sc->dc_intrhand, |
| 2179 | ifp->if_serializer); |
| 2180 | if (error) { |
| 2181 | ether_ifdetach(ifp); |
| 2182 | device_printf(dev, "couldn't set up irq\n"); |
| 2183 | goto fail; |
| 2184 | } |
| 2185 | |
| 2186 | ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->dc_irq)); |
| 2187 | KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); |
| 2188 | |
| 2189 | return(0); |
| 2190 | |
| 2191 | fail: |
| 2192 | dc_detach(dev); |
| 2193 | return(error); |
| 2194 | } |
| 2195 | |
| 2196 | static int |
| 2197 | dc_detach(device_t dev) |
| 2198 | { |
| 2199 | struct dc_softc *sc = device_get_softc(dev); |
| 2200 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2201 | struct dc_mediainfo *m; |
| 2202 | |
| 2203 | if (device_is_attached(dev)) { |
| 2204 | lwkt_serialize_enter(ifp->if_serializer); |
| 2205 | dc_stop(sc); |
| 2206 | bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); |
| 2207 | lwkt_serialize_exit(ifp->if_serializer); |
| 2208 | |
| 2209 | ether_ifdetach(ifp); |
| 2210 | } |
| 2211 | |
| 2212 | if (sc->dc_miibus) |
| 2213 | device_delete_child(dev, sc->dc_miibus); |
| 2214 | bus_generic_detach(dev); |
| 2215 | |
| 2216 | if (sc->dc_irq) |
| 2217 | bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); |
| 2218 | if (sc->dc_res) |
| 2219 | bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); |
| 2220 | |
| 2221 | if (sc->dc_ldata) |
| 2222 | contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); |
| 2223 | if (sc->dc_pnic_rx_buf != NULL) |
| 2224 | kfree(sc->dc_pnic_rx_buf, M_DEVBUF); |
| 2225 | |
| 2226 | while (sc->dc_mi != NULL) { |
| 2227 | m = sc->dc_mi->dc_next; |
| 2228 | kfree(sc->dc_mi, M_DEVBUF); |
| 2229 | sc->dc_mi = m; |
| 2230 | } |
| 2231 | |
| 2232 | if (sc->dc_srom) |
| 2233 | kfree(sc->dc_srom, M_DEVBUF); |
| 2234 | |
| 2235 | return(0); |
| 2236 | } |
| 2237 | |
| 2238 | /* |
| 2239 | * Initialize the transmit descriptors. |
| 2240 | */ |
| 2241 | static int |
| 2242 | dc_list_tx_init(struct dc_softc *sc) |
| 2243 | { |
| 2244 | struct dc_chain_data *cd; |
| 2245 | struct dc_list_data *ld; |
| 2246 | int i; |
| 2247 | |
| 2248 | cd = &sc->dc_cdata; |
| 2249 | ld = sc->dc_ldata; |
| 2250 | for (i = 0; i < DC_TX_LIST_CNT; i++) { |
| 2251 | if (i == (DC_TX_LIST_CNT - 1)) { |
| 2252 | ld->dc_tx_list[i].dc_next = |
| 2253 | vtophys(&ld->dc_tx_list[0]); |
| 2254 | } else { |
| 2255 | ld->dc_tx_list[i].dc_next = |
| 2256 | vtophys(&ld->dc_tx_list[i + 1]); |
| 2257 | } |
| 2258 | cd->dc_tx_chain[i] = NULL; |
| 2259 | ld->dc_tx_list[i].dc_data = 0; |
| 2260 | ld->dc_tx_list[i].dc_ctl = 0; |
| 2261 | } |
| 2262 | |
| 2263 | cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; |
| 2264 | |
| 2265 | return(0); |
| 2266 | } |
| 2267 | |
| 2268 | |
| 2269 | /* |
| 2270 | * Initialize the RX descriptors and allocate mbufs for them. Note that |
| 2271 | * we arrange the descriptors in a closed ring, so that the last descriptor |
| 2272 | * points back to the first. |
| 2273 | */ |
| 2274 | static int |
| 2275 | dc_list_rx_init(struct dc_softc *sc) |
| 2276 | { |
| 2277 | struct dc_chain_data *cd; |
| 2278 | struct dc_list_data *ld; |
| 2279 | int i; |
| 2280 | |
| 2281 | cd = &sc->dc_cdata; |
| 2282 | ld = sc->dc_ldata; |
| 2283 | |
| 2284 | for (i = 0; i < DC_RX_LIST_CNT; i++) { |
| 2285 | if (dc_newbuf(sc, i, NULL) == ENOBUFS) |
| 2286 | return(ENOBUFS); |
| 2287 | if (i == (DC_RX_LIST_CNT - 1)) { |
| 2288 | ld->dc_rx_list[i].dc_next = |
| 2289 | vtophys(&ld->dc_rx_list[0]); |
| 2290 | } else { |
| 2291 | ld->dc_rx_list[i].dc_next = |
| 2292 | vtophys(&ld->dc_rx_list[i + 1]); |
| 2293 | } |
| 2294 | } |
| 2295 | |
| 2296 | cd->dc_rx_prod = 0; |
| 2297 | |
| 2298 | return(0); |
| 2299 | } |
| 2300 | |
| 2301 | /* |
| 2302 | * Initialize an RX descriptor and attach an MBUF cluster. |
| 2303 | */ |
| 2304 | static int |
| 2305 | dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m) |
| 2306 | { |
| 2307 | struct mbuf *m_new = NULL; |
| 2308 | struct dc_desc *c; |
| 2309 | |
| 2310 | c = &sc->dc_ldata->dc_rx_list[i]; |
| 2311 | |
| 2312 | if (m == NULL) { |
| 2313 | m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); |
| 2314 | if (m_new == NULL) |
| 2315 | return (ENOBUFS); |
| 2316 | m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; |
| 2317 | } else { |
| 2318 | m_new = m; |
| 2319 | m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; |
| 2320 | m_new->m_data = m_new->m_ext.ext_buf; |
| 2321 | } |
| 2322 | |
| 2323 | m_adj(m_new, sizeof(u_int64_t)); |
| 2324 | |
| 2325 | /* |
| 2326 | * If this is a PNIC chip, zero the buffer. This is part |
| 2327 | * of the workaround for the receive bug in the 82c168 and |
| 2328 | * 82c169 chips. |
| 2329 | */ |
| 2330 | if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) |
| 2331 | bzero((char *)mtod(m_new, char *), m_new->m_len); |
| 2332 | |
| 2333 | sc->dc_cdata.dc_rx_chain[i] = m_new; |
| 2334 | c->dc_data = vtophys(mtod(m_new, caddr_t)); |
| 2335 | c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; |
| 2336 | c->dc_status = DC_RXSTAT_OWN; |
| 2337 | |
| 2338 | return(0); |
| 2339 | } |
| 2340 | |
| 2341 | /* |
| 2342 | * Grrrrr. |
| 2343 | * The PNIC chip has a terrible bug in it that manifests itself during |
| 2344 | * periods of heavy activity. The exact mode of failure if difficult to |
| 2345 | * pinpoint: sometimes it only happens in promiscuous mode, sometimes it |
| 2346 | * will happen on slow machines. The bug is that sometimes instead of |
| 2347 | * uploading one complete frame during reception, it uploads what looks |
| 2348 | * like the entire contents of its FIFO memory. The frame we want is at |
| 2349 | * the end of the whole mess, but we never know exactly how much data has |
| 2350 | * been uploaded, so salvaging the frame is hard. |
| 2351 | * |
| 2352 | * There is only one way to do it reliably, and it's disgusting. |
| 2353 | * Here's what we know: |
| 2354 | * |
| 2355 | * - We know there will always be somewhere between one and three extra |
| 2356 | * descriptors uploaded. |
| 2357 | * |
| 2358 | * - We know the desired received frame will always be at the end of the |
| 2359 | * total data upload. |
| 2360 | * |
| 2361 | * - We know the size of the desired received frame because it will be |
| 2362 | * provided in the length field of the status word in the last descriptor. |
| 2363 | * |
| 2364 | * Here's what we do: |
| 2365 | * |
| 2366 | * - When we allocate buffers for the receive ring, we bzero() them. |
| 2367 | * This means that we know that the buffer contents should be all |
| 2368 | * zeros, except for data uploaded by the chip. |
| 2369 | * |
| 2370 | * - We also force the PNIC chip to upload frames that include the |
| 2371 | * ethernet CRC at the end. |
| 2372 | * |
| 2373 | * - We gather all of the bogus frame data into a single buffer. |
| 2374 | * |
| 2375 | * - We then position a pointer at the end of this buffer and scan |
| 2376 | * backwards until we encounter the first non-zero byte of data. |
| 2377 | * This is the end of the received frame. We know we will encounter |
| 2378 | * some data at the end of the frame because the CRC will always be |
| 2379 | * there, so even if the sender transmits a packet of all zeros, |
| 2380 | * we won't be fooled. |
| 2381 | * |
| 2382 | * - We know the size of the actual received frame, so we subtract |
| 2383 | * that value from the current pointer location. This brings us |
| 2384 | * to the start of the actual received packet. |
| 2385 | * |
| 2386 | * - We copy this into an mbuf and pass it on, along with the actual |
| 2387 | * frame length. |
| 2388 | * |
| 2389 | * The performance hit is tremendous, but it beats dropping frames all |
| 2390 | * the time. |
| 2391 | */ |
| 2392 | |
| 2393 | #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) |
| 2394 | static void |
| 2395 | dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) |
| 2396 | { |
| 2397 | struct dc_desc *cur_rx; |
| 2398 | struct dc_desc *c = NULL; |
| 2399 | struct mbuf *m = NULL; |
| 2400 | unsigned char *ptr; |
| 2401 | int i, total_len; |
| 2402 | u_int32_t rxstat = 0; |
| 2403 | |
| 2404 | i = sc->dc_pnic_rx_bug_save; |
| 2405 | cur_rx = &sc->dc_ldata->dc_rx_list[idx]; |
| 2406 | ptr = sc->dc_pnic_rx_buf; |
| 2407 | bzero(ptr, DC_RXLEN * 5); |
| 2408 | |
| 2409 | /* Copy all the bytes from the bogus buffers. */ |
| 2410 | while (1) { |
| 2411 | c = &sc->dc_ldata->dc_rx_list[i]; |
| 2412 | rxstat = c->dc_status; |
| 2413 | m = sc->dc_cdata.dc_rx_chain[i]; |
| 2414 | bcopy(mtod(m, char *), ptr, DC_RXLEN); |
| 2415 | ptr += DC_RXLEN; |
| 2416 | /* If this is the last buffer, break out. */ |
| 2417 | if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) |
| 2418 | break; |
| 2419 | dc_newbuf(sc, i, m); |
| 2420 | DC_INC(i, DC_RX_LIST_CNT); |
| 2421 | } |
| 2422 | |
| 2423 | /* Find the length of the actual receive frame. */ |
| 2424 | total_len = DC_RXBYTES(rxstat); |
| 2425 | |
| 2426 | /* Scan backwards until we hit a non-zero byte. */ |
| 2427 | while(*ptr == 0x00) |
| 2428 | ptr--; |
| 2429 | |
| 2430 | /* Round off. */ |
| 2431 | if ((uintptr_t)(ptr) & 0x3) |
| 2432 | ptr -= 1; |
| 2433 | |
| 2434 | /* Now find the start of the frame. */ |
| 2435 | ptr -= total_len; |
| 2436 | if (ptr < sc->dc_pnic_rx_buf) |
| 2437 | ptr = sc->dc_pnic_rx_buf; |
| 2438 | |
| 2439 | /* |
| 2440 | * Now copy the salvaged frame to the last mbuf and fake up |
| 2441 | * the status word to make it look like a successful |
| 2442 | * frame reception. |
| 2443 | */ |
| 2444 | dc_newbuf(sc, i, m); |
| 2445 | bcopy(ptr, mtod(m, char *), total_len); |
| 2446 | cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; |
| 2447 | |
| 2448 | return; |
| 2449 | } |
| 2450 | |
| 2451 | /* |
| 2452 | * This routine searches the RX ring for dirty descriptors in the |
| 2453 | * event that the rxeof routine falls out of sync with the chip's |
| 2454 | * current descriptor pointer. This may happen sometimes as a result |
| 2455 | * of a "no RX buffer available" condition that happens when the chip |
| 2456 | * consumes all of the RX buffers before the driver has a chance to |
| 2457 | * process the RX ring. This routine may need to be called more than |
| 2458 | * once to bring the driver back in sync with the chip, however we |
| 2459 | * should still be getting RX DONE interrupts to drive the search |
| 2460 | * for new packets in the RX ring, so we should catch up eventually. |
| 2461 | */ |
| 2462 | static int |
| 2463 | dc_rx_resync(struct dc_softc *sc) |
| 2464 | { |
| 2465 | int i, pos; |
| 2466 | struct dc_desc *cur_rx; |
| 2467 | |
| 2468 | pos = sc->dc_cdata.dc_rx_prod; |
| 2469 | |
| 2470 | for (i = 0; i < DC_RX_LIST_CNT; i++) { |
| 2471 | cur_rx = &sc->dc_ldata->dc_rx_list[pos]; |
| 2472 | if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) |
| 2473 | break; |
| 2474 | DC_INC(pos, DC_RX_LIST_CNT); |
| 2475 | } |
| 2476 | |
| 2477 | /* If the ring really is empty, then just return. */ |
| 2478 | if (i == DC_RX_LIST_CNT) |
| 2479 | return(0); |
| 2480 | |
| 2481 | /* We've fallen behing the chip: catch it. */ |
| 2482 | sc->dc_cdata.dc_rx_prod = pos; |
| 2483 | |
| 2484 | return(EAGAIN); |
| 2485 | } |
| 2486 | |
| 2487 | /* |
| 2488 | * A frame has been uploaded: pass the resulting mbuf chain up to |
| 2489 | * the higher level protocols. |
| 2490 | */ |
| 2491 | static void |
| 2492 | dc_rxeof(struct dc_softc *sc) |
| 2493 | { |
| 2494 | struct mbuf *m; |
| 2495 | struct ifnet *ifp; |
| 2496 | struct dc_desc *cur_rx; |
| 2497 | int i, total_len = 0; |
| 2498 | u_int32_t rxstat; |
| 2499 | |
| 2500 | ifp = &sc->arpcom.ac_if; |
| 2501 | i = sc->dc_cdata.dc_rx_prod; |
| 2502 | |
| 2503 | while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { |
| 2504 | |
| 2505 | #ifdef DEVICE_POLLING |
| 2506 | if (ifp->if_flags & IFF_POLLING) { |
| 2507 | if (sc->rxcycles <= 0) |
| 2508 | break; |
| 2509 | sc->rxcycles--; |
| 2510 | } |
| 2511 | #endif /* DEVICE_POLLING */ |
| 2512 | cur_rx = &sc->dc_ldata->dc_rx_list[i]; |
| 2513 | rxstat = cur_rx->dc_status; |
| 2514 | m = sc->dc_cdata.dc_rx_chain[i]; |
| 2515 | total_len = DC_RXBYTES(rxstat); |
| 2516 | |
| 2517 | if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { |
| 2518 | if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { |
| 2519 | if (rxstat & DC_RXSTAT_FIRSTFRAG) |
| 2520 | sc->dc_pnic_rx_bug_save = i; |
| 2521 | if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { |
| 2522 | DC_INC(i, DC_RX_LIST_CNT); |
| 2523 | continue; |
| 2524 | } |
| 2525 | dc_pnic_rx_bug_war(sc, i); |
| 2526 | rxstat = cur_rx->dc_status; |
| 2527 | total_len = DC_RXBYTES(rxstat); |
| 2528 | } |
| 2529 | } |
| 2530 | |
| 2531 | sc->dc_cdata.dc_rx_chain[i] = NULL; |
| 2532 | |
| 2533 | /* |
| 2534 | * If an error occurs, update stats, clear the |
| 2535 | * status word and leave the mbuf cluster in place: |
| 2536 | * it should simply get re-used next time this descriptor |
| 2537 | * comes up in the ring. However, don't report long |
| 2538 | * frames as errors since they could be vlans |
| 2539 | */ |
| 2540 | if ((rxstat & DC_RXSTAT_RXERR)){ |
| 2541 | if (!(rxstat & DC_RXSTAT_GIANT) || |
| 2542 | (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | |
| 2543 | DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | |
| 2544 | DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { |
| 2545 | ifp->if_ierrors++; |
| 2546 | if (rxstat & DC_RXSTAT_COLLSEEN) |
| 2547 | ifp->if_collisions++; |
| 2548 | dc_newbuf(sc, i, m); |
| 2549 | if (rxstat & DC_RXSTAT_CRCERR) { |
| 2550 | DC_INC(i, DC_RX_LIST_CNT); |
| 2551 | continue; |
| 2552 | } else { |
| 2553 | dc_init(sc); |
| 2554 | return; |
| 2555 | } |
| 2556 | } |
| 2557 | } |
| 2558 | |
| 2559 | /* No errors; receive the packet. */ |
| 2560 | total_len -= ETHER_CRC_LEN; |
| 2561 | |
| 2562 | #ifdef __i386__ |
| 2563 | /* |
| 2564 | * On the x86 we do not have alignment problems, so try to |
| 2565 | * allocate a new buffer for the receive ring, and pass up |
| 2566 | * the one where the packet is already, saving the expensive |
| 2567 | * copy done in m_devget(). |
| 2568 | * If we are on an architecture with alignment problems, or |
| 2569 | * if the allocation fails, then use m_devget and leave the |
| 2570 | * existing buffer in the receive ring. |
| 2571 | */ |
| 2572 | if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { |
| 2573 | m->m_pkthdr.rcvif = ifp; |
| 2574 | m->m_pkthdr.len = m->m_len = total_len; |
| 2575 | DC_INC(i, DC_RX_LIST_CNT); |
| 2576 | } else |
| 2577 | #endif |
| 2578 | { |
| 2579 | struct mbuf *m0; |
| 2580 | |
| 2581 | m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, |
| 2582 | total_len + ETHER_ALIGN, 0, ifp, NULL); |
| 2583 | dc_newbuf(sc, i, m); |
| 2584 | DC_INC(i, DC_RX_LIST_CNT); |
| 2585 | if (m0 == NULL) { |
| 2586 | ifp->if_ierrors++; |
| 2587 | continue; |
| 2588 | } |
| 2589 | m_adj(m0, ETHER_ALIGN); |
| 2590 | m = m0; |
| 2591 | } |
| 2592 | |
| 2593 | ifp->if_ipackets++; |
| 2594 | ifp->if_input(ifp, m); |
| 2595 | } |
| 2596 | |
| 2597 | sc->dc_cdata.dc_rx_prod = i; |
| 2598 | } |
| 2599 | |
| 2600 | /* |
| 2601 | * A frame was downloaded to the chip. It's safe for us to clean up |
| 2602 | * the list buffers. |
| 2603 | */ |
| 2604 | |
| 2605 | static void |
| 2606 | dc_txeof(struct dc_softc *sc) |
| 2607 | { |
| 2608 | struct dc_desc *cur_tx = NULL; |
| 2609 | struct ifnet *ifp; |
| 2610 | int idx; |
| 2611 | |
| 2612 | ifp = &sc->arpcom.ac_if; |
| 2613 | |
| 2614 | /* |
| 2615 | * Go through our tx list and free mbufs for those |
| 2616 | * frames that have been transmitted. |
| 2617 | */ |
| 2618 | idx = sc->dc_cdata.dc_tx_cons; |
| 2619 | while(idx != sc->dc_cdata.dc_tx_prod) { |
| 2620 | u_int32_t txstat; |
| 2621 | |
| 2622 | cur_tx = &sc->dc_ldata->dc_tx_list[idx]; |
| 2623 | txstat = cur_tx->dc_status; |
| 2624 | |
| 2625 | if (txstat & DC_TXSTAT_OWN) |
| 2626 | break; |
| 2627 | |
| 2628 | if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || |
| 2629 | cur_tx->dc_ctl & DC_TXCTL_SETUP) { |
| 2630 | if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { |
| 2631 | /* |
| 2632 | * Yes, the PNIC is so brain damaged |
| 2633 | * that it will sometimes generate a TX |
| 2634 | * underrun error while DMAing the RX |
| 2635 | * filter setup frame. If we detect this, |
| 2636 | * we have to send the setup frame again, |
| 2637 | * or else the filter won't be programmed |
| 2638 | * correctly. |
| 2639 | */ |
| 2640 | if (DC_IS_PNIC(sc)) { |
| 2641 | if (txstat & DC_TXSTAT_ERRSUM) |
| 2642 | dc_setfilt(sc); |
| 2643 | } |
| 2644 | sc->dc_cdata.dc_tx_chain[idx] = NULL; |
| 2645 | } |
| 2646 | sc->dc_cdata.dc_tx_cnt--; |
| 2647 | DC_INC(idx, DC_TX_LIST_CNT); |
| 2648 | continue; |
| 2649 | } |
| 2650 | |
| 2651 | if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { |
| 2652 | /* |
| 2653 | * XXX: Why does my Xircom taunt me so? |
| 2654 | * For some reason Conexant chips like |
| 2655 | * setting the CARRLOST flag even when |
| 2656 | * the carrier is there. In CURRENT we |
| 2657 | * have the same problem for Xircom |
| 2658 | * cards ! |
| 2659 | */ |
| 2660 | if (/*sc->dc_type == DC_TYPE_21143 &&*/ |
| 2661 | sc->dc_pmode == DC_PMODE_MII && |
| 2662 | ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| |
| 2663 | DC_TXSTAT_NOCARRIER))) |
| 2664 | txstat &= ~DC_TXSTAT_ERRSUM; |
| 2665 | } else { |
| 2666 | if (/*sc->dc_type == DC_TYPE_21143 &&*/ |
| 2667 | sc->dc_pmode == DC_PMODE_MII && |
| 2668 | ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| |
| 2669 | DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) |
| 2670 | txstat &= ~DC_TXSTAT_ERRSUM; |
| 2671 | } |
| 2672 | |
| 2673 | if (txstat & DC_TXSTAT_ERRSUM) { |
| 2674 | ifp->if_oerrors++; |
| 2675 | if (txstat & DC_TXSTAT_EXCESSCOLL) |
| 2676 | ifp->if_collisions++; |
| 2677 | if (txstat & DC_TXSTAT_LATECOLL) |
| 2678 | ifp->if_collisions++; |
| 2679 | if (!(txstat & DC_TXSTAT_UNDERRUN)) { |
| 2680 | dc_init(sc); |
| 2681 | return; |
| 2682 | } |
| 2683 | } |
| 2684 | |
| 2685 | ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; |
| 2686 | |
| 2687 | ifp->if_opackets++; |
| 2688 | if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { |
| 2689 | m_freem(sc->dc_cdata.dc_tx_chain[idx]); |
| 2690 | sc->dc_cdata.dc_tx_chain[idx] = NULL; |
| 2691 | } |
| 2692 | |
| 2693 | sc->dc_cdata.dc_tx_cnt--; |
| 2694 | DC_INC(idx, DC_TX_LIST_CNT); |
| 2695 | } |
| 2696 | |
| 2697 | if (idx != sc->dc_cdata.dc_tx_cons) { |
| 2698 | /* some buffers have been freed */ |
| 2699 | sc->dc_cdata.dc_tx_cons = idx; |
| 2700 | ifp->if_flags &= ~IFF_OACTIVE; |
| 2701 | } |
| 2702 | ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; |
| 2703 | |
| 2704 | return; |
| 2705 | } |
| 2706 | |
| 2707 | static void |
| 2708 | dc_tick(void *xsc) |
| 2709 | { |
| 2710 | struct dc_softc *sc = xsc; |
| 2711 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2712 | struct mii_data *mii; |
| 2713 | u_int32_t r; |
| 2714 | |
| 2715 | lwkt_serialize_enter(ifp->if_serializer); |
| 2716 | |
| 2717 | mii = device_get_softc(sc->dc_miibus); |
| 2718 | |
| 2719 | if (sc->dc_flags & DC_REDUCED_MII_POLL) { |
| 2720 | if (sc->dc_flags & DC_21143_NWAY) { |
| 2721 | r = CSR_READ_4(sc, DC_10BTSTAT); |
| 2722 | if (IFM_SUBTYPE(mii->mii_media_active) == |
| 2723 | IFM_100_TX && (r & DC_TSTAT_LS100)) { |
| 2724 | sc->dc_link = 0; |
| 2725 | mii_mediachg(mii); |
| 2726 | } |
| 2727 | if (IFM_SUBTYPE(mii->mii_media_active) == |
| 2728 | IFM_10_T && (r & DC_TSTAT_LS10)) { |
| 2729 | sc->dc_link = 0; |
| 2730 | mii_mediachg(mii); |
| 2731 | } |
| 2732 | if (sc->dc_link == 0) |
| 2733 | mii_tick(mii); |
| 2734 | } else { |
| 2735 | r = CSR_READ_4(sc, DC_ISR); |
| 2736 | if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && |
| 2737 | sc->dc_cdata.dc_tx_cnt == 0) { |
| 2738 | mii_tick(mii); |
| 2739 | if (!(mii->mii_media_status & IFM_ACTIVE)) |
| 2740 | sc->dc_link = 0; |
| 2741 | } |
| 2742 | } |
| 2743 | } else { |
| 2744 | mii_tick(mii); |
| 2745 | } |
| 2746 | |
| 2747 | /* |
| 2748 | * When the init routine completes, we expect to be able to send |
| 2749 | * packets right away, and in fact the network code will send a |
| 2750 | * gratuitous ARP the moment the init routine marks the interface |
| 2751 | * as running. However, even though the MAC may have been initialized, |
| 2752 | * there may be a delay of a few seconds before the PHY completes |
| 2753 | * autonegotiation and the link is brought up. Any transmissions |
| 2754 | * made during that delay will be lost. Dealing with this is tricky: |
| 2755 | * we can't just pause in the init routine while waiting for the |
| 2756 | * PHY to come ready since that would bring the whole system to |
| 2757 | * a screeching halt for several seconds. |
| 2758 | * |
| 2759 | * What we do here is prevent the TX start routine from sending |
| 2760 | * any packets until a link has been established. After the |
| 2761 | * interface has been initialized, the tick routine will poll |
| 2762 | * the state of the PHY until the IFM_ACTIVE flag is set. Until |
| 2763 | * that time, packets will stay in the send queue, and once the |
| 2764 | * link comes up, they will be flushed out to the wire. |
| 2765 | */ |
| 2766 | if (!sc->dc_link) { |
| 2767 | mii_pollstat(mii); |
| 2768 | if (mii->mii_media_status & IFM_ACTIVE && |
| 2769 | IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { |
| 2770 | sc->dc_link++; |
| 2771 | if (!ifq_is_empty(&ifp->if_snd)) |
| 2772 | if_devstart(ifp); |
| 2773 | } |
| 2774 | } |
| 2775 | |
| 2776 | if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) |
| 2777 | callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc); |
| 2778 | else |
| 2779 | callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); |
| 2780 | |
| 2781 | lwkt_serialize_exit(ifp->if_serializer); |
| 2782 | } |
| 2783 | |
| 2784 | /* |
| 2785 | * A transmit underrun has occurred. Back off the transmit threshold, |
| 2786 | * or switch to store and forward mode if we have to. |
| 2787 | */ |
| 2788 | static void |
| 2789 | dc_tx_underrun(struct dc_softc *sc) |
| 2790 | { |
| 2791 | u_int32_t isr; |
| 2792 | int i; |
| 2793 | |
| 2794 | if (DC_IS_DAVICOM(sc)) |
| 2795 | dc_init(sc); |
| 2796 | |
| 2797 | if (DC_IS_INTEL(sc)) { |
| 2798 | /* |
| 2799 | * The real 21143 requires that the transmitter be idle |
| 2800 | * in order to change the transmit threshold or store |
| 2801 | * and forward state. |
| 2802 | */ |
| 2803 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); |
| 2804 | |
| 2805 | for (i = 0; i < DC_TIMEOUT; i++) { |
| 2806 | isr = CSR_READ_4(sc, DC_ISR); |
| 2807 | if (isr & DC_ISR_TX_IDLE) |
| 2808 | break; |
| 2809 | DELAY(10); |
| 2810 | } |
| 2811 | if (i == DC_TIMEOUT) { |
| 2812 | if_printf(&sc->arpcom.ac_if, |
| 2813 | "failed to force tx to idle state\n"); |
| 2814 | dc_init(sc); |
| 2815 | } |
| 2816 | } |
| 2817 | |
| 2818 | if_printf(&sc->arpcom.ac_if, "TX underrun -- "); |
| 2819 | sc->dc_txthresh += DC_TXTHRESH_INC; |
| 2820 | if (sc->dc_txthresh > DC_TXTHRESH_MAX) { |
| 2821 | kprintf("using store and forward mode\n"); |
| 2822 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); |
| 2823 | } else { |
| 2824 | kprintf("increasing TX threshold\n"); |
| 2825 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); |
| 2826 | DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); |
| 2827 | } |
| 2828 | |
| 2829 | if (DC_IS_INTEL(sc)) |
| 2830 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); |
| 2831 | |
| 2832 | return; |
| 2833 | } |
| 2834 | |
| 2835 | #ifdef DEVICE_POLLING |
| 2836 | |
| 2837 | static void |
| 2838 | dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) |
| 2839 | { |
| 2840 | struct dc_softc *sc = ifp->if_softc; |
| 2841 | u_int32_t status; |
| 2842 | |
| 2843 | switch(cmd) { |
| 2844 | case POLL_REGISTER: |
| 2845 | /* Disable interrupts */ |
| 2846 | CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
| 2847 | break; |
| 2848 | case POLL_DEREGISTER: |
| 2849 | /* Re-enable interrupts. */ |
| 2850 | CSR_WRITE_4(sc, DC_IMR, DC_INTRS); |
| 2851 | break; |
| 2852 | case POLL_ONLY: |
| 2853 | sc->rxcycles = count; |
| 2854 | dc_rxeof(sc); |
| 2855 | dc_txeof(sc); |
| 2856 | if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) |
| 2857 | if_devstart(ifp); |
| 2858 | break; |
| 2859 | case POLL_AND_CHECK_STATUS: |
| 2860 | sc->rxcycles = count; |
| 2861 | dc_rxeof(sc); |
| 2862 | dc_txeof(sc); |
| 2863 | if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) |
| 2864 | if_devstart(ifp); |
| 2865 | status = CSR_READ_4(sc, DC_ISR); |
| 2866 | status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| |
| 2867 | DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| |
| 2868 | DC_ISR_BUS_ERR); |
| 2869 | if (!status) |
| 2870 | break; |
| 2871 | /* ack what we have */ |
| 2872 | CSR_WRITE_4(sc, DC_ISR, status); |
| 2873 | |
| 2874 | if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { |
| 2875 | u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); |
| 2876 | ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); |
| 2877 | |
| 2878 | if (dc_rx_resync(sc)) |
| 2879 | dc_rxeof(sc); |
| 2880 | } |
| 2881 | /* restart transmit unit if necessary */ |
| 2882 | if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) |
| 2883 | CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); |
| 2884 | |
| 2885 | if (status & DC_ISR_TX_UNDERRUN) |
| 2886 | dc_tx_underrun(sc); |
| 2887 | |
| 2888 | if (status & DC_ISR_BUS_ERR) { |
| 2889 | if_printf(ifp, "dc_poll: bus error\n"); |
| 2890 | dc_reset(sc); |
| 2891 | dc_init(sc); |
| 2892 | } |
| 2893 | break; |
| 2894 | } |
| 2895 | } |
| 2896 | #endif /* DEVICE_POLLING */ |
| 2897 | |
| 2898 | static void |
| 2899 | dc_intr(void *arg) |
| 2900 | { |
| 2901 | struct dc_softc *sc; |
| 2902 | struct ifnet *ifp; |
| 2903 | u_int32_t status; |
| 2904 | |
| 2905 | sc = arg; |
| 2906 | |
| 2907 | if (sc->suspended) { |
| 2908 | return; |
| 2909 | } |
| 2910 | |
| 2911 | ifp = &sc->arpcom.ac_if; |
| 2912 | |
| 2913 | if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) |
| 2914 | return ; |
| 2915 | |
| 2916 | /* Suppress unwanted interrupts */ |
| 2917 | if ((ifp->if_flags & IFF_RUNNING) == 0) { |
| 2918 | if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) |
| 2919 | dc_stop(sc); |
| 2920 | return; |
| 2921 | } |
| 2922 | |
| 2923 | /* Disable interrupts. */ |
| 2924 | CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
| 2925 | |
| 2926 | while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && |
| 2927 | status != 0xFFFFFFFF) { |
| 2928 | |
| 2929 | CSR_WRITE_4(sc, DC_ISR, status); |
| 2930 | |
| 2931 | if (status & DC_ISR_RX_OK) { |
| 2932 | int curpkts; |
| 2933 | curpkts = ifp->if_ipackets; |
| 2934 | dc_rxeof(sc); |
| 2935 | if (curpkts == ifp->if_ipackets) { |
| 2936 | while(dc_rx_resync(sc)) |
| 2937 | dc_rxeof(sc); |
| 2938 | } |
| 2939 | } |
| 2940 | |
| 2941 | if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) |
| 2942 | dc_txeof(sc); |
| 2943 | |
| 2944 | if (status & DC_ISR_TX_IDLE) { |
| 2945 | dc_txeof(sc); |
| 2946 | if (sc->dc_cdata.dc_tx_cnt) { |
| 2947 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); |
| 2948 | CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); |
| 2949 | } |
| 2950 | } |
| 2951 | |
| 2952 | if (status & DC_ISR_TX_UNDERRUN) |
| 2953 | dc_tx_underrun(sc); |
| 2954 | |
| 2955 | if ((status & DC_ISR_RX_WATDOGTIMEO) |
| 2956 | || (status & DC_ISR_RX_NOBUF)) { |
| 2957 | int curpkts; |
| 2958 | curpkts = ifp->if_ipackets; |
| 2959 | dc_rxeof(sc); |
| 2960 | if (curpkts == ifp->if_ipackets) { |
| 2961 | while(dc_rx_resync(sc)) |
| 2962 | dc_rxeof(sc); |
| 2963 | } |
| 2964 | } |
| 2965 | |
| 2966 | if (status & DC_ISR_BUS_ERR) { |
| 2967 | dc_reset(sc); |
| 2968 | dc_init(sc); |
| 2969 | } |
| 2970 | } |
| 2971 | |
| 2972 | /* Re-enable interrupts. */ |
| 2973 | CSR_WRITE_4(sc, DC_IMR, DC_INTRS); |
| 2974 | |
| 2975 | if (!ifq_is_empty(&ifp->if_snd)) |
| 2976 | if_devstart(ifp); |
| 2977 | } |
| 2978 | |
| 2979 | /* |
| 2980 | * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data |
| 2981 | * pointers to the fragment pointers. |
| 2982 | */ |
| 2983 | static int |
| 2984 | dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx) |
| 2985 | { |
| 2986 | struct dc_desc *f = NULL; |
| 2987 | struct mbuf *m; |
| 2988 | int frag, cur, cnt = 0; |
| 2989 | |
| 2990 | /* |
| 2991 | * Start packing the mbufs in this chain into |
| 2992 | * the fragment pointers. Stop when we run out |
| 2993 | * of fragments or hit the end of the mbuf chain. |
| 2994 | */ |
| 2995 | m = m_head; |
| 2996 | cur = frag = *txidx; |
| 2997 | |
| 2998 | for (m = m_head; m != NULL; m = m->m_next) { |
| 2999 | if (m->m_len != 0) { |
| 3000 | if (sc->dc_flags & DC_TX_ADMTEK_WAR) { |
| 3001 | if (*txidx != sc->dc_cdata.dc_tx_prod && |
| 3002 | frag == (DC_TX_LIST_CNT - 1)) |
| 3003 | return(ENOBUFS); |
| 3004 | } |
| 3005 | if ((DC_TX_LIST_CNT - |
| 3006 | (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) |
| 3007 | return(ENOBUFS); |
| 3008 | |
| 3009 | f = &sc->dc_ldata->dc_tx_list[frag]; |
| 3010 | f->dc_ctl = DC_TXCTL_TLINK | m->m_len; |
| 3011 | if (cnt == 0) { |
| 3012 | f->dc_status = 0; |
| 3013 | f->dc_ctl |= DC_TXCTL_FIRSTFRAG; |
| 3014 | } else |
| 3015 | f->dc_status = DC_TXSTAT_OWN; |
| 3016 | f->dc_data = vtophys(mtod(m, vm_offset_t)); |
| 3017 | cur = frag; |
| 3018 | DC_INC(frag, DC_TX_LIST_CNT); |
| 3019 | cnt++; |
| 3020 | } |
| 3021 | } |
| 3022 | |
| 3023 | if (m != NULL) |
| 3024 | return(ENOBUFS); |
| 3025 | |
| 3026 | sc->dc_cdata.dc_tx_cnt += cnt; |
| 3027 | sc->dc_cdata.dc_tx_chain[cur] = m_head; |
| 3028 | sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; |
| 3029 | if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) |
| 3030 | sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; |
| 3031 | if (sc->dc_flags & DC_TX_INTR_ALWAYS) |
| 3032 | sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; |
| 3033 | if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) |
| 3034 | sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; |
| 3035 | sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; |
| 3036 | *txidx = frag; |
| 3037 | |
| 3038 | return(0); |
| 3039 | } |
| 3040 | |
| 3041 | /* |
| 3042 | * Main transmit routine. To avoid having to do mbuf copies, we put pointers |
| 3043 | * to the mbuf data regions directly in the transmit lists. We also save a |
| 3044 | * copy of the pointers since the transmit list fragment pointers are |
| 3045 | * physical addresses. |
| 3046 | */ |
| 3047 | |
| 3048 | static void |
| 3049 | dc_start(struct ifnet *ifp) |
| 3050 | { |
| 3051 | struct dc_softc *sc; |
| 3052 | struct mbuf *m_head, *m_defragged; |
| 3053 | int idx, need_trans; |
| 3054 | |
| 3055 | sc = ifp->if_softc; |
| 3056 | |
| 3057 | if (!sc->dc_link) { |
| 3058 | ifq_purge(&ifp->if_snd); |
| 3059 | return; |
| 3060 | } |
| 3061 | |
| 3062 | if (ifp->if_flags & IFF_OACTIVE) |
| 3063 | return; |
| 3064 | |
| 3065 | idx = sc->dc_cdata.dc_tx_prod; |
| 3066 | |
| 3067 | need_trans = 0; |
| 3068 | while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { |
| 3069 | m_defragged = NULL; |
| 3070 | m_head = ifq_dequeue(&ifp->if_snd, NULL); |
| 3071 | if (m_head == NULL) |
| 3072 | break; |
| 3073 | |
| 3074 | if ((sc->dc_flags & DC_TX_COALESCE) && |
| 3075 | (m_head->m_next != NULL || (sc->dc_flags & DC_TX_ALIGN))) { |
| 3076 | /* |
| 3077 | * Check first if coalescing allows us to queue |
| 3078 | * the packet. We don't want to loose it if |
| 3079 | * the TX queue is full. |
| 3080 | */ |
| 3081 | if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && |
| 3082 | idx != sc->dc_cdata.dc_tx_prod && |
| 3083 | idx == (DC_TX_LIST_CNT - 1)) { |
| 3084 | ifp->if_flags |= IFF_OACTIVE; |
| 3085 | ifq_prepend(&ifp->if_snd, m_head); |
| 3086 | break; |
| 3087 | } |
| 3088 | if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) { |
| 3089 | ifp->if_flags |= IFF_OACTIVE; |
| 3090 | ifq_prepend(&ifp->if_snd, m_head); |
| 3091 | break; |
| 3092 | } |
| 3093 | |
| 3094 | /* only coalesce if have >1 mbufs */ |
| 3095 | m_defragged = m_defrag(m_head, MB_DONTWAIT); |
| 3096 | if (m_defragged == NULL) { |
| 3097 | ifp->if_flags |= IFF_OACTIVE; |
| 3098 | ifq_prepend(&ifp->if_snd, m_head); |
| 3099 | break; |
| 3100 | } |
| 3101 | m_head = m_defragged; |
| 3102 | } |
| 3103 | |
| 3104 | if (dc_encap(sc, m_head, &idx)) { |
| 3105 | if (m_defragged) { |
| 3106 | /* |
| 3107 | * Throw away the original packet if the |
| 3108 | * defragged packet could not be encapsulated, |
| 3109 | * as well as the defragged packet. |
| 3110 | */ |
| 3111 | m_freem(m_head); |
| 3112 | } else { |
| 3113 | ifq_prepend(&ifp->if_snd, m_head); |
| 3114 | } |
| 3115 | ifp->if_flags |= IFF_OACTIVE; |
| 3116 | break; |
| 3117 | } |
| 3118 | |
| 3119 | need_trans = 1; |
| 3120 | |
| 3121 | /* |
| 3122 | * If there's a BPF listener, bounce a copy of this frame |
| 3123 | * to him. |
| 3124 | */ |
| 3125 | BPF_MTAP(ifp, m_head); |
| 3126 | |
| 3127 | if (sc->dc_flags & DC_TX_ONE) { |
| 3128 | ifp->if_flags |= IFF_OACTIVE; |
| 3129 | break; |
| 3130 | } |
| 3131 | } |
| 3132 | |
| 3133 | if (!need_trans) |
| 3134 | return; |
| 3135 | |
| 3136 | /* Transmit */ |
| 3137 | sc->dc_cdata.dc_tx_prod = idx; |
| 3138 | if (!(sc->dc_flags & DC_TX_POLL)) |
| 3139 | CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); |
| 3140 | |
| 3141 | /* |
| 3142 | * Set a timeout in case the chip goes out to lunch. |
| 3143 | */ |
| 3144 | ifp->if_timer = 5; |
| 3145 | } |
| 3146 | |
| 3147 | static void |
| 3148 | dc_init(void *xsc) |
| 3149 | { |
| 3150 | struct dc_softc *sc = xsc; |
| 3151 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 3152 | struct mii_data *mii; |
| 3153 | |
| 3154 | mii = device_get_softc(sc->dc_miibus); |
| 3155 | |
| 3156 | /* |
| 3157 | * Cancel pending I/O and free all RX/TX buffers. |
| 3158 | */ |
| 3159 | dc_stop(sc); |
| 3160 | dc_reset(sc); |
| 3161 | |
| 3162 | /* |
| 3163 | * Set cache alignment and burst length. |
| 3164 | */ |
| 3165 | if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) |
| 3166 | CSR_WRITE_4(sc, DC_BUSCTL, 0); |
| 3167 | else |
| 3168 | CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); |
| 3169 | /* |
| 3170 | * Evenly share the bus between receive and transmit process. |
| 3171 | */ |
| 3172 | if (DC_IS_INTEL(sc)) |
| 3173 | DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); |
| 3174 | if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { |
| 3175 | DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); |
| 3176 | } else { |
| 3177 | DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); |
| 3178 | } |
| 3179 | if (sc->dc_flags & DC_TX_POLL) |
| 3180 | DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); |
| 3181 | switch(sc->dc_cachesize) { |
| 3182 | case 32: |
| 3183 | DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); |
| 3184 | break; |
| 3185 | case 16: |
| 3186 | DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); |
| 3187 | break; |
| 3188 | case 8: |
| 3189 | DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); |
| 3190 | break; |
| 3191 | case 0: |
| 3192 | default: |
| 3193 | DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); |
| 3194 | break; |
| 3195 | } |
| 3196 | |
| 3197 | if (sc->dc_flags & DC_TX_STORENFWD) |
| 3198 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); |
| 3199 | else { |
| 3200 | if (sc->dc_txthresh > DC_TXTHRESH_MAX) { |
| 3201 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); |
| 3202 | } else { |
| 3203 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); |
| 3204 | DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); |
| 3205 | } |
| 3206 | } |
| 3207 | |
| 3208 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); |
| 3209 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); |
| 3210 | |
| 3211 | if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { |
| 3212 | /* |
| 3213 | * The app notes for the 98713 and 98715A say that |
| 3214 | * in order to have the chips operate properly, a magic |
| 3215 | * number must be written to CSR16. Macronix does not |
| 3216 | * document the meaning of these bits so there's no way |
| 3217 | * to know exactly what they do. The 98713 has a magic |
| 3218 | * number all its own; the rest all use a different one. |
| 3219 | */ |
| 3220 | DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); |
| 3221 | if (sc->dc_type == DC_TYPE_98713) |
| 3222 | DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); |
| 3223 | else |
| 3224 | DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); |
| 3225 | } |
| 3226 | |
| 3227 | if (DC_IS_XIRCOM(sc)) { |
| 3228 | /* |
| 3229 | * Setup General Purpose Port mode and data so the tulip |
| 3230 | * can talk to the MII. |
| 3231 | */ |
| 3232 | CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | |
| 3233 | DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); |
| 3234 | DELAY(10); |
| 3235 | CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | |
| 3236 | DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); |
| 3237 | DELAY(10); |
| 3238 | } |
| 3239 | |
| 3240 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); |
| 3241 | DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); |
| 3242 | |
| 3243 | /* Init circular RX list. */ |
| 3244 | if (dc_list_rx_init(sc) == ENOBUFS) { |
| 3245 | if_printf(ifp, "initialization failed: no " |
| 3246 | "memory for rx buffers\n"); |
| 3247 | dc_stop(sc); |
| 3248 | return; |
| 3249 | } |
| 3250 | |
| 3251 | /* |
| 3252 | * Init tx descriptors. |
| 3253 | */ |
| 3254 | dc_list_tx_init(sc); |
| 3255 | |
| 3256 | /* |
| 3257 | * Load the address of the RX list. |
| 3258 | */ |
| 3259 | CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); |
| 3260 | CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); |
| 3261 | |
| 3262 | /* |
| 3263 | * Enable interrupts. |
| 3264 | */ |
| 3265 | #ifdef DEVICE_POLLING |
| 3266 | /* |
| 3267 | * ... but only if we are not polling, and make sure they are off in |
| 3268 | * the case of polling. Some cards (e.g. fxp) turn interrupts on |
| 3269 | * after a reset. |
| 3270 | */ |
| 3271 | if (ifp->if_flags & IFF_POLLING) |
| 3272 | CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
| 3273 | else |
| 3274 | #endif |
| 3275 | CSR_WRITE_4(sc, DC_IMR, DC_INTRS); |
| 3276 | CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); |
| 3277 | |
| 3278 | /* Enable transmitter. */ |
| 3279 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); |
| 3280 | |
| 3281 | /* |
| 3282 | * If this is an Intel 21143 and we're not using the |
| 3283 | * MII port, program the LED control pins so we get |
| 3284 | * link and activity indications. |
| 3285 | */ |
| 3286 | if (sc->dc_flags & DC_TULIP_LEDS) { |
| 3287 | CSR_WRITE_4(sc, DC_WATCHDOG, |
| 3288 | DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); |
| 3289 | CSR_WRITE_4(sc, DC_WATCHDOG, 0); |
| 3290 | } |
| 3291 | |
| 3292 | /* |
| 3293 | * Set IFF_RUNNING here to keep the assertion in dc_setfilt() |
| 3294 | * working. |
| 3295 | */ |
| 3296 | ifp->if_flags |= IFF_RUNNING; |
| 3297 | ifp->if_flags &= ~IFF_OACTIVE; |
| 3298 | |
| 3299 | /* |
| 3300 | * Load the RX/multicast filter. We do this sort of late |
| 3301 | * because the filter programming scheme on the 21143 and |
| 3302 | * some clones requires DMAing a setup frame via the TX |
| 3303 | * engine, and we need the transmitter enabled for that. |
| 3304 | */ |
| 3305 | dc_setfilt(sc); |
| 3306 | |
| 3307 | /* Enable receiver. */ |
| 3308 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); |
| 3309 | CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); |
| 3310 | |
| 3311 | mii_mediachg(mii); |
| 3312 | dc_setcfg(sc, sc->dc_if_media); |
| 3313 | |
| 3314 | /* Don't start the ticker if this is a homePNA link. */ |
| 3315 | if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) |
| 3316 | sc->dc_link = 1; |
| 3317 | else { |
| 3318 | if (sc->dc_flags & DC_21143_NWAY) |
| 3319 | callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc); |
| 3320 | else |
| 3321 | callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); |
| 3322 | } |
| 3323 | } |
| 3324 | |
| 3325 | /* |
| 3326 | * Set media options. |
| 3327 | */ |
| 3328 | static int |
| 3329 | dc_ifmedia_upd(struct ifnet *ifp) |
| 3330 | { |
| 3331 | struct dc_softc *sc; |
| 3332 | struct mii_data *mii; |
| 3333 | struct ifmedia *ifm; |
| 3334 | |
| 3335 | sc = ifp->if_softc; |
| 3336 | mii = device_get_softc(sc->dc_miibus); |
| 3337 | mii_mediachg(mii); |
| 3338 | ifm = &mii->mii_media; |
| 3339 | |
| 3340 | if (DC_IS_DAVICOM(sc) && |
| 3341 | IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) |
| 3342 | dc_setcfg(sc, ifm->ifm_media); |
| 3343 | else |
| 3344 | sc->dc_link = 0; |
| 3345 | |
| 3346 | return(0); |
| 3347 | } |
| 3348 | |
| 3349 | /* |
| 3350 | * Report current media status. |
| 3351 | */ |
| 3352 | static void |
| 3353 | dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) |
| 3354 | { |
| 3355 | struct dc_softc *sc; |
| 3356 | struct mii_data *mii; |
| 3357 | struct ifmedia *ifm; |
| 3358 | |
| 3359 | sc = ifp->if_softc; |
| 3360 | mii = device_get_softc(sc->dc_miibus); |
| 3361 | mii_pollstat(mii); |
| 3362 | ifm = &mii->mii_media; |
| 3363 | if (DC_IS_DAVICOM(sc)) { |
| 3364 | if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { |
| 3365 | ifmr->ifm_active = ifm->ifm_media; |
| 3366 | ifmr->ifm_status = 0; |
| 3367 | return; |
| 3368 | } |
| 3369 | } |
| 3370 | ifmr->ifm_active = mii->mii_media_active; |
| 3371 | ifmr->ifm_status = mii->mii_media_status; |
| 3372 | |
| 3373 | return; |
| 3374 | } |
| 3375 | |
| 3376 | static int |
| 3377 | dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) |
| 3378 | { |
| 3379 | struct dc_softc *sc = ifp->if_softc; |
| 3380 | struct ifreq *ifr = (struct ifreq *) data; |
| 3381 | struct mii_data *mii; |
| 3382 | int error = 0; |
| 3383 | |
| 3384 | switch(command) { |
| 3385 | case SIOCSIFFLAGS: |
| 3386 | if (ifp->if_flags & IFF_UP) { |
| 3387 | int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & |
| 3388 | (IFF_PROMISC | IFF_ALLMULTI); |
| 3389 | if (ifp->if_flags & IFF_RUNNING) { |
| 3390 | if (need_setfilt) |
| 3391 | dc_setfilt(sc); |
| 3392 | } else { |
| 3393 | sc->dc_txthresh = 0; |
| 3394 | dc_init(sc); |
| 3395 | } |
| 3396 | } else { |
| 3397 | if (ifp->if_flags & IFF_RUNNING) |
| 3398 | dc_stop(sc); |
| 3399 | } |
| 3400 | sc->dc_if_flags = ifp->if_flags; |
| 3401 | break; |
| 3402 | case SIOCADDMULTI: |
| 3403 | case SIOCDELMULTI: |
| 3404 | if (ifp->if_flags & IFF_RUNNING) |
| 3405 | dc_setfilt(sc); |
| 3406 | break; |
| 3407 | case SIOCGIFMEDIA: |
| 3408 | case SIOCSIFMEDIA: |
| 3409 | mii = device_get_softc(sc->dc_miibus); |
| 3410 | error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); |
| 3411 | break; |
| 3412 | default: |
| 3413 | error = ether_ioctl(ifp, command, data); |
| 3414 | break; |
| 3415 | } |
| 3416 | |
| 3417 | return(error); |
| 3418 | } |
| 3419 | |
| 3420 | static void |
| 3421 | dc_watchdog(struct ifnet *ifp) |
| 3422 | { |
| 3423 | struct dc_softc *sc; |
| 3424 | |
| 3425 | sc = ifp->if_softc; |
| 3426 | |
| 3427 | ifp->if_oerrors++; |
| 3428 | if_printf(ifp, "watchdog timeout\n"); |
| 3429 | |
| 3430 | dc_stop(sc); |
| 3431 | dc_reset(sc); |
| 3432 | dc_init(sc); |
| 3433 | |
| 3434 | if (!ifq_is_empty(&ifp->if_snd)) |
| 3435 | if_devstart(ifp); |
| 3436 | } |
| 3437 | |
| 3438 | /* |
| 3439 | * Stop the adapter and free any mbufs allocated to the |
| 3440 | * RX and TX lists. |
| 3441 | */ |
| 3442 | static void |
| 3443 | dc_stop(struct dc_softc *sc) |
| 3444 | { |
| 3445 | int i; |
| 3446 | struct ifnet *ifp; |
| 3447 | |
| 3448 | ifp = &sc->arpcom.ac_if; |
| 3449 | ifp->if_timer = 0; |
| 3450 | |
| 3451 | callout_stop(&sc->dc_stat_timer); |
| 3452 | |
| 3453 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
| 3454 | |
| 3455 | DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); |
| 3456 | CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
| 3457 | CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); |
| 3458 | CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); |
| 3459 | sc->dc_link = 0; |
| 3460 | |
| 3461 | /* |
| 3462 | * Free data in the RX lists. |
| 3463 | */ |
| 3464 | for (i = 0; i < DC_RX_LIST_CNT; i++) { |
| 3465 | if (sc->dc_cdata.dc_rx_chain[i] != NULL) { |
| 3466 | m_freem(sc->dc_cdata.dc_rx_chain[i]); |
| 3467 | sc->dc_cdata.dc_rx_chain[i] = NULL; |
| 3468 | } |
| 3469 | } |
| 3470 | bzero((char *)&sc->dc_ldata->dc_rx_list, |
| 3471 | sizeof(sc->dc_ldata->dc_rx_list)); |
| 3472 | |
| 3473 | /* |
| 3474 | * Free the TX list buffers. |
| 3475 | */ |
| 3476 | for (i = 0; i < DC_TX_LIST_CNT; i++) { |
| 3477 | if (sc->dc_cdata.dc_tx_chain[i] != NULL) { |
| 3478 | if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & |
| 3479 | DC_TXCTL_SETUP) || |
| 3480 | !(sc->dc_ldata->dc_tx_list[i].dc_ctl & |
| 3481 | DC_TXCTL_LASTFRAG)) { |
| 3482 | sc->dc_cdata.dc_tx_chain[i] = NULL; |
| 3483 | continue; |
| 3484 | } |
| 3485 | m_freem(sc->dc_cdata.dc_tx_chain[i]); |
| 3486 | sc->dc_cdata.dc_tx_chain[i] = NULL; |
| 3487 | } |
| 3488 | } |
| 3489 | bzero((char *)&sc->dc_ldata->dc_tx_list, |
| 3490 | sizeof(sc->dc_ldata->dc_tx_list)); |
| 3491 | } |
| 3492 | |
| 3493 | /* |
| 3494 | * Stop all chip I/O so that the kernel's probe routines don't |
| 3495 | * get confused by errant DMAs when rebooting. |
| 3496 | */ |
| 3497 | static void |
| 3498 | dc_shutdown(device_t dev) |
| 3499 | { |
| 3500 | struct dc_softc *sc; |
| 3501 | struct ifnet *ifp; |
| 3502 | |
| 3503 | sc = device_get_softc(dev); |
| 3504 | ifp = &sc->arpcom.ac_if; |
| 3505 | lwkt_serialize_enter(ifp->if_serializer); |
| 3506 | |
| 3507 | dc_stop(sc); |
| 3508 | |
| 3509 | lwkt_serialize_exit(ifp->if_serializer); |
| 3510 | } |
| 3511 | |
| 3512 | /* |
| 3513 | * Device suspend routine. Stop the interface and save some PCI |
| 3514 | * settings in case the BIOS doesn't restore them properly on |
| 3515 | * resume. |
| 3516 | */ |
| 3517 | static int |
| 3518 | dc_suspend(device_t dev) |
| 3519 | { |
| 3520 | struct dc_softc *sc = device_get_softc(dev); |
| 3521 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 3522 | int i; |
| 3523 | lwkt_serialize_enter(ifp->if_serializer); |
| 3524 | |
| 3525 | dc_stop(sc); |
| 3526 | for (i = 0; i < 5; i++) |
| 3527 | sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); |
| 3528 | sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); |
| 3529 | sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); |
| 3530 | sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); |
| 3531 | sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); |
| 3532 | |
| 3533 | sc->suspended = 1; |
| 3534 | |
| 3535 | lwkt_serialize_exit(ifp->if_serializer); |
| 3536 | return (0); |
| 3537 | } |
| 3538 | |
| 3539 | /* |
| 3540 | * Device resume routine. Restore some PCI settings in case the BIOS |
| 3541 | * doesn't, re-enable busmastering, and restart the interface if |
| 3542 | * appropriate. |
| 3543 | */ |
| 3544 | static int |
| 3545 | dc_resume(device_t dev) |
| 3546 | { |
| 3547 | struct dc_softc *sc = device_get_softc(dev); |
| 3548 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 3549 | int i; |
| 3550 | |
| 3551 | lwkt_serialize_enter(ifp->if_serializer); |
| 3552 | dc_acpi(dev); |
| 3553 | |
| 3554 | /* better way to do this? */ |
| 3555 | for (i = 0; i < 5; i++) |
| 3556 | pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); |
| 3557 | pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); |
| 3558 | pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); |
| 3559 | pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); |
| 3560 | pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); |
| 3561 | |
| 3562 | /* reenable busmastering */ |
| 3563 | pci_enable_busmaster(dev); |
| 3564 | pci_enable_io(dev, DC_RES); |
| 3565 | |
| 3566 | /* reinitialize interface if necessary */ |
| 3567 | if (ifp->if_flags & IFF_UP) |
| 3568 | dc_init(sc); |
| 3569 | |
| 3570 | sc->suspended = 0; |
| 3571 | lwkt_serialize_exit(ifp->if_serializer); |
| 3572 | |
| 3573 | return (0); |
| 3574 | } |
| 3575 | |
| 3576 | static uint32_t |
| 3577 | dc_mchash_xircom(struct dc_softc *sc, const uint8_t *addr) |
| 3578 | { |
| 3579 | uint32_t crc; |
| 3580 | |
| 3581 | /* Compute CRC for the address value. */ |
| 3582 | crc = ether_crc32_le(addr, ETHER_ADDR_LEN); |
| 3583 | |
| 3584 | if ((crc & 0x180) == 0x180) |
| 3585 | return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); |
| 3586 | else |
| 3587 | return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + (12 << 4)); |
| 3588 | } |