sys/platform/pc32/icu/icu_vector.s

   1 /*
   2  *      from: vector.s, 386BSD 0.1 unknown origin
   3  * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $
   4  * $DragonFly: src/sys/platform/pc32/icu/icu_vector.s,v 1.30 2007/01/22 19:37:04 corecode Exp $
   5  */
   6 /*
   7  * WARNING!  SMP builds can use the ICU now so this code must be MP safe.
   8  */
   9
  10 #include "use_npx.h"
  11 #include "opt_auto_eoi.h"
  12
  13 #include <machine/asmacros.h>
  14 #include <machine/lock.h>
  15 #include <machine/psl.h>
  16 #include <machine/trap.h>
  17
  18 #include <machine_base/icu/icu.h>
  19 #include <bus/isa/i386/isa.h>
  20
  21 #include "assym.s"
  22 #include "icu_ipl.h"
  23
  24 #ifndef APIC_IO
  25
  26 #define ICU_IMR_OFFSET          1       /* IO_ICU{1,2} + 1 */
  27
  28 #define ICU_EOI                 0x20    /* XXX - define elsewhere */
  29
  30 #define IRQ_LBIT(irq_num)       (1 << (irq_num))
  31 #define IRQ_BIT(irq_num)        (1 << ((irq_num) % 8))
  32 #define IRQ_BYTE(irq_num)       ((irq_num) >> 3)
  33
  34 #ifdef AUTO_EOI_1
  35 #define ENABLE_ICU1             /* use auto-EOI to reduce i/o */
  36 #define OUTB_ICU1
  37 #else
  38 #define ENABLE_ICU1                                                     \
  39         movb    $ICU_EOI,%al ;  /* as soon as possible send EOI ... */  \
  40         OUTB_ICU1 ;             /* ... to clear in service bit */       \
  41
  42 #define OUTB_ICU1                                                       \
  43         outb    %al,$IO_ICU1 ;                                          \
  44
  45 #endif
  46
  47 #ifdef AUTO_EOI_2
  48 /*
  49  * The data sheet says no auto-EOI on slave, but it sometimes works.
  50  */
  51 #define ENABLE_ICU1_AND_2       ENABLE_ICU1
  52 #else
  53 #define ENABLE_ICU1_AND_2                                               \
  54         movb    $ICU_EOI,%al ;  /* as above */                          \
  55         outb    %al,$IO_ICU2 ;  /* but do second icu first ... */       \
  56         OUTB_ICU1 ;     /* ... then first icu (if !AUTO_EOI_1) */       \
  57
  58 #endif
  59
  60 /*
  61  * Macro helpers
  62  */
  63 #define PUSH_FRAME                                                      \
  64         pushl   $0 ;            /* dummy error code */                  \
  65         pushl   $0 ;            /* dummy trap type */                   \
  66         pushl   $0 ;            /* dummy xflags */                      \
  67         pushal ;                /* 8 registers */                       \
  68         pushl   %ds ;                                                   \
  69         pushl   %es ;                                                   \
  70         pushl   %fs ;                                                   \
  71         pushl   %gs ;                                                   \
  72         mov     $KDSEL,%ax ;                                            \
  73         mov     %ax,%ds ;                                               \
  74         mov     %ax,%es ;                                               \
  75         mov     %ax,%gs ;                                               \
  76         mov     $KPSEL,%ax ;                                            \
  77         mov     %ax,%fs ;                                               \
  78
  79 #define PUSH_DUMMY                                                      \
  80         pushfl ;                /* phys int frame / flags */            \
  81         pushl %cs ;             /* phys int frame / cs */               \
  82         pushl   12(%esp) ;      /* original caller eip */               \
  83         pushl   $0 ;            /* dummy error code */                  \
  84         pushl   $0 ;            /* dummy trap type */                   \
  85         pushl   $0 ;            /* dummy xflags */                      \
  86         subl    $13*4,%esp ;    /* pushal + 4 seg regs (dummy) + CPL */ \
  87
  88 /*
  89  * Warning: POP_FRAME can only be used if there is no chance of a
  90  * segment register being changed (e.g. by procfs), which is why syscalls
  91  * have to use doreti.
  92  */
  93 #define POP_FRAME                                                       \
  94         popl    %gs ;                                                   \
  95         popl    %fs ;                                                   \
  96         popl    %es ;                                                   \
  97         popl    %ds ;                                                   \
  98         popal ;                                                         \
  99         addl    $2*4,%esp ;     /* dummy trap & error codes */          \
 100
 101 #define POP_DUMMY                                                       \
 102         addl    $19*4,%esp ;                                            \
 103
 104 #define MASK_IRQ(icu, irq_num)                                          \
 105         ICU_IMASK_LOCK ;                                                \
 106         movb    icu_imen + IRQ_BYTE(irq_num),%al ;                      \
 107         orb     $IRQ_BIT(irq_num),%al ;                                 \
 108         movb    %al,icu_imen + IRQ_BYTE(irq_num) ;                      \
 109         outb    %al,$icu+ICU_IMR_OFFSET ;                               \
 110         ICU_IMASK_UNLOCK ;                                              \
 111
 112 #define UNMASK_IRQ(icu, irq_num)                                        \
 113         cmpl    $0,%eax ;                                               \
 114         jnz     8f ;                                                    \
 115         ICU_IMASK_LOCK ;                                                \
 116         movb    icu_imen + IRQ_BYTE(irq_num),%al ;                      \
 117         andb    $~IRQ_BIT(irq_num),%al ;                                \
 118         movb    %al,icu_imen + IRQ_BYTE(irq_num) ;                      \
 119         outb    %al,$icu+ICU_IMR_OFFSET ;                               \
 120         ICU_IMASK_UNLOCK ;                                              \
 121 8: ;                                                                    \
 122
 123 /*
 124  * Fast interrupt call handlers run in the following sequence:
 125  *
 126  *      - Push the trap frame required by doreti.
 127  *      - Mask the interrupt and reenable its source.
 128  *      - If we cannot take the interrupt set its fpending bit and
 129  *        doreti.
 130  *      - If we can take the interrupt clear its fpending bit,
 131  *        call the handler, then unmask the interrupt and doreti.
 132  *
 133  *      YYY can cache gd base pointer instead of using hidden %fs
 134  *      prefixes.
 135  */
 136
 137 #define FAST_INTR(irq_num, vec_name, icu, enable_icus)                   \
 138         .text ;                                                         \
 139         SUPERALIGN_TEXT ;                                               \
 140 IDTVEC(vec_name) ;                                                      \
 141         PUSH_FRAME ;                                                    \
 142         FAKE_MCOUNT(15*4(%esp)) ;                                       \
 143         MASK_IRQ(icu, irq_num) ;                                        \
 144         enable_icus ;                                                   \
 145         movl    PCPU(curthread),%ebx ;                                  \
 146         pushl   $0 ;                    /* DUMMY CPL FOR DORETI */      \
 147         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 148         jl      2f ;                                                    \
 149 1: ;                                                                    \
 150         /* set pending bit and return, leave interrupt masked */        \
 151         orl     $IRQ_LBIT(irq_num),PCPU(fpending) ;                     \
 152         orl     $RQF_INTPEND, PCPU(reqflags) ;                          \
 153         jmp     5f ;                                                    \
 154 2: ;                                                                    \
 155         /* clear pending bit, run handler */                            \
 156         andl    $~IRQ_LBIT(irq_num),PCPU(fpending) ;                    \
 157         pushl   $irq_num ;                                              \
 158         pushl   %esp ;                  /* pass frame by reference */   \
 159         call    ithread_fast_handler ;  /* returns 0 to unmask int */   \
 160         addl    $8,%esp ;                                               \
 161         UNMASK_IRQ(icu, irq_num) ;                                      \
 162 5: ;                                                                    \
 163         MEXITCOUNT ;                                                    \
 164         jmp     doreti ;                                                \
 165
 166 /*
 167  * Slow interrupt call handlers run in the following sequence:
 168  *
 169  *      - Push the trap frame required by doreti.
 170  *      - Mask the interrupt and reenable its source.
 171  *      - If we cannot take the interrupt set its ipending bit and
 172  *        doreti.  In addition to checking for a critical section
 173  *        and cpl mask we also check to see if the thread is still
 174  *        running.
 175  *      - If we can take the interrupt clear its ipending bit
 176  *        and schedule its thread.  Leave interrupts masked and doreti.
 177  *
 178  *      sched_ithd() is called with interrupts enabled and outside of a
 179  *      critical section (so it can preempt us).
 180  *
 181  *      YYY sched_ithd may preempt us synchronously (fix interrupt stacking)
 182  *
 183  *      Note that intr_nesting_level is not bumped during sched_ithd because
 184  *      blocking allocations are allowed in the preemption case.
 185  *
 186  *      YYY can cache gd base pointer instead of using hidden %fs
 187  *      prefixes.
 188  */
 189
 190 #define SLOW_INTR(irq_num, vec_name, icu, enable_icus)                   \
 191         .text ;                                                         \
 192         SUPERALIGN_TEXT ;                                               \
 193 IDTVEC(vec_name) ;                                                      \
 194         PUSH_FRAME ;                                                    \
 195         FAKE_MCOUNT(15*4(%esp)) ;                                       \
 196         MASK_IRQ(icu, irq_num) ;                                        \
 197         incl    PCPU(cnt) + V_INTR ;                                    \
 198         enable_icus ;                                                   \
 199         movl    PCPU(curthread),%ebx ;                                  \
 200         pushl   $0 ;                    /* DUMMY CPL FOR DORETI */      \
 201         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 202         jl      2f ;                                                    \
 203 1: ;                                                                    \
 204         /* set the pending bit and return, leave interrupt masked */    \
 205         orl     $IRQ_LBIT(irq_num), PCPU(ipending) ;                    \
 206         orl     $RQF_INTPEND, PCPU(reqflags) ;                          \
 207         jmp     5f ;                                                    \
 208 2: ;                                                                    \
 209         /* set running bit, clear pending bit, run handler */           \
 210         andl    $~IRQ_LBIT(irq_num), PCPU(ipending) ;                   \
 211         sti ;                                                           \
 212         pushl   $irq_num ;                                              \
 213         call    sched_ithd ;                                            \
 214         addl    $4,%esp ;                                               \
 215 5: ;                                                                    \
 216         MEXITCOUNT ;                                                    \
 217         jmp     doreti ;                                                \
 218
 219 /*
 220  * Unmask a slow interrupt.  This function is used by interrupt threads
 221  * after they have descheduled themselves to reenable interrupts and
 222  * possibly cause a reschedule to occur.
 223  */
 224
 225 #define INTR_UNMASK(irq_num, vec_name, icu)                             \
 226         .text ;                                                         \
 227         SUPERALIGN_TEXT ;                                               \
 228 IDTVEC(vec_name) ;                                                      \
 229         pushl %ebp ;     /* frame for ddb backtrace */                  \
 230         movl    %esp, %ebp ;                                            \
 231         subl    %eax, %eax ;                                            \
 232         UNMASK_IRQ(icu, irq_num) ;                                      \
 233         popl %ebp ;                                                     \
 234         ret ;                                                           \
 235
 236 MCOUNT_LABEL(bintr)
 237         FAST_INTR(0,icu_fastintr0, IO_ICU1, ENABLE_ICU1)
 238         FAST_INTR(1,icu_fastintr1, IO_ICU1, ENABLE_ICU1)
 239         FAST_INTR(2,icu_fastintr2, IO_ICU1, ENABLE_ICU1)
 240         FAST_INTR(3,icu_fastintr3, IO_ICU1, ENABLE_ICU1)
 241         FAST_INTR(4,icu_fastintr4, IO_ICU1, ENABLE_ICU1)
 242         FAST_INTR(5,icu_fastintr5, IO_ICU1, ENABLE_ICU1)
 243         FAST_INTR(6,icu_fastintr6, IO_ICU1, ENABLE_ICU1)
 244         FAST_INTR(7,icu_fastintr7, IO_ICU1, ENABLE_ICU1)
 245         FAST_INTR(8,icu_fastintr8, IO_ICU2, ENABLE_ICU1_AND_2)
 246         FAST_INTR(9,icu_fastintr9, IO_ICU2, ENABLE_ICU1_AND_2)
 247         FAST_INTR(10,icu_fastintr10, IO_ICU2, ENABLE_ICU1_AND_2)
 248         FAST_INTR(11,icu_fastintr11, IO_ICU2, ENABLE_ICU1_AND_2)
 249         FAST_INTR(12,icu_fastintr12, IO_ICU2, ENABLE_ICU1_AND_2)
 250         FAST_INTR(13,icu_fastintr13, IO_ICU2, ENABLE_ICU1_AND_2)
 251         FAST_INTR(14,icu_fastintr14, IO_ICU2, ENABLE_ICU1_AND_2)
 252         FAST_INTR(15,icu_fastintr15, IO_ICU2, ENABLE_ICU1_AND_2)
 253
 254         SLOW_INTR(0,icu_slowintr0, IO_ICU1, ENABLE_ICU1)
 255         SLOW_INTR(1,icu_slowintr1, IO_ICU1, ENABLE_ICU1)
 256         SLOW_INTR(2,icu_slowintr2, IO_ICU1, ENABLE_ICU1)
 257         SLOW_INTR(3,icu_slowintr3, IO_ICU1, ENABLE_ICU1)
 258         SLOW_INTR(4,icu_slowintr4, IO_ICU1, ENABLE_ICU1)
 259         SLOW_INTR(5,icu_slowintr5, IO_ICU1, ENABLE_ICU1)
 260         SLOW_INTR(6,icu_slowintr6, IO_ICU1, ENABLE_ICU1)
 261         SLOW_INTR(7,icu_slowintr7, IO_ICU1, ENABLE_ICU1)
 262         SLOW_INTR(8,icu_slowintr8, IO_ICU2, ENABLE_ICU1_AND_2)
 263         SLOW_INTR(9,icu_slowintr9, IO_ICU2, ENABLE_ICU1_AND_2)
 264         SLOW_INTR(10,icu_slowintr10, IO_ICU2, ENABLE_ICU1_AND_2)
 265         SLOW_INTR(11,icu_slowintr11, IO_ICU2, ENABLE_ICU1_AND_2)
 266         SLOW_INTR(12,icu_slowintr12, IO_ICU2, ENABLE_ICU1_AND_2)
 267         SLOW_INTR(13,icu_slowintr13, IO_ICU2, ENABLE_ICU1_AND_2)
 268         SLOW_INTR(14,icu_slowintr14, IO_ICU2, ENABLE_ICU1_AND_2)
 269         SLOW_INTR(15,icu_slowintr15, IO_ICU2, ENABLE_ICU1_AND_2)
 270
 271 MCOUNT_LABEL(eintr)
 272
 273         .data
 274
 275         .text
 276
 277 #endif