2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <machine/globaldata.h>
32 #include <machine/smp.h>
33 #include <machine/md_var.h>
34 #include <machine_base/apic/mpapic.h>
35 #include <machine/segments.h>
36 #include <sys/thread2.h>
38 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
40 /* EISA Edge/Level trigger control registers */
41 #define ELCR0 0x4d0 /* eisa irq 0-7 */
42 #define ELCR1 0x4d1 /* eisa irq 8-15 */
44 static void lapic_timer_calibrate(void);
47 * pointers to pmapped apic hardware.
50 volatile ioapic_t **ioapic;
53 * Enable APIC, configure interrupts.
56 apic_initialize(boolean_t bsp)
61 * setup LVT1 as ExtINT on the BSP. This is theoretically an
62 * aggregate interrupt input from the 8259. The INTA cycle
63 * will be routed to the external controller (the 8259) which
64 * is expected to supply the vector.
66 * Must be setup edge triggered, active high.
68 * Disable LVT1 on the APs. It doesn't matter what delivery
69 * mode we use because we leave it masked.
71 temp = lapic.lvt_lint0;
72 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
73 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
74 if (mycpu->gd_cpuid == 0)
75 temp |= APIC_LVT_DM_EXTINT;
77 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
78 lapic.lvt_lint0 = temp;
81 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
83 temp = lapic.lvt_lint1;
84 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
85 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
86 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
87 lapic.lvt_lint1 = temp;
90 * Mask the apic error interrupt, apic performance counter
91 * interrupt, and the apic timer interrupt.
93 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
94 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
95 lapic.lvt_timer = lapic.lvt_timer | APIC_LVT_MASKED;
98 * Set the Task Priority Register as needed. At the moment allow
99 * interrupts on all cpus (the APs will remain CLId until they are
100 * ready to deal). We could disable all but IPIs by setting
101 * temp |= TPR_IPI_ONLY for cpu != 0.
104 temp &= ~APIC_TPR_PRIO; /* clear priority field */
107 * If we are NOT running the IO APICs, the LAPIC will only be used
108 * for IPIs. Set the TPR to prevent any unintentional interrupts.
110 temp |= TPR_IPI_ONLY;
116 * enable the local APIC
119 temp |= APIC_SVR_ENABLE; /* enable the APIC */
120 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
123 * Set the spurious interrupt vector. The low 4 bits of the vector
126 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
127 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
128 temp &= ~APIC_SVR_VECTOR;
129 temp |= XSPURIOUSINT_OFFSET;
134 * Pump out a few EOIs to clean out interrupts that got through
135 * before we were able to set the TPR.
141 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
143 * Detect the presence of C1E capability mostly on latest
144 * dual-cores (or future) k8 family. This feature renders
145 * the local APIC timer dead, so we disable it by reading
146 * the Interrupt Pending Message register and clearing both
147 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
150 * "BIOS and Kernel Developer's Guide for AMD NPT
151 * Family 0Fh Processors"
152 * #32559 revision 3.00
154 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
155 (cpu_id & 0x0fff0000) >= 0x00040000) {
158 msr = rdmsr(0xc0010055);
159 if (msr & 0x18000000)
160 wrmsr(0xc0010055, msr & ~0x18000000ULL);
165 lapic_timer_calibrate();
168 apic_dump("apic_initialize()");
172 static sysclock_t lapic_timer_freq;
173 static int lapic_timer_divisor_idx = -1;
174 static const uint32_t lapic_timer_divisors[] = {
175 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
176 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
178 #define APIC_TIMER_NDIVISORS \
179 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
182 lapic_timer_set_divisor(int divisor_idx)
184 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
185 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
189 lapic_timer_oneshot(u_int count)
193 value = lapic.lvt_timer;
194 value &= ~APIC_LVTT_PERIODIC;
195 lapic.lvt_timer = value;
196 lapic.icr_timer = count;
200 lapic_timer_calibrate(void)
204 /* Try to calibrate the local APIC timer. */
205 for (lapic_timer_divisor_idx = 0;
206 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
207 lapic_timer_divisor_idx++) {
208 lapic_timer_set_divisor(lapic_timer_divisor_idx);
209 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
211 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
212 if (value != APIC_TIMER_MAX_COUNT)
215 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
216 panic("lapic: no proper timer divisor?!\n");
217 lapic_timer_freq = value / 2;
219 kprintf("lapic: divisor index %d, frequency %u Hz\n",
220 lapic_timer_divisor_idx, lapic_timer_freq);
225 * dump contents of local APIC registers
230 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
231 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
232 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
242 #define IOAPIC_ISA_INTS 16
243 #define REDIRCNT_IOAPIC(A) \
244 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
246 static int trigger (int apic, int pin, u_int32_t * flags);
247 static void polarity (int apic, int pin, u_int32_t * flags, int level);
249 #define DEFAULT_FLAGS \
255 #define DEFAULT_ISA_FLAGS \
264 io_apic_set_id(int apic, int id)
268 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
269 if (((ux & APIC_ID_MASK) >> 24) != id) {
270 kprintf("Changing APIC ID for IO APIC #%d"
271 " from %d to %d on chip\n",
272 apic, ((ux & APIC_ID_MASK) >> 24), id);
273 ux &= ~APIC_ID_MASK; /* clear the ID field */
275 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
276 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
277 if (((ux & APIC_ID_MASK) >> 24) != id)
278 panic("can't control IO APIC #%d ID, reg: 0x%08x",
285 io_apic_get_id(int apic)
287 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
296 extern int apic_pin_trigger; /* 'opaque' */
299 io_apic_setup_intpin(int apic, int pin)
301 int bus, bustype, irq;
302 u_char select; /* the select register is 8 bits */
303 u_int32_t flags; /* the window register is 32 bits */
304 u_int32_t target; /* the window register is 32 bits */
305 u_int32_t vector; /* the window register is 32 bits */
308 select = pin * 2 + IOAPIC_REDTBL0; /* register */
311 * Always clear an IO APIC pin before [re]programming it. This is
312 * particularly important if the pin is set up for a level interrupt
313 * as the IOART_REM_IRR bit might be set. When we reprogram the
314 * vector any EOI from pending ints on this pin could be lost and
315 * IRR might never get reset.
317 * To fix this problem, clear the vector and make sure it is
318 * programmed as an edge interrupt. This should theoretically
319 * clear IRR so we can later, safely program it as a level
324 flags = io_apic_read(apic, select) & IOART_RESV;
325 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
326 flags |= IOART_DESTPHY | IOART_DELFIXED;
328 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
329 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
333 io_apic_write(apic, select, flags | vector);
334 io_apic_write(apic, select + 1, target);
339 * We only deal with vectored interrupts here. ? documentation is
340 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
343 * This test also catches unconfigured pins.
345 if (apic_int_type(apic, pin) != 0)
349 * Leave the pin unprogrammed if it does not correspond to
352 irq = apic_irq(apic, pin);
356 /* determine the bus type for this pin */
357 bus = apic_src_bus_id(apic, pin);
360 bustype = apic_bus_type(bus);
362 if ((bustype == ISA) &&
363 (pin < IOAPIC_ISA_INTS) &&
365 (apic_polarity(apic, pin) == 0x1) &&
366 (apic_trigger(apic, pin) == 0x3)) {
368 * A broken BIOS might describe some ISA
369 * interrupts as active-high level-triggered.
370 * Use default ISA flags for those interrupts.
372 flags = DEFAULT_ISA_FLAGS;
375 * Program polarity and trigger mode according to
378 flags = DEFAULT_FLAGS;
379 level = trigger(apic, pin, &flags);
381 apic_pin_trigger |= (1 << irq);
382 polarity(apic, pin, &flags, level);
386 kprintf("IOAPIC #%d intpin %d -> irq %d\n",
391 * Program the appropriate registers. This routing may be
392 * overridden when an interrupt handler for a device is
393 * actually added (see register_int(), which calls through
394 * the MACHINTR ABI to set up an interrupt handler/vector).
396 * The order in which we must program the two registers for
397 * safety is unclear! XXX
401 vector = IDT_OFFSET + irq; /* IDT vec */
402 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
403 target |= IOART_HI_DEST_BROADCAST;
404 flags |= io_apic_read(apic, select) & IOART_RESV;
405 io_apic_write(apic, select, flags | vector);
406 io_apic_write(apic, select + 1, target);
412 io_apic_setup(int apic)
418 apic_pin_trigger = 0; /* default to edge-triggered */
420 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
421 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
423 for (pin = 0; pin < maxpin; ++pin) {
424 io_apic_setup_intpin(apic, pin);
427 if (apic_int_type(apic, pin) >= 0) {
428 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
429 " cannot program!\n", apic, pin);
434 /* return GOOD status */
437 #undef DEFAULT_ISA_FLAGS
441 #define DEFAULT_EXTINT_FLAGS \
450 * Setup the source of External INTerrupts.
453 ext_int_setup(int apic, int intr)
455 u_char select; /* the select register is 8 bits */
456 u_int32_t flags; /* the window register is 32 bits */
457 u_int32_t target; /* the window register is 32 bits */
458 u_int32_t vector; /* the window register is 32 bits */
460 if (apic_int_type(apic, intr) != 3)
463 target = IOART_HI_DEST_BROADCAST;
464 select = IOAPIC_REDTBL0 + (2 * intr);
465 vector = IDT_OFFSET + intr;
466 flags = DEFAULT_EXTINT_FLAGS;
468 io_apic_write(apic, select, flags | vector);
469 io_apic_write(apic, select + 1, target);
473 #undef DEFAULT_EXTINT_FLAGS
477 * Set the trigger level for an IO APIC pin.
480 trigger(int apic, int pin, u_int32_t * flags)
485 static int intcontrol = -1;
487 switch (apic_trigger(apic, pin)) {
493 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
497 *flags |= IOART_TRGRLVL;
505 if ((id = apic_src_bus_id(apic, pin)) == -1)
508 switch (apic_bus_type(id)) {
510 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
514 eirq = apic_src_bus_irq(apic, pin);
516 if (eirq < 0 || eirq > 15) {
517 kprintf("EISA IRQ %d?!?!\n", eirq);
521 if (intcontrol == -1) {
522 intcontrol = inb(ELCR1) << 8;
523 intcontrol |= inb(ELCR0);
524 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
527 /* Use ELCR settings to determine level or edge mode */
528 level = (intcontrol >> eirq) & 1;
531 * Note that on older Neptune chipset based systems, any
532 * pci interrupts often show up here and in the ELCR as well
533 * as level sensitive interrupts attributed to the EISA bus.
537 *flags |= IOART_TRGRLVL;
539 *flags &= ~IOART_TRGRLVL;
544 *flags |= IOART_TRGRLVL;
553 panic("bad APIC IO INT flags");
558 * Set the polarity value for an IO APIC pin.
561 polarity(int apic, int pin, u_int32_t * flags, int level)
565 switch (apic_polarity(apic, pin)) {
571 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
575 *flags |= IOART_INTALO;
583 if ((id = apic_src_bus_id(apic, pin)) == -1)
586 switch (apic_bus_type(id)) {
588 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
592 /* polarity converter always gives active high */
593 *flags &= ~IOART_INTALO;
597 *flags |= IOART_INTALO;
606 panic("bad APIC IO INT flags");
611 * Print contents of apic_imen.
613 extern u_int apic_imen; /* keep apic_imen 'opaque' */
619 kprintf("SMP: enabled INTs: ");
620 for (x = 0; x < 24; ++x)
621 if ((apic_imen & (1 << x)) == 0)
623 kprintf("apic_imen: 0x%08x\n", apic_imen);
628 * Inter Processor Interrupt functions.
634 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
636 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
637 * vector is any valid SYSTEM INT vector
638 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
640 * A backlog of requests can create a deadlock between cpus. To avoid this
641 * we have to be able to accept IPIs at the same time we are trying to send
642 * them. The critical section prevents us from attempting to send additional
643 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
644 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
645 * to occur but fortunately it does not happen too often.
648 apic_ipi(int dest_type, int vector, int delivery_mode)
653 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
654 unsigned int eflags = read_eflags();
656 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
659 write_eflags(eflags);
662 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
663 delivery_mode | vector;
664 lapic.icr_lo = icr_lo;
670 single_apic_ipi(int cpu, int vector, int delivery_mode)
676 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
677 unsigned int eflags = read_eflags();
679 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
682 write_eflags(eflags);
684 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
685 icr_hi |= (CPU_TO_ID(cpu) << 24);
686 lapic.icr_hi = icr_hi;
689 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
690 | APIC_DEST_DESTFLD | delivery_mode | vector;
693 lapic.icr_lo = icr_lo;
700 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
702 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
703 * to the target, and the scheduler does not 'poll' for IPI messages.
706 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
712 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
716 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
717 icr_hi |= (CPU_TO_ID(cpu) << 24);
718 lapic.icr_hi = icr_hi;
721 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
722 | APIC_DEST_DESTFLD | delivery_mode | vector;
725 lapic.icr_lo = icr_lo;
733 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
735 * target is a bitmask of destination cpus. Vector is any
736 * valid system INT vector. Delivery mode may be either
737 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
740 selected_apic_ipi(u_int target, int vector, int delivery_mode)
744 int n = bsfl(target);
746 single_apic_ipi(n, vector, delivery_mode);
752 * Timer code, in development...
753 * - suggested by rgrimes@gndrsh.aac.dev.com
757 * Load a 'downcount time' in uSeconds.
760 set_apic_timer(int us)
765 * When we reach here, lapic timer's frequency
766 * must have been calculated as well as the
767 * divisor (lapic.dcr_timer is setup during the
768 * divisor calculation).
770 KKASSERT(lapic_timer_freq != 0 &&
771 lapic_timer_divisor_idx >= 0);
773 count = ((us * (int64_t)lapic_timer_freq) + 999999) / 1000000;
774 lapic_timer_oneshot(count);
779 * Read remaining time in timer.
782 read_apic_timer(void)
785 /** XXX FIXME: we need to return the actual remaining time,
786 * for now we just return the remaining count.
789 return lapic.ccr_timer;
795 * Spin-style delay, set delay time in uS, spin till it drains.
800 set_apic_timer(count);
801 while (read_apic_timer())