2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.54 2006/12/22 23:26:19 swildner Exp $
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985
48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
49 * Accton EN1217 (www.accton.com)
50 * Xircom X3201 (www.xircom.com)
51 * Conexant LANfinity (www.conexant.com)
53 * Datasheets for the 21143 are available at developer.intel.com.
54 * Datasheets for the clone parts can be found at their respective sites.
55 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
56 * The PNIC II is essentially a Macronix 98715A chip; the only difference
57 * worth noting is that its multicast hash table is only 128 bits wide
60 * Written by Bill Paul <wpaul@ee.columbia.edu>
61 * Electrical Engineering Department
62 * Columbia University, New York City
66 * The Intel 21143 is the successor to the DEC 21140. It is basically
67 * the same as the 21140 but with a few new features. The 21143 supports
68 * three kinds of media attachments:
70 * o MII port, for 10Mbps and 100Mbps support and NWAY
71 * autonegotiation provided by an external PHY.
72 * o SYM port, for symbol mode 100Mbps support.
76 * The 100Mbps SYM port and 10baseT port can be used together in
77 * combination with the internal NWAY support to create a 10/100
78 * autosensing configuration.
80 * Note that not all tulip workalikes are handled in this driver: we only
81 * deal with those which are relatively well behaved. The Winbond is
82 * handled separately due to its different register offsets and the
83 * special handling needed for its various bugs. The PNIC is handled
84 * here, but I'm not thrilled about it.
86 * All of the workalike chips use some form of MII transceiver support
87 * with the exception of the Macronix chips, which also have a SYM port.
88 * The ASIX AX88140A is also documented to have a SYM port, but all
89 * the cards I've seen use an MII transceiver, probably because the
90 * AX88140A doesn't support internal NWAY.
93 #include "opt_polling.h"
95 #include <sys/param.h>
96 #include <sys/systm.h>
97 #include <sys/sockio.h>
99 #include <sys/malloc.h>
100 #include <sys/kernel.h>
101 #include <sys/socket.h>
102 #include <sys/sysctl.h>
104 #include <sys/rman.h>
105 #include <sys/thread2.h>
108 #include <net/ifq_var.h>
109 #include <net/if_arp.h>
110 #include <net/ethernet.h>
111 #include <net/if_dl.h>
112 #include <net/if_media.h>
113 #include <net/if_types.h>
114 #include <net/vlan/if_vlan_var.h>
118 #include <vm/vm.h> /* for vtophys */
119 #include <vm/pmap.h> /* for vtophys */
121 #include "../mii_layer/mii.h"
122 #include "../mii_layer/miivar.h"
124 #include <bus/pci/pcireg.h>
125 #include <bus/pci/pcivar.h>
127 #define DC_USEIOSPACE
129 #include "if_dcreg.h"
131 /* "controller miibus0" required. See GENERIC if you get errors here. */
132 #include "miibus_if.h"
135 * Various supported device vendors/types and their names.
137 static const struct dc_type dc_devs[] = {
138 { DC_VENDORID_DEC, DC_DEVICEID_21143,
139 "Intel 21143 10/100BaseTX" },
140 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
141 "Davicom DM9009 10/100BaseTX" },
142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
143 "Davicom DM9100 10/100BaseTX" },
144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
145 "Davicom DM9102 10/100BaseTX" },
146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
147 "Davicom DM9102A 10/100BaseTX" },
148 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
149 "ADMtek AL981 10/100BaseTX" },
150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
151 "ADMtek AN985 10/100BaseTX" },
152 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511,
153 "Netgear FA511 10/100BaseTX" },
154 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511,
155 "ADMtek ADM9511 10/100BaseTX" },
156 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513,
157 "ADMtek ADM9513 10/100BaseTX" },
158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
159 "ASIX AX88140A 10/100BaseTX" },
160 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
161 "ASIX AX88141 10/100BaseTX" },
162 { DC_VENDORID_MX, DC_DEVICEID_98713,
163 "Macronix 98713 10/100BaseTX" },
164 { DC_VENDORID_MX, DC_DEVICEID_98713,
165 "Macronix 98713A 10/100BaseTX" },
166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
167 "Compex RL100-TX 10/100BaseTX" },
168 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
169 "Compex RL100-TX 10/100BaseTX" },
170 { DC_VENDORID_MX, DC_DEVICEID_987x5,
171 "Macronix 98715/98715A 10/100BaseTX" },
172 { DC_VENDORID_MX, DC_DEVICEID_987x5,
173 "Macronix 98715AEC-C 10/100BaseTX" },
174 { DC_VENDORID_MX, DC_DEVICEID_987x5,
175 "Macronix 98725 10/100BaseTX" },
176 { DC_VENDORID_MX, DC_DEVICEID_98727,
177 "Macronix 98727/98732 10/100BaseTX" },
178 { DC_VENDORID_LO, DC_DEVICEID_82C115,
179 "LC82C115 PNIC II 10/100BaseTX" },
180 { DC_VENDORID_LO, DC_DEVICEID_82C168,
181 "82c168 PNIC 10/100BaseTX" },
182 { DC_VENDORID_LO, DC_DEVICEID_82C168,
183 "82c169 PNIC 10/100BaseTX" },
184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
185 "Accton EN1217 10/100BaseTX" },
186 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
187 "Accton EN2242 MiniPCI 10/100BaseTX" },
188 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201,
189 "Xircom X3201 10/100BaseTX" },
190 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
191 "Conexant LANfinity MiniPCI 10/100BaseTX" },
192 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
193 "3Com OfficeConnect 10/100B" },
197 static int dc_probe (device_t);
198 static int dc_attach (device_t);
199 static int dc_detach (device_t);
200 static int dc_suspend (device_t);
201 static int dc_resume (device_t);
202 static void dc_acpi (device_t);
203 static const struct dc_type *dc_devtype (device_t);
204 static int dc_newbuf (struct dc_softc *, int, struct mbuf *);
205 static int dc_encap (struct dc_softc *, struct mbuf *,
207 static void dc_pnic_rx_bug_war (struct dc_softc *, int);
208 static int dc_rx_resync (struct dc_softc *);
209 static void dc_rxeof (struct dc_softc *);
210 static void dc_txeof (struct dc_softc *);
211 static void dc_tick (void *);
212 static void dc_tx_underrun (struct dc_softc *);
213 static void dc_intr (void *);
214 static void dc_start (struct ifnet *);
215 static int dc_ioctl (struct ifnet *, u_long, caddr_t,
217 #ifdef DEVICE_POLLING
218 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd,
221 static void dc_init (void *);
222 static void dc_stop (struct dc_softc *);
223 static void dc_watchdog (struct ifnet *);
224 static void dc_shutdown (device_t);
225 static int dc_ifmedia_upd (struct ifnet *);
226 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *);
228 static void dc_delay (struct dc_softc *);
229 static void dc_eeprom_idle (struct dc_softc *);
230 static void dc_eeprom_putbyte (struct dc_softc *, int);
231 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *);
232 static void dc_eeprom_getword_pnic
233 (struct dc_softc *, int, u_int16_t *);
234 static void dc_eeprom_getword_xircom
235 (struct dc_softc *, int, u_int16_t *);
236 static void dc_eeprom_width (struct dc_softc *);
237 static void dc_read_eeprom (struct dc_softc *, caddr_t, int,
240 static void dc_mii_writebit (struct dc_softc *, int);
241 static int dc_mii_readbit (struct dc_softc *);
242 static void dc_mii_sync (struct dc_softc *);
243 static void dc_mii_send (struct dc_softc *, u_int32_t, int);
244 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *);
245 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *);
246 static int dc_miibus_readreg (device_t, int, int);
247 static int dc_miibus_writereg (device_t, int, int, int);
248 static void dc_miibus_statchg (device_t);
249 static void dc_miibus_mediainit (device_t);
251 static u_int32_t dc_crc_mask (struct dc_softc *);
252 static void dc_setcfg (struct dc_softc *, int);
253 static void dc_setfilt_21143 (struct dc_softc *);
254 static void dc_setfilt_asix (struct dc_softc *);
255 static void dc_setfilt_admtek (struct dc_softc *);
256 static void dc_setfilt_xircom (struct dc_softc *);
258 static void dc_setfilt (struct dc_softc *);
260 static void dc_reset (struct dc_softc *);
261 static int dc_list_rx_init (struct dc_softc *);
262 static int dc_list_tx_init (struct dc_softc *);
264 static void dc_read_srom (struct dc_softc *, int);
265 static void dc_parse_21143_srom (struct dc_softc *);
266 static void dc_decode_leaf_sia (struct dc_softc *,
267 struct dc_eblock_sia *);
268 static void dc_decode_leaf_mii (struct dc_softc *,
269 struct dc_eblock_mii *);
270 static void dc_decode_leaf_sym (struct dc_softc *,
271 struct dc_eblock_sym *);
272 static void dc_apply_fixup (struct dc_softc *, int);
273 static uint32_t dc_mchash_xircom(struct dc_softc *, const uint8_t *);
276 #define DC_RES SYS_RES_IOPORT
277 #define DC_RID DC_PCI_CFBIO
279 #define DC_RES SYS_RES_MEMORY
280 #define DC_RID DC_PCI_CFBMA
283 static device_method_t dc_methods[] = {
284 /* Device interface */
285 DEVMETHOD(device_probe, dc_probe),
286 DEVMETHOD(device_attach, dc_attach),
287 DEVMETHOD(device_detach, dc_detach),
288 DEVMETHOD(device_suspend, dc_suspend),
289 DEVMETHOD(device_resume, dc_resume),
290 DEVMETHOD(device_shutdown, dc_shutdown),
293 DEVMETHOD(bus_print_child, bus_generic_print_child),
294 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
297 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
298 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
299 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
300 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
305 static driver_t dc_driver = {
308 sizeof(struct dc_softc)
311 static devclass_t dc_devclass;
314 static int dc_quick=1;
315 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
316 &dc_quick,0,"do not mdevget in dc driver");
319 DECLARE_DUMMY_MODULE(if_dc);
320 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0);
321 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
322 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
324 #define DC_SETBIT(sc, reg, x) \
325 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
327 #define DC_CLRBIT(sc, reg, x) \
328 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
330 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
331 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
334 dc_delay(struct dc_softc *sc)
338 for (idx = (300 / 33) + 1; idx > 0; idx--)
339 CSR_READ_4(sc, DC_BUSCTL);
343 dc_eeprom_width(struct dc_softc *sc)
347 /* Force EEPROM to idle state. */
350 /* Enter EEPROM access mode. */
351 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
353 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
355 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
357 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
362 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
364 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
366 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
368 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
372 for (i = 1; i <= 12; i++) {
373 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
375 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
376 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
380 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
384 /* Turn off EEPROM access mode. */
392 /* Enter EEPROM access mode. */
393 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
395 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
399 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
402 /* Turn off EEPROM access mode. */
407 dc_eeprom_idle(struct dc_softc *sc)
411 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
413 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
415 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
417 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
420 for (i = 0; i < 25; i++) {
421 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
423 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
427 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
429 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
431 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
437 * Send a read command and address to the EEPROM, check for ACK.
440 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
444 d = DC_EECMD_READ >> 6;
447 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
451 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
458 * Feed in each bit and strobe the clock.
460 for (i = sc->dc_romwidth; i--;) {
461 if (addr & (1 << i)) {
462 SIO_SET(DC_SIO_EE_DATAIN);
464 SIO_CLR(DC_SIO_EE_DATAIN);
467 SIO_SET(DC_SIO_EE_CLK);
469 SIO_CLR(DC_SIO_EE_CLK);
477 * Read a word of data stored in the EEPROM at address 'addr.'
478 * The PNIC 82c168/82c169 has its own non-standard way to read
482 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
487 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
489 for (i = 0; i < DC_TIMEOUT; i++) {
491 r = CSR_READ_4(sc, DC_SIO);
492 if (!(r & DC_PN_SIOCTL_BUSY)) {
493 *dest = (u_int16_t)(r & 0xFFFF);
502 * Read a word of data stored in the EEPROM at address 'addr.'
503 * The Xircom X3201 has its own non-standard way to read
507 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
509 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
512 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
513 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff;
515 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
516 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8;
518 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
522 * Read a word of data stored in the EEPROM at address 'addr.'
525 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
530 /* Force EEPROM to idle state. */
533 /* Enter EEPROM access mode. */
534 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
536 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
538 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
540 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
544 * Send address of word we want to read.
546 dc_eeprom_putbyte(sc, addr);
549 * Start reading bits from EEPROM.
551 for (i = 0x8000; i; i >>= 1) {
552 SIO_SET(DC_SIO_EE_CLK);
554 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
557 SIO_CLR(DC_SIO_EE_CLK);
561 /* Turn off EEPROM access mode. */
570 * Read a sequence of words from the EEPROM.
573 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap)
576 u_int16_t word = 0, *ptr;
578 for (i = 0; i < cnt; i++) {
580 dc_eeprom_getword_pnic(sc, off + i, &word);
581 else if (DC_IS_XIRCOM(sc))
582 dc_eeprom_getword_xircom(sc, off + i, &word);
584 dc_eeprom_getword(sc, off + i, &word);
585 ptr = (u_int16_t *)(dest + (i * 2));
596 * The following two routines are taken from the Macronix 98713
597 * Application Notes pp.19-21.
600 * Write a bit to the MII bus.
603 dc_mii_writebit(struct dc_softc *sc, int bit)
606 CSR_WRITE_4(sc, DC_SIO,
607 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
609 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
611 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
612 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
618 * Read a bit from the MII bus.
621 dc_mii_readbit(struct dc_softc *sc)
623 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
624 CSR_READ_4(sc, DC_SIO);
625 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
626 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
627 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
634 * Sync the PHYs by setting data bit and strobing the clock 32 times.
637 dc_mii_sync(struct dc_softc *sc)
641 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
643 for (i = 0; i < 32; i++)
644 dc_mii_writebit(sc, 1);
650 * Clock a series of bits through the MII.
653 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
657 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
658 dc_mii_writebit(sc, bits & i);
662 * Read an PHY register through the MII.
665 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
670 * Set up frame for RX.
672 frame->mii_stdelim = DC_MII_STARTDELIM;
673 frame->mii_opcode = DC_MII_READOP;
674 frame->mii_turnaround = 0;
683 * Send command/address info.
685 dc_mii_send(sc, frame->mii_stdelim, 2);
686 dc_mii_send(sc, frame->mii_opcode, 2);
687 dc_mii_send(sc, frame->mii_phyaddr, 5);
688 dc_mii_send(sc, frame->mii_regaddr, 5);
692 dc_mii_writebit(sc, 1);
693 dc_mii_writebit(sc, 0);
697 ack = dc_mii_readbit(sc);
700 * Now try reading data bits. If the ack failed, we still
701 * need to clock through 16 cycles to keep the PHY(s) in sync.
704 for(i = 0; i < 16; i++) {
710 for (i = 0x8000; i; i >>= 1) {
712 if (dc_mii_readbit(sc))
713 frame->mii_data |= i;
719 dc_mii_writebit(sc, 0);
720 dc_mii_writebit(sc, 0);
728 * Write to a PHY register through the MII.
731 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
734 * Set up frame for TX.
737 frame->mii_stdelim = DC_MII_STARTDELIM;
738 frame->mii_opcode = DC_MII_WRITEOP;
739 frame->mii_turnaround = DC_MII_TURNAROUND;
746 dc_mii_send(sc, frame->mii_stdelim, 2);
747 dc_mii_send(sc, frame->mii_opcode, 2);
748 dc_mii_send(sc, frame->mii_phyaddr, 5);
749 dc_mii_send(sc, frame->mii_regaddr, 5);
750 dc_mii_send(sc, frame->mii_turnaround, 2);
751 dc_mii_send(sc, frame->mii_data, 16);
754 dc_mii_writebit(sc, 0);
755 dc_mii_writebit(sc, 0);
761 dc_miibus_readreg(device_t dev, int phy, int reg)
763 struct dc_mii_frame frame;
765 int i, rval, phy_reg = 0;
767 sc = device_get_softc(dev);
768 bzero((char *)&frame, sizeof(frame));
771 * Note: both the AL981 and AN985 have internal PHYs,
772 * however the AL981 provides direct access to the PHY
773 * registers while the AN985 uses a serial MII interface.
774 * The AN985's MII interface is also buggy in that you
775 * can read from any MII address (0 to 31), but only address 1
776 * behaves normally. To deal with both cases, we pretend
777 * that the PHY is at MII address 1.
779 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
783 * Note: the ukphy probes of the RS7112 report a PHY at
784 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
785 * so we only respond to correct one.
787 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
790 if (sc->dc_pmode != DC_PMODE_MII) {
791 if (phy == (MII_NPHY - 1)) {
795 * Fake something to make the probe
796 * code think there's a PHY here.
798 return(BMSR_MEDIAMASK);
802 return(DC_VENDORID_LO);
803 return(DC_VENDORID_DEC);
807 return(DC_DEVICEID_82C168);
808 return(DC_DEVICEID_21143);
818 if (DC_IS_PNIC(sc)) {
819 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
820 (phy << 23) | (reg << 18));
821 for (i = 0; i < DC_TIMEOUT; i++) {
823 rval = CSR_READ_4(sc, DC_PN_MII);
824 if (!(rval & DC_PN_MII_BUSY)) {
826 return(rval == 0xFFFF ? 0 : rval);
832 if (DC_IS_COMET(sc)) {
835 phy_reg = DC_AL_BMCR;
838 phy_reg = DC_AL_BMSR;
841 phy_reg = DC_AL_VENID;
844 phy_reg = DC_AL_DEVID;
847 phy_reg = DC_AL_ANAR;
850 phy_reg = DC_AL_LPAR;
853 phy_reg = DC_AL_ANER;
856 if_printf(&sc->arpcom.ac_if,
857 "phy_read: bad phy register %x\n", reg);
862 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
869 frame.mii_phyaddr = phy;
870 frame.mii_regaddr = reg;
871 if (sc->dc_type == DC_TYPE_98713) {
872 phy_reg = CSR_READ_4(sc, DC_NETCFG);
873 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
875 dc_mii_readreg(sc, &frame);
876 if (sc->dc_type == DC_TYPE_98713)
877 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
879 return(frame.mii_data);
883 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
886 struct dc_mii_frame frame;
889 sc = device_get_softc(dev);
890 bzero((char *)&frame, sizeof(frame));
892 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
895 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
898 if (DC_IS_PNIC(sc)) {
899 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
900 (phy << 23) | (reg << 10) | data);
901 for (i = 0; i < DC_TIMEOUT; i++) {
902 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
908 if (DC_IS_COMET(sc)) {
911 phy_reg = DC_AL_BMCR;
914 phy_reg = DC_AL_BMSR;
917 phy_reg = DC_AL_VENID;
920 phy_reg = DC_AL_DEVID;
923 phy_reg = DC_AL_ANAR;
926 phy_reg = DC_AL_LPAR;
929 phy_reg = DC_AL_ANER;
932 if_printf(&sc->arpcom.ac_if,
933 "phy_write: bad phy register %x\n", reg);
938 CSR_WRITE_4(sc, phy_reg, data);
942 frame.mii_phyaddr = phy;
943 frame.mii_regaddr = reg;
944 frame.mii_data = data;
946 if (sc->dc_type == DC_TYPE_98713) {
947 phy_reg = CSR_READ_4(sc, DC_NETCFG);
948 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
950 dc_mii_writereg(sc, &frame);
951 if (sc->dc_type == DC_TYPE_98713)
952 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
958 dc_miibus_statchg(device_t dev)
961 struct mii_data *mii;
964 sc = device_get_softc(dev);
965 if (DC_IS_ADMTEK(sc))
968 mii = device_get_softc(sc->dc_miibus);
969 ifm = &mii->mii_media;
970 if (DC_IS_DAVICOM(sc) &&
971 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
972 dc_setcfg(sc, ifm->ifm_media);
973 sc->dc_if_media = ifm->ifm_media;
975 dc_setcfg(sc, mii->mii_media_active);
976 sc->dc_if_media = mii->mii_media_active;
983 * Special support for DM9102A cards with HomePNA PHYs. Note:
984 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
985 * to be impossible to talk to the management interface of the DM9801
986 * PHY (its MDIO pin is not connected to anything). Consequently,
987 * the driver has to just 'know' about the additional mode and deal
988 * with it itself. *sigh*
991 dc_miibus_mediainit(device_t dev)
994 struct mii_data *mii;
998 rev = pci_get_revid(dev);
1000 sc = device_get_softc(dev);
1001 mii = device_get_softc(sc->dc_miibus);
1002 ifm = &mii->mii_media;
1004 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1005 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1010 #define DC_BITS_512 9
1011 #define DC_BITS_128 7
1012 #define DC_BITS_64 6
1015 dc_crc_mask(struct dc_softc *sc)
1018 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1019 * chips is only 128 bits wide.
1021 if (sc->dc_flags & DC_128BIT_HASH)
1022 return ((1 << DC_BITS_128) - 1);
1024 /* The hash table on the MX98715BEC is only 64 bits wide. */
1025 if (sc->dc_flags & DC_64BIT_HASH)
1026 return ((1 << DC_BITS_64) - 1);
1028 return ((1 << DC_BITS_512) - 1);
1032 * 21143-style RX filter setup routine. Filter programming is done by
1033 * downloading a special setup frame into the TX engine. 21143, Macronix,
1034 * PNIC, PNIC II and Davicom chips are programmed this way.
1036 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1037 * address (our node address) and a 512-bit hash filter for multicast
1038 * frames. We also sneak the broadcast address into the hash filter since
1042 dc_setfilt_21143(struct dc_softc *sc)
1044 struct dc_desc *sframe;
1045 u_int32_t h, crc_mask, *sp;
1046 struct ifmultiaddr *ifma;
1050 ifp = &sc->arpcom.ac_if;
1052 i = sc->dc_cdata.dc_tx_prod;
1053 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1054 sc->dc_cdata.dc_tx_cnt++;
1055 sframe = &sc->dc_ldata->dc_tx_list[i];
1056 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1057 bzero((char *)sp, DC_SFRAME_LEN);
1059 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1060 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1061 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1063 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1065 /* If we want promiscuous mode, set the allframes bit. */
1066 if (ifp->if_flags & IFF_PROMISC)
1067 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1069 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1071 if (ifp->if_flags & IFF_ALLMULTI)
1072 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1074 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1076 crc_mask = dc_crc_mask(sc);
1077 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1078 if (ifma->ifma_addr->sa_family != AF_LINK)
1081 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1082 ETHER_ADDR_LEN) & crc_mask;
1083 sp[h >> 4] |= 1 << (h & 0xF);
1086 if (ifp->if_flags & IFF_BROADCAST) {
1087 h = ether_crc32_le(ifp->if_broadcastaddr,
1088 ETHER_ADDR_LEN) & crc_mask;
1089 sp[h >> 4] |= 1 << (h & 0xF);
1092 /* Set our MAC address */
1093 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1094 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1095 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1097 sframe->dc_status = DC_TXSTAT_OWN;
1098 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1101 * The PNIC takes an exceedingly long time to process its
1102 * setup frame; wait 10ms after posting the setup frame
1103 * before proceeding, just so it has time to swallow its
1114 dc_setfilt_admtek(struct dc_softc *sc)
1119 u_int32_t hashes[2] = { 0, 0 };
1120 struct ifmultiaddr *ifma;
1122 ifp = &sc->arpcom.ac_if;
1124 /* Init our MAC address */
1125 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1126 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1128 /* If we want promiscuous mode, set the allframes bit. */
1129 if (ifp->if_flags & IFF_PROMISC)
1130 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1132 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1134 if (ifp->if_flags & IFF_ALLMULTI)
1135 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1137 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1139 /* first, zot all the existing hash bits */
1140 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1141 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1144 * If we're already in promisc or allmulti mode, we
1145 * don't have to bother programming the multicast filter.
1147 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1150 /* now program new ones */
1151 if (DC_IS_CENTAUR(sc))
1152 crc_mask = dc_crc_mask(sc);
1155 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1156 if (ifma->ifma_addr->sa_family != AF_LINK)
1158 if (DC_IS_CENTAUR(sc)) {
1160 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1161 ETHER_ADDR_LEN) & crc_mask;
1164 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1166 h = (h >> 26) & crc_mask;
1169 hashes[0] |= (1 << h);
1171 hashes[1] |= (1 << (h - 32));
1174 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1175 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1181 dc_setfilt_asix(struct dc_softc *sc)
1185 u_int32_t hashes[2] = { 0, 0 };
1186 struct ifmultiaddr *ifma;
1188 ifp = &sc->arpcom.ac_if;
1190 /* Init our MAC address */
1191 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1192 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1193 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1194 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1195 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1196 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1198 /* If we want promiscuous mode, set the allframes bit. */
1199 if (ifp->if_flags & IFF_PROMISC)
1200 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1202 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1204 if (ifp->if_flags & IFF_ALLMULTI)
1205 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1207 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1210 * The ASIX chip has a special bit to enable reception
1211 * of broadcast frames.
1213 if (ifp->if_flags & IFF_BROADCAST)
1214 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1216 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1218 /* first, zot all the existing hash bits */
1219 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1220 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1221 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1222 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1225 * If we're already in promisc or allmulti mode, we
1226 * don't have to bother programming the multicast filter.
1228 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1231 /* now program new ones */
1232 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1233 if (ifma->ifma_addr->sa_family != AF_LINK)
1236 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1238 h = (h >> 26) & 0x3f;
1240 hashes[0] |= (1 << h);
1242 hashes[1] |= (1 << (h - 32));
1245 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1246 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1247 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1248 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1254 dc_setfilt_xircom(struct dc_softc *sc)
1256 struct dc_desc *sframe;
1258 struct ifmultiaddr *ifma;
1262 ifp = &sc->arpcom.ac_if;
1263 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1265 i = sc->dc_cdata.dc_tx_prod;
1266 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1267 sc->dc_cdata.dc_tx_cnt++;
1268 sframe = &sc->dc_ldata->dc_tx_list[i];
1269 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1270 bzero(sp, DC_SFRAME_LEN);
1272 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1273 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1274 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1276 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1278 /* If we want promiscuous mode, set the allframes bit. */
1279 if (ifp->if_flags & IFF_PROMISC)
1280 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1282 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1284 if (ifp->if_flags & IFF_ALLMULTI)
1285 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1287 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1289 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1290 if (ifma->ifma_addr->sa_family != AF_LINK)
1292 h = dc_mchash_xircom(sc,
1293 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1294 sp[h >> 4] |= 1 << (h & 0xF);
1297 if (ifp->if_flags & IFF_BROADCAST) {
1298 h = dc_mchash_xircom(sc, (caddr_t)ðerbroadcastaddr);
1299 sp[h >> 4] |= 1 << (h & 0xF);
1302 /* Set our MAC address */
1303 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1304 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1305 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1308 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1309 ifp->if_flags |= IFF_RUNNING;
1310 sframe->dc_status = DC_TXSTAT_OWN;
1311 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1322 dc_setfilt(struct dc_softc *sc)
1324 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1325 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1326 dc_setfilt_21143(sc);
1329 dc_setfilt_asix(sc);
1331 if (DC_IS_ADMTEK(sc))
1332 dc_setfilt_admtek(sc);
1334 if (DC_IS_XIRCOM(sc))
1335 dc_setfilt_xircom(sc);
1339 * In order to fiddle with the
1340 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1341 * first have to put the transmit and/or receive logic in the idle state.
1344 dc_setcfg(struct dc_softc *sc, int media)
1349 if (IFM_SUBTYPE(media) == IFM_NONE)
1352 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1354 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1356 for (i = 0; i < DC_TIMEOUT; i++) {
1357 isr = CSR_READ_4(sc, DC_ISR);
1358 if ((isr & DC_ISR_TX_IDLE) &&
1359 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1360 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1365 if (i == DC_TIMEOUT) {
1366 if_printf(&sc->arpcom.ac_if,
1367 "failed to force tx and rx to idle state\n");
1371 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1372 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1373 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1374 if (sc->dc_pmode == DC_PMODE_MII) {
1377 if (DC_IS_INTEL(sc)) {
1378 /* there's a write enable bit here that reads as 1 */
1379 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1380 watchdogreg &= ~DC_WDOG_CTLWREN;
1381 watchdogreg |= DC_WDOG_JABBERDIS;
1382 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1384 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1386 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1387 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1388 if (sc->dc_type == DC_TYPE_98713)
1389 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1390 DC_NETCFG_SCRAMBLER));
1391 if (!DC_IS_DAVICOM(sc))
1392 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1393 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1394 if (DC_IS_INTEL(sc))
1395 dc_apply_fixup(sc, IFM_AUTO);
1397 if (DC_IS_PNIC(sc)) {
1398 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1399 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1400 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1402 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1403 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1404 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1405 if (DC_IS_INTEL(sc))
1407 (media & IFM_GMASK) == IFM_FDX ?
1408 IFM_100_TX|IFM_FDX : IFM_100_TX);
1412 if (IFM_SUBTYPE(media) == IFM_10_T) {
1413 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1414 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1415 if (sc->dc_pmode == DC_PMODE_MII) {
1418 /* there's a write enable bit here that reads as 1 */
1419 if (DC_IS_INTEL(sc)) {
1420 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1421 watchdogreg &= ~DC_WDOG_CTLWREN;
1422 watchdogreg |= DC_WDOG_JABBERDIS;
1423 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1425 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1427 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1428 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1429 if (sc->dc_type == DC_TYPE_98713)
1430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1431 if (!DC_IS_DAVICOM(sc))
1432 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1433 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1434 if (DC_IS_INTEL(sc))
1435 dc_apply_fixup(sc, IFM_AUTO);
1437 if (DC_IS_PNIC(sc)) {
1438 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1439 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1440 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1442 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1443 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1444 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1445 if (DC_IS_INTEL(sc)) {
1446 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1447 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1448 if ((media & IFM_GMASK) == IFM_FDX)
1449 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1451 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1452 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1453 DC_CLRBIT(sc, DC_10BTCTRL,
1454 DC_TCTL_AUTONEGENBL);
1456 (media & IFM_GMASK) == IFM_FDX ?
1457 IFM_10_T|IFM_FDX : IFM_10_T);
1464 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1465 * PHY and we want HomePNA mode, set the portsel bit to turn
1466 * on the external MII port.
1468 if (DC_IS_DAVICOM(sc)) {
1469 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1473 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1477 if ((media & IFM_GMASK) == IFM_FDX) {
1478 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1479 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1480 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1482 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1483 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1484 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1488 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1494 dc_reset(struct dc_softc *sc)
1498 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1500 for (i = 0; i < DC_TIMEOUT; i++) {
1502 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1506 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) ||
1507 DC_IS_CONEXANT(sc)) {
1509 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1513 if (i == DC_TIMEOUT)
1514 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
1516 /* Wait a little while for the chip to get its brains in order. */
1519 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1520 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1521 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1524 * Bring the SIA out of reset. In some cases, it looks
1525 * like failing to unreset the SIA soon enough gets it
1526 * into a state where it will never come out of reset
1527 * until we reset the whole chip again.
1529 if (DC_IS_INTEL(sc)) {
1530 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1531 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1532 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1538 static const struct dc_type *
1539 dc_devtype(device_t dev)
1541 const struct dc_type *t;
1546 while(t->dc_name != NULL) {
1547 if ((pci_get_vendor(dev) == t->dc_vid) &&
1548 (pci_get_device(dev) == t->dc_did)) {
1549 /* Check the PCI revision */
1550 rev = pci_get_revid(dev);
1551 if (t->dc_did == DC_DEVICEID_98713 &&
1552 rev >= DC_REVISION_98713A)
1554 if (t->dc_did == DC_DEVICEID_98713_CP &&
1555 rev >= DC_REVISION_98713A)
1557 if (t->dc_did == DC_DEVICEID_987x5 &&
1558 rev >= DC_REVISION_98715AEC_C)
1560 if (t->dc_did == DC_DEVICEID_987x5 &&
1561 rev >= DC_REVISION_98725)
1563 if (t->dc_did == DC_DEVICEID_AX88140A &&
1564 rev >= DC_REVISION_88141)
1566 if (t->dc_did == DC_DEVICEID_82C168 &&
1567 rev >= DC_REVISION_82C169)
1569 if (t->dc_did == DC_DEVICEID_DM9102 &&
1570 rev >= DC_REVISION_DM9102A)
1581 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1582 * IDs against our list and return a device name if we find a match.
1583 * We do a little bit of extra work to identify the exact type of
1584 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1585 * but different revision IDs. The same is true for 98715/98715A
1586 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1587 * cases, the exact chip revision affects driver behavior.
1590 dc_probe(device_t dev)
1592 const struct dc_type *t;
1594 t = dc_devtype(dev);
1596 struct dc_softc *sc = device_get_softc(dev);
1598 /* Need this info to decide on a chip type. */
1600 device_set_desc(dev, t->dc_name);
1608 dc_acpi(device_t dev)
1610 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1611 uint32_t iobase, membase, irq;
1612 struct dc_softc *sc;
1614 /* Save important PCI config data. */
1615 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1616 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1617 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1619 sc = device_get_softc(dev);
1620 /* Reset the power state. */
1621 if_printf(&sc->arpcom.ac_if,
1622 "chip is in D%d power mode "
1623 "-- setting to D0\n", pci_get_powerstate(dev));
1624 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1626 /* Restore PCI config data. */
1627 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1628 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1629 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1634 dc_apply_fixup(struct dc_softc *sc, int media)
1636 struct dc_mediainfo *m;
1644 if (m->dc_media == media)
1652 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1653 reg = (p[0] | (p[1] << 8)) << 16;
1654 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1657 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1658 reg = (p[0] | (p[1] << 8)) << 16;
1659 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1666 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1668 struct dc_mediainfo *m;
1670 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1671 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){
1672 case DC_SIA_CODE_10BT:
1673 m->dc_media = IFM_10_T;
1676 case DC_SIA_CODE_10BT_FDX:
1677 m->dc_media = IFM_10_T|IFM_FDX;
1680 case DC_SIA_CODE_10B2:
1681 m->dc_media = IFM_10_2;
1684 case DC_SIA_CODE_10B5:
1685 m->dc_media = IFM_10_5;
1688 if (l->dc_sia_code & DC_SIA_CODE_EXT){
1691 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1695 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1698 m->dc_next = sc->dc_mi;
1701 sc->dc_pmode = DC_PMODE_SIA;
1707 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1709 struct dc_mediainfo *m;
1711 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1712 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1713 m->dc_media = IFM_100_TX;
1715 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1716 m->dc_media = IFM_100_TX|IFM_FDX;
1719 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1721 m->dc_next = sc->dc_mi;
1724 sc->dc_pmode = DC_PMODE_SYM;
1730 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1733 struct dc_mediainfo *m;
1735 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1736 /* We abuse IFM_AUTO to represent MII. */
1737 m->dc_media = IFM_AUTO;
1738 m->dc_gp_len = l->dc_gpr_len;
1741 p += sizeof(struct dc_eblock_mii);
1743 p += 2 * l->dc_gpr_len;
1744 m->dc_reset_len = *p;
1746 m->dc_reset_ptr = p;
1748 m->dc_next = sc->dc_mi;
1755 dc_read_srom(struct dc_softc *sc, int bits)
1760 sc->dc_srom = kmalloc(size, M_DEVBUF, M_INTWAIT);
1761 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1765 dc_parse_21143_srom(struct dc_softc *sc)
1767 struct dc_leaf_hdr *lhdr;
1768 struct dc_eblock_hdr *hdr;
1774 loff = sc->dc_srom[27];
1775 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1778 ptr += sizeof(struct dc_leaf_hdr) - 1;
1780 * Look if we got a MII media block.
1782 for (i = 0; i < lhdr->dc_mcnt; i++) {
1783 hdr = (struct dc_eblock_hdr *)ptr;
1784 if (hdr->dc_type == DC_EBLOCK_MII)
1787 ptr += (hdr->dc_len & 0x7F);
1792 * Do the same thing again. Only use SIA and SYM media
1793 * blocks if no MII media block is available.
1796 ptr += sizeof(struct dc_leaf_hdr) - 1;
1797 for (i = 0; i < lhdr->dc_mcnt; i++) {
1798 hdr = (struct dc_eblock_hdr *)ptr;
1799 switch(hdr->dc_type) {
1801 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1805 dc_decode_leaf_sia(sc,
1806 (struct dc_eblock_sia *)hdr);
1810 dc_decode_leaf_sym(sc,
1811 (struct dc_eblock_sym *)hdr);
1814 /* Don't care. Yet. */
1817 ptr += (hdr->dc_len & 0x7F);
1825 * Attach the interface. Allocate softc structures, do ifmedia
1826 * setup and ethernet/BPF attach.
1829 dc_attach(device_t dev)
1832 u_char eaddr[ETHER_ADDR_LEN];
1834 struct dc_softc *sc;
1837 int error = 0, rid, mac_offset;
1840 sc = device_get_softc(dev);
1841 callout_init(&sc->dc_stat_timer);
1843 ifp = &sc->arpcom.ac_if;
1844 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1847 * Handle power management nonsense.
1852 * Map control/status registers.
1854 pci_enable_busmaster(dev);
1857 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1859 if (sc->dc_res == NULL) {
1860 device_printf(dev, "couldn't map ports/memory\n");
1865 sc->dc_btag = rman_get_bustag(sc->dc_res);
1866 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1868 /* Allocate interrupt */
1870 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1871 RF_SHAREABLE | RF_ACTIVE);
1873 if (sc->dc_irq == NULL) {
1874 device_printf(dev, "couldn't map interrupt\n");
1879 revision = pci_get_revid(dev);
1881 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
1882 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 &&
1883 sc->dc_info->dc_did != DC_DEVICEID_X3201)
1884 dc_eeprom_width(sc);
1886 switch(sc->dc_info->dc_did) {
1887 case DC_DEVICEID_21143:
1888 sc->dc_type = DC_TYPE_21143;
1889 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1890 sc->dc_flags |= DC_REDUCED_MII_POLL;
1891 /* Save EEPROM contents so we can parse them later. */
1892 dc_read_srom(sc, sc->dc_romwidth);
1894 case DC_DEVICEID_DM9009:
1895 case DC_DEVICEID_DM9100:
1896 case DC_DEVICEID_DM9102:
1897 sc->dc_type = DC_TYPE_DM9102;
1898 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1899 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1900 sc->dc_flags |= DC_TX_ALIGN;
1901 sc->dc_pmode = DC_PMODE_MII;
1902 /* Increase the latency timer value. */
1903 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1904 command &= 0xFFFF00FF;
1905 command |= 0x00008000;
1906 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1908 case DC_DEVICEID_AL981:
1909 sc->dc_type = DC_TYPE_AL981;
1910 sc->dc_flags |= DC_TX_USE_TX_INTR;
1911 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1912 sc->dc_pmode = DC_PMODE_MII;
1913 dc_read_srom(sc, sc->dc_romwidth);
1915 case DC_DEVICEID_AN985:
1916 case DC_DEVICEID_ADM9511:
1917 case DC_DEVICEID_ADM9513:
1918 case DC_DEVICEID_FA511:
1919 case DC_DEVICEID_EN2242:
1920 case DC_DEVICEID_3CSOHOB:
1921 sc->dc_type = DC_TYPE_AN985;
1922 sc->dc_flags |= DC_64BIT_HASH;
1923 sc->dc_flags |= DC_TX_USE_TX_INTR;
1924 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1925 sc->dc_pmode = DC_PMODE_MII;
1927 case DC_DEVICEID_98713:
1928 case DC_DEVICEID_98713_CP:
1929 if (revision < DC_REVISION_98713A) {
1930 sc->dc_type = DC_TYPE_98713;
1932 if (revision >= DC_REVISION_98713A) {
1933 sc->dc_type = DC_TYPE_98713A;
1934 sc->dc_flags |= DC_21143_NWAY;
1936 sc->dc_flags |= DC_REDUCED_MII_POLL;
1937 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1939 case DC_DEVICEID_987x5:
1940 case DC_DEVICEID_EN1217:
1942 * Macronix MX98715AEC-C/D/E parts have only a
1943 * 128-bit hash table. We need to deal with these
1944 * in the same manner as the PNIC II so that we
1945 * get the right number of bits out of the
1948 if (revision >= DC_REVISION_98715AEC_C &&
1949 revision < DC_REVISION_98725)
1950 sc->dc_flags |= DC_128BIT_HASH;
1951 sc->dc_type = DC_TYPE_987x5;
1952 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1953 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1955 case DC_DEVICEID_98727:
1956 sc->dc_type = DC_TYPE_987x5;
1957 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1958 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1960 case DC_DEVICEID_82C115:
1961 sc->dc_type = DC_TYPE_PNICII;
1962 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
1963 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1965 case DC_DEVICEID_82C168:
1966 sc->dc_type = DC_TYPE_PNIC;
1967 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
1968 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1969 sc->dc_pnic_rx_buf = kmalloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK);
1970 if (revision < DC_REVISION_82C169)
1971 sc->dc_pmode = DC_PMODE_SYM;
1973 case DC_DEVICEID_AX88140A:
1974 sc->dc_type = DC_TYPE_ASIX;
1975 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
1976 sc->dc_flags |= DC_REDUCED_MII_POLL;
1977 sc->dc_pmode = DC_PMODE_MII;
1979 case DC_DEVICEID_RS7112:
1980 sc->dc_type = DC_TYPE_CONEXANT;
1981 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1982 sc->dc_flags |= DC_REDUCED_MII_POLL;
1983 sc->dc_pmode = DC_PMODE_MII;
1984 dc_read_srom(sc, sc->dc_romwidth);
1986 case DC_DEVICEID_X3201:
1987 sc->dc_type = DC_TYPE_XIRCOM;
1988 sc->dc_flags |= (DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
1991 * We don't actually need to coalesce, but we're doing
1992 * it to obtain a double word aligned buffer.
1993 * The DC_TX_COALESCE flag is required.
1995 sc->dc_pmode = DC_PMODE_MII;
1998 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did);
2002 /* Save the cache line size. */
2003 if (DC_IS_DAVICOM(sc))
2004 sc->dc_cachesize = 0;
2006 sc->dc_cachesize = pci_read_config(dev,
2007 DC_PCI_CFLT, 4) & 0xFF;
2009 /* Reset the adapter. */
2012 /* Take 21143 out of snooze mode */
2013 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2014 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2015 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
2016 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2020 * Try to learn something about the supported media.
2021 * We know that ASIX and ADMtek and Davicom devices
2022 * will *always* be using MII media, so that's a no-brainer.
2023 * The tricky ones are the Macronix/PNIC II and the
2026 if (DC_IS_INTEL(sc))
2027 dc_parse_21143_srom(sc);
2028 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2029 if (sc->dc_type == DC_TYPE_98713)
2030 sc->dc_pmode = DC_PMODE_MII;
2032 sc->dc_pmode = DC_PMODE_SYM;
2033 } else if (!sc->dc_pmode)
2034 sc->dc_pmode = DC_PMODE_MII;
2037 * Get station address from the EEPROM.
2039 switch(sc->dc_type) {
2041 case DC_TYPE_98713A:
2043 case DC_TYPE_PNICII:
2044 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2045 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2046 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2049 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2051 case DC_TYPE_DM9102:
2054 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2058 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0);
2059 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1);
2061 case DC_TYPE_CONEXANT:
2062 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2064 case DC_TYPE_XIRCOM:
2065 /* The MAC comes from the CIS */
2066 mac = pci_get_ether(dev);
2068 device_printf(dev, "No station address in CIS!\n");
2072 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2075 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2079 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
2080 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
2082 if (sc->dc_ldata == NULL) {
2083 device_printf(dev, "no memory for list buffers!\n");
2088 bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2091 ifp->if_mtu = ETHERMTU;
2092 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2093 ifp->if_ioctl = dc_ioctl;
2094 ifp->if_start = dc_start;
2095 #ifdef DEVICE_POLLING
2096 ifp->if_poll = dc_poll;
2098 ifp->if_watchdog = dc_watchdog;
2099 ifp->if_init = dc_init;
2100 ifp->if_baudrate = 10000000;
2101 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2102 ifq_set_ready(&ifp->if_snd);
2105 * Do MII setup. If this is a 21143, check for a PHY on the
2106 * MII bus after applying any necessary fixups to twiddle the
2107 * GPIO bits. If we don't end up finding a PHY, restore the
2108 * old selection (SIA only or SIA/SYM) and attach the dcphy
2111 if (DC_IS_INTEL(sc)) {
2112 dc_apply_fixup(sc, IFM_AUTO);
2114 sc->dc_pmode = DC_PMODE_MII;
2118 * Setup General Purpose port mode and data so the tulip can talk
2119 * to the MII. This needs to be done before mii_phy_probe so that
2120 * we can actually see them.
2122 if (DC_IS_XIRCOM(sc)) {
2123 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2124 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2126 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2127 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2131 error = mii_phy_probe(dev, &sc->dc_miibus,
2132 dc_ifmedia_upd, dc_ifmedia_sts);
2134 if (error && DC_IS_INTEL(sc)) {
2136 if (sc->dc_pmode != DC_PMODE_SIA)
2137 sc->dc_pmode = DC_PMODE_SYM;
2138 sc->dc_flags |= DC_21143_NWAY;
2139 mii_phy_probe(dev, &sc->dc_miibus,
2140 dc_ifmedia_upd, dc_ifmedia_sts);
2142 * For non-MII cards, we need to have the 21143
2143 * drive the LEDs. Except there are some systems
2144 * like the NEC VersaPro NoteBook PC which have no
2145 * LEDs, and twiddling these bits has adverse effects
2146 * on them. (I.e. you suddenly can't get a link.)
2148 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2149 sc->dc_flags |= DC_TULIP_LEDS;
2154 device_printf(dev, "MII without any PHY!\n");
2160 * Call MI attach routine.
2162 ether_ifattach(ifp, eaddr, NULL);
2164 if (DC_IS_ADMTEK(sc)) {
2166 * Set automatic TX underrun recovery for the ADMtek chips
2168 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2172 * Tell the upper layer(s) we support long frames.
2174 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2176 error = bus_setup_intr(dev, sc->dc_irq, INTR_NETSAFE,
2177 dc_intr, sc, &sc->dc_intrhand,
2178 ifp->if_serializer);
2180 ether_ifdetach(ifp);
2181 device_printf(dev, "couldn't set up irq\n");
2193 dc_detach(device_t dev)
2195 struct dc_softc *sc = device_get_softc(dev);
2196 struct ifnet *ifp = &sc->arpcom.ac_if;
2197 struct dc_mediainfo *m;
2199 if (device_is_attached(dev)) {
2200 lwkt_serialize_enter(ifp->if_serializer);
2202 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2203 lwkt_serialize_exit(ifp->if_serializer);
2205 ether_ifdetach(ifp);
2209 device_delete_child(dev, sc->dc_miibus);
2210 bus_generic_detach(dev);
2213 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2215 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2218 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2219 if (sc->dc_pnic_rx_buf != NULL)
2220 kfree(sc->dc_pnic_rx_buf, M_DEVBUF);
2222 while (sc->dc_mi != NULL) {
2223 m = sc->dc_mi->dc_next;
2224 kfree(sc->dc_mi, M_DEVBUF);
2229 kfree(sc->dc_srom, M_DEVBUF);
2235 * Initialize the transmit descriptors.
2238 dc_list_tx_init(struct dc_softc *sc)
2240 struct dc_chain_data *cd;
2241 struct dc_list_data *ld;
2246 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2247 if (i == (DC_TX_LIST_CNT - 1)) {
2248 ld->dc_tx_list[i].dc_next =
2249 vtophys(&ld->dc_tx_list[0]);
2251 ld->dc_tx_list[i].dc_next =
2252 vtophys(&ld->dc_tx_list[i + 1]);
2254 cd->dc_tx_chain[i] = NULL;
2255 ld->dc_tx_list[i].dc_data = 0;
2256 ld->dc_tx_list[i].dc_ctl = 0;
2259 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2266 * Initialize the RX descriptors and allocate mbufs for them. Note that
2267 * we arrange the descriptors in a closed ring, so that the last descriptor
2268 * points back to the first.
2271 dc_list_rx_init(struct dc_softc *sc)
2273 struct dc_chain_data *cd;
2274 struct dc_list_data *ld;
2280 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2281 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2283 if (i == (DC_RX_LIST_CNT - 1)) {
2284 ld->dc_rx_list[i].dc_next =
2285 vtophys(&ld->dc_rx_list[0]);
2287 ld->dc_rx_list[i].dc_next =
2288 vtophys(&ld->dc_rx_list[i + 1]);
2298 * Initialize an RX descriptor and attach an MBUF cluster.
2301 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m)
2303 struct mbuf *m_new = NULL;
2306 c = &sc->dc_ldata->dc_rx_list[i];
2309 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2312 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2315 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2316 m_new->m_data = m_new->m_ext.ext_buf;
2319 m_adj(m_new, sizeof(u_int64_t));
2322 * If this is a PNIC chip, zero the buffer. This is part
2323 * of the workaround for the receive bug in the 82c168 and
2326 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2327 bzero((char *)mtod(m_new, char *), m_new->m_len);
2329 sc->dc_cdata.dc_rx_chain[i] = m_new;
2330 c->dc_data = vtophys(mtod(m_new, caddr_t));
2331 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2332 c->dc_status = DC_RXSTAT_OWN;
2339 * The PNIC chip has a terrible bug in it that manifests itself during
2340 * periods of heavy activity. The exact mode of failure if difficult to
2341 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2342 * will happen on slow machines. The bug is that sometimes instead of
2343 * uploading one complete frame during reception, it uploads what looks
2344 * like the entire contents of its FIFO memory. The frame we want is at
2345 * the end of the whole mess, but we never know exactly how much data has
2346 * been uploaded, so salvaging the frame is hard.
2348 * There is only one way to do it reliably, and it's disgusting.
2349 * Here's what we know:
2351 * - We know there will always be somewhere between one and three extra
2352 * descriptors uploaded.
2354 * - We know the desired received frame will always be at the end of the
2355 * total data upload.
2357 * - We know the size of the desired received frame because it will be
2358 * provided in the length field of the status word in the last descriptor.
2360 * Here's what we do:
2362 * - When we allocate buffers for the receive ring, we bzero() them.
2363 * This means that we know that the buffer contents should be all
2364 * zeros, except for data uploaded by the chip.
2366 * - We also force the PNIC chip to upload frames that include the
2367 * ethernet CRC at the end.
2369 * - We gather all of the bogus frame data into a single buffer.
2371 * - We then position a pointer at the end of this buffer and scan
2372 * backwards until we encounter the first non-zero byte of data.
2373 * This is the end of the received frame. We know we will encounter
2374 * some data at the end of the frame because the CRC will always be
2375 * there, so even if the sender transmits a packet of all zeros,
2376 * we won't be fooled.
2378 * - We know the size of the actual received frame, so we subtract
2379 * that value from the current pointer location. This brings us
2380 * to the start of the actual received packet.
2382 * - We copy this into an mbuf and pass it on, along with the actual
2385 * The performance hit is tremendous, but it beats dropping frames all
2389 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2391 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2393 struct dc_desc *cur_rx;
2394 struct dc_desc *c = NULL;
2395 struct mbuf *m = NULL;
2398 u_int32_t rxstat = 0;
2400 i = sc->dc_pnic_rx_bug_save;
2401 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2402 ptr = sc->dc_pnic_rx_buf;
2403 bzero(ptr, DC_RXLEN * 5);
2405 /* Copy all the bytes from the bogus buffers. */
2407 c = &sc->dc_ldata->dc_rx_list[i];
2408 rxstat = c->dc_status;
2409 m = sc->dc_cdata.dc_rx_chain[i];
2410 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2412 /* If this is the last buffer, break out. */
2413 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2415 dc_newbuf(sc, i, m);
2416 DC_INC(i, DC_RX_LIST_CNT);
2419 /* Find the length of the actual receive frame. */
2420 total_len = DC_RXBYTES(rxstat);
2422 /* Scan backwards until we hit a non-zero byte. */
2427 if ((uintptr_t)(ptr) & 0x3)
2430 /* Now find the start of the frame. */
2432 if (ptr < sc->dc_pnic_rx_buf)
2433 ptr = sc->dc_pnic_rx_buf;
2436 * Now copy the salvaged frame to the last mbuf and fake up
2437 * the status word to make it look like a successful
2440 dc_newbuf(sc, i, m);
2441 bcopy(ptr, mtod(m, char *), total_len);
2442 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2448 * This routine searches the RX ring for dirty descriptors in the
2449 * event that the rxeof routine falls out of sync with the chip's
2450 * current descriptor pointer. This may happen sometimes as a result
2451 * of a "no RX buffer available" condition that happens when the chip
2452 * consumes all of the RX buffers before the driver has a chance to
2453 * process the RX ring. This routine may need to be called more than
2454 * once to bring the driver back in sync with the chip, however we
2455 * should still be getting RX DONE interrupts to drive the search
2456 * for new packets in the RX ring, so we should catch up eventually.
2459 dc_rx_resync(struct dc_softc *sc)
2462 struct dc_desc *cur_rx;
2464 pos = sc->dc_cdata.dc_rx_prod;
2466 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2467 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2468 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2470 DC_INC(pos, DC_RX_LIST_CNT);
2473 /* If the ring really is empty, then just return. */
2474 if (i == DC_RX_LIST_CNT)
2477 /* We've fallen behing the chip: catch it. */
2478 sc->dc_cdata.dc_rx_prod = pos;
2484 * A frame has been uploaded: pass the resulting mbuf chain up to
2485 * the higher level protocols.
2488 dc_rxeof(struct dc_softc *sc)
2492 struct dc_desc *cur_rx;
2493 int i, total_len = 0;
2496 ifp = &sc->arpcom.ac_if;
2497 i = sc->dc_cdata.dc_rx_prod;
2499 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2501 #ifdef DEVICE_POLLING
2502 if (ifp->if_flags & IFF_POLLING) {
2503 if (sc->rxcycles <= 0)
2507 #endif /* DEVICE_POLLING */
2508 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2509 rxstat = cur_rx->dc_status;
2510 m = sc->dc_cdata.dc_rx_chain[i];
2511 total_len = DC_RXBYTES(rxstat);
2513 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2514 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2515 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2516 sc->dc_pnic_rx_bug_save = i;
2517 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2518 DC_INC(i, DC_RX_LIST_CNT);
2521 dc_pnic_rx_bug_war(sc, i);
2522 rxstat = cur_rx->dc_status;
2523 total_len = DC_RXBYTES(rxstat);
2527 sc->dc_cdata.dc_rx_chain[i] = NULL;
2530 * If an error occurs, update stats, clear the
2531 * status word and leave the mbuf cluster in place:
2532 * it should simply get re-used next time this descriptor
2533 * comes up in the ring. However, don't report long
2534 * frames as errors since they could be vlans
2536 if ((rxstat & DC_RXSTAT_RXERR)){
2537 if (!(rxstat & DC_RXSTAT_GIANT) ||
2538 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2539 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2540 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2542 if (rxstat & DC_RXSTAT_COLLSEEN)
2543 ifp->if_collisions++;
2544 dc_newbuf(sc, i, m);
2545 if (rxstat & DC_RXSTAT_CRCERR) {
2546 DC_INC(i, DC_RX_LIST_CNT);
2555 /* No errors; receive the packet. */
2556 total_len -= ETHER_CRC_LEN;
2560 * On the x86 we do not have alignment problems, so try to
2561 * allocate a new buffer for the receive ring, and pass up
2562 * the one where the packet is already, saving the expensive
2563 * copy done in m_devget().
2564 * If we are on an architecture with alignment problems, or
2565 * if the allocation fails, then use m_devget and leave the
2566 * existing buffer in the receive ring.
2568 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2569 m->m_pkthdr.rcvif = ifp;
2570 m->m_pkthdr.len = m->m_len = total_len;
2571 DC_INC(i, DC_RX_LIST_CNT);
2577 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2578 total_len + ETHER_ALIGN, 0, ifp, NULL);
2579 dc_newbuf(sc, i, m);
2580 DC_INC(i, DC_RX_LIST_CNT);
2585 m_adj(m0, ETHER_ALIGN);
2590 ifp->if_input(ifp, m);
2593 sc->dc_cdata.dc_rx_prod = i;
2597 * A frame was downloaded to the chip. It's safe for us to clean up
2602 dc_txeof(struct dc_softc *sc)
2604 struct dc_desc *cur_tx = NULL;
2608 ifp = &sc->arpcom.ac_if;
2611 * Go through our tx list and free mbufs for those
2612 * frames that have been transmitted.
2614 idx = sc->dc_cdata.dc_tx_cons;
2615 while(idx != sc->dc_cdata.dc_tx_prod) {
2618 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2619 txstat = cur_tx->dc_status;
2621 if (txstat & DC_TXSTAT_OWN)
2624 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2625 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2626 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2628 * Yes, the PNIC is so brain damaged
2629 * that it will sometimes generate a TX
2630 * underrun error while DMAing the RX
2631 * filter setup frame. If we detect this,
2632 * we have to send the setup frame again,
2633 * or else the filter won't be programmed
2636 if (DC_IS_PNIC(sc)) {
2637 if (txstat & DC_TXSTAT_ERRSUM)
2640 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2642 sc->dc_cdata.dc_tx_cnt--;
2643 DC_INC(idx, DC_TX_LIST_CNT);
2647 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2649 * XXX: Why does my Xircom taunt me so?
2650 * For some reason Conexant chips like
2651 * setting the CARRLOST flag even when
2652 * the carrier is there. In CURRENT we
2653 * have the same problem for Xircom
2656 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2657 sc->dc_pmode == DC_PMODE_MII &&
2658 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2659 DC_TXSTAT_NOCARRIER)))
2660 txstat &= ~DC_TXSTAT_ERRSUM;
2662 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2663 sc->dc_pmode == DC_PMODE_MII &&
2664 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2665 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2666 txstat &= ~DC_TXSTAT_ERRSUM;
2669 if (txstat & DC_TXSTAT_ERRSUM) {
2671 if (txstat & DC_TXSTAT_EXCESSCOLL)
2672 ifp->if_collisions++;
2673 if (txstat & DC_TXSTAT_LATECOLL)
2674 ifp->if_collisions++;
2675 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2681 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2684 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2685 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2686 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2689 sc->dc_cdata.dc_tx_cnt--;
2690 DC_INC(idx, DC_TX_LIST_CNT);
2693 if (idx != sc->dc_cdata.dc_tx_cons) {
2694 /* some buffers have been freed */
2695 sc->dc_cdata.dc_tx_cons = idx;
2696 ifp->if_flags &= ~IFF_OACTIVE;
2698 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2706 struct dc_softc *sc = xsc;
2707 struct ifnet *ifp = &sc->arpcom.ac_if;
2708 struct mii_data *mii;
2711 lwkt_serialize_enter(ifp->if_serializer);
2713 mii = device_get_softc(sc->dc_miibus);
2715 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2716 if (sc->dc_flags & DC_21143_NWAY) {
2717 r = CSR_READ_4(sc, DC_10BTSTAT);
2718 if (IFM_SUBTYPE(mii->mii_media_active) ==
2719 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2723 if (IFM_SUBTYPE(mii->mii_media_active) ==
2724 IFM_10_T && (r & DC_TSTAT_LS10)) {
2728 if (sc->dc_link == 0)
2731 r = CSR_READ_4(sc, DC_ISR);
2732 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2733 sc->dc_cdata.dc_tx_cnt == 0) {
2735 if (!(mii->mii_media_status & IFM_ACTIVE))
2744 * When the init routine completes, we expect to be able to send
2745 * packets right away, and in fact the network code will send a
2746 * gratuitous ARP the moment the init routine marks the interface
2747 * as running. However, even though the MAC may have been initialized,
2748 * there may be a delay of a few seconds before the PHY completes
2749 * autonegotiation and the link is brought up. Any transmissions
2750 * made during that delay will be lost. Dealing with this is tricky:
2751 * we can't just pause in the init routine while waiting for the
2752 * PHY to come ready since that would bring the whole system to
2753 * a screeching halt for several seconds.
2755 * What we do here is prevent the TX start routine from sending
2756 * any packets until a link has been established. After the
2757 * interface has been initialized, the tick routine will poll
2758 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2759 * that time, packets will stay in the send queue, and once the
2760 * link comes up, they will be flushed out to the wire.
2764 if (mii->mii_media_status & IFM_ACTIVE &&
2765 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2767 if (!ifq_is_empty(&ifp->if_snd))
2772 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2773 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc);
2775 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
2777 lwkt_serialize_exit(ifp->if_serializer);
2781 * A transmit underrun has occurred. Back off the transmit threshold,
2782 * or switch to store and forward mode if we have to.
2785 dc_tx_underrun(struct dc_softc *sc)
2790 if (DC_IS_DAVICOM(sc))
2793 if (DC_IS_INTEL(sc)) {
2795 * The real 21143 requires that the transmitter be idle
2796 * in order to change the transmit threshold or store
2797 * and forward state.
2799 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2801 for (i = 0; i < DC_TIMEOUT; i++) {
2802 isr = CSR_READ_4(sc, DC_ISR);
2803 if (isr & DC_ISR_TX_IDLE)
2807 if (i == DC_TIMEOUT) {
2808 if_printf(&sc->arpcom.ac_if,
2809 "failed to force tx to idle state\n");
2814 if_printf(&sc->arpcom.ac_if, "TX underrun -- ");
2815 sc->dc_txthresh += DC_TXTHRESH_INC;
2816 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2817 kprintf("using store and forward mode\n");
2818 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2820 kprintf("increasing TX threshold\n");
2821 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2822 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2825 if (DC_IS_INTEL(sc))
2826 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2831 #ifdef DEVICE_POLLING
2834 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2836 struct dc_softc *sc = ifp->if_softc;
2841 /* Disable interrupts */
2842 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2844 case POLL_DEREGISTER:
2845 /* Re-enable interrupts. */
2846 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2849 sc->rxcycles = count;
2852 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2855 case POLL_AND_CHECK_STATUS:
2856 sc->rxcycles = count;
2859 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2861 status = CSR_READ_4(sc, DC_ISR);
2862 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2863 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2867 /* ack what we have */
2868 CSR_WRITE_4(sc, DC_ISR, status);
2870 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) {
2871 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2872 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2874 if (dc_rx_resync(sc))
2877 /* restart transmit unit if necessary */
2878 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2879 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2881 if (status & DC_ISR_TX_UNDERRUN)
2884 if (status & DC_ISR_BUS_ERR) {
2885 if_printf(ifp, "dc_poll: bus error\n");
2892 #endif /* DEVICE_POLLING */
2897 struct dc_softc *sc;
2903 if (sc->suspended) {
2907 ifp = &sc->arpcom.ac_if;
2909 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
2912 /* Suppress unwanted interrupts */
2913 if (!(ifp->if_flags & IFF_UP)) {
2914 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2919 /* Disable interrupts. */
2920 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2922 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
2923 status != 0xFFFFFFFF) {
2925 CSR_WRITE_4(sc, DC_ISR, status);
2927 if (status & DC_ISR_RX_OK) {
2929 curpkts = ifp->if_ipackets;
2931 if (curpkts == ifp->if_ipackets) {
2932 while(dc_rx_resync(sc))
2937 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2940 if (status & DC_ISR_TX_IDLE) {
2942 if (sc->dc_cdata.dc_tx_cnt) {
2943 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2944 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2948 if (status & DC_ISR_TX_UNDERRUN)
2951 if ((status & DC_ISR_RX_WATDOGTIMEO)
2952 || (status & DC_ISR_RX_NOBUF)) {
2954 curpkts = ifp->if_ipackets;
2956 if (curpkts == ifp->if_ipackets) {
2957 while(dc_rx_resync(sc))
2962 if (status & DC_ISR_BUS_ERR) {
2968 /* Re-enable interrupts. */
2969 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2971 if (!ifq_is_empty(&ifp->if_snd))
2978 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2979 * pointers to the fragment pointers.
2982 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
2984 struct dc_desc *f = NULL;
2986 int frag, cur, cnt = 0;
2989 * Start packing the mbufs in this chain into
2990 * the fragment pointers. Stop when we run out
2991 * of fragments or hit the end of the mbuf chain.
2994 cur = frag = *txidx;
2996 for (m = m_head; m != NULL; m = m->m_next) {
2997 if (m->m_len != 0) {
2998 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
2999 if (*txidx != sc->dc_cdata.dc_tx_prod &&
3000 frag == (DC_TX_LIST_CNT - 1))
3003 if ((DC_TX_LIST_CNT -
3004 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3007 f = &sc->dc_ldata->dc_tx_list[frag];
3008 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
3011 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
3013 f->dc_status = DC_TXSTAT_OWN;
3014 f->dc_data = vtophys(mtod(m, vm_offset_t));
3016 DC_INC(frag, DC_TX_LIST_CNT);
3024 sc->dc_cdata.dc_tx_cnt += cnt;
3025 sc->dc_cdata.dc_tx_chain[cur] = m_head;
3026 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
3027 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3028 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
3029 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3030 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3031 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3032 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3033 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3040 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3041 * to the mbuf data regions directly in the transmit lists. We also save a
3042 * copy of the pointers since the transmit list fragment pointers are
3043 * physical addresses.
3047 dc_start(struct ifnet *ifp)
3049 struct dc_softc *sc;
3050 struct mbuf *m_head;
3051 struct mbuf *m_defragged;
3052 int idx, need_trans;
3059 if (ifp->if_flags & IFF_OACTIVE)
3062 idx = sc->dc_cdata.dc_tx_prod;
3065 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3067 m_head = ifq_poll(&ifp->if_snd);
3071 if (sc->dc_flags & DC_TX_COALESCE &&
3072 (m_head->m_next != NULL ||
3073 sc->dc_flags & DC_TX_ALIGN)){
3075 * Check first if coalescing allows us to queue
3076 * the packet. We don't want to loose it if
3077 * the TX queue is full.
3079 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3080 idx != sc->dc_cdata.dc_tx_prod &&
3081 idx == (DC_TX_LIST_CNT - 1)) {
3082 ifp->if_flags |= IFF_OACTIVE;
3085 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) {
3086 ifp->if_flags |= IFF_OACTIVE;
3090 /* only coalesce if have >1 mbufs */
3091 m_defragged = m_defrag_nofree(m_head, MB_DONTWAIT);
3092 if (m_defragged == NULL) {
3093 ifp->if_flags |= IFF_OACTIVE;
3098 if (dc_encap(sc, (m_defragged ? m_defragged : m_head), &idx)) {
3101 * Throw away the original packet if the
3102 * defragged packet could not be encapsulated,
3103 * as well as the defragged packet.
3105 ifq_dequeue(&ifp->if_snd, m_head);
3107 m_freem(m_defragged);
3109 ifp->if_flags |= IFF_OACTIVE;
3113 ifq_dequeue(&ifp->if_snd, m_head);
3118 * If there's a BPF listener, bounce a copy of this frame
3121 BPF_MTAP(ifp, (m_defragged ? m_defragged : m_head));
3124 * If we defragged the packet, m_head is not the one we
3125 * encapsulated so we can throw it away.
3130 if (sc->dc_flags & DC_TX_ONE) {
3131 ifp->if_flags |= IFF_OACTIVE;
3140 sc->dc_cdata.dc_tx_prod = idx;
3141 if (!(sc->dc_flags & DC_TX_POLL))
3142 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3145 * Set a timeout in case the chip goes out to lunch.
3153 struct dc_softc *sc = xsc;
3154 struct ifnet *ifp = &sc->arpcom.ac_if;
3155 struct mii_data *mii;
3157 mii = device_get_softc(sc->dc_miibus);
3160 * Cancel pending I/O and free all RX/TX buffers.
3166 * Set cache alignment and burst length.
3168 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3169 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3171 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3173 * Evenly share the bus between receive and transmit process.
3175 if (DC_IS_INTEL(sc))
3176 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3177 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3178 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3180 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3182 if (sc->dc_flags & DC_TX_POLL)
3183 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3184 switch(sc->dc_cachesize) {
3186 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3189 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3192 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3196 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3200 if (sc->dc_flags & DC_TX_STORENFWD)
3201 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3203 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3204 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3206 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3207 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3211 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3212 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3214 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3216 * The app notes for the 98713 and 98715A say that
3217 * in order to have the chips operate properly, a magic
3218 * number must be written to CSR16. Macronix does not
3219 * document the meaning of these bits so there's no way
3220 * to know exactly what they do. The 98713 has a magic
3221 * number all its own; the rest all use a different one.
3223 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3224 if (sc->dc_type == DC_TYPE_98713)
3225 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3227 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3230 if (DC_IS_XIRCOM(sc)) {
3232 * Setup General Purpose Port mode and data so the tulip
3233 * can talk to the MII.
3235 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3236 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3238 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3239 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3243 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3244 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3246 /* Init circular RX list. */
3247 if (dc_list_rx_init(sc) == ENOBUFS) {
3248 if_printf(ifp, "initialization failed: no "
3249 "memory for rx buffers\n");
3255 * Init tx descriptors.
3257 dc_list_tx_init(sc);
3260 * Load the address of the RX list.
3262 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3263 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3266 * Enable interrupts.
3268 #ifdef DEVICE_POLLING
3270 * ... but only if we are not polling, and make sure they are off in
3271 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3274 if (ifp->if_flags & IFF_POLLING)
3275 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3278 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3279 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3281 /* Enable transmitter. */
3282 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3285 * If this is an Intel 21143 and we're not using the
3286 * MII port, program the LED control pins so we get
3287 * link and activity indications.
3289 if (sc->dc_flags & DC_TULIP_LEDS) {
3290 CSR_WRITE_4(sc, DC_WATCHDOG,
3291 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3292 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3296 * Load the RX/multicast filter. We do this sort of late
3297 * because the filter programming scheme on the 21143 and
3298 * some clones requires DMAing a setup frame via the TX
3299 * engine, and we need the transmitter enabled for that.
3303 /* Enable receiver. */
3304 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3305 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3308 dc_setcfg(sc, sc->dc_if_media);
3310 ifp->if_flags |= IFF_RUNNING;
3311 ifp->if_flags &= ~IFF_OACTIVE;
3313 /* Don't start the ticker if this is a homePNA link. */
3314 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3317 if (sc->dc_flags & DC_21143_NWAY)
3318 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc);
3320 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
3327 * Set media options.
3330 dc_ifmedia_upd(struct ifnet *ifp)
3332 struct dc_softc *sc;
3333 struct mii_data *mii;
3334 struct ifmedia *ifm;
3337 mii = device_get_softc(sc->dc_miibus);
3339 ifm = &mii->mii_media;
3341 if (DC_IS_DAVICOM(sc) &&
3342 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3343 dc_setcfg(sc, ifm->ifm_media);
3351 * Report current media status.
3354 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3356 struct dc_softc *sc;
3357 struct mii_data *mii;
3358 struct ifmedia *ifm;
3361 mii = device_get_softc(sc->dc_miibus);
3363 ifm = &mii->mii_media;
3364 if (DC_IS_DAVICOM(sc)) {
3365 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3366 ifmr->ifm_active = ifm->ifm_media;
3367 ifmr->ifm_status = 0;
3371 ifmr->ifm_active = mii->mii_media_active;
3372 ifmr->ifm_status = mii->mii_media_status;
3378 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3380 struct dc_softc *sc = ifp->if_softc;
3381 struct ifreq *ifr = (struct ifreq *) data;
3382 struct mii_data *mii;
3387 if (ifp->if_flags & IFF_UP) {
3388 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3389 (IFF_PROMISC | IFF_ALLMULTI);
3390 if (ifp->if_flags & IFF_RUNNING) {
3394 sc->dc_txthresh = 0;
3398 if (ifp->if_flags & IFF_RUNNING)
3401 sc->dc_if_flags = ifp->if_flags;
3411 mii = device_get_softc(sc->dc_miibus);
3412 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3415 error = ether_ioctl(ifp, command, data);
3423 dc_watchdog(struct ifnet *ifp)
3425 struct dc_softc *sc;
3430 if_printf(ifp, "watchdog timeout\n");
3436 if (!ifq_is_empty(&ifp->if_snd))
3443 * Stop the adapter and free any mbufs allocated to the
3447 dc_stop(struct dc_softc *sc)
3452 ifp = &sc->arpcom.ac_if;
3455 callout_stop(&sc->dc_stat_timer);
3457 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3459 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3460 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3461 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3462 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3466 * Free data in the RX lists.
3468 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3469 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3470 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3471 sc->dc_cdata.dc_rx_chain[i] = NULL;
3474 bzero((char *)&sc->dc_ldata->dc_rx_list,
3475 sizeof(sc->dc_ldata->dc_rx_list));
3478 * Free the TX list buffers.
3480 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3481 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3482 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl &
3484 !(sc->dc_ldata->dc_tx_list[i].dc_ctl &
3485 DC_TXCTL_LASTFRAG)) {
3486 sc->dc_cdata.dc_tx_chain[i] = NULL;
3489 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3490 sc->dc_cdata.dc_tx_chain[i] = NULL;
3494 bzero((char *)&sc->dc_ldata->dc_tx_list,
3495 sizeof(sc->dc_ldata->dc_tx_list));
3501 * Stop all chip I/O so that the kernel's probe routines don't
3502 * get confused by errant DMAs when rebooting.
3505 dc_shutdown(device_t dev)
3507 struct dc_softc *sc;
3510 sc = device_get_softc(dev);
3511 ifp = &sc->arpcom.ac_if;
3512 lwkt_serialize_enter(ifp->if_serializer);
3516 lwkt_serialize_exit(ifp->if_serializer);
3520 * Device suspend routine. Stop the interface and save some PCI
3521 * settings in case the BIOS doesn't restore them properly on
3525 dc_suspend(device_t dev)
3527 struct dc_softc *sc = device_get_softc(dev);
3528 struct ifnet *ifp = &sc->arpcom.ac_if;
3530 lwkt_serialize_enter(ifp->if_serializer);
3533 for (i = 0; i < 5; i++)
3534 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3535 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3536 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3537 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3538 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3542 lwkt_serialize_exit(ifp->if_serializer);
3547 * Device resume routine. Restore some PCI settings in case the BIOS
3548 * doesn't, re-enable busmastering, and restart the interface if
3552 dc_resume(device_t dev)
3554 struct dc_softc *sc = device_get_softc(dev);
3555 struct ifnet *ifp = &sc->arpcom.ac_if;
3558 lwkt_serialize_enter(ifp->if_serializer);
3561 /* better way to do this? */
3562 for (i = 0; i < 5; i++)
3563 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3564 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3565 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3566 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3567 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3569 /* reenable busmastering */
3570 pci_enable_busmaster(dev);
3571 pci_enable_io(dev, DC_RES);
3573 /* reinitialize interface if necessary */
3574 if (ifp->if_flags & IFF_UP)
3578 lwkt_serialize_exit(ifp->if_serializer);
3584 dc_mchash_xircom(struct dc_softc *sc, const uint8_t *addr)
3588 /* Compute CRC for the address value. */
3589 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
3591 if ((crc & 0x180) == 0x180)
3592 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
3594 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + (12 << 4));