sys/platform/pc32/icu/icu_vector.s

   1 /*
   2  *      from: vector.s, 386BSD 0.1 unknown origin
   3  * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $
   4  * $DragonFly: src/sys/platform/pc32/icu/icu_vector.s,v 1.33 2008/08/02 01:14:43 dillon Exp $
   5  */
   6 /*
   7  * WARNING!  SMP builds can use the ICU now so this code must be MP safe.
   8  */
   9
  10 #include "use_npx.h"
  11 #include "opt_auto_eoi.h"
  12
  13 #include <machine/asmacros.h>
  14 #include <machine/lock.h>
  15 #include <machine/psl.h>
  16 #include <machine/trap.h>
  17
  18 #include <machine_base/icu/icu.h>
  19 #include <bus/isa/isa.h>
  20
  21 #include "assym.s"
  22 #include "icu_ipl.h"
  23
  24 #ifndef APIC_IO
  25
  26 #define ICU_IMR_OFFSET          1       /* IO_ICU{1,2} + 1 */
  27
  28 #define ICU_EOI                 0x20    /* XXX - define elsewhere */
  29
  30 #define IRQ_LBIT(irq_num)       (1 << (irq_num))
  31 #define IRQ_BIT(irq_num)        (1 << ((irq_num) % 8))
  32 #define IRQ_BYTE(irq_num)       ((irq_num) >> 3)
  33
  34 #ifdef AUTO_EOI_1
  35 #define ENABLE_ICU1             /* use auto-EOI to reduce i/o */
  36 #define OUTB_ICU1
  37 #else
  38 #define ENABLE_ICU1                                                     \
  39         movb    $ICU_EOI,%al ;  /* as soon as possible send EOI ... */  \
  40         OUTB_ICU1 ;             /* ... to clear in service bit */       \
  41
  42 #define OUTB_ICU1                                                       \
  43         outb    %al,$IO_ICU1 ;                                          \
  44
  45 #endif
  46
  47 #ifdef AUTO_EOI_2
  48 /*
  49  * The data sheet says no auto-EOI on slave, but it sometimes works.
  50  */
  51 #define ENABLE_ICU1_AND_2       ENABLE_ICU1
  52 #else
  53 #define ENABLE_ICU1_AND_2                                               \
  54         movb    $ICU_EOI,%al ;  /* as above */                          \
  55         outb    %al,$IO_ICU2 ;  /* but do second icu first ... */       \
  56         OUTB_ICU1 ;     /* ... then first icu (if !AUTO_EOI_1) */       \
  57
  58 #endif
  59
  60 /*
  61  * Macro helpers
  62  */
  63 #define PUSH_FRAME                                                      \
  64         pushl   $0 ;            /* dummy error code */                  \
  65         pushl   $0 ;            /* dummy trap type */                   \
  66         pushl   $0 ;            /* dummy xflags */                      \
  67         pushal ;                /* 8 registers */                       \
  68         pushl   %ds ;                                                   \
  69         pushl   %es ;                                                   \
  70         pushl   %fs ;                                                   \
  71         pushl   %gs ;                                                   \
  72         cld ;                                                           \
  73         mov     $KDSEL,%ax ;                                            \
  74         mov     %ax,%ds ;                                               \
  75         mov     %ax,%es ;                                               \
  76         mov     %ax,%gs ;                                               \
  77         mov     $KPSEL,%ax ;                                            \
  78         mov     %ax,%fs ;                                               \
  79
  80 #define PUSH_DUMMY                                                      \
  81         pushfl ;                /* phys int frame / flags */            \
  82         pushl %cs ;             /* phys int frame / cs */               \
  83         pushl   12(%esp) ;      /* original caller eip */               \
  84         pushl   $0 ;            /* dummy error code */                  \
  85         pushl   $0 ;            /* dummy trap type */                   \
  86         pushl   $0 ;            /* dummy xflags */                      \
  87         subl    $13*4,%esp ;    /* pushal + 4 seg regs (dummy) + CPL */ \
  88
  89 /*
  90  * Warning: POP_FRAME can only be used if there is no chance of a
  91  * segment register being changed (e.g. by procfs), which is why syscalls
  92  * have to use doreti.
  93  */
  94 #define POP_FRAME                                                       \
  95         popl    %gs ;                                                   \
  96         popl    %fs ;                                                   \
  97         popl    %es ;                                                   \
  98         popl    %ds ;                                                   \
  99         popal ;                                                         \
 100         addl    $2*4,%esp ;     /* dummy trap & error codes */          \
 101
 102 #define POP_DUMMY                                                       \
 103         addl    $19*4,%esp ;                                            \
 104
 105 #define MASK_IRQ(icu, irq_num)                                          \
 106         ICU_IMASK_LOCK ;                                                \
 107         movb    icu_imen + IRQ_BYTE(irq_num),%al ;                      \
 108         orb     $IRQ_BIT(irq_num),%al ;                                 \
 109         movb    %al,icu_imen + IRQ_BYTE(irq_num) ;                      \
 110         outb    %al,$icu+ICU_IMR_OFFSET ;                               \
 111         ICU_IMASK_UNLOCK ;                                              \
 112
 113 #define UNMASK_IRQ(icu, irq_num)                                        \
 114         cmpl    $0,%eax ;                                               \
 115         jnz     8f ;                                                    \
 116         ICU_IMASK_LOCK ;                                                \
 117         movb    icu_imen + IRQ_BYTE(irq_num),%al ;                      \
 118         andb    $~IRQ_BIT(irq_num),%al ;                                \
 119         movb    %al,icu_imen + IRQ_BYTE(irq_num) ;                      \
 120         outb    %al,$icu+ICU_IMR_OFFSET ;                               \
 121         ICU_IMASK_UNLOCK ;                                              \
 122 8: ;                                                                    \
 123
 124 /*
 125  * Fast interrupt call handlers run in the following sequence:
 126  *
 127  *      - Push the trap frame required by doreti.
 128  *      - Mask the interrupt and reenable its source.
 129  *      - If we cannot take the interrupt set its fpending bit and
 130  *        doreti.
 131  *      - If we can take the interrupt clear its fpending bit,
 132  *        call the handler, then unmask the interrupt and doreti.
 133  *
 134  *      YYY can cache gd base pointer instead of using hidden %fs
 135  *      prefixes.
 136  */
 137
 138 #define FAST_INTR(irq_num, vec_name, icu, enable_icus)                   \
 139         .text ;                                                         \
 140         SUPERALIGN_TEXT ;                                               \
 141 IDTVEC(vec_name) ;                                                      \
 142         PUSH_FRAME ;                                                    \
 143         FAKE_MCOUNT(15*4(%esp)) ;                                       \
 144         MASK_IRQ(icu, irq_num) ;                                        \
 145         enable_icus ;                                                   \
 146         movl    PCPU(curthread),%ebx ;                                  \
 147         pushl   $0 ;                    /* DUMMY CPL FOR DORETI */      \
 148         testl   $-1,TD_NEST_COUNT(%ebx) ;                               \
 149         jne     1f ;                                                    \
 150         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 151         jl      2f ;                                                    \
 152 1: ;                                                                    \
 153         /* set pending bit and return, leave interrupt masked */        \
 154         orl     $IRQ_LBIT(irq_num),PCPU(fpending) ;                     \
 155         orl     $RQF_INTPEND, PCPU(reqflags) ;                          \
 156         jmp     5f ;                                                    \
 157 2: ;                                                                    \
 158         /* clear pending bit, run handler */                            \
 159         andl    $~IRQ_LBIT(irq_num),PCPU(fpending) ;                    \
 160         pushl   $irq_num ;                                              \
 161         pushl   %esp ;                  /* pass frame by reference */   \
 162         call    ithread_fast_handler ;  /* returns 0 to unmask int */   \
 163         addl    $8,%esp ;                                               \
 164         UNMASK_IRQ(icu, irq_num) ;                                      \
 165 5: ;                                                                    \
 166         MEXITCOUNT ;                                                    \
 167         jmp     doreti ;                                                \
 168
 169 /*
 170  * Slow interrupt call handlers run in the following sequence:
 171  *
 172  *      - Push the trap frame required by doreti.
 173  *      - Mask the interrupt and reenable its source.
 174  *      - If we cannot take the interrupt set its ipending bit and
 175  *        doreti.  In addition to checking for a critical section
 176  *        and cpl mask we also check to see if the thread is still
 177  *        running.
 178  *      - If we can take the interrupt clear its ipending bit
 179  *        and schedule its thread.  Leave interrupts masked and doreti.
 180  *
 181  *      sched_ithd() is called with interrupts enabled and outside of a
 182  *      critical section (so it can preempt us).
 183  *
 184  *      YYY sched_ithd may preempt us synchronously (fix interrupt stacking)
 185  *
 186  *      Note that intr_nesting_level is not bumped during sched_ithd because
 187  *      blocking allocations are allowed in the preemption case.
 188  *
 189  *      YYY can cache gd base pointer instead of using hidden %fs
 190  *      prefixes.
 191  */
 192
 193 #define SLOW_INTR(irq_num, vec_name, icu, enable_icus)                   \
 194         .text ;                                                         \
 195         SUPERALIGN_TEXT ;                                               \
 196 IDTVEC(vec_name) ;                                                      \
 197         PUSH_FRAME ;                                                    \
 198         FAKE_MCOUNT(15*4(%esp)) ;                                       \
 199         MASK_IRQ(icu, irq_num) ;                                        \
 200         incl    PCPU(cnt) + V_INTR ;                                    \
 201         enable_icus ;                                                   \
 202         movl    PCPU(curthread),%ebx ;                                  \
 203         pushl   $0 ;                    /* DUMMY CPL FOR DORETI */      \
 204         testl   $-1,TD_NEST_COUNT(%ebx) ;                               \
 205         jne     1f ;                                                    \
 206         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 207         jl      2f ;                                                    \
 208 1: ;                                                                    \
 209         /* set the pending bit and return, leave interrupt masked */    \
 210         orl     $IRQ_LBIT(irq_num), PCPU(ipending) ;                    \
 211         orl     $RQF_INTPEND, PCPU(reqflags) ;                          \
 212         jmp     5f ;                                                    \
 213 2: ;                                                                    \
 214         /* set running bit, clear pending bit, run handler */           \
 215         andl    $~IRQ_LBIT(irq_num), PCPU(ipending) ;                   \
 216         incl    TD_NEST_COUNT(%ebx) ;                                   \
 217         sti ;                                                           \
 218         pushl   $irq_num ;                                              \
 219         call    sched_ithd ;                                            \
 220         addl    $4,%esp ;                                               \
 221         cli ;                                                           \
 222         decl    TD_NEST_COUNT(%ebx) ;                                   \
 223 5: ;                                                                    \
 224         MEXITCOUNT ;                                                    \
 225         jmp     doreti ;                                                \
 226
 227 /*
 228  * Unmask a slow interrupt.  This function is used by interrupt threads
 229  * after they have descheduled themselves to reenable interrupts and
 230  * possibly cause a reschedule to occur.
 231  */
 232
 233 #define INTR_UNMASK(irq_num, vec_name, icu)                             \
 234         .text ;                                                         \
 235         SUPERALIGN_TEXT ;                                               \
 236 IDTVEC(vec_name) ;                                                      \
 237         pushl %ebp ;     /* frame for ddb backtrace */                  \
 238         movl    %esp, %ebp ;                                            \
 239         subl    %eax, %eax ;                                            \
 240         UNMASK_IRQ(icu, irq_num) ;                                      \
 241         popl %ebp ;                                                     \
 242         ret ;                                                           \
 243
 244 MCOUNT_LABEL(bintr)
 245         FAST_INTR(0,icu_fastintr0, IO_ICU1, ENABLE_ICU1)
 246         FAST_INTR(1,icu_fastintr1, IO_ICU1, ENABLE_ICU1)
 247         FAST_INTR(2,icu_fastintr2, IO_ICU1, ENABLE_ICU1)
 248         FAST_INTR(3,icu_fastintr3, IO_ICU1, ENABLE_ICU1)
 249         FAST_INTR(4,icu_fastintr4, IO_ICU1, ENABLE_ICU1)
 250         FAST_INTR(5,icu_fastintr5, IO_ICU1, ENABLE_ICU1)
 251         FAST_INTR(6,icu_fastintr6, IO_ICU1, ENABLE_ICU1)
 252         FAST_INTR(7,icu_fastintr7, IO_ICU1, ENABLE_ICU1)
 253         FAST_INTR(8,icu_fastintr8, IO_ICU2, ENABLE_ICU1_AND_2)
 254         FAST_INTR(9,icu_fastintr9, IO_ICU2, ENABLE_ICU1_AND_2)
 255         FAST_INTR(10,icu_fastintr10, IO_ICU2, ENABLE_ICU1_AND_2)
 256         FAST_INTR(11,icu_fastintr11, IO_ICU2, ENABLE_ICU1_AND_2)
 257         FAST_INTR(12,icu_fastintr12, IO_ICU2, ENABLE_ICU1_AND_2)
 258         FAST_INTR(13,icu_fastintr13, IO_ICU2, ENABLE_ICU1_AND_2)
 259         FAST_INTR(14,icu_fastintr14, IO_ICU2, ENABLE_ICU1_AND_2)
 260         FAST_INTR(15,icu_fastintr15, IO_ICU2, ENABLE_ICU1_AND_2)
 261
 262         SLOW_INTR(0,icu_slowintr0, IO_ICU1, ENABLE_ICU1)
 263         SLOW_INTR(1,icu_slowintr1, IO_ICU1, ENABLE_ICU1)
 264         SLOW_INTR(2,icu_slowintr2, IO_ICU1, ENABLE_ICU1)
 265         SLOW_INTR(3,icu_slowintr3, IO_ICU1, ENABLE_ICU1)
 266         SLOW_INTR(4,icu_slowintr4, IO_ICU1, ENABLE_ICU1)
 267         SLOW_INTR(5,icu_slowintr5, IO_ICU1, ENABLE_ICU1)
 268         SLOW_INTR(6,icu_slowintr6, IO_ICU1, ENABLE_ICU1)
 269         SLOW_INTR(7,icu_slowintr7, IO_ICU1, ENABLE_ICU1)
 270         SLOW_INTR(8,icu_slowintr8, IO_ICU2, ENABLE_ICU1_AND_2)
 271         SLOW_INTR(9,icu_slowintr9, IO_ICU2, ENABLE_ICU1_AND_2)
 272         SLOW_INTR(10,icu_slowintr10, IO_ICU2, ENABLE_ICU1_AND_2)
 273         SLOW_INTR(11,icu_slowintr11, IO_ICU2, ENABLE_ICU1_AND_2)
 274         SLOW_INTR(12,icu_slowintr12, IO_ICU2, ENABLE_ICU1_AND_2)
 275         SLOW_INTR(13,icu_slowintr13, IO_ICU2, ENABLE_ICU1_AND_2)
 276         SLOW_INTR(14,icu_slowintr14, IO_ICU2, ENABLE_ICU1_AND_2)
 277         SLOW_INTR(15,icu_slowintr15, IO_ICU2, ENABLE_ICU1_AND_2)
 278
 279 MCOUNT_LABEL(eintr)
 280
 281         .data
 282
 283         .text
 284
 285 #endif