2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/machintr.h>
46 #include <sys/interrupt.h>
49 #include <machine/segments.h>
50 #include <machine/md_var.h>
51 #include <machine/intr_machdep.h>
52 #include <machine/globaldata.h>
53 #include <machine/smp.h>
55 #include <sys/thread2.h>
57 #include <machine_base/apic/ioapic_abi.h>
63 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
64 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
65 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
66 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
67 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
68 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
69 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
70 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
72 static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
73 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
74 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
75 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
76 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
77 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
78 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
79 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
80 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
83 extern void ICU_INTREN(int);
84 extern void ICU_INTRDIS(int);
86 static int icu_vectorctl(int, int, int);
87 static int icu_setvar(int, const void *);
88 static int icu_getvar(int, void *);
89 static void icu_finalize(void);
90 static void icu_cleanup(void);
91 static void icu_setdefault(void);
92 static void icu_stabilize(void);
94 struct machintr_abi MachIntrABI_ICU = {
96 .intrdis = ICU_INTRDIS,
98 .vectorctl = icu_vectorctl,
100 .getvar = icu_getvar,
101 .finalize = icu_finalize,
102 .cleanup = icu_cleanup,
103 .setdefault = icu_setdefault,
104 .stabilize = icu_stabilize
107 static int icu_imcr_present;
110 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
113 icu_setvar(int varid, const void *buf)
118 case MACHINTR_VAR_IMCR_PRESENT:
119 icu_imcr_present = *(const int *)buf;
130 icu_getvar(int varid, void *buf)
135 case MACHINTR_VAR_IMCR_PRESENT:
136 *(int *)buf = icu_imcr_present;
147 * Called before interrupts are physically enabled
154 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
155 machintr_intrdis(intr);
156 machintr_intren(ICU_IRQ_SLAVE);
160 * Called after interrupts physically enabled but before the
161 * critical section is released.
166 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
170 * Called after stablize and cleanup; critical section is not
171 * held and interrupts are not physically disabled.
174 * Further delayed after BSP's LAPIC is initialized
179 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
182 if (apic_io_enable) {
184 * MachIntrABI switching will happen in
185 * MachIntrABI_IOAPIC.finalize()
187 MachIntrABI_IOAPIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
189 MachIntrABI_IOAPIC.finalize();
194 * If an IMCR is present, programming bit 0 disconnects the 8259
195 * from the BSP. The 8259 may still be connected to LINT0 on the
198 * If we are running SMP the LAPIC is active, try to use virtual
199 * wire mode so we can use other interrupt sources within the LAPIC
200 * in addition to the 8259.
202 if (icu_imcr_present) {
221 icu_vectorctl(int op, int intr, int flags)
226 if (intr < 0 || intr >= ICU_HWI_VECTORS || intr == ICU_IRQ_SLAVE)
234 case MACHINTR_VECTOR_SETUP:
235 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
236 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
237 machintr_intren(intr);
240 case MACHINTR_VECTOR_TEARDOWN:
241 machintr_intrdis(intr);
242 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
243 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
259 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
260 if (intr == ICU_IRQ_SLAVE)
262 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
263 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));