2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
164 vm_size_t mp_cth_mapsz;
167 typedef int (*mptable_iter_func)(void *, const void *, int);
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
175 #if defined(CHECK_POINTS)
176 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
179 #define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
187 #define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
197 #else /* CHECK_POINTS */
199 #define CHECK_INIT(D)
200 #define CHECK_PRINT(S)
202 #endif /* CHECK_POINTS */
205 * Values to send to the POST hardware.
207 #define MP_BOOTADDRESS_POST 0x10
208 #define MP_PROBE_POST 0x11
209 #define MPTABLE_PASS1_POST 0x12
211 #define MP_START_POST 0x13
212 #define MP_ENABLE_POST 0x14
213 #define MPTABLE_PASS2_POST 0x15
215 #define START_ALL_APS_POST 0x16
216 #define INSTALL_AP_TRAMP_POST 0x17
217 #define START_AP_POST 0x18
219 #define MP_ANNOUNCE_POST 0x19
221 static int madt_probe_test;
222 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
224 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
225 int current_postcode;
227 /** XXX FIXME: what system files declare these??? */
228 extern struct region_descriptor r_gdt, r_idt;
230 int mp_naps; /* # of Applications processors */
232 static int mp_nbusses; /* # of busses */
233 int mp_napics; /* # of IO APICs */
235 static vm_offset_t cpu_apic_address;
237 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
238 u_int32_t *io_apic_versions;
242 u_int32_t cpu_apic_versions[MAXCPU];
244 extern int64_t tsc_offsets[];
246 extern u_long ebda_addr;
249 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
253 * APIC ID logical/physical mapping structures.
254 * We oversize these to simplify boot-time config.
256 int cpu_num_to_apic_id[NAPICID];
258 int io_num_to_apic_id[NAPICID];
260 int apic_id_to_logical[NAPICID];
262 /* AP uses this during bootstrap. Do not staticize. */
266 /* Hotwire a 0->4MB V==P mapping */
267 extern pt_entry_t *KPTphys;
270 * SMP page table page. Setup by locore to point to a page table
271 * page from which we allocate per-cpu privatespace areas io_apics,
275 #define IO_MAPPING_START_INDEX \
276 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
278 extern pt_entry_t *SMPpt;
279 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
281 struct pcb stoppcbs[MAXCPU];
283 static basetable_entry basetable_entry_types[] =
285 {0, 20, "Processor"},
293 * Local data and functions.
296 static u_int boot_address;
297 static u_int base_memory;
298 static int mp_finish;
300 static void mp_enable(u_int boot_addr);
302 static int mptable_iterate_entries(const mpcth_t,
303 mptable_iter_func, void *);
304 static int mptable_probe(void);
305 static int mptable_check(vm_paddr_t);
306 static int mptable_search_sig(u_int32_t target, int count);
307 static int mptable_hyperthread_fixup(u_int, int);
308 static void mptable_pass1(struct mptable_pos *);
309 static int mptable_pass2(struct mptable_pos *);
310 static void mptable_default(int type);
311 static void mptable_fix(void);
312 static int mptable_map(struct mptable_pos *, vm_paddr_t);
313 static void mptable_unmap(struct mptable_pos *);
314 static void mptable_lapic_enumerate(struct mptable_pos *);
315 static void mptable_lapic_default(void);
318 static void setup_apic_irq_mapping(void);
319 static int apic_int_is_bus_type(int intr, int bus_type);
321 static int start_all_aps(u_int boot_addr);
322 static void install_ap_tramp(u_int boot_addr);
323 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
324 static void lapic_init(vm_offset_t);
326 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
327 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
328 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
331 * Calculate usable address in base memory for AP trampoline code.
334 mp_bootaddress(u_int basemem)
336 POSTCODE(MP_BOOTADDRESS_POST);
338 base_memory = basemem;
340 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
341 if ((base_memory - boot_address) < bootMP_size)
342 boot_address -= 4096; /* not enough, lower by 4k */
349 * Look for an Intel MP spec table (ie, SMP capable hardware).
358 * Make sure our SMPpt[] page table is big enough to hold all the
361 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
363 POSTCODE(MP_PROBE_POST);
365 /* see if EBDA exists */
366 if (ebda_addr != 0) {
367 /* search first 1K of EBDA */
368 target = (u_int32_t)ebda_addr;
369 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
372 /* last 1K of base memory, effective 'top of base' passed in */
373 target = (u_int32_t)(base_memory - 0x400);
374 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
378 /* search the BIOS */
379 target = (u_int32_t)BIOS_BASE;
380 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
387 struct mptable_check_cbarg {
393 mptable_check_callback(void *xarg, const void *pos, int type)
395 const struct PROCENTRY *ent;
396 struct mptable_check_cbarg *arg = xarg;
402 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
406 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
407 if (arg->found_bsp) {
408 kprintf("more than one BSP in base MP table\n");
417 mptable_check(vm_paddr_t mpfps_paddr)
419 struct mptable_pos mpt;
420 struct mptable_check_cbarg arg;
424 if (mpfps_paddr == 0)
427 error = mptable_map(&mpt, mpfps_paddr);
431 if (mpt.mp_fps->mpfb1 != 0)
439 if (cth->apic_address == 0)
442 bzero(&arg, sizeof(arg));
443 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
445 if (arg.cpu_count == 0) {
446 kprintf("MP table contains no processor entries\n");
448 } else if (!arg.found_bsp) {
449 kprintf("MP table does not contains BSP entry\n");
459 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
461 int count, total_size;
462 const void *position;
464 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
465 total_size = cth->base_table_length - sizeof(struct MPCTH);
466 position = (const uint8_t *)cth + sizeof(struct MPCTH);
467 count = cth->entry_count;
472 KKASSERT(total_size >= 0);
473 if (total_size == 0) {
474 kprintf("invalid base MP table, "
475 "entry count and length mismatch\n");
479 type = *(const uint8_t *)position;
481 case 0: /* processor_entry */
482 case 1: /* bus_entry */
483 case 2: /* io_apic_entry */
484 case 3: /* int_entry */
485 case 4: /* int_entry */
488 kprintf("unknown base MP table entry type %d\n", type);
492 if (total_size < basetable_entry_types[type].length) {
493 kprintf("invalid base MP table length, "
494 "does not contain all entries\n");
497 total_size -= basetable_entry_types[type].length;
499 error = func(arg, position, type);
503 position = (const uint8_t *)position +
504 basetable_entry_types[type].length;
511 * Startup the SMP processors.
516 POSTCODE(MP_START_POST);
517 mp_enable(boot_address);
522 * Print various information about the SMP system hardware and setup.
529 POSTCODE(MP_ANNOUNCE_POST);
531 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
532 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
533 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
534 kprintf(", at 0x%08x\n", cpu_apic_address);
535 for (x = 1; x <= mp_naps; ++x) {
536 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
537 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
538 kprintf(", at 0x%08x\n", cpu_apic_address);
542 for (x = 0; x < mp_napics; ++x) {
543 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
544 kprintf(", version: 0x%08x", io_apic_versions[x]);
545 kprintf(", at 0x%08x\n", io_apic_address[x]);
548 kprintf(" Warning: APIC I/O disabled\n");
553 * AP cpu's call this to sync up protected mode.
555 * WARNING! We must ensure that the cpu is sufficiently initialized to
556 * be able to use to the FP for our optimized bzero/bcopy code before
557 * we enter more mainstream C code.
559 * WARNING! %fs is not set up on entry. This routine sets up %fs.
565 int x, myid = bootAP;
567 struct mdglobaldata *md;
568 struct privatespace *ps;
570 ps = &CPU_prvspace[myid];
572 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
573 gdt_segs[GPROC0_SEL].ssd_base =
574 (int) &ps->mdglobaldata.gd_common_tss;
575 ps->mdglobaldata.mi.gd_prvspace = ps;
577 for (x = 0; x < NGDT; x++) {
578 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
581 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
582 r_gdt.rd_base = (int) &gdt[myid * NGDT];
583 lgdt(&r_gdt); /* does magic intra-segment return */
588 mdcpu->gd_currentldt = _default_ldt;
590 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
591 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
593 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
595 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
596 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
597 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
598 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
599 md->gd_common_tssd = *md->gd_tss_gdt;
603 * Set to a known state:
604 * Set by mpboot.s: CR0_PG, CR0_PE
605 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
608 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
610 pmap_set_opt(); /* PSE/4MB pages, etc */
612 /* set up CPU registers and state */
615 /* set up FPU state on the AP */
616 npxinit(__INITIAL_NPXCW__);
618 /* set up SSE registers */
622 /*******************************************************************
623 * local functions and data
627 * start the SMP system
630 mp_enable(u_int boot_addr)
637 vm_paddr_t mpfps_paddr;
639 POSTCODE(MP_ENABLE_POST);
641 if (madt_probe_test) {
644 mpfps_paddr = mptable_probe();
645 if (mptable_check(mpfps_paddr))
650 struct mptable_pos mpt;
652 mptable_map(&mpt, mpfps_paddr);
654 mptable_lapic_enumerate(&mpt);
657 * We can safely map physical memory into SMPpt after
658 * mptable_pass1() completes.
663 * Examine the MP table for needed info
665 x = mptable_pass2(&mpt);
670 * Can't process default configs till the
671 * CPU APIC is pmapped
676 /* Post scan cleanup */
679 vm_paddr_t madt_paddr;
680 vm_offset_t lapic_addr;
683 madt_paddr = madt_probe();
685 panic("mp_enable: madt_probe failed\n");
687 lapic_addr = madt_pass1(madt_paddr);
689 panic("mp_enable: no local apic (madt)!\n");
691 lapic_init(lapic_addr);
693 bsp_apic_id = APIC_ID(lapic.id);
694 if (madt_pass2(madt_paddr, bsp_apic_id))
695 panic("mp_enable: madt_pass2 failed\n");
700 setup_apic_irq_mapping();
702 /* fill the LOGICAL io_apic_versions table */
703 for (apic = 0; apic < mp_napics; ++apic) {
704 ux = io_apic_read(apic, IOAPIC_VER);
705 io_apic_versions[apic] = ux;
706 io_apic_set_id(apic, IO_TO_ID(apic));
709 /* program each IO APIC in the system */
710 for (apic = 0; apic < mp_napics; ++apic)
711 if (io_apic_setup(apic) < 0)
712 panic("IO APIC setup failure");
717 * These are required for SMP operation
720 /* install a 'Spurious INTerrupt' vector */
721 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
722 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
724 /* install an inter-CPU IPI for TLB invalidation */
725 setidt(XINVLTLB_OFFSET, Xinvltlb,
726 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
728 /* install an inter-CPU IPI for IPIQ messaging */
729 setidt(XIPIQ_OFFSET, Xipiq,
730 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
732 /* install a timer vector */
733 setidt(XTIMER_OFFSET, Xtimer,
734 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
736 /* install an inter-CPU IPI for CPU stop/restart */
737 setidt(XCPUSTOP_OFFSET, Xcpustop,
738 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
740 /* start each Application Processor */
741 start_all_aps(boot_addr);
746 * look for the MP spec signature
749 /* string defined by the Intel MP Spec as identifying the MP table */
750 #define MP_SIG 0x5f504d5f /* _MP_ */
751 #define NEXT(X) ((X) += 4)
753 mptable_search_sig(u_int32_t target, int count)
759 KKASSERT(target != 0);
761 map_size = count * sizeof(u_int32_t);
762 addr = pmap_mapdev((vm_paddr_t)target, map_size);
765 for (x = 0; x < count; NEXT(x)) {
766 if (addr[x] == MP_SIG) {
767 /* make array index a byte index */
768 ret = target + (x * sizeof(u_int32_t));
773 pmap_unmapdev((vm_offset_t)addr, map_size);
778 typedef struct BUSDATA {
780 enum busTypes bus_type;
783 typedef struct INTDATA {
793 typedef struct BUSTYPENAME {
798 static bus_type_name bus_type_table[] =
804 {UNKNOWN_BUSTYPE, "---"},
807 {UNKNOWN_BUSTYPE, "---"},
808 {UNKNOWN_BUSTYPE, "---"},
809 {UNKNOWN_BUSTYPE, "---"},
810 {UNKNOWN_BUSTYPE, "---"},
811 {UNKNOWN_BUSTYPE, "---"},
813 {UNKNOWN_BUSTYPE, "---"},
814 {UNKNOWN_BUSTYPE, "---"},
815 {UNKNOWN_BUSTYPE, "---"},
816 {UNKNOWN_BUSTYPE, "---"},
818 {UNKNOWN_BUSTYPE, "---"}
820 /* from MP spec v1.4, table 5-1 */
821 static int default_data[7][5] =
823 /* nbus, id0, type0, id1, type1 */
824 {1, 0, ISA, 255, 255},
825 {1, 0, EISA, 255, 255},
826 {1, 0, EISA, 255, 255},
827 {1, 0, MCA, 255, 255},
829 {2, 0, EISA, 1, PCI},
837 static bus_datum *bus_data;
839 /* the IO INT data, one entry per possible APIC INTerrupt */
840 static io_int *io_apic_ints;
845 static int processor_entry (const struct PROCENTRY *entry, int cpu);
847 static int bus_entry (bus_entry_ptr entry, int bus);
848 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
849 static int int_entry (int_entry_ptr entry, int intr);
851 static int lookup_bus_type (char *name);
856 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
858 const struct IOAPICENTRY *ioapic_ent;
861 case 1: /* bus_entry */
865 case 2: /* io_apic_entry */
867 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
868 io_apic_address[mp_napics++] =
869 (vm_offset_t)ioapic_ent->apic_address;
873 case 3: /* int_entry */
883 * 1st pass on motherboard's Intel MP specification table.
892 mptable_pass1(struct mptable_pos *mpt)
898 POSTCODE(MPTABLE_PASS1_POST);
901 KKASSERT(fps != NULL);
903 /* clear various tables */
904 for (x = 0; x < NAPICID; ++x)
905 io_apic_address[x] = ~0; /* IO APIC address table */
911 /* check for use of 'default' configuration */
912 if (fps->mpfb1 != 0) {
913 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
914 mp_nbusses = default_data[fps->mpfb1 - 1][0];
920 error = mptable_iterate_entries(mpt->mp_cth,
921 mptable_ioapic_pass1_callback, NULL);
923 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
930 * 2nd pass on motherboard's Intel MP specification table.
933 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
934 * IO_TO_ID(N), logical IO to APIC ID table
939 mptable_pass2(struct mptable_pos *mpt)
951 POSTCODE(MPTABLE_PASS2_POST);
954 KKASSERT(fps != NULL);
957 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
959 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
960 M_DEVBUF, M_WAITOK | M_ZERO);
961 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
963 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
968 for (i = 0; i < mp_napics; i++) {
969 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
973 /* clear various tables */
974 for (x = 0; x < NAPICID; ++x) {
976 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
977 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
982 /* clear bus data table */
983 for (x = 0; x < mp_nbusses; ++x)
984 bus_data[x].bus_id = 0xff;
986 /* clear IO APIC INT table */
987 for (x = 0; x < (nintrs + 1); ++x) {
988 io_apic_ints[x].int_type = 0xff;
989 io_apic_ints[x].int_vector = 0xff;
993 /* record whether PIC or virtual-wire mode */
994 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
996 /* check for use of 'default' configuration */
998 return fps->mpfb1; /* return default configuration type */
1001 KKASSERT(cth != NULL);
1003 /* walk the table, recording info of interest */
1004 totalSize = cth->base_table_length - sizeof(struct MPCTH);
1005 position = (u_char *) cth + sizeof(struct MPCTH);
1006 count = cth->entry_count;
1007 apic = bus = intr = 0;
1010 switch (type = *(u_char *) position) {
1015 if (bus_entry(position, bus))
1021 if (io_apic_entry(position, apic))
1027 if (int_entry(position, intr))
1032 /* int_entry(position); */
1035 panic("mpfps Base Table HOSED!");
1039 totalSize -= basetable_entry_types[type].length;
1040 position = (uint8_t *)position + basetable_entry_types[type].length;
1043 /* report fact that its NOT a default configuration */
1048 * Check if we should perform a hyperthreading "fix-up" to
1049 * enumerate any logical CPU's that aren't already listed
1052 * XXX: We assume that all of the physical CPUs in the
1053 * system have the same number of logical CPUs.
1055 * XXX: We assume that APIC ID's are allocated such that
1056 * the APIC ID's for a physical processor are aligned
1057 * with the number of logical CPU's in the processor.
1060 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1062 int i, id, lcpus_max, logical_cpus;
1064 if ((cpu_feature & CPUID_HTT) == 0)
1067 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1071 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1073 * INSTRUCTION SET REFERENCE, A-M (#253666)
1074 * Page 3-181, Table 3-20
1075 * "The nearest power-of-2 integer that is not smaller
1076 * than EBX[23:16] is the number of unique initial APIC
1077 * IDs reserved for addressing different logical
1078 * processors in a physical package."
1080 for (i = 0; ; ++i) {
1081 if ((1 << i) >= lcpus_max) {
1088 KKASSERT(cpu_count != 0);
1089 if (cpu_count == lcpus_max) {
1090 /* We have nothing to fix */
1092 } else if (cpu_count == 1) {
1093 /* XXX this may be incorrect */
1094 logical_cpus = lcpus_max;
1096 int cur, prev, dist;
1099 * Calculate the distances between two nearest
1100 * APIC IDs. If all such distances are same,
1101 * then it is the number of missing cpus that
1102 * we are going to fill later.
1104 dist = cur = prev = -1;
1105 for (id = 0; id < MAXCPU; ++id) {
1106 if ((id_mask & 1 << id) == 0)
1111 int new_dist = cur - prev;
1117 * Make sure that all distances
1118 * between two nearest APIC IDs
1121 if (dist != new_dist)
1129 /* Must be power of 2 */
1130 if (dist & (dist - 1))
1133 /* Can't exceed CPU package capacity */
1134 if (dist > lcpus_max)
1135 logical_cpus = lcpus_max;
1137 logical_cpus = dist;
1141 * For each APIC ID of a CPU that is set in the mask,
1142 * scan the other candidate APIC ID's for this
1143 * physical processor. If any of those ID's are
1144 * already in the table, then kill the fixup.
1146 for (id = 0; id < MAXCPU; id++) {
1147 if ((id_mask & 1 << id) == 0)
1149 /* First, make sure we are on a logical_cpus boundary. */
1150 if (id % logical_cpus != 0)
1152 for (i = id + 1; i < id + logical_cpus; i++)
1153 if ((id_mask & 1 << i) != 0)
1156 return logical_cpus;
1160 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1164 vm_size_t cth_mapsz = 0;
1166 bzero(mpt, sizeof(*mpt));
1168 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1169 if (fps->pap != 0) {
1171 * Map configuration table header to get
1172 * the base table size
1174 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1175 cth_mapsz = cth->base_table_length;
1176 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1178 if (cth_mapsz < sizeof(*cth)) {
1179 kprintf("invalid base MP table length %d\n",
1181 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1186 * Map the base table
1188 cth = pmap_mapdev(fps->pap, cth_mapsz);
1193 mpt->mp_cth_mapsz = cth_mapsz;
1199 mptable_unmap(struct mptable_pos *mpt)
1201 if (mpt->mp_cth != NULL) {
1202 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1204 mpt->mp_cth_mapsz = 0;
1206 if (mpt->mp_fps != NULL) {
1207 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1215 assign_apic_irq(int apic, int intpin, int irq)
1219 if (int_to_apicintpin[irq].ioapic != -1)
1220 panic("assign_apic_irq: inconsistent table");
1222 int_to_apicintpin[irq].ioapic = apic;
1223 int_to_apicintpin[irq].int_pin = intpin;
1224 int_to_apicintpin[irq].apic_address = ioapic[apic];
1225 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1227 for (x = 0; x < nintrs; x++) {
1228 if ((io_apic_ints[x].int_type == 0 ||
1229 io_apic_ints[x].int_type == 3) &&
1230 io_apic_ints[x].int_vector == 0xff &&
1231 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1232 io_apic_ints[x].dst_apic_int == intpin)
1233 io_apic_ints[x].int_vector = irq;
1238 revoke_apic_irq(int irq)
1244 if (int_to_apicintpin[irq].ioapic == -1)
1245 panic("revoke_apic_irq: inconsistent table");
1247 oldapic = int_to_apicintpin[irq].ioapic;
1248 oldintpin = int_to_apicintpin[irq].int_pin;
1250 int_to_apicintpin[irq].ioapic = -1;
1251 int_to_apicintpin[irq].int_pin = 0;
1252 int_to_apicintpin[irq].apic_address = NULL;
1253 int_to_apicintpin[irq].redirindex = 0;
1255 for (x = 0; x < nintrs; x++) {
1256 if ((io_apic_ints[x].int_type == 0 ||
1257 io_apic_ints[x].int_type == 3) &&
1258 io_apic_ints[x].int_vector != 0xff &&
1259 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1260 io_apic_ints[x].dst_apic_int == oldintpin)
1261 io_apic_ints[x].int_vector = 0xff;
1269 allocate_apic_irq(int intr)
1275 if (io_apic_ints[intr].int_vector != 0xff)
1276 return; /* Interrupt handler already assigned */
1278 if (io_apic_ints[intr].int_type != 0 &&
1279 (io_apic_ints[intr].int_type != 3 ||
1280 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1281 io_apic_ints[intr].dst_apic_int == 0)))
1282 return; /* Not INT or ExtInt on != (0, 0) */
1285 while (irq < APIC_INTMAPSIZE &&
1286 int_to_apicintpin[irq].ioapic != -1)
1289 if (irq >= APIC_INTMAPSIZE)
1290 return; /* No free interrupt handlers */
1292 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1293 intpin = io_apic_ints[intr].dst_apic_int;
1295 assign_apic_irq(apic, intpin, irq);
1296 io_apic_setup_intpin(apic, intpin);
1301 swap_apic_id(int apic, int oldid, int newid)
1308 return; /* Nothing to do */
1310 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1311 apic, oldid, newid);
1313 /* Swap physical APIC IDs in interrupt entries */
1314 for (x = 0; x < nintrs; x++) {
1315 if (io_apic_ints[x].dst_apic_id == oldid)
1316 io_apic_ints[x].dst_apic_id = newid;
1317 else if (io_apic_ints[x].dst_apic_id == newid)
1318 io_apic_ints[x].dst_apic_id = oldid;
1321 /* Swap physical APIC IDs in IO_TO_ID mappings */
1322 for (oapic = 0; oapic < mp_napics; oapic++)
1323 if (IO_TO_ID(oapic) == newid)
1326 if (oapic < mp_napics) {
1327 kprintf("Changing APIC ID for IO APIC #%d from "
1328 "%d to %d in MP table\n",
1329 oapic, newid, oldid);
1330 IO_TO_ID(oapic) = oldid;
1332 IO_TO_ID(apic) = newid;
1337 fix_id_to_io_mapping(void)
1341 for (x = 0; x < NAPICID; x++)
1344 for (x = 0; x <= mp_naps; x++)
1345 if (CPU_TO_ID(x) < NAPICID)
1346 ID_TO_IO(CPU_TO_ID(x)) = x;
1348 for (x = 0; x < mp_napics; x++)
1349 if (IO_TO_ID(x) < NAPICID)
1350 ID_TO_IO(IO_TO_ID(x)) = x;
1355 first_free_apic_id(void)
1359 for (freeid = 0; freeid < NAPICID; freeid++) {
1360 for (x = 0; x <= mp_naps; x++)
1361 if (CPU_TO_ID(x) == freeid)
1365 for (x = 0; x < mp_napics; x++)
1366 if (IO_TO_ID(x) == freeid)
1377 io_apic_id_acceptable(int apic, int id)
1379 int cpu; /* Logical CPU number */
1380 int oapic; /* Logical IO APIC number for other IO APIC */
1383 return 0; /* Out of range */
1385 for (cpu = 0; cpu <= mp_naps; cpu++)
1386 if (CPU_TO_ID(cpu) == id)
1387 return 0; /* Conflict with CPU */
1389 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1390 if (IO_TO_ID(oapic) == id)
1391 return 0; /* Conflict with other APIC */
1393 return 1; /* ID is acceptable for IO APIC */
1398 io_apic_find_int_entry(int apic, int pin)
1402 /* search each of the possible INTerrupt sources */
1403 for (x = 0; x < nintrs; ++x) {
1404 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1405 (pin == io_apic_ints[x].dst_apic_int))
1406 return (&io_apic_ints[x]);
1414 * parse an Intel MP specification table
1422 int apic; /* IO APIC unit number */
1423 int freeid; /* Free physical APIC ID */
1424 int physid; /* Current physical IO APIC ID */
1426 int bus_0 = 0; /* Stop GCC warning */
1427 int bus_pci = 0; /* Stop GCC warning */
1431 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1432 * did it wrong. The MP spec says that when more than 1 PCI bus
1433 * exists the BIOS must begin with bus entries for the PCI bus and use
1434 * actual PCI bus numbering. This implies that when only 1 PCI bus
1435 * exists the BIOS can choose to ignore this ordering, and indeed many
1436 * MP motherboards do ignore it. This causes a problem when the PCI
1437 * sub-system makes requests of the MP sub-system based on PCI bus
1438 * numbers. So here we look for the situation and renumber the
1439 * busses and associated INTs in an effort to "make it right".
1442 /* find bus 0, PCI bus, count the number of PCI busses */
1443 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1444 if (bus_data[x].bus_id == 0) {
1447 if (bus_data[x].bus_type == PCI) {
1453 * bus_0 == slot of bus with ID of 0
1454 * bus_pci == slot of last PCI bus encountered
1457 /* check the 1 PCI bus case for sanity */
1458 /* if it is number 0 all is well */
1459 if (num_pci_bus == 1 &&
1460 bus_data[bus_pci].bus_id != 0) {
1462 /* mis-numbered, swap with whichever bus uses slot 0 */
1464 /* swap the bus entry types */
1465 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1466 bus_data[bus_0].bus_type = PCI;
1468 /* swap each relavant INTerrupt entry */
1469 id = bus_data[bus_pci].bus_id;
1470 for (x = 0; x < nintrs; ++x) {
1471 if (io_apic_ints[x].src_bus_id == id) {
1472 io_apic_ints[x].src_bus_id = 0;
1474 else if (io_apic_ints[x].src_bus_id == 0) {
1475 io_apic_ints[x].src_bus_id = id;
1480 /* Assign IO APIC IDs.
1482 * First try the existing ID. If a conflict is detected, try
1483 * the ID in the MP table. If a conflict is still detected, find
1486 * We cannot use the ID_TO_IO table before all conflicts has been
1487 * resolved and the table has been corrected.
1489 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1491 /* First try to use the value set by the BIOS */
1492 physid = io_apic_get_id(apic);
1493 if (io_apic_id_acceptable(apic, physid)) {
1494 if (IO_TO_ID(apic) != physid)
1495 swap_apic_id(apic, IO_TO_ID(apic), physid);
1499 /* Then check if the value in the MP table is acceptable */
1500 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1503 /* Last resort, find a free APIC ID and use it */
1504 freeid = first_free_apic_id();
1505 if (freeid >= NAPICID)
1506 panic("No free physical APIC IDs found");
1508 if (io_apic_id_acceptable(apic, freeid)) {
1509 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1512 panic("Free physical APIC ID not usable");
1514 fix_id_to_io_mapping();
1516 /* detect and fix broken Compaq MP table */
1517 if (apic_int_type(0, 0) == -1) {
1518 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1519 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1520 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1521 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1522 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1523 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1525 } else if (apic_int_type(0, 0) == 0) {
1526 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1527 for (x = 0; x < nintrs; ++x)
1528 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1529 (0 == io_apic_ints[x].dst_apic_int)) {
1530 io_apic_ints[x].int_type = 3;
1531 io_apic_ints[x].int_vector = 0xff;
1537 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1538 * controllers universally come in pairs. If IRQ 14 is specified
1539 * as an ISA interrupt, then IRQ 15 had better be too.
1541 * [ Shuttle XPC / AMD Athlon X2 ]
1542 * The MPTable is missing an entry for IRQ 15. Note that the
1543 * ACPI table has an entry for both 14 and 15.
1545 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1546 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1547 io14 = io_apic_find_int_entry(0, 14);
1548 io_apic_ints[nintrs] = *io14;
1549 io_apic_ints[nintrs].src_bus_irq = 15;
1550 io_apic_ints[nintrs].dst_apic_int = 15;
1558 /* Assign low level interrupt handlers */
1560 setup_apic_irq_mapping(void)
1566 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1567 int_to_apicintpin[x].ioapic = -1;
1568 int_to_apicintpin[x].int_pin = 0;
1569 int_to_apicintpin[x].apic_address = NULL;
1570 int_to_apicintpin[x].redirindex = 0;
1573 /* First assign ISA/EISA interrupts */
1574 for (x = 0; x < nintrs; x++) {
1575 int_vector = io_apic_ints[x].src_bus_irq;
1576 if (int_vector < APIC_INTMAPSIZE &&
1577 io_apic_ints[x].int_vector == 0xff &&
1578 int_to_apicintpin[int_vector].ioapic == -1 &&
1579 (apic_int_is_bus_type(x, ISA) ||
1580 apic_int_is_bus_type(x, EISA)) &&
1581 io_apic_ints[x].int_type == 0) {
1582 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1583 io_apic_ints[x].dst_apic_int,
1588 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1589 for (x = 0; x < nintrs; x++) {
1590 if (io_apic_ints[x].dst_apic_int == 0 &&
1591 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1592 io_apic_ints[x].int_vector == 0xff &&
1593 int_to_apicintpin[0].ioapic == -1 &&
1594 io_apic_ints[x].int_type == 3) {
1595 assign_apic_irq(0, 0, 0);
1599 /* PCI interrupt assignment is deferred */
1605 mp_set_cpuids(int cpu_id, int apic_id)
1607 CPU_TO_ID(cpu_id) = apic_id;
1608 ID_TO_CPU(apic_id) = cpu_id;
1612 processor_entry(const struct PROCENTRY *entry, int cpu)
1616 /* check for usability */
1617 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1620 /* check for BSP flag */
1621 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1622 mp_set_cpuids(0, entry->apic_id);
1623 return 0; /* its already been counted */
1626 /* add another AP to list, if less than max number of CPUs */
1627 else if (cpu < MAXCPU) {
1628 mp_set_cpuids(cpu, entry->apic_id);
1638 bus_entry(bus_entry_ptr entry, int bus)
1643 /* encode the name into an index */
1644 for (x = 0; x < 6; ++x) {
1645 if ((c = entry->bus_type[x]) == ' ')
1651 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1652 panic("unknown bus type: '%s'", name);
1654 bus_data[bus].bus_id = entry->bus_id;
1655 bus_data[bus].bus_type = x;
1661 io_apic_entry(io_apic_entry_ptr entry, int apic)
1663 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1666 IO_TO_ID(apic) = entry->apic_id;
1667 ID_TO_IO(entry->apic_id) = apic;
1675 lookup_bus_type(char *name)
1679 for (x = 0; x < MAX_BUSTYPE; ++x)
1680 if (strcmp(bus_type_table[x].name, name) == 0)
1681 return bus_type_table[x].type;
1683 return UNKNOWN_BUSTYPE;
1689 int_entry(int_entry_ptr entry, int intr)
1693 io_apic_ints[intr].int_type = entry->int_type;
1694 io_apic_ints[intr].int_flags = entry->int_flags;
1695 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1696 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1697 if (entry->dst_apic_id == 255) {
1698 /* This signal goes to all IO APICS. Select an IO APIC
1699 with sufficient number of interrupt pins */
1700 for (apic = 0; apic < mp_napics; apic++)
1701 if (((io_apic_read(apic, IOAPIC_VER) &
1702 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1703 entry->dst_apic_int)
1705 if (apic < mp_napics)
1706 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1708 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1710 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1711 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1717 apic_int_is_bus_type(int intr, int bus_type)
1721 for (bus = 0; bus < mp_nbusses; ++bus)
1722 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1723 && ((int) bus_data[bus].bus_type == bus_type))
1730 * Given a traditional ISA INT mask, return an APIC mask.
1733 isa_apic_mask(u_int isa_mask)
1738 #if defined(SKIP_IRQ15_REDIRECT)
1739 if (isa_mask == (1 << 15)) {
1740 kprintf("skipping ISA IRQ15 redirect\n");
1743 #endif /* SKIP_IRQ15_REDIRECT */
1745 isa_irq = ffs(isa_mask); /* find its bit position */
1746 if (isa_irq == 0) /* doesn't exist */
1748 --isa_irq; /* make it zero based */
1750 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1754 return (1 << apic_pin); /* convert pin# to a mask */
1758 * Determine which APIC pin an ISA/EISA INT is attached to.
1760 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1761 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1762 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1763 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1765 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1767 isa_apic_irq(int isa_irq)
1771 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1772 if (INTTYPE(intr) == 0) { /* standard INT */
1773 if (SRCBUSIRQ(intr) == isa_irq) {
1774 if (apic_int_is_bus_type(intr, ISA) ||
1775 apic_int_is_bus_type(intr, EISA)) {
1776 if (INTIRQ(intr) == 0xff)
1777 return -1; /* unassigned */
1778 return INTIRQ(intr); /* found */
1783 return -1; /* NOT found */
1788 * Determine which APIC pin a PCI INT is attached to.
1790 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1791 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1792 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1794 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1798 --pciInt; /* zero based */
1800 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1801 if ((INTTYPE(intr) == 0) /* standard INT */
1802 && (SRCBUSID(intr) == pciBus)
1803 && (SRCBUSDEVICE(intr) == pciDevice)
1804 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1805 if (apic_int_is_bus_type(intr, PCI)) {
1806 if (INTIRQ(intr) == 0xff)
1807 allocate_apic_irq(intr);
1808 if (INTIRQ(intr) == 0xff)
1809 return -1; /* unassigned */
1810 return INTIRQ(intr); /* exact match */
1815 return -1; /* NOT found */
1819 next_apic_irq(int irq)
1826 for (intr = 0; intr < nintrs; intr++) {
1827 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1829 bus = SRCBUSID(intr);
1830 bustype = apic_bus_type(bus);
1831 if (bustype != ISA &&
1837 if (intr >= nintrs) {
1840 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1841 if (INTTYPE(ointr) != 0)
1843 if (bus != SRCBUSID(ointr))
1845 if (bustype == PCI) {
1846 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1848 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1851 if (bustype == ISA || bustype == EISA) {
1852 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1855 if (INTPIN(intr) == INTPIN(ointr))
1859 if (ointr >= nintrs) {
1862 return INTIRQ(ointr);
1877 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1880 * Exactly what this means is unclear at this point. It is a solution
1881 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1882 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1883 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1887 undirect_isa_irq(int rirq)
1891 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1892 /** FIXME: tickle the MB redirector chip */
1896 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1903 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1906 undirect_pci_irq(int rirq)
1910 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1912 /** FIXME: tickle the MB redirector chip */
1916 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1926 * given a bus ID, return:
1927 * the bus type if found
1931 apic_bus_type(int id)
1935 for (x = 0; x < mp_nbusses; ++x)
1936 if (bus_data[x].bus_id == id)
1937 return bus_data[x].bus_type;
1943 * given a LOGICAL APIC# and pin#, return:
1944 * the associated src bus ID if found
1948 apic_src_bus_id(int apic, int pin)
1952 /* search each of the possible INTerrupt sources */
1953 for (x = 0; x < nintrs; ++x)
1954 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1955 (pin == io_apic_ints[x].dst_apic_int))
1956 return (io_apic_ints[x].src_bus_id);
1958 return -1; /* NOT found */
1962 * given a LOGICAL APIC# and pin#, return:
1963 * the associated src bus IRQ if found
1967 apic_src_bus_irq(int apic, int pin)
1971 for (x = 0; x < nintrs; x++)
1972 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1973 (pin == io_apic_ints[x].dst_apic_int))
1974 return (io_apic_ints[x].src_bus_irq);
1976 return -1; /* NOT found */
1981 * given a LOGICAL APIC# and pin#, return:
1982 * the associated INTerrupt type if found
1986 apic_int_type(int apic, int pin)
1990 /* search each of the possible INTerrupt sources */
1991 for (x = 0; x < nintrs; ++x) {
1992 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1993 (pin == io_apic_ints[x].dst_apic_int))
1994 return (io_apic_ints[x].int_type);
1996 return -1; /* NOT found */
2000 * Return the IRQ associated with an APIC pin
2003 apic_irq(int apic, int pin)
2008 for (x = 0; x < nintrs; ++x) {
2009 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2010 (pin == io_apic_ints[x].dst_apic_int)) {
2011 res = io_apic_ints[x].int_vector;
2014 if (apic != int_to_apicintpin[res].ioapic)
2015 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2016 if (pin != int_to_apicintpin[res].int_pin)
2017 panic("apic_irq inconsistent table (2)");
2026 * given a LOGICAL APIC# and pin#, return:
2027 * the associated trigger mode if found
2031 apic_trigger(int apic, int pin)
2035 /* search each of the possible INTerrupt sources */
2036 for (x = 0; x < nintrs; ++x)
2037 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2038 (pin == io_apic_ints[x].dst_apic_int))
2039 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2041 return -1; /* NOT found */
2046 * given a LOGICAL APIC# and pin#, return:
2047 * the associated 'active' level if found
2051 apic_polarity(int apic, int pin)
2055 /* search each of the possible INTerrupt sources */
2056 for (x = 0; x < nintrs; ++x)
2057 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2058 (pin == io_apic_ints[x].dst_apic_int))
2059 return (io_apic_ints[x].int_flags & 0x03);
2061 return -1; /* NOT found */
2067 * set data according to MP defaults
2068 * FIXME: probably not complete yet...
2071 mptable_default(int type)
2073 #if defined(APIC_IO)
2076 #endif /* APIC_IO */
2079 kprintf(" MP default config type: %d\n", type);
2082 kprintf(" bus: ISA, APIC: 82489DX\n");
2085 kprintf(" bus: EISA, APIC: 82489DX\n");
2088 kprintf(" bus: EISA, APIC: 82489DX\n");
2091 kprintf(" bus: MCA, APIC: 82489DX\n");
2094 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2097 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2100 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2103 kprintf(" future type\n");
2109 #if defined(APIC_IO)
2110 /* one and only IO APIC */
2111 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2114 * sanity check, refer to MP spec section 3.6.6, last paragraph
2115 * necessary as some hardware isn't properly setting up the IO APIC
2117 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2118 if (io_apic_id != 2) {
2120 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2121 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2122 io_apic_set_id(0, 2);
2125 IO_TO_ID(0) = io_apic_id;
2126 ID_TO_IO(io_apic_id) = 0;
2127 #endif /* APIC_IO */
2129 /* fill out bus entries */
2139 bus_data[0].bus_id = default_data[type - 1][1];
2140 bus_data[0].bus_type = default_data[type - 1][2];
2141 bus_data[1].bus_id = default_data[type - 1][3];
2142 bus_data[1].bus_type = default_data[type - 1][4];
2146 /* case 4: case 7: MCA NOT supported */
2147 default: /* illegal/reserved */
2148 panic("BAD default MP config: %d", type);
2152 #if defined(APIC_IO)
2153 /* general cases from MP v1.4, table 5-2 */
2154 for (pin = 0; pin < 16; ++pin) {
2155 io_apic_ints[pin].int_type = 0;
2156 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2157 io_apic_ints[pin].src_bus_id = 0;
2158 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2159 io_apic_ints[pin].dst_apic_id = io_apic_id;
2160 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2163 /* special cases from MP v1.4, table 5-2 */
2165 io_apic_ints[2].int_type = 0xff; /* N/C */
2166 io_apic_ints[13].int_type = 0xff; /* N/C */
2167 #if !defined(APIC_MIXED_MODE)
2169 panic("sorry, can't support type 2 default yet");
2170 #endif /* APIC_MIXED_MODE */
2173 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2176 io_apic_ints[0].int_type = 0xff; /* N/C */
2178 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2179 #endif /* APIC_IO */
2183 * Map a physical memory address representing I/O into KVA. The I/O
2184 * block is assumed not to cross a page boundary.
2187 permanent_io_mapping(vm_paddr_t pa)
2193 KKASSERT(pa < 0x100000000LL);
2195 pgeflag = 0; /* not used for SMP yet */
2198 * If the requested physical address has already been incidently
2199 * mapped, just use the existing mapping. Otherwise create a new
2202 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2203 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2204 ((vm_offset_t)pa & PG_FRAME)) {
2208 if (i == SMPpt_alloc_index) {
2209 if (i == NPTEPG - 2) {
2210 panic("permanent_io_mapping: We ran out of space"
2213 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2214 ((vm_offset_t)pa & PG_FRAME));
2215 ++SMPpt_alloc_index;
2217 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2218 ((vm_offset_t)pa & PAGE_MASK);
2219 return ((void *)vaddr);
2223 * start each AP in our list
2226 start_all_aps(u_int boot_addr)
2230 u_char mpbiosreason;
2231 u_long mpbioswarmvec;
2232 struct mdglobaldata *gd;
2233 struct privatespace *ps;
2237 POSTCODE(START_ALL_APS_POST);
2239 /* Initialize BSP's local APIC */
2240 apic_initialize(TRUE);
2242 /* install the AP 1st level boot code */
2243 install_ap_tramp(boot_addr);
2246 /* save the current value of the warm-start vector */
2247 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2248 outb(CMOS_REG, BIOS_RESET);
2249 mpbiosreason = inb(CMOS_DATA);
2251 /* set up temporary P==V mapping for AP boot */
2252 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2253 kptbase = (uintptr_t)(void *)KPTphys;
2254 for (x = 0; x < NKPT; x++) {
2255 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2256 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2261 for (x = 1; x <= mp_naps; ++x) {
2263 /* This is a bit verbose, it will go away soon. */
2265 /* first page of AP's private space */
2266 pg = x * i386_btop(sizeof(struct privatespace));
2268 /* allocate new private data page(s) */
2269 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2270 MDGLOBALDATA_BASEALLOC_SIZE);
2271 /* wire it into the private page table page */
2272 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2273 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2274 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2276 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2278 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2279 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2280 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2281 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2283 /* allocate and set up an idle stack data page */
2284 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2285 for (i = 0; i < UPAGES; i++) {
2286 SMPpt[pg + 4 + i] = (pt_entry_t)
2287 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2290 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2291 bzero(gd, sizeof(*gd));
2292 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2294 /* prime data page for it to use */
2295 mi_gdinit(&gd->mi, x);
2297 gd->gd_CMAP1 = &SMPpt[pg + 0];
2298 gd->gd_CMAP2 = &SMPpt[pg + 1];
2299 gd->gd_CMAP3 = &SMPpt[pg + 2];
2300 gd->gd_PMAP1 = &SMPpt[pg + 3];
2301 gd->gd_CADDR1 = ps->CPAGE1;
2302 gd->gd_CADDR2 = ps->CPAGE2;
2303 gd->gd_CADDR3 = ps->CPAGE3;
2304 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2305 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2306 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2308 /* setup a vector to our boot code */
2309 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2310 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2311 outb(CMOS_REG, BIOS_RESET);
2312 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2315 * Setup the AP boot stack
2317 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2320 /* attempt to start the Application Processor */
2321 CHECK_INIT(99); /* setup checkpoints */
2322 if (!start_ap(gd, boot_addr)) {
2323 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2324 CHECK_PRINT("trace"); /* show checkpoints */
2325 /* better panic as the AP may be running loose */
2326 kprintf("panic y/n? [y] ");
2327 if (cngetc() != 'n')
2330 CHECK_PRINT("trace"); /* show checkpoints */
2332 /* record its version info */
2333 cpu_apic_versions[x] = cpu_apic_versions[0];
2336 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2339 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2340 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2343 ncpus2_shift = shift;
2344 ncpus2 = 1 << shift;
2345 ncpus2_mask = ncpus2 - 1;
2347 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2348 if ((1 << shift) < ncpus)
2350 ncpus_fit = 1 << shift;
2351 ncpus_fit_mask = ncpus_fit - 1;
2353 /* build our map of 'other' CPUs */
2354 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2355 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2356 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2358 /* fill in our (BSP) APIC version */
2359 cpu_apic_versions[0] = lapic.version;
2361 /* restore the warmstart vector */
2362 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2363 outb(CMOS_REG, BIOS_RESET);
2364 outb(CMOS_DATA, mpbiosreason);
2367 * NOTE! The idlestack for the BSP was setup by locore. Finish
2368 * up, clean out the P==V mapping we did earlier.
2370 for (x = 0; x < NKPT; x++)
2374 /* number of APs actually started */
2380 * load the 1st level AP boot code into base memory.
2383 /* targets for relocation */
2384 extern void bigJump(void);
2385 extern void bootCodeSeg(void);
2386 extern void bootDataSeg(void);
2387 extern void MPentry(void);
2388 extern u_int MP_GDT;
2389 extern u_int mp_gdtbase;
2392 install_ap_tramp(u_int boot_addr)
2395 int size = *(int *) ((u_long) & bootMP_size);
2396 u_char *src = (u_char *) ((u_long) bootMP);
2397 u_char *dst = (u_char *) boot_addr + KERNBASE;
2398 u_int boot_base = (u_int) bootMP;
2403 POSTCODE(INSTALL_AP_TRAMP_POST);
2405 for (x = 0; x < size; ++x)
2409 * modify addresses in code we just moved to basemem. unfortunately we
2410 * need fairly detailed info about mpboot.s for this to work. changes
2411 * to mpboot.s might require changes here.
2414 /* boot code is located in KERNEL space */
2415 dst = (u_char *) boot_addr + KERNBASE;
2417 /* modify the lgdt arg */
2418 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2419 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2421 /* modify the ljmp target for MPentry() */
2422 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2423 *dst32 = ((u_int) MPentry - KERNBASE);
2425 /* modify the target for boot code segment */
2426 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2427 dst8 = (u_int8_t *) (dst16 + 1);
2428 *dst16 = (u_int) boot_addr & 0xffff;
2429 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2431 /* modify the target for boot data segment */
2432 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2433 dst8 = (u_int8_t *) (dst16 + 1);
2434 *dst16 = (u_int) boot_addr & 0xffff;
2435 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2440 * this function starts the AP (application processor) identified
2441 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2442 * to accomplish this. This is necessary because of the nuances
2443 * of the different hardware we might encounter. It ain't pretty,
2444 * but it seems to work.
2446 * NOTE: eventually an AP gets to ap_init(), which is called just
2447 * before the AP goes into the LWKT scheduler's idle loop.
2450 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2454 u_long icr_lo, icr_hi;
2456 POSTCODE(START_AP_POST);
2458 /* get the PHYSICAL APIC ID# */
2459 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2461 /* calculate the vector */
2462 vector = (boot_addr >> 12) & 0xff;
2464 /* Make sure the target cpu sees everything */
2468 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2469 * and running the target CPU. OR this INIT IPI might be latched (P5
2470 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2474 /* setup the address for the target AP */
2475 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2476 icr_hi |= (physical_cpu << 24);
2477 lapic.icr_hi = icr_hi;
2479 /* do an INIT IPI: assert RESET */
2480 icr_lo = lapic.icr_lo & 0xfff00000;
2481 lapic.icr_lo = icr_lo | 0x0000c500;
2483 /* wait for pending status end */
2484 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2487 /* do an INIT IPI: deassert RESET */
2488 lapic.icr_lo = icr_lo | 0x00008500;
2490 /* wait for pending status end */
2491 u_sleep(10000); /* wait ~10mS */
2492 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2496 * next we do a STARTUP IPI: the previous INIT IPI might still be
2497 * latched, (P5 bug) this 1st STARTUP would then terminate
2498 * immediately, and the previously started INIT IPI would continue. OR
2499 * the previous INIT IPI has already run. and this STARTUP IPI will
2500 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2504 /* do a STARTUP IPI */
2505 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2506 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2508 u_sleep(200); /* wait ~200uS */
2511 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2512 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2513 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2514 * recognized after hardware RESET or INIT IPI.
2517 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2518 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2520 u_sleep(200); /* wait ~200uS */
2522 /* wait for it to start, see ap_init() */
2523 set_apic_timer(5000000);/* == 5 seconds */
2524 while (read_apic_timer()) {
2525 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2526 return 1; /* return SUCCESS */
2528 return 0; /* return FAILURE */
2533 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2535 * If for some reason we were unable to start all cpus we cannot safely
2536 * use broadcast IPIs.
2542 if (smp_startup_mask == smp_active_mask) {
2543 all_but_self_ipi(XINVLTLB_OFFSET);
2545 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2546 APIC_DELMODE_FIXED);
2552 * When called the executing CPU will send an IPI to all other CPUs
2553 * requesting that they halt execution.
2555 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2557 * - Signals all CPUs in map to stop.
2558 * - Waits for each to stop.
2565 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2566 * from executing at same time.
2569 stop_cpus(u_int map)
2571 map &= smp_active_mask;
2573 /* send the Xcpustop IPI to all CPUs in map */
2574 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2576 while ((stopped_cpus & map) != map)
2584 * Called by a CPU to restart stopped CPUs.
2586 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2588 * - Signals all CPUs in map to restart.
2589 * - Waits for each to restart.
2597 restart_cpus(u_int map)
2599 /* signal other cpus to restart */
2600 started_cpus = map & smp_active_mask;
2602 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2609 * This is called once the mpboot code has gotten us properly relocated
2610 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2611 * and when it returns the scheduler will call the real cpu_idle() main
2612 * loop for the idlethread. Interrupts are disabled on entry and should
2613 * remain disabled at return.
2621 * Adjust smp_startup_mask to signal the BSP that we have started
2622 * up successfully. Note that we do not yet hold the BGL. The BSP
2623 * is waiting for our signal.
2625 * We can't set our bit in smp_active_mask yet because we are holding
2626 * interrupts physically disabled and remote cpus could deadlock
2627 * trying to send us an IPI.
2629 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2633 * Interlock for finalization. Wait until mp_finish is non-zero,
2634 * then get the MP lock.
2636 * Note: We are in a critical section.
2638 * Note: We have to synchronize td_mpcount to our desired MP state
2639 * before calling cpu_try_mplock().
2641 * Note: we are the idle thread, we can only spin.
2643 * Note: The load fence is memory volatile and prevents the compiler
2644 * from improperly caching mp_finish, and the cpu from improperly
2647 while (mp_finish == 0)
2649 ++curthread->td_mpcount;
2650 while (cpu_try_mplock() == 0)
2653 if (cpu_feature & CPUID_TSC) {
2655 * The BSP is constantly updating tsc0_offset, figure out the
2656 * relative difference to synchronize ktrdump.
2658 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2661 /* BSP may have changed PTD while we're waiting for the lock */
2664 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2668 /* Build our map of 'other' CPUs. */
2669 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2671 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2673 /* A quick check from sanity claus */
2674 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2675 if (mycpu->gd_cpuid != apic_id) {
2676 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2677 kprintf("SMP: apic_id = %d\n", apic_id);
2678 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2679 panic("cpuid mismatch! boom!!");
2682 /* Initialize AP's local APIC for irq's */
2683 apic_initialize(FALSE);
2685 /* Set memory range attributes for this CPU to match the BSP */
2686 mem_range_AP_init();
2689 * Once we go active we must process any IPIQ messages that may
2690 * have been queued, because no actual IPI will occur until we
2691 * set our bit in the smp_active_mask. If we don't the IPI
2692 * message interlock could be left set which would also prevent
2695 * The idle loop doesn't expect the BGL to be held and while
2696 * lwkt_switch() normally cleans things up this is a special case
2697 * because we returning almost directly into the idle loop.
2699 * The idle thread is never placed on the runq, make sure
2700 * nothing we've done put it there.
2702 KKASSERT(curthread->td_mpcount == 1);
2703 smp_active_mask |= 1 << mycpu->gd_cpuid;
2706 * Enable interrupts here. idle_restore will also do it, but
2707 * doing it here lets us clean up any strays that got posted to
2708 * the CPU during the AP boot while we are still in a critical
2711 __asm __volatile("sti; pause; pause"::);
2712 mdcpu->gd_fpending = 0;
2713 mdcpu->gd_ipending = 0;
2715 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2716 lwkt_process_ipiq();
2719 * Releasing the mp lock lets the BSP finish up the SMP init
2722 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2726 * Get SMP fully working before we start initializing devices.
2734 kprintf("Finish MP startup\n");
2735 if (cpu_feature & CPUID_TSC)
2736 tsc0_offset = rdtsc();
2739 while (smp_active_mask != smp_startup_mask) {
2741 if (cpu_feature & CPUID_TSC)
2742 tsc0_offset = rdtsc();
2744 while (try_mplock() == 0)
2747 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2750 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2753 cpu_send_ipiq(int dcpu)
2755 if ((1 << dcpu) & smp_active_mask)
2756 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2759 #if 0 /* single_apic_ipi_passive() not working yet */
2761 * Returns 0 on failure, 1 on success
2764 cpu_send_ipiq_passive(int dcpu)
2767 if ((1 << dcpu) & smp_active_mask) {
2768 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2769 APIC_DELMODE_FIXED);
2775 struct mptable_lapic_cbarg1 {
2778 u_int ht_apicid_mask;
2782 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2784 const struct PROCENTRY *ent;
2785 struct mptable_lapic_cbarg1 *arg = xarg;
2791 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2795 if (ent->apic_id < 32) {
2796 arg->ht_apicid_mask |= 1 << ent->apic_id;
2797 } else if (arg->ht_fixup) {
2798 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2804 struct mptable_lapic_cbarg2 {
2811 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2813 const struct PROCENTRY *ent;
2814 struct mptable_lapic_cbarg2 *arg = xarg;
2820 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2821 KKASSERT(!arg->found_bsp);
2825 if (processor_entry(ent, arg->cpu))
2828 if (arg->logical_cpus) {
2829 struct PROCENTRY proc;
2833 * Create fake mptable processor entries
2834 * and feed them to processor_entry() to
2835 * enumerate the logical CPUs.
2837 bzero(&proc, sizeof(proc));
2839 proc.cpu_flags = PROCENTRY_FLAG_EN;
2840 proc.apic_id = ent->apic_id;
2842 for (i = 1; i < arg->logical_cpus; i++) {
2844 processor_entry(&proc, arg->cpu);
2852 mptable_lapic_default(void)
2854 int ap_apicid, bsp_apicid;
2856 mp_naps = 1; /* exclude BSP */
2858 /* Map local apic before the id field is accessed */
2859 lapic_init(DEFAULT_APIC_BASE);
2861 bsp_apicid = APIC_ID(lapic.id);
2862 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2865 mp_set_cpuids(0, bsp_apicid);
2866 /* one and only AP */
2867 mp_set_cpuids(1, ap_apicid);
2872 * cpu_apic_address (common to all CPUs)
2874 * ID_TO_CPU(N), APIC ID to logical CPU table
2875 * CPU_TO_ID(N), logical CPU to APIC ID table
2878 mptable_lapic_enumerate(struct mptable_pos *mpt)
2880 struct mptable_lapic_cbarg1 arg1;
2881 struct mptable_lapic_cbarg2 arg2;
2883 int error, logical_cpus = 0;
2884 vm_offset_t lapic_addr;
2886 KKASSERT(mpt->mp_fps != NULL);
2889 * Check for use of 'default' configuration
2891 if (mpt->mp_fps->mpfb1 != 0) {
2892 mptable_lapic_default();
2897 KKASSERT(cth != NULL);
2899 /* Save local apic address */
2900 lapic_addr = (vm_offset_t)cth->apic_address;
2901 KKASSERT(lapic_addr != 0);
2904 * Find out how many CPUs do we have
2906 bzero(&arg1, sizeof(arg1));
2907 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2909 error = mptable_iterate_entries(cth,
2910 mptable_lapic_pass1_callback, &arg1);
2912 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2913 KKASSERT(arg1.cpu_count != 0);
2915 /* See if we need to fixup HT logical CPUs. */
2916 if (arg1.ht_fixup) {
2917 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2919 if (logical_cpus != 0)
2920 arg1.cpu_count *= logical_cpus;
2922 mp_naps = arg1.cpu_count;
2924 /* Qualify the numbers again, after possible HT fixup */
2925 if (mp_naps > MAXCPU) {
2926 kprintf("Warning: only using %d of %d available CPUs!\n",
2931 --mp_naps; /* subtract the BSP */
2934 * Link logical CPU id to local apic id
2936 bzero(&arg2, sizeof(arg2));
2938 arg2.logical_cpus = logical_cpus;
2940 error = mptable_iterate_entries(cth,
2941 mptable_lapic_pass2_callback, &arg2);
2943 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2944 KKASSERT(arg2.found_bsp);
2946 /* Map local apic */
2947 lapic_init(lapic_addr);
2951 lapic_init(vm_offset_t lapic_addr)
2953 /* Local apic is mapped on last page */
2954 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
2955 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
2957 /* Just for printing */
2958 cpu_apic_address = lapic_addr;