2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>. AMD register addresses and
6 * values were pulled from MemTest-86 and Linux.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
42 #include <bus/pci/pcivar.h>
43 #include <bus/pci/pcireg.h>
44 #include <bus/pci/pcibus.h>
45 #include <bus/pci/pci_cfgreg.h>
46 #include <bus/pci/pcib_private.h>
50 static int setup_none(device_t dev);
51 static int setup_amd64(device_t dev);
52 static void poll_amd64(void *dev_arg);
54 struct pci_memory_controller {
58 int (*setup)(device_t dev);
61 struct pci_ecc_softc {
62 struct pci_memory_controller *config;
63 struct callout poll_callout;
67 static struct pci_memory_controller mem_controllers[] = {
69 { 0x1022, 0x7006, "AMD 751", setup_none },
70 { 0x1022, 0x700c, "AMD 762", setup_none },
71 { 0x1022, 0x700e, "AMD 761", setup_none },
72 { 0x1022, 0x1100, "AMD 8000", setup_amd64 },
73 { 0x1022, 0x7454, "AMD 8000", setup_amd64 }
77 pci_ecc_probe(device_t dev)
79 struct pci_ecc_softc *sc;
84 vid = pci_get_vendor(dev);
85 did = pci_get_device(dev);
87 for (i = 0; i < NELEM(mem_controllers); ++i) {
88 if (mem_controllers[i].vid == vid &&
89 mem_controllers[i].did == did
91 sc = device_get_softc(dev);
92 sc->config = &mem_controllers[i];
100 pci_ecc_attach(device_t dev)
102 struct pci_ecc_softc *sc = device_get_softc(dev);
104 return (sc->config->setup(dev));
107 static device_method_t pci_ecc_methods[] = {
108 /* Device interface */
109 DEVMETHOD(device_probe, pci_ecc_probe),
110 DEVMETHOD(device_attach, pci_ecc_attach),
111 DEVMETHOD(device_shutdown, bus_generic_shutdown),
112 DEVMETHOD(device_suspend, bus_generic_suspend),
113 DEVMETHOD(device_resume, bus_generic_resume),
117 static driver_t pci_ecc_driver = {
120 sizeof(struct pci_ecc_softc)
122 static devclass_t ecc_devclass;
123 DRIVER_MODULE(ecc, pci, pci_ecc_driver, ecc_devclass, NULL, NULL);
124 MODULE_DEPEND(ecc, pci, 1, 1, 1);
127 * Architecture-specific procedures
131 setup_none(device_t dev)
138 setup_amd64(device_t dev)
140 struct pci_ecc_softc *sc = device_get_softc(dev);
143 int bus = pci_get_bus(dev);
144 int slot = pci_get_slot(dev);
147 * The memory bridge is recognized as four PCI devices
148 * using function codes 0, 1, 2, and 3. We probe for the
149 * device at function code 0 and assume that all four exist.
151 draminfo = pcib_read_config(dev, bus, slot, 2, 0x90, 4);
152 eccinfo = pcib_read_config(dev, bus, slot, 3, 0x44, 4);
154 device_printf(dev, "attached %s memory controller\n", sc->config->desc);
155 if ((draminfo >> 17) & 1)
156 device_printf(dev, "memory type: ECC\n");
158 device_printf(dev, "memory type: NON-ECC\n");
159 switch((eccinfo >> 22) & 3) {
161 device_printf(dev, "ecc mode: DISABLED\n");
164 device_printf(dev, "ecc mode: ENABLED/CORRECT-MODE\n");
168 device_printf(dev, "ecc mode: ENABLED/RESERVED (disabled)\n");
171 device_printf(dev, "ecc mode: ENABLED/CHIPKILL-MODE\n");
177 * Enable ECC logging and clear any previous error.
179 if (sc->poll_enable) {
184 wrmsr(0x17B, (v64 & ~0xFFFFFFFFLL) | 0x00000010LL);
185 v32 = pcib_read_config(dev, bus, slot, 3, 0x4C, 4);
187 pcib_write_config(dev, bus, slot, 3, 0x4C, v32, 4);
189 callout_init(&sc->poll_callout);
190 callout_reset(&sc->poll_callout, hz, poll_amd64, dev);
197 poll_amd64(void *dev_arg)
199 device_t dev = dev_arg;
200 struct pci_ecc_softc *sc = device_get_softc(dev);
201 int bus = pci_get_bus(dev);
202 int slot = pci_get_slot(dev);
207 * The address calculation is not entirely correct. We need to
208 * look at the AMD chipset documentation.
210 v32 = pcib_read_config(dev, bus, slot, 3, 0x4C, 4);
211 if ((v32 & 0x80004000) == 0x80004000) {
212 addr = pcib_read_config(dev, bus, slot, 3, 0x50, 4);
213 device_printf(dev, "Correctable ECC error at %08x\n", addr);
214 pcib_write_config(dev, bus, slot, 3, 0x4C, v32 & 0x7F801EFC, 4);
215 } else if ((v32 & 0x80002000) == 0x80002000) {
216 addr = pcib_read_config(dev, bus ,slot, 3, 0x50, 4);
217 device_printf(dev, "Uncorrectable ECC error at %08x\n", addr);
218 pcib_write_config(dev, bus, slot, 3, 0x4C, v32 & 0x7F801EFC, 4);
220 callout_reset(&sc->poll_callout, hz, poll_amd64, dev);