sys/dev/drm/r600_blit.c

   1 /*-
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  * __FBSDID("$FreeBSD: src/sys/dev/drm/r600_blit.c,v 1.5 2009/10/30 18:08:46 rnoland Exp $");
  26  */
  27
  28 #include "dev/drm/drmP.h"
  29 #include "dev/drm/drm.h"
  30 #include "dev/drm/radeon_drm.h"
  31 #include "dev/drm/radeon_drv.h"
  32
  33 static u32 r6xx_default_state[] =
  34 {
  35         0xc0002400,
  36         0x00000000,
  37         0xc0012800,
  38         0x80000000,
  39         0x80000000,
  40         0xc0004600,
  41         0x00000016,
  42         0xc0016800,
  43         0x00000010,
  44         0x00028000,
  45         0xc0016800,
  46         0x00000010,
  47         0x00008000,
  48         0xc0016800,
  49         0x00000542,
  50         0x07000003,
  51         0xc0016800,
  52         0x000005c5,
  53         0x00000000,
  54         0xc0016800,
  55         0x00000363,
  56         0x00000000,
  57         0xc0016800,
  58         0x0000060c,
  59         0x82000000,
  60         0xc0016800,
  61         0x0000060e,
  62         0x01020204,
  63         0xc0016f00,
  64         0x00000000,
  65         0x00000000,
  66         0xc0016f00,
  67         0x00000001,
  68         0x00000000,
  69         0xc0096900,
  70         0x0000022a,
  71         0x00000000,
  72         0x00000000,
  73         0x00000000,
  74         0x00000000,
  75         0x00000000,
  76         0x00000000,
  77         0x00000000,
  78         0x00000000,
  79         0x00000000,
  80         0xc0016900,
  81         0x00000004,
  82         0x00000000,
  83         0xc0016900,
  84         0x0000000a,
  85         0x00000000,
  86         0xc0016900,
  87         0x0000000b,
  88         0x00000000,
  89         0xc0016900,
  90         0x0000010c,
  91         0x00000000,
  92         0xc0016900,
  93         0x0000010d,
  94         0x00000000,
  95         0xc0016900,
  96         0x00000200,
  97         0x00000000,
  98         0xc0016900,
  99         0x00000343,
 100         0x00000060,
 101         0xc0016900,
 102         0x00000344,
 103         0x00000040,
 104         0xc0016900,
 105         0x00000351,
 106         0x0000aa00,
 107         0xc0016900,
 108         0x00000104,
 109         0x00000000,
 110         0xc0016900,
 111         0x0000010e,
 112         0x00000000,
 113         0xc0046900,
 114         0x00000105,
 115         0x00000000,
 116         0x00000000,
 117         0x00000000,
 118         0x00000000,
 119         0xc0036900,
 120         0x00000109,
 121         0x00000000,
 122         0x00000000,
 123         0x00000000,
 124         0xc0046900,
 125         0x0000030c,
 126         0x01000000,
 127         0x00000000,
 128         0x00000000,
 129         0x00000000,
 130         0xc0046900,
 131         0x00000048,
 132         0x3f800000,
 133         0x00000000,
 134         0x3f800000,
 135         0x3f800000,
 136         0xc0016900,
 137         0x0000008e,
 138         0x0000000f,
 139         0xc0016900,
 140         0x00000080,
 141         0x00000000,
 142         0xc0016900,
 143         0x00000083,
 144         0x0000ffff,
 145         0xc0016900,
 146         0x00000084,
 147         0x00000000,
 148         0xc0016900,
 149         0x00000085,
 150         0x20002000,
 151         0xc0016900,
 152         0x00000086,
 153         0x00000000,
 154         0xc0016900,
 155         0x00000087,
 156         0x20002000,
 157         0xc0016900,
 158         0x00000088,
 159         0x00000000,
 160         0xc0016900,
 161         0x00000089,
 162         0x20002000,
 163         0xc0016900,
 164         0x0000008a,
 165         0x00000000,
 166         0xc0016900,
 167         0x0000008b,
 168         0x20002000,
 169         0xc0016900,
 170         0x0000008c,
 171         0x00000000,
 172         0xc0016900,
 173         0x00000094,
 174         0x80000000,
 175         0xc0016900,
 176         0x00000095,
 177         0x20002000,
 178         0xc0026900,
 179         0x000000b4,
 180         0x00000000,
 181         0x3f800000,
 182         0xc0016900,
 183         0x00000096,
 184         0x80000000,
 185         0xc0016900,
 186         0x00000097,
 187         0x20002000,
 188         0xc0026900,
 189         0x000000b6,
 190         0x00000000,
 191         0x3f800000,
 192         0xc0016900,
 193         0x00000098,
 194         0x80000000,
 195         0xc0016900,
 196         0x00000099,
 197         0x20002000,
 198         0xc0026900,
 199         0x000000b8,
 200         0x00000000,
 201         0x3f800000,
 202         0xc0016900,
 203         0x0000009a,
 204         0x80000000,
 205         0xc0016900,
 206         0x0000009b,
 207         0x20002000,
 208         0xc0026900,
 209         0x000000ba,
 210         0x00000000,
 211         0x3f800000,
 212         0xc0016900,
 213         0x0000009c,
 214         0x80000000,
 215         0xc0016900,
 216         0x0000009d,
 217         0x20002000,
 218         0xc0026900,
 219         0x000000bc,
 220         0x00000000,
 221         0x3f800000,
 222         0xc0016900,
 223         0x0000009e,
 224         0x80000000,
 225         0xc0016900,
 226         0x0000009f,
 227         0x20002000,
 228         0xc0026900,
 229         0x000000be,
 230         0x00000000,
 231         0x3f800000,
 232         0xc0016900,
 233         0x000000a0,
 234         0x80000000,
 235         0xc0016900,
 236         0x000000a1,
 237         0x20002000,
 238         0xc0026900,
 239         0x000000c0,
 240         0x00000000,
 241         0x3f800000,
 242         0xc0016900,
 243         0x000000a2,
 244         0x80000000,
 245         0xc0016900,
 246         0x000000a3,
 247         0x20002000,
 248         0xc0026900,
 249         0x000000c2,
 250         0x00000000,
 251         0x3f800000,
 252         0xc0016900,
 253         0x000000a4,
 254         0x80000000,
 255         0xc0016900,
 256         0x000000a5,
 257         0x20002000,
 258         0xc0026900,
 259         0x000000c4,
 260         0x00000000,
 261         0x3f800000,
 262         0xc0016900,
 263         0x000000a6,
 264         0x80000000,
 265         0xc0016900,
 266         0x000000a7,
 267         0x20002000,
 268         0xc0026900,
 269         0x000000c6,
 270         0x00000000,
 271         0x3f800000,
 272         0xc0016900,
 273         0x000000a8,
 274         0x80000000,
 275         0xc0016900,
 276         0x000000a9,
 277         0x20002000,
 278         0xc0026900,
 279         0x000000c8,
 280         0x00000000,
 281         0x3f800000,
 282         0xc0016900,
 283         0x000000aa,
 284         0x80000000,
 285         0xc0016900,
 286         0x000000ab,
 287         0x20002000,
 288         0xc0026900,
 289         0x000000ca,
 290         0x00000000,
 291         0x3f800000,
 292         0xc0016900,
 293         0x000000ac,
 294         0x80000000,
 295         0xc0016900,
 296         0x000000ad,
 297         0x20002000,
 298         0xc0026900,
 299         0x000000cc,
 300         0x00000000,
 301         0x3f800000,
 302         0xc0016900,
 303         0x000000ae,
 304         0x80000000,
 305         0xc0016900,
 306         0x000000af,
 307         0x20002000,
 308         0xc0026900,
 309         0x000000ce,
 310         0x00000000,
 311         0x3f800000,
 312         0xc0016900,
 313         0x000000b0,
 314         0x80000000,
 315         0xc0016900,
 316         0x000000b1,
 317         0x20002000,
 318         0xc0026900,
 319         0x000000d0,
 320         0x00000000,
 321         0x3f800000,
 322         0xc0016900,
 323         0x000000b2,
 324         0x80000000,
 325         0xc0016900,
 326         0x000000b3,
 327         0x20002000,
 328         0xc0026900,
 329         0x000000d2,
 330         0x00000000,
 331         0x3f800000,
 332         0xc0016900,
 333         0x00000293,
 334         0x00004010,
 335         0xc0016900,
 336         0x00000300,
 337         0x00000000,
 338         0xc0016900,
 339         0x00000301,
 340         0x00000000,
 341         0xc0016900,
 342         0x00000312,
 343         0xffffffff,
 344         0xc0016900,
 345         0x00000307,
 346         0x00000000,
 347         0xc0016900,
 348         0x00000308,
 349         0x00000000,
 350         0xc0016900,
 351         0x00000283,
 352         0x00000000,
 353         0xc0016900,
 354         0x00000292,
 355         0x00000000,
 356         0xc0066900,
 357         0x0000010f,
 358         0x00000000,
 359         0x00000000,
 360         0x00000000,
 361         0x00000000,
 362         0x00000000,
 363         0x00000000,
 364         0xc0016900,
 365         0x00000206,
 366         0x00000000,
 367         0xc0016900,
 368         0x00000207,
 369         0x00000000,
 370         0xc0016900,
 371         0x00000208,
 372         0x00000000,
 373         0xc0046900,
 374         0x00000303,
 375         0x3f800000,
 376         0x3f800000,
 377         0x3f800000,
 378         0x3f800000,
 379         0xc0016900,
 380         0x00000205,
 381         0x00000004,
 382         0xc0016900,
 383         0x00000280,
 384         0x00000000,
 385         0xc0016900,
 386         0x00000281,
 387         0x00000000,
 388         0xc0016900,
 389         0x0000037e,
 390         0x00000000,
 391         0xc0016900,
 392         0x00000382,
 393         0x00000000,
 394         0xc0016900,
 395         0x00000380,
 396         0x00000000,
 397         0xc0016900,
 398         0x00000383,
 399         0x00000000,
 400         0xc0016900,
 401         0x00000381,
 402         0x00000000,
 403         0xc0016900,
 404         0x00000282,
 405         0x00000008,
 406         0xc0016900,
 407         0x00000302,
 408         0x0000002d,
 409         0xc0016900,
 410         0x0000037f,
 411         0x00000000,
 412         0xc0016900,
 413         0x000001b2,
 414         0x00000000,
 415         0xc0016900,
 416         0x000001b6,
 417         0x00000000,
 418         0xc0016900,
 419         0x000001b7,
 420         0x00000000,
 421         0xc0016900,
 422         0x000001b8,
 423         0x00000000,
 424         0xc0016900,
 425         0x000001b9,
 426         0x00000000,
 427         0xc0016900,
 428         0x00000225,
 429         0x00000000,
 430         0xc0016900,
 431         0x00000229,
 432         0x00000000,
 433         0xc0016900,
 434         0x00000237,
 435         0x00000000,
 436         0xc0016900,
 437         0x00000100,
 438         0x00000800,
 439         0xc0016900,
 440         0x00000101,
 441         0x00000000,
 442         0xc0016900,
 443         0x00000102,
 444         0x00000000,
 445         0xc0016900,
 446         0x000002a8,
 447         0x00000000,
 448         0xc0016900,
 449         0x000002a9,
 450         0x00000000,
 451         0xc0016900,
 452         0x00000103,
 453         0x00000000,
 454         0xc0016900,
 455         0x00000284,
 456         0x00000000,
 457         0xc0016900,
 458         0x00000290,
 459         0x00000000,
 460         0xc0016900,
 461         0x00000285,
 462         0x00000000,
 463         0xc0016900,
 464         0x00000286,
 465         0x00000000,
 466         0xc0016900,
 467         0x00000287,
 468         0x00000000,
 469         0xc0016900,
 470         0x00000288,
 471         0x00000000,
 472         0xc0016900,
 473         0x00000289,
 474         0x00000000,
 475         0xc0016900,
 476         0x0000028a,
 477         0x00000000,
 478         0xc0016900,
 479         0x0000028b,
 480         0x00000000,
 481         0xc0016900,
 482         0x0000028c,
 483         0x00000000,
 484         0xc0016900,
 485         0x0000028d,
 486         0x00000000,
 487         0xc0016900,
 488         0x0000028e,
 489         0x00000000,
 490         0xc0016900,
 491         0x0000028f,
 492         0x00000000,
 493         0xc0016900,
 494         0x000002a1,
 495         0x00000000,
 496         0xc0016900,
 497         0x000002a5,
 498         0x00000000,
 499         0xc0016900,
 500         0x000002ac,
 501         0x00000000,
 502         0xc0016900,
 503         0x000002ad,
 504         0x00000000,
 505         0xc0016900,
 506         0x000002ae,
 507         0x00000000,
 508         0xc0016900,
 509         0x000002c8,
 510         0x00000000,
 511         0xc0016900,
 512         0x00000206,
 513         0x00000100,
 514         0xc0016900,
 515         0x00000204,
 516         0x00010000,
 517         0xc0036e00,
 518         0x00000000,
 519         0x00000012,
 520         0x00000000,
 521         0x00000000,
 522         0xc0016900,
 523         0x0000008f,
 524         0x0000000f,
 525         0xc0016900,
 526         0x000001e8,
 527         0x00000001,
 528         0xc0016900,
 529         0x00000202,
 530         0x00cc0000,
 531         0xc0016900,
 532         0x00000205,
 533         0x00000244,
 534         0xc0016900,
 535         0x00000203,
 536         0x00000210,
 537         0xc0016900,
 538         0x000001b1,
 539         0x00000000,
 540         0xc0016900,
 541         0x00000185,
 542         0x00000000,
 543         0xc0016900,
 544         0x000001b3,
 545         0x00000001,
 546         0xc0016900,
 547         0x000001b4,
 548         0x00000000,
 549         0xc0016900,
 550         0x00000191,
 551         0x00000b00,
 552         0xc0016900,
 553         0x000001b5,
 554         0x00000000,
 555 };
 556
 557 static u32 r7xx_default_state[] =
 558 {
 559         0xc0012800,
 560         0x80000000,
 561         0x80000000,
 562         0xc0004600,
 563         0x00000016,
 564         0xc0016800,
 565         0x00000010,
 566         0x00028000,
 567         0xc0016800,
 568         0x00000010,
 569         0x00008000,
 570         0xc0016800,
 571         0x00000542,
 572         0x07000002,
 573         0xc0016800,
 574         0x000005c5,
 575         0x00000000,
 576         0xc0016800,
 577         0x00000363,
 578         0x00004000,
 579         0xc0016800,
 580         0x0000060c,
 581         0x00000000,
 582         0xc0016800,
 583         0x0000060e,
 584         0x00420204,
 585         0xc0016f00,
 586         0x00000000,
 587         0x00000000,
 588         0xc0016f00,
 589         0x00000001,
 590         0x00000000,
 591         0xc0096900,
 592         0x0000022a,
 593         0x00000000,
 594         0x00000000,
 595         0x00000000,
 596         0x00000000,
 597         0x00000000,
 598         0x00000000,
 599         0x00000000,
 600         0x00000000,
 601         0x00000000,
 602         0xc0016900,
 603         0x00000004,
 604         0x00000000,
 605         0xc0016900,
 606         0x0000000a,
 607         0x00000000,
 608         0xc0016900,
 609         0x0000000b,
 610         0x00000000,
 611         0xc0016900,
 612         0x0000010c,
 613         0x00000000,
 614         0xc0016900,
 615         0x0000010d,
 616         0x00000000,
 617         0xc0016900,
 618         0x00000200,
 619         0x00000000,
 620         0xc0016900,
 621         0x00000343,
 622         0x00000060,
 623         0xc0016900,
 624         0x00000344,
 625         0x00000000,
 626         0xc0016900,
 627         0x00000351,
 628         0x0000aa00,
 629         0xc0016900,
 630         0x00000104,
 631         0x00000000,
 632         0xc0016900,
 633         0x0000010e,
 634         0x00000000,
 635         0xc0046900,
 636         0x00000105,
 637         0x00000000,
 638         0x00000000,
 639         0x00000000,
 640         0x00000000,
 641         0xc0046900,
 642         0x0000030c,
 643         0x01000000,
 644         0x00000000,
 645         0x00000000,
 646         0x00000000,
 647         0xc0016900,
 648         0x0000008e,
 649         0x0000000f,
 650         0xc0016900,
 651         0x00000080,
 652         0x00000000,
 653         0xc0016900,
 654         0x00000083,
 655         0x0000ffff,
 656         0xc0016900,
 657         0x00000084,
 658         0x00000000,
 659         0xc0016900,
 660         0x00000085,
 661         0x20002000,
 662         0xc0016900,
 663         0x00000086,
 664         0x00000000,
 665         0xc0016900,
 666         0x00000087,
 667         0x20002000,
 668         0xc0016900,
 669         0x00000088,
 670         0x00000000,
 671         0xc0016900,
 672         0x00000089,
 673         0x20002000,
 674         0xc0016900,
 675         0x0000008a,
 676         0x00000000,
 677         0xc0016900,
 678         0x0000008b,
 679         0x20002000,
 680         0xc0016900,
 681         0x0000008c,
 682         0xaaaaaaaa,
 683         0xc0016900,
 684         0x00000094,
 685         0x80000000,
 686         0xc0016900,
 687         0x00000095,
 688         0x20002000,
 689         0xc0026900,
 690         0x000000b4,
 691         0x00000000,
 692         0x3f800000,
 693         0xc0016900,
 694         0x00000096,
 695         0x80000000,
 696         0xc0016900,
 697         0x00000097,
 698         0x20002000,
 699         0xc0026900,
 700         0x000000b6,
 701         0x00000000,
 702         0x3f800000,
 703         0xc0016900,
 704         0x00000098,
 705         0x80000000,
 706         0xc0016900,
 707         0x00000099,
 708         0x20002000,
 709         0xc0026900,
 710         0x000000b8,
 711         0x00000000,
 712         0x3f800000,
 713         0xc0016900,
 714         0x0000009a,
 715         0x80000000,
 716         0xc0016900,
 717         0x0000009b,
 718         0x20002000,
 719         0xc0026900,
 720         0x000000ba,
 721         0x00000000,
 722         0x3f800000,
 723         0xc0016900,
 724         0x0000009c,
 725         0x80000000,
 726         0xc0016900,
 727         0x0000009d,
 728         0x20002000,
 729         0xc0026900,
 730         0x000000bc,
 731         0x00000000,
 732         0x3f800000,
 733         0xc0016900,
 734         0x0000009e,
 735         0x80000000,
 736         0xc0016900,
 737         0x0000009f,
 738         0x20002000,
 739         0xc0026900,
 740         0x000000be,
 741         0x00000000,
 742         0x3f800000,
 743         0xc0016900,
 744         0x000000a0,
 745         0x80000000,
 746         0xc0016900,
 747         0x000000a1,
 748         0x20002000,
 749         0xc0026900,
 750         0x000000c0,
 751         0x00000000,
 752         0x3f800000,
 753         0xc0016900,
 754         0x000000a2,
 755         0x80000000,
 756         0xc0016900,
 757         0x000000a3,
 758         0x20002000,
 759         0xc0026900,
 760         0x000000c2,
 761         0x00000000,
 762         0x3f800000,
 763         0xc0016900,
 764         0x000000a4,
 765         0x80000000,
 766         0xc0016900,
 767         0x000000a5,
 768         0x20002000,
 769         0xc0026900,
 770         0x000000c4,
 771         0x00000000,
 772         0x3f800000,
 773         0xc0016900,
 774         0x000000a6,
 775         0x80000000,
 776         0xc0016900,
 777         0x000000a7,
 778         0x20002000,
 779         0xc0026900,
 780         0x000000c6,
 781         0x00000000,
 782         0x3f800000,
 783         0xc0016900,
 784         0x000000a8,
 785         0x80000000,
 786         0xc0016900,
 787         0x000000a9,
 788         0x20002000,
 789         0xc0026900,
 790         0x000000c8,
 791         0x00000000,
 792         0x3f800000,
 793         0xc0016900,
 794         0x000000aa,
 795         0x80000000,
 796         0xc0016900,
 797         0x000000ab,
 798         0x20002000,
 799         0xc0026900,
 800         0x000000ca,
 801         0x00000000,
 802         0x3f800000,
 803         0xc0016900,
 804         0x000000ac,
 805         0x80000000,
 806         0xc0016900,
 807         0x000000ad,
 808         0x20002000,
 809         0xc0026900,
 810         0x000000cc,
 811         0x00000000,
 812         0x3f800000,
 813         0xc0016900,
 814         0x000000ae,
 815         0x80000000,
 816         0xc0016900,
 817         0x000000af,
 818         0x20002000,
 819         0xc0026900,
 820         0x000000ce,
 821         0x00000000,
 822         0x3f800000,
 823         0xc0016900,
 824         0x000000b0,
 825         0x80000000,
 826         0xc0016900,
 827         0x000000b1,
 828         0x20002000,
 829         0xc0026900,
 830         0x000000d0,
 831         0x00000000,
 832         0x3f800000,
 833         0xc0016900,
 834         0x000000b2,
 835         0x80000000,
 836         0xc0016900,
 837         0x000000b3,
 838         0x20002000,
 839         0xc0026900,
 840         0x000000d2,
 841         0x00000000,
 842         0x3f800000,
 843         0xc0016900,
 844         0x00000293,
 845         0x00514000,
 846         0xc0016900,
 847         0x00000300,
 848         0x00000000,
 849         0xc0016900,
 850         0x00000301,
 851         0x00000000,
 852         0xc0016900,
 853         0x00000312,
 854         0xffffffff,
 855         0xc0016900,
 856         0x00000307,
 857         0x00000000,
 858         0xc0016900,
 859         0x00000308,
 860         0x00000000,
 861         0xc0016900,
 862         0x00000283,
 863         0x00000000,
 864         0xc0016900,
 865         0x00000292,
 866         0x00000000,
 867         0xc0066900,
 868         0x0000010f,
 869         0x00000000,
 870         0x00000000,
 871         0x00000000,
 872         0x00000000,
 873         0x00000000,
 874         0x00000000,
 875         0xc0016900,
 876         0x00000206,
 877         0x00000000,
 878         0xc0016900,
 879         0x00000207,
 880         0x00000000,
 881         0xc0016900,
 882         0x00000208,
 883         0x00000000,
 884         0xc0046900,
 885         0x00000303,
 886         0x3f800000,
 887         0x3f800000,
 888         0x3f800000,
 889         0x3f800000,
 890         0xc0016900,
 891         0x00000205,
 892         0x00000004,
 893         0xc0016900,
 894         0x00000280,
 895         0x00000000,
 896         0xc0016900,
 897         0x00000281,
 898         0x00000000,
 899         0xc0016900,
 900         0x0000037e,
 901         0x00000000,
 902         0xc0016900,
 903         0x00000382,
 904         0x00000000,
 905         0xc0016900,
 906         0x00000380,
 907         0x00000000,
 908         0xc0016900,
 909         0x00000383,
 910         0x00000000,
 911         0xc0016900,
 912         0x00000381,
 913         0x00000000,
 914         0xc0016900,
 915         0x00000282,
 916         0x00000008,
 917         0xc0016900,
 918         0x00000302,
 919         0x0000002d,
 920         0xc0016900,
 921         0x0000037f,
 922         0x00000000,
 923         0xc0016900,
 924         0x000001b2,
 925         0x00000001,
 926         0xc0016900,
 927         0x000001b6,
 928         0x00000000,
 929         0xc0016900,
 930         0x000001b7,
 931         0x00000000,
 932         0xc0016900,
 933         0x000001b8,
 934         0x00000000,
 935         0xc0016900,
 936         0x000001b9,
 937         0x00000000,
 938         0xc0016900,
 939         0x00000225,
 940         0x00000000,
 941         0xc0016900,
 942         0x00000229,
 943         0x00000000,
 944         0xc0016900,
 945         0x00000237,
 946         0x00000000,
 947         0xc0016900,
 948         0x00000100,
 949         0x00000800,
 950         0xc0016900,
 951         0x00000101,
 952         0x00000000,
 953         0xc0016900,
 954         0x00000102,
 955         0x00000000,
 956         0xc0016900,
 957         0x000002a8,
 958         0x00000000,
 959         0xc0016900,
 960         0x000002a9,
 961         0x00000000,
 962         0xc0016900,
 963         0x00000103,
 964         0x00000000,
 965         0xc0016900,
 966         0x00000284,
 967         0x00000000,
 968         0xc0016900,
 969         0x00000290,
 970         0x00000000,
 971         0xc0016900,
 972         0x00000285,
 973         0x00000000,
 974         0xc0016900,
 975         0x00000286,
 976         0x00000000,
 977         0xc0016900,
 978         0x00000287,
 979         0x00000000,
 980         0xc0016900,
 981         0x00000288,
 982         0x00000000,
 983         0xc0016900,
 984         0x00000289,
 985         0x00000000,
 986         0xc0016900,
 987         0x0000028a,
 988         0x00000000,
 989         0xc0016900,
 990         0x0000028b,
 991         0x00000000,
 992         0xc0016900,
 993         0x0000028c,
 994         0x00000000,
 995         0xc0016900,
 996         0x0000028d,
 997         0x00000000,
 998         0xc0016900,
 999         0x0000028e,
1000         0x00000000,
1001         0xc0016900,
1002         0x0000028f,
1003         0x00000000,
1004         0xc0016900,
1005         0x000002a1,
1006         0x00000000,
1007         0xc0016900,
1008         0x000002a5,
1009         0x00000000,
1010         0xc0016900,
1011         0x000002ac,
1012         0x00000000,
1013         0xc0016900,
1014         0x000002ad,
1015         0x00000000,
1016         0xc0016900,
1017         0x000002ae,
1018         0x00000000,
1019         0xc0016900,
1020         0x000002c8,
1021         0x00000000,
1022         0xc0016900,
1023         0x00000206,
1024         0x00000100,
1025         0xc0016900,
1026         0x00000204,
1027         0x00010000,
1028         0xc0036e00,
1029         0x00000000,
1030         0x00000012,
1031         0x00000000,
1032         0x00000000,
1033         0xc0016900,
1034         0x0000008f,
1035         0x0000000f,
1036         0xc0016900,
1037         0x000001e8,
1038         0x00000001,
1039         0xc0016900,
1040         0x00000202,
1041         0x00cc0000,
1042         0xc0016900,
1043         0x00000205,
1044         0x00000244,
1045         0xc0016900,
1046         0x00000203,
1047         0x00000210,
1048         0xc0016900,
1049         0x000001b1,
1050         0x00000000,
1051         0xc0016900,
1052         0x00000185,
1053         0x00000000,
1054         0xc0016900,
1055         0x000001b3,
1056         0x00000001,
1057         0xc0016900,
1058         0x000001b4,
1059         0x00000000,
1060         0xc0016900,
1061         0x00000191,
1062         0x00000b00,
1063         0xc0016900,
1064         0x000001b5,
1065         0x00000000,
1066 };
1067
1068 /* same for r6xx/r7xx */
1069 static u32 r6xx_vs[] =
1070 {
1071         0x00000004,
1072         0x81000000,
1073         0x0000203c,
1074         0x94000b08,
1075         0x00004000,
1076         0x14200b1a,
1077         0x00000000,
1078         0x00000000,
1079         0x3c000000,
1080         0x68cd1000,
1081         0x00080000,
1082         0x00000000,
1083 };
1084
1085 static u32 r6xx_ps[] =
1086 {
1087         0x00000002,
1088         0x80800000,
1089         0x00000000,
1090         0x94200688,
1091         0x00000010,
1092         0x000d1000,
1093         0xb0800000,
1094         0x00000000,
1095 };
1096
1097 #define DI_PT_RECTLIST 0x11
1098 #define DI_INDEX_SIZE_16_BIT 0x0
1099 #define DI_SRC_SEL_AUTO_INDEX 0x2
1100
1101 #define FMT_8 1
1102 #define FMT_5_6_5 8
1103 #define FMT_8_8_8_8 0x1a
1104 #define COLOR_8 1
1105 #define COLOR_5_6_5 8
1106 #define COLOR_8_8_8_8 0x1a
1107
1108 #define R600_CB0_DEST_BASE_ENA (1 << 6)
1109 #define R600_TC_ACTION_ENA (1 << 23)
1110 #define R600_VC_ACTION_ENA (1 << 24)
1111 #define R600_CB_ACTION_ENA (1 << 25)
1112 #define R600_DB_ACTION_ENA (1 << 26)
1113 #define R600_SH_ACTION_ENA (1 << 27)
1114 #define R600_SMX_ACTION_ENA (1 << 28)
1115
1116 #define R600_CB_COLOR0_SIZE 0x28060
1117 #define R600_CB_COLOR0_VIEW 0x28080
1118 #define R600_CB_COLOR0_INFO 0x280a0
1119 #define R600_CB_COLOR0_TILE 0x280c0
1120 #define R600_CB_COLOR0_FRAG 0x280e0
1121 #define R600_CB_COLOR0_MASK 0x28100
1122
1123 #define R600_SQ_PGM_START_VS                                   0x28858
1124 #define R600_SQ_PGM_RESOURCES_VS 0x28868
1125 #define R600_SQ_PGM_CF_OFFSET_VS 0x288d0
1126 #define R600_SQ_PGM_START_PS                                   0x28840
1127 #define R600_SQ_PGM_RESOURCES_PS 0x28850
1128 #define R600_SQ_PGM_EXPORTS_PS 0x28854
1129 #define R600_SQ_PGM_CF_OFFSET_PS 0x288cc
1130
1131 #define R600_VGT_PRIMITIVE_TYPE 0x8958
1132
1133 #define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030
1134 #define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240
1135 #define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204
1136
1137 #define R600_SQ_TEX_VTX_INVALID_TEXTURE                        0x0
1138 #define R600_SQ_TEX_VTX_INVALID_BUFFER                         0x1
1139 #define R600_SQ_TEX_VTX_VALID_TEXTURE                          0x2
1140 #define R600_SQ_TEX_VTX_VALID_BUFFER                           0x3
1141
1142 /* packet 3 type offsets */
1143 #define R600_SET_CONFIG_REG_OFFSET                             0x00008000
1144 #define R600_SET_CONFIG_REG_END                                0x0000ac00
1145 #define R600_SET_CONTEXT_REG_OFFSET                            0x00028000
1146 #define R600_SET_CONTEXT_REG_END                               0x00029000
1147 #define R600_SET_ALU_CONST_OFFSET                              0x00030000
1148 #define R600_SET_ALU_CONST_END                                 0x00032000
1149 #define R600_SET_RESOURCE_OFFSET                               0x00038000
1150 #define R600_SET_RESOURCE_END                                  0x0003c000
1151 #define R600_SET_SAMPLER_OFFSET                                0x0003c000
1152 #define R600_SET_SAMPLER_END                                   0x0003cff0
1153 #define R600_SET_CTL_CONST_OFFSET                              0x0003cff0
1154 #define R600_SET_CTL_CONST_END                                 0x0003e200
1155 #define R600_SET_LOOP_CONST_OFFSET                             0x0003e200
1156 #define R600_SET_LOOP_CONST_END                                0x0003e380
1157 #define R600_SET_BOOL_CONST_OFFSET                             0x0003e380
1158 #define R600_SET_BOOL_CONST_END                                0x00040000
1159
1160 /* Packet 3 types */
1161 #define R600_IT_INDIRECT_BUFFER_END               0x00001700
1162 #define R600_IT_SET_PREDICATION                   0x00002000
1163 #define R600_IT_REG_RMW                           0x00002100
1164 #define R600_IT_COND_EXEC                         0x00002200
1165 #define R600_IT_PRED_EXEC                         0x00002300
1166 #define R600_IT_START_3D_CMDBUF                   0x00002400
1167 #define R600_IT_DRAW_INDEX_2                      0x00002700
1168 #define R600_IT_CONTEXT_CONTROL                   0x00002800
1169 #define R600_IT_DRAW_INDEX_IMMD_BE                0x00002900
1170 #define R600_IT_INDEX_TYPE                        0x00002A00
1171 #define R600_IT_DRAW_INDEX                        0x00002B00
1172 #define R600_IT_DRAW_INDEX_AUTO                   0x00002D00
1173 #define R600_IT_DRAW_INDEX_IMMD                   0x00002E00
1174 #define R600_IT_NUM_INSTANCES                     0x00002F00
1175 #define R600_IT_STRMOUT_BUFFER_UPDATE             0x00003400
1176 #define R600_IT_INDIRECT_BUFFER_MP                0x00003800
1177 #define R600_IT_MEM_SEMAPHORE                     0x00003900
1178 #define R600_IT_MPEG_INDEX                        0x00003A00
1179 #define R600_IT_WAIT_REG_MEM                      0x00003C00
1180 #define R600_IT_MEM_WRITE                         0x00003D00
1181 #define R600_IT_INDIRECT_BUFFER                   0x00003200
1182 #define R600_IT_CP_INTERRUPT                      0x00004000
1183 #define R600_IT_SURFACE_SYNC                      0x00004300
1184 #define R600_IT_ME_INITIALIZE                     0x00004400
1185 #define R600_IT_COND_WRITE                        0x00004500
1186 #define R600_IT_EVENT_WRITE                       0x00004600
1187 #define R600_IT_EVENT_WRITE_EOP                   0x00004700
1188 #define R600_IT_ONE_REG_WRITE                     0x00005700
1189 #define R600_IT_SET_CONFIG_REG                    0x00006800
1190 #define R600_IT_SET_CONTEXT_REG                   0x00006900
1191 #define R600_IT_SET_ALU_CONST                     0x00006A00
1192 #define R600_IT_SET_BOOL_CONST                    0x00006B00
1193 #define R600_IT_SET_LOOP_CONST                    0x00006C00
1194 #define R600_IT_SET_RESOURCE                      0x00006D00
1195 #define R600_IT_SET_SAMPLER                       0x00006E00
1196 #define R600_IT_SET_CTL_CONST                     0x00006F00
1197 #define R600_IT_SURFACE_BASE_UPDATE               0x00007300
1198
1199 static inline void
1200 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)
1201 {
1202         u32 cb_color_info;
1203         int pitch, slice;
1204         RING_LOCALS;
1205         DRM_DEBUG("\n");
1206
1207         h = (h + 7) & ~7;
1208         if (h < 8)
1209                 h = 8;
1210
1211         cb_color_info = ((format << 2) | (1 << 27));
1212         pitch = (w / 8) - 1;
1213         slice = ((w * h) / 64) - 1;
1214
1215         if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) &&
1216             ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) {
1217                 BEGIN_RING(21 + 2);
1218                 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1219                 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1220                 OUT_RING(gpu_addr >> 8);
1221                 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
1222                 OUT_RING(2 << 0);
1223         } else {
1224                 BEGIN_RING(21);
1225                 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1226                 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1227                 OUT_RING(gpu_addr >> 8);
1228         }
1229
1230         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1231         OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1232         OUT_RING((pitch << 0) | (slice << 10));
1233
1234         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1235         OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1236         OUT_RING(0);
1237
1238         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1239         OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1240         OUT_RING(cb_color_info);
1241
1242         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1243         OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1244         OUT_RING(0);
1245
1246         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1247         OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1248         OUT_RING(0);
1249
1250         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1251         OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1252         OUT_RING(0);
1253
1254         ADVANCE_RING();
1255 }
1256
1257 static inline void
1258 cp_set_surface_sync(drm_radeon_private_t *dev_priv,
1259                     u32 sync_type, u32 size, u64 mc_addr)
1260 {
1261         u32 cp_coher_size;
1262         RING_LOCALS;
1263         DRM_DEBUG("\n");
1264
1265         if (size == 0xffffffff)
1266                 cp_coher_size = 0xffffffff;
1267         else
1268                 cp_coher_size = ((size + 255) >> 8);
1269
1270         BEGIN_RING(5);
1271         OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
1272         OUT_RING(sync_type);
1273         OUT_RING(cp_coher_size);
1274         OUT_RING((mc_addr >> 8));
1275         OUT_RING(10); /* poll interval */
1276         ADVANCE_RING();
1277 }
1278
1279 static inline void
1280 set_shaders(struct drm_device *dev)
1281 {
1282         drm_radeon_private_t *dev_priv = dev->dev_private;
1283         u64 gpu_addr;
1284         int shader_size, i;
1285         u32 *vs, *ps;
1286         uint32_t sq_pgm_resources;
1287         RING_LOCALS;
1288         DRM_DEBUG("\n");
1289
1290         /* load shaders */
1291         vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset);
1292         ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
1293
1294         shader_size = sizeof(r6xx_vs) / 4;
1295         for (i= 0; i < shader_size; i++)
1296                 vs[i] = r6xx_vs[i];
1297         shader_size = sizeof(r6xx_ps) / 4;
1298         for (i= 0; i < shader_size; i++)
1299                 ps[i] = r6xx_ps[i];
1300
1301         dev_priv->blit_vb->used = 512;
1302
1303         gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset;
1304
1305         /* setup shader regs */
1306         sq_pgm_resources = (1 << 0);
1307
1308         BEGIN_RING(9 + 12);
1309         /* VS */
1310         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1311         OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1312         OUT_RING(gpu_addr >> 8);
1313
1314         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1315         OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1316         OUT_RING(sq_pgm_resources);
1317
1318         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1319         OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1320         OUT_RING(0);
1321
1322         /* PS */
1323         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1324         OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1325         OUT_RING((gpu_addr + 256) >> 8);
1326
1327         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1328         OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1329         OUT_RING(sq_pgm_resources | (1 << 28));
1330
1331         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1332         OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1333         OUT_RING(2);
1334
1335         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1336         OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1337         OUT_RING(0);
1338         ADVANCE_RING();
1339
1340         cp_set_surface_sync(dev_priv,
1341                             R600_SH_ACTION_ENA, 512, gpu_addr);
1342 }
1343
1344 static inline void
1345 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
1346 {
1347         uint32_t sq_vtx_constant_word2;
1348         RING_LOCALS;
1349         DRM_DEBUG("\n");
1350
1351         sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
1352
1353         BEGIN_RING(9);
1354         OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
1355         OUT_RING(0x460);
1356         OUT_RING(gpu_addr & 0xffffffff);
1357         OUT_RING(48 - 1);
1358         OUT_RING(sq_vtx_constant_word2);
1359         OUT_RING(1 << 0);
1360         OUT_RING(0);
1361         OUT_RING(0);
1362         OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30);
1363         ADVANCE_RING();
1364
1365         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1366             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1367             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1368             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
1369             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
1370                 cp_set_surface_sync(dev_priv,
1371                                     R600_TC_ACTION_ENA, 48, gpu_addr);
1372         else
1373                 cp_set_surface_sync(dev_priv,
1374                                     R600_VC_ACTION_ENA, 48, gpu_addr);
1375 }
1376
1377 static inline void
1378 set_tex_resource(drm_radeon_private_t *dev_priv,
1379                  int format, int w, int h, int pitch, u64 gpu_addr)
1380 {
1381         uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
1382         RING_LOCALS;
1383         DRM_DEBUG("\n");
1384
1385         if (h < 1)
1386                 h = 1;
1387
1388         sq_tex_resource_word0 = (1 << 0);
1389         sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
1390                                   ((w - 1) << 19));
1391
1392         sq_tex_resource_word1 = (format << 26);
1393         sq_tex_resource_word1 |= ((h - 1) << 0);
1394
1395         sq_tex_resource_word4 = ((1 << 14) |
1396                                  (0 << 16) |
1397                                  (1 << 19) |
1398                                  (2 << 22) |
1399                                  (3 << 25));
1400
1401         BEGIN_RING(9);
1402         OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
1403         OUT_RING(0);
1404         OUT_RING(sq_tex_resource_word0);
1405         OUT_RING(sq_tex_resource_word1);
1406         OUT_RING(gpu_addr >> 8);
1407         OUT_RING(gpu_addr >> 8);
1408         OUT_RING(sq_tex_resource_word4);
1409         OUT_RING(0);
1410         OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30);
1411         ADVANCE_RING();
1412
1413 }
1414
1415 static inline void
1416 set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
1417 {
1418         RING_LOCALS;
1419         DRM_DEBUG("\n");
1420
1421         BEGIN_RING(12);
1422         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
1423         OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1424         OUT_RING((x1 << 0) | (y1 << 16));
1425         OUT_RING((x2 << 0) | (y2 << 16));
1426
1427         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
1428         OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1429         OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
1430         OUT_RING((x2 << 0) | (y2 << 16));
1431
1432         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
1433         OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1434         OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
1435         OUT_RING((x2 << 0) | (y2 << 16));
1436         ADVANCE_RING();
1437 }
1438
1439 static inline void
1440 draw_auto(drm_radeon_private_t *dev_priv)
1441 {
1442         RING_LOCALS;
1443         DRM_DEBUG("\n");
1444
1445         BEGIN_RING(10);
1446         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
1447         OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2);
1448         OUT_RING(DI_PT_RECTLIST);
1449
1450         OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
1451         OUT_RING(DI_INDEX_SIZE_16_BIT);
1452
1453         OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
1454         OUT_RING(1);
1455
1456         OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
1457         OUT_RING(3);
1458         OUT_RING(DI_SRC_SEL_AUTO_INDEX);
1459
1460         ADVANCE_RING();
1461         COMMIT_RING();
1462 }
1463
1464 static inline void
1465 set_default_state(drm_radeon_private_t *dev_priv)
1466 {
1467         int default_state_dw, i;
1468         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
1469         u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
1470         int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
1471         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
1472         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
1473         RING_LOCALS;
1474
1475         switch ((dev_priv->flags & RADEON_FAMILY_MASK)) {
1476         case CHIP_R600:
1477                 num_ps_gprs = 192;
1478                 num_vs_gprs = 56;
1479                 num_temp_gprs = 4;
1480                 num_gs_gprs = 0;
1481                 num_es_gprs = 0;
1482                 num_ps_threads = 136;
1483                 num_vs_threads = 48;
1484                 num_gs_threads = 4;
1485                 num_es_threads = 4;
1486                 num_ps_stack_entries = 128;
1487                 num_vs_stack_entries = 128;
1488                 num_gs_stack_entries = 0;
1489                 num_es_stack_entries = 0;
1490                 break;
1491         case CHIP_RV630:
1492         case CHIP_RV635:
1493                 num_ps_gprs = 84;
1494                 num_vs_gprs = 36;
1495                 num_temp_gprs = 4;
1496                 num_gs_gprs = 0;
1497                 num_es_gprs = 0;
1498                 num_ps_threads = 144;
1499                 num_vs_threads = 40;
1500                 num_gs_threads = 4;
1501                 num_es_threads = 4;
1502                 num_ps_stack_entries = 40;
1503                 num_vs_stack_entries = 40;
1504                 num_gs_stack_entries = 32;
1505                 num_es_stack_entries = 16;
1506                 break;
1507         case CHIP_RV610:
1508         case CHIP_RV620:
1509         case CHIP_RS780:
1510         case CHIP_RS880:
1511         default:
1512                 num_ps_gprs = 84;
1513                 num_vs_gprs = 36;
1514                 num_temp_gprs = 4;
1515                 num_gs_gprs = 0;
1516                 num_es_gprs = 0;
1517                 num_ps_threads = 136;
1518                 num_vs_threads = 48;
1519                 num_gs_threads = 4;
1520                 num_es_threads = 4;
1521                 num_ps_stack_entries = 40;
1522                 num_vs_stack_entries = 40;
1523                 num_gs_stack_entries = 32;
1524                 num_es_stack_entries = 16;
1525                 break;
1526         case CHIP_RV670:
1527                 num_ps_gprs = 144;
1528                 num_vs_gprs = 40;
1529                 num_temp_gprs = 4;
1530                 num_gs_gprs = 0;
1531                 num_es_gprs = 0;
1532                 num_ps_threads = 136;
1533                 num_vs_threads = 48;
1534                 num_gs_threads = 4;
1535                 num_es_threads = 4;
1536                 num_ps_stack_entries = 40;
1537                 num_vs_stack_entries = 40;
1538                 num_gs_stack_entries = 32;
1539                 num_es_stack_entries = 16;
1540                 break;
1541         case CHIP_RV770:
1542                 num_ps_gprs = 192;
1543                 num_vs_gprs = 56;
1544                 num_temp_gprs = 4;
1545                 num_gs_gprs = 0;
1546                 num_es_gprs = 0;
1547                 num_ps_threads = 188;
1548                 num_vs_threads = 60;
1549                 num_gs_threads = 0;
1550                 num_es_threads = 0;
1551                 num_ps_stack_entries = 256;
1552                 num_vs_stack_entries = 256;
1553                 num_gs_stack_entries = 0;
1554                 num_es_stack_entries = 0;
1555                 break;
1556         case CHIP_RV730:
1557         case CHIP_RV740:
1558                 num_ps_gprs = 84;
1559                 num_vs_gprs = 36;
1560                 num_temp_gprs = 4;
1561                 num_gs_gprs = 0;
1562                 num_es_gprs = 0;
1563                 num_ps_threads = 188;
1564                 num_vs_threads = 60;
1565                 num_gs_threads = 0;
1566                 num_es_threads = 0;
1567                 num_ps_stack_entries = 128;
1568                 num_vs_stack_entries = 128;
1569                 num_gs_stack_entries = 0;
1570                 num_es_stack_entries = 0;
1571                 break;
1572         case CHIP_RV710:
1573                 num_ps_gprs = 192;
1574                 num_vs_gprs = 56;
1575                 num_temp_gprs = 4;
1576                 num_gs_gprs = 0;
1577                 num_es_gprs = 0;
1578                 num_ps_threads = 144;
1579                 num_vs_threads = 48;
1580                 num_gs_threads = 0;
1581                 num_es_threads = 0;
1582                 num_ps_stack_entries = 128;
1583                 num_vs_stack_entries = 128;
1584                 num_gs_stack_entries = 0;
1585                 num_es_stack_entries = 0;
1586                 break;
1587         }
1588
1589         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1590             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1591             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1592             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
1593             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
1594                 sq_config = 0;
1595         else
1596                 sq_config = R600_VC_ENABLE;
1597
1598         sq_config |= (R600_DX9_CONSTS |
1599                       R600_ALU_INST_PREFER_VECTOR |
1600                       R600_PS_PRIO(0) |
1601                       R600_VS_PRIO(1) |
1602                       R600_GS_PRIO(2) |
1603                       R600_ES_PRIO(3));
1604
1605         sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) |
1606                                   R600_NUM_VS_GPRS(num_vs_gprs) |
1607                                   R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
1608         sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) |
1609                                   R600_NUM_ES_GPRS(num_es_gprs));
1610         sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) |
1611                                    R600_NUM_VS_THREADS(num_vs_threads) |
1612                                    R600_NUM_GS_THREADS(num_gs_threads) |
1613                                    R600_NUM_ES_THREADS(num_es_threads));
1614         sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
1615                                     R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
1616         sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
1617                                     R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries));
1618
1619         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
1620                 default_state_dw = sizeof(r7xx_default_state) / 4;
1621                 BEGIN_RING(default_state_dw + 10);
1622                 for (i = 0; i < default_state_dw; i++)
1623                         OUT_RING(r7xx_default_state[i]);
1624         } else {
1625                 default_state_dw = sizeof(r6xx_default_state) / 4;
1626                 BEGIN_RING(default_state_dw + 10);
1627                 for (i = 0; i < default_state_dw; i++)
1628                         OUT_RING(r6xx_default_state[i]);
1629         }
1630         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
1631         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
1632         /* SQ config */
1633         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6));
1634         OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2);
1635         OUT_RING(sq_config);
1636         OUT_RING(sq_gpr_resource_mgmt_1);
1637         OUT_RING(sq_gpr_resource_mgmt_2);
1638         OUT_RING(sq_thread_resource_mgmt);
1639         OUT_RING(sq_stack_resource_mgmt_1);
1640         OUT_RING(sq_stack_resource_mgmt_2);
1641         ADVANCE_RING();
1642 }
1643
1644 static inline uint32_t i2f(uint32_t input)
1645 {
1646         u32 result, i, exponent, fraction;
1647
1648         if ((input & 0x3fff) == 0)
1649                 result = 0; /* 0 is a special case */
1650         else {
1651                 exponent = 140; /* exponent biased by 127; */
1652                 fraction = (input & 0x3fff) << 10; /* cheat and only
1653                                                       handle numbers below 2^^15 */
1654                 for (i = 0; i < 14; i++) {
1655                         if (fraction & 0x800000)
1656                                 break;
1657                         else {
1658                                 fraction = fraction << 1; /* keep
1659                                                              shifting left until top bit = 1 */
1660                                 exponent = exponent -1;
1661                         }
1662                 }
1663                 result = exponent << 23 | (fraction & 0x7fffff); /* mask
1664                                                                     off top bit; assumed 1 */
1665         }
1666         return result;
1667 }
1668
1669 int
1670 r600_prepare_blit_copy(struct drm_device *dev)
1671 {
1672         drm_radeon_private_t *dev_priv = dev->dev_private;
1673         DRM_DEBUG("\n");
1674
1675         dev_priv->blit_vb = radeon_freelist_get(dev);
1676         if (!dev_priv->blit_vb) {
1677                 DRM_ERROR("Unable to allocate vertex buffer for blit\n");
1678                 return -EAGAIN;
1679         }
1680
1681         set_default_state(dev_priv);
1682         set_shaders(dev);
1683
1684         return 0;
1685 }
1686
1687 void
1688 r600_done_blit_copy(struct drm_device *dev)
1689 {
1690         drm_radeon_private_t *dev_priv = dev->dev_private;
1691         RING_LOCALS;
1692         DRM_DEBUG("\n");
1693
1694         BEGIN_RING(5);
1695         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
1696         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
1697         /* wait for 3D idle clean */
1698         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
1699         OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
1700         OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
1701
1702         ADVANCE_RING();
1703         COMMIT_RING();
1704
1705         dev_priv->blit_vb->used = 0;
1706         radeon_cp_discard_buffer(dev, dev_priv->blit_vb);
1707 }
1708
1709 void
1710 r600_blit_copy(struct drm_device *dev,
1711                uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
1712                int size_bytes)
1713 {
1714         drm_radeon_private_t *dev_priv = dev->dev_private;
1715         int max_bytes;
1716         u64 vb_addr;
1717         u32 *vb;
1718
1719         vb = (u32 *) ((char *)dev->agp_buffer_map->handle +
1720             dev_priv->blit_vb->offset + dev_priv->blit_vb->used);
1721         DRM_DEBUG("src=0x%016llx, dst=0x%016llx, size=%d\n",
1722             (unsigned long long)src_gpu_addr,
1723             (unsigned long long)dst_gpu_addr, size_bytes);
1724
1725         if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
1726                 max_bytes = 8192;
1727
1728                 while (size_bytes) {
1729                         int cur_size = size_bytes;
1730                         int src_x = src_gpu_addr & 255;
1731                         int dst_x = dst_gpu_addr & 255;
1732                         int h = 1;
1733                         src_gpu_addr = src_gpu_addr & ~255;
1734                         dst_gpu_addr = dst_gpu_addr & ~255;
1735
1736                         if (!src_x && !dst_x) {
1737                                 h = (cur_size / max_bytes);
1738                                 if (h > 8192)
1739                                         h = 8192;
1740                                 if (h == 0)
1741                                         h = 1;
1742                                 else
1743                                         cur_size = max_bytes;
1744                         } else {
1745                                 if (cur_size > max_bytes)
1746                                         cur_size = max_bytes;
1747                                 if (cur_size > (max_bytes - dst_x))
1748                                         cur_size = (max_bytes - dst_x);
1749                                 if (cur_size > (max_bytes - src_x))
1750                                         cur_size = (max_bytes - src_x);
1751                         }
1752
1753                         if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
1754                                 dev_priv->blit_vb->used = 0;
1755                                 radeon_cp_discard_buffer(dev, dev_priv->blit_vb);
1756                                 dev_priv->blit_vb = radeon_freelist_get(dev);
1757                                 if (!dev_priv->blit_vb)
1758                                         return;
1759                                 set_shaders(dev);
1760                                 vb = (u32 *) ((char *)dev->agp_buffer_map->handle +
1761                                     dev_priv->blit_vb->offset + dev_priv->blit_vb->used);
1762                         }
1763
1764                         vb[0] = i2f(dst_x);
1765                         vb[1] = 0;
1766                         vb[2] = i2f(src_x);
1767                         vb[3] = 0;
1768
1769                         vb[4] = i2f(dst_x);
1770                         vb[5] = i2f(h);
1771                         vb[6] = i2f(src_x);
1772                         vb[7] = i2f(h);
1773
1774                         vb[8] = i2f(dst_x + cur_size);
1775                         vb[9] = i2f(h);
1776                         vb[10] = i2f(src_x + cur_size);
1777                         vb[11] = i2f(h);
1778
1779                         /* src */
1780                         set_tex_resource(dev_priv, FMT_8,
1781                                          src_x + cur_size, h, src_x + cur_size,
1782                                          src_gpu_addr);
1783
1784                         cp_set_surface_sync(dev_priv,
1785                                             R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
1786
1787                         /* dst */
1788                         set_render_target(dev_priv, COLOR_8,
1789                                           dst_x + cur_size, h,
1790                                           dst_gpu_addr);
1791
1792                         /* scissors */
1793                         set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h);
1794
1795                         /* Vertex buffer setup */
1796                         vb_addr = dev_priv->gart_buffers_offset +
1797                                 dev_priv->blit_vb->offset +
1798                                 dev_priv->blit_vb->used;
1799                         set_vtx_resource(dev_priv, vb_addr);
1800
1801                         /* draw */
1802                         draw_auto(dev_priv);
1803
1804                         cp_set_surface_sync(dev_priv,
1805                                             R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
1806                                             cur_size * h, dst_gpu_addr);
1807
1808                         vb += 12;
1809                         dev_priv->blit_vb->used += 12 * 4;
1810
1811                         src_gpu_addr += cur_size * h;
1812                         dst_gpu_addr += cur_size * h;
1813                         size_bytes -= cur_size * h;
1814                 }
1815         } else {
1816                 max_bytes = 8192 * 4;
1817
1818                 while (size_bytes) {
1819                         int cur_size = size_bytes;
1820                         int src_x = (src_gpu_addr & 255);
1821                         int dst_x = (dst_gpu_addr & 255);
1822                         int h = 1;
1823                         src_gpu_addr = src_gpu_addr & ~255;
1824                         dst_gpu_addr = dst_gpu_addr & ~255;
1825
1826                         if (!src_x && !dst_x) {
1827                                 h = (cur_size / max_bytes);
1828                                 if (h > 8192)
1829                                         h = 8192;
1830                                 if (h == 0)
1831                                         h = 1;
1832                                 else
1833                                         cur_size = max_bytes;
1834                         } else {
1835                                 if (cur_size > max_bytes)
1836                                     cur_size = max_bytes;
1837                                 if (cur_size > (max_bytes - dst_x))
1838                                         cur_size = (max_bytes - dst_x);
1839                                 if (cur_size > (max_bytes - src_x))
1840                                         cur_size = (max_bytes - src_x);
1841                         }
1842
1843                         if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
1844                                 dev_priv->blit_vb->used = 0;
1845                                 radeon_cp_discard_buffer(dev, dev_priv->blit_vb);
1846                                 dev_priv->blit_vb = radeon_freelist_get(dev);
1847                                 if (!dev_priv->blit_vb)
1848                                         return;
1849                                 set_shaders(dev);
1850                                 vb = (u32 *) ((char *)dev->agp_buffer_map->handle +
1851                                     dev_priv->blit_vb->offset + dev_priv->blit_vb->used);
1852                         }
1853
1854                         vb[0] = i2f(dst_x / 4);
1855                         vb[1] = 0;
1856                         vb[2] = i2f(src_x / 4);
1857                         vb[3] = 0;
1858
1859                         vb[4] = i2f(dst_x / 4);
1860                         vb[5] = i2f(h);
1861                         vb[6] = i2f(src_x / 4);
1862                         vb[7] = i2f(h);
1863
1864                         vb[8] = i2f((dst_x + cur_size) / 4);
1865                         vb[9] = i2f(h);
1866                         vb[10] = i2f((src_x + cur_size) / 4);
1867                         vb[11] = i2f(h);
1868
1869                         /* src */
1870                         set_tex_resource(dev_priv, FMT_8_8_8_8,
1871                                          (src_x + cur_size) / 4,
1872                                          h, (src_x + cur_size) / 4,
1873                                          src_gpu_addr);
1874
1875                         cp_set_surface_sync(dev_priv,
1876                                             R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
1877
1878                         /* dst */
1879                         set_render_target(dev_priv, COLOR_8_8_8_8,
1880                                           (dst_x + cur_size) / 4, h,
1881                                           dst_gpu_addr);
1882
1883                         /* scissors */
1884                         set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
1885
1886                         /* Vertex buffer setup */
1887                         vb_addr = dev_priv->gart_buffers_offset +
1888                                 dev_priv->blit_vb->offset +
1889                                 dev_priv->blit_vb->used;
1890                         set_vtx_resource(dev_priv, vb_addr);
1891
1892                         /* draw */
1893                         draw_auto(dev_priv);
1894
1895                         cp_set_surface_sync(dev_priv,
1896                                             R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
1897                                             cur_size * h, dst_gpu_addr);
1898
1899                         vb += 12;
1900                         dev_priv->blit_vb->used += 12 * 4;
1901
1902                         src_gpu_addr += cur_size * h;
1903                         dst_gpu_addr += cur_size * h;
1904                         size_bytes -= cur_size * h;
1905                 }
1906         }
1907 }
1908
1909 void
1910 r600_blit_swap(struct drm_device *dev,
1911                uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
1912                int sx, int sy, int dx, int dy,
1913                int w, int h, int src_pitch, int dst_pitch, int cpp)
1914 {
1915         drm_radeon_private_t *dev_priv = dev->dev_private;
1916         int cb_format, tex_format;
1917         int sx2, sy2, dx2, dy2;
1918         u64 vb_addr;
1919         u32 *vb;
1920
1921         if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
1922                 dev_priv->blit_vb->used = 0;
1923                 radeon_cp_discard_buffer(dev, dev_priv->blit_vb);
1924                 dev_priv->blit_vb = radeon_freelist_get(dev);
1925                 if (!dev_priv->blit_vb)
1926                         return;
1927                 set_shaders(dev);
1928         }
1929         vb = (u32 *) ((char *)dev->agp_buffer_map->handle +
1930             dev_priv->blit_vb->offset + dev_priv->blit_vb->used);
1931
1932         sx2 = sx + w;
1933         sy2 = sy + h;
1934         dx2 = dx + w;
1935         dy2 = dy + h;
1936
1937         vb[0] = i2f(dx);
1938         vb[1] = i2f(dy);
1939         vb[2] = i2f(sx);
1940         vb[3] = i2f(sy);
1941
1942         vb[4] = i2f(dx);
1943         vb[5] = i2f(dy2);
1944         vb[6] = i2f(sx);
1945         vb[7] = i2f(sy2);
1946
1947         vb[8] = i2f(dx2);
1948         vb[9] = i2f(dy2);
1949         vb[10] = i2f(sx2);
1950         vb[11] = i2f(sy2);
1951
1952         switch(cpp) {
1953         case 4:
1954                 cb_format = COLOR_8_8_8_8;
1955                 tex_format = FMT_8_8_8_8;
1956                 break;
1957         case 2:
1958                 cb_format = COLOR_5_6_5;
1959                 tex_format = FMT_5_6_5;
1960                 break;
1961         default:
1962                 cb_format = COLOR_8;
1963                 tex_format = FMT_8;
1964                 break;
1965         }
1966
1967         /* src */
1968         set_tex_resource(dev_priv, tex_format,
1969                          src_pitch / cpp,
1970                          sy2, src_pitch / cpp,
1971                          src_gpu_addr);
1972
1973         cp_set_surface_sync(dev_priv,
1974                             R600_TC_ACTION_ENA, src_pitch * sy2, src_gpu_addr);
1975
1976         /* dst */
1977         set_render_target(dev_priv, cb_format,
1978                           dst_pitch / cpp, dy2,
1979                           dst_gpu_addr);
1980
1981         /* scissors */
1982         set_scissors(dev_priv, dx, dy, dx2, dy2);
1983
1984         /* Vertex buffer setup */
1985         vb_addr = dev_priv->gart_buffers_offset +
1986                 dev_priv->blit_vb->offset +
1987                 dev_priv->blit_vb->used;
1988         set_vtx_resource(dev_priv, vb_addr);
1989
1990         /* draw */
1991         draw_auto(dev_priv);
1992
1993         cp_set_surface_sync(dev_priv,
1994                             R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
1995                             dst_pitch * dy2, dst_gpu_addr);
1996
1997         dev_priv->blit_vb->used += 12 * 4;
1998 }