2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2004 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c 192397 2009-05-19 17:35:15Z sam $
23 #include "ah_internal.h"
25 #include "ar5210/ar5210.h"
26 #include "ar5210/ar5210reg.h"
29 * Return non-zero if an interrupt is pending.
32 ar5210IsInterruptPending(struct ath_hal *ah)
34 return (OS_REG_READ(ah, AR_INTPEND) ? AH_TRUE : AH_FALSE);
38 * Read the Interrupt Status Register value and return
39 * an abstracted bitmask of the data found in the ISR.
40 * Note that reading the ISR clear pending interrupts.
43 ar5210GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
45 #define AR_FATAL_INT \
46 (AR_ISR_MCABT_INT | AR_ISR_SSERR_INT | AR_ISR_DPERR_INT | AR_ISR_RXORN_INT)
47 struct ath_hal_5210 *ahp = AH5210(ah);
50 isr = OS_REG_READ(ah, AR_ISR);
51 if (isr == 0xffffffff) {
57 * Mask interrupts that have no device-independent
58 * representation; these are added back below. We
59 * also masked with the abstracted IMR to insure no
60 * status bits leak through that weren't requested
61 * (e.g. RXNOFRM) and that might confuse the caller.
63 *masked = (isr & (HAL_INT_COMMON - HAL_INT_BNR)) & ahp->ah_maskReg;
65 if (isr & AR_FATAL_INT)
66 *masked |= HAL_INT_FATAL;
67 if (isr & (AR_ISR_RXOK_INT | AR_ISR_RXERR_INT))
68 *masked |= HAL_INT_RX;
69 if (isr & (AR_ISR_TXOK_INT | AR_ISR_TXDESC_INT | AR_ISR_TXERR_INT | AR_ISR_TXEOL_INT))
70 *masked |= HAL_INT_TX;
73 * On fatal errors collect ISR state for debugging.
75 if (*masked & HAL_INT_FATAL) {
76 AH_PRIVATE(ah)->ah_fatalState[0] = isr;
84 ar5210GetInterrupts(struct ath_hal *ah)
86 return AH5210(ah)->ah_maskReg;
90 ar5210SetInterrupts(struct ath_hal *ah, HAL_INT ints)
92 struct ath_hal_5210 *ahp = AH5210(ah);
93 uint32_t omask = ahp->ah_maskReg;
96 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
97 __func__, omask, ints);
100 * Disable interrupts here before reading & modifying
101 * the mask so that the ISR does not modify the mask
104 if (omask & HAL_INT_GLOBAL) {
105 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
106 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
109 mask = ints & (HAL_INT_COMMON - HAL_INT_BNR);
110 if (ints & HAL_INT_RX)
111 mask |= AR_IMR_RXOK_INT | AR_IMR_RXERR_INT;
112 if (ints & HAL_INT_TX) {
113 if (ahp->ah_txOkInterruptMask)
114 mask |= AR_IMR_TXOK_INT;
115 if (ahp->ah_txErrInterruptMask)
116 mask |= AR_IMR_TXERR_INT;
117 if (ahp->ah_txDescInterruptMask)
118 mask |= AR_IMR_TXDESC_INT;
119 if (ahp->ah_txEolInterruptMask)
120 mask |= AR_IMR_TXEOL_INT;
123 /* Write the new IMR and store off our SW copy. */
124 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
125 OS_REG_WRITE(ah, AR_IMR, mask);
126 ahp->ah_maskReg = ints;
128 /* Re-enable interrupts as appropriate. */
129 if (ints & HAL_INT_GLOBAL) {
130 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
131 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);