2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2004 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5210/ar5210_misc.c 188974 2009-02-24 00:12:16Z sam $
23 #include "ah_internal.h"
25 #include "ar5210/ar5210.h"
26 #include "ar5210/ar5210reg.h"
27 #include "ar5210/ar5210phy.h"
29 #include "ah_eeprom_v1.h"
31 #define AR_NUM_GPIO 6 /* 6 GPIO bits */
32 #define AR_GPIOD_MASK 0x2f /* 6-bit mask */
35 ar5210GetMacAddress(struct ath_hal *ah, uint8_t *mac)
37 struct ath_hal_5210 *ahp = AH5210(ah);
39 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
43 ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
45 struct ath_hal_5210 *ahp = AH5210(ah);
47 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
52 ar5210GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
54 static const uint8_t ones[IEEE80211_ADDR_LEN] =
55 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
56 OS_MEMCPY(mask, ones, IEEE80211_ADDR_LEN);
60 ar5210SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
66 * Read 16 bits of data from the specified EEPROM offset.
69 ar5210EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)
71 (void) OS_REG_READ(ah, AR_EP_AIR(off)); /* activate read op */
72 if (!ath_hal_wait(ah, AR_EP_STA,
73 AR_EP_STA_RDCMPLT | AR_EP_STA_RDERR, AR_EP_STA_RDCMPLT)) {
74 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: read failed for entry 0x%x\n",
75 __func__, AR_EP_AIR(off));
78 *data = OS_REG_READ(ah, AR_EP_RDATA) & 0xffff;
82 #ifdef AH_SUPPORT_WRITE_EEPROM
84 * Write 16 bits of data to the specified EEPROM offset.
87 ar5210EepromWrite(struct ath_hal *ah, u_int off, uint16_t data)
91 #endif /* AH_SUPPORT_WRITE_EEPROM */
94 * Attempt to change the cards operating regulatory domain to the given value
97 ar5210SetRegulatoryDomain(struct ath_hal *ah,
98 uint16_t regDomain, HAL_STATUS *status)
102 if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
107 * Check if EEPROM is configured to allow this; must
108 * be a proper version and the protection bits must
109 * permit re-writing that segment of the EEPROM.
111 if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
115 ecode = HAL_EIO; /* disallow all writes */
123 * Return the wireless modes (a,b,g,t) supported by hardware.
125 * This value is what is actually supported by the hardware
126 * and is unaffected by regulatory/country code settings.
130 ar5210GetWirelessModes(struct ath_hal *ah)
132 /* XXX could enable turbo mode but can't do all rates */
137 * Called if RfKill is supported (according to EEPROM). Set the interrupt and
138 * GPIO values so the ISR and can disable RF on a switch signal
141 ar5210EnableRfKill(struct ath_hal *ah)
143 uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
144 int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL);
145 int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY);
148 * If radio disable switch connection to GPIO bit 0 is enabled
149 * program GPIO interrupt.
150 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
151 * verified that it is a later version of eeprom, it has a place for
152 * rfkill bit and it is set to 1, indicating that GPIO bit 0 hardware
153 * connection is present.
155 ar5210Gpio0SetIntr(ah, select, (ar5210GpioGet(ah, select) == polarity));
159 * Configure GPIO Output lines
162 ar5210GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
164 HALASSERT(gpio < AR_NUM_GPIO);
166 OS_REG_WRITE(ah, AR_GPIOCR,
167 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
168 | AR_GPIOCR_OUT1(gpio));
174 * Configure GPIO Input lines
177 ar5210GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
179 HALASSERT(gpio < AR_NUM_GPIO);
181 OS_REG_WRITE(ah, AR_GPIOCR,
182 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
183 | AR_GPIOCR_IN(gpio));
189 * Once configured for I/O - set output lines
192 ar5210GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
196 HALASSERT(gpio < AR_NUM_GPIO);
198 reg = OS_REG_READ(ah, AR_GPIODO);
200 reg |= (val&1) << gpio;
202 OS_REG_WRITE(ah, AR_GPIODO, reg);
207 * Once configured for I/O - get input lines
210 ar5210GpioGet(struct ath_hal *ah, uint32_t gpio)
212 if (gpio < AR_NUM_GPIO) {
213 uint32_t val = OS_REG_READ(ah, AR_GPIODI);
214 val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1;
222 * Set the GPIO 0 Interrupt
225 ar5210Gpio0SetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
227 uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
229 /* Clear the bits that we will modify. */
230 val &= ~(AR_GPIOCR_INT_SEL(gpio) | AR_GPIOCR_INT_SELH | AR_GPIOCR_INT_ENA |
231 AR_GPIOCR_ALL(gpio));
233 val |= AR_GPIOCR_INT_SEL(gpio) | AR_GPIOCR_INT_ENA;
235 val |= AR_GPIOCR_INT_SELH;
237 /* Don't need to change anything for low level interrupt. */
238 OS_REG_WRITE(ah, AR_GPIOCR, val);
240 /* Change the interrupt mask. */
241 ar5210SetInterrupts(ah, AH5210(ah)->ah_maskReg | HAL_INT_GPIO);
245 * Change the LED blinking pattern to correspond to the connectivity
248 ar5210SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
252 val = OS_REG_READ(ah, AR_PCICFG);
255 val &= ~(AR_PCICFG_LED_PEND | AR_PCICFG_LED_ACT);
258 /* normal blink when connected */
259 val &= ~AR_PCICFG_LED_PEND;
260 val |= AR_PCICFG_LED_ACT;
263 val |= AR_PCICFG_LED_PEND;
264 val &= ~AR_PCICFG_LED_ACT;
267 OS_REG_WRITE(ah, AR_PCICFG, val);
271 * Return 1 or 2 for the corresponding antenna that is in use
274 ar5210GetDefAntenna(struct ath_hal *ah)
276 uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
277 return (val & AR_STA_ID1_DEFAULT_ANTENNA ? 2 : 1);
281 ar5210SetDefAntenna(struct ath_hal *ah, u_int antenna)
283 uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
285 if (antenna != (val & AR_STA_ID1_DEFAULT_ANTENNA ? 2 : 1)) {
287 * Antenna change requested, force a toggle of the default.
289 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_DEFAULT_ANTENNA);
294 ar5210GetAntennaSwitch(struct ath_hal *ah)
296 return HAL_ANT_VARIABLE;
300 ar5210SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
302 /* XXX not sure how to fix antenna */
303 return (settings == HAL_ANT_VARIABLE);
307 * Change association related fields programmed into the hardware.
308 * Writing a valid BSSID to the hardware effectively enables the hardware
309 * to synchronize its TSF to the correct beacons and receive frames coming
310 * from that BSSID. It is called by the SME JOIN operation.
313 ar5210WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
315 struct ath_hal_5210 *ahp = AH5210(ah);
317 /* XXX save bssid for possible re-use on reset */
318 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
319 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
320 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
321 ((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
323 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);
325 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);
329 * Get the current hardware tsf for stamlme.
332 ar5210GetTsf64(struct ath_hal *ah)
334 uint32_t low1, low2, u32;
336 /* sync multi-word read */
337 low1 = OS_REG_READ(ah, AR_TSF_L32);
338 u32 = OS_REG_READ(ah, AR_TSF_U32);
339 low2 = OS_REG_READ(ah, AR_TSF_L32);
340 if (low2 < low1) { /* roll over */
342 * If we are not preempted this will work. If we are
343 * then we re-reading AR_TSF_U32 does no good as the
344 * low bits will be meaningless. Likewise reading
345 * L32, U32, U32, then comparing the last two reads
346 * to check for rollover doesn't help if preempted--so
347 * we take this approach as it costs one less PCI
348 * read which can be noticeable when doing things
349 * like timestamping packets in monitor mode.
353 return (((uint64_t) u32) << 32) | ((uint64_t) low2);
357 * Get the current hardware tsf for stamlme.
360 ar5210GetTsf32(struct ath_hal *ah)
362 return OS_REG_READ(ah, AR_TSF_L32);
366 * Reset the current hardware tsf for stamlme
369 ar5210ResetTsf(struct ath_hal *ah)
371 uint32_t val = OS_REG_READ(ah, AR_BEACON);
373 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
377 * Grab a semi-random value from hardware registers - may not
381 ar5210GetRandomSeed(struct ath_hal *ah)
385 nf = (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) >> 19) & 0x1ff;
387 nf = 0 - ((nf ^ 0x1ff) + 1);
388 return (OS_REG_READ(ah, AR_TSF_U32) ^
389 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
393 * Detect if our card is present
396 ar5210DetectCardPresent(struct ath_hal *ah)
399 * Read the Silicon Revision register and compare that
400 * to what we read at attach time. If the same, we say
401 * a card/device is present.
403 return (AH_PRIVATE(ah)->ah_macRev == (OS_REG_READ(ah, AR_SREV) & 0xff));
407 * Update MIB Counters
410 ar5210UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats)
412 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
413 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
414 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
415 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
416 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
420 ar5210SetSifsTime(struct ath_hal *ah, u_int us)
422 struct ath_hal_5210 *ahp = AH5210(ah);
424 if (us > ath_hal_mac_usec(ah, 0x7ff)) {
425 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
427 ahp->ah_sifstime = (u_int) -1; /* restore default handling */
430 /* convert to system clocks */
431 OS_REG_RMW_FIELD(ah, AR_IFS0, AR_IFS0_SIFS,
432 ath_hal_mac_clks(ah, us));
433 ahp->ah_sifstime = us;
439 ar5210GetSifsTime(struct ath_hal *ah)
441 u_int clks = OS_REG_READ(ah, AR_IFS0) & 0x7ff;
442 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
446 ar5210SetSlotTime(struct ath_hal *ah, u_int us)
448 struct ath_hal_5210 *ahp = AH5210(ah);
450 if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) {
451 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
453 ahp->ah_slottime = (u_int) -1; /* restore default handling */
456 /* convert to system clocks */
457 OS_REG_WRITE(ah, AR_SLOT_TIME, ath_hal_mac_clks(ah, us));
458 ahp->ah_slottime = us;
464 ar5210GetSlotTime(struct ath_hal *ah)
466 u_int clks = OS_REG_READ(ah, AR_SLOT_TIME) & 0xffff;
467 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
471 ar5210SetAckTimeout(struct ath_hal *ah, u_int us)
473 struct ath_hal_5210 *ahp = AH5210(ah);
475 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
476 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
478 ahp->ah_acktimeout = (u_int) -1; /* restore default handling */
481 /* convert to system clocks */
482 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
483 AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
484 ahp->ah_acktimeout = us;
490 ar5210GetAckTimeout(struct ath_hal *ah)
492 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
493 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
497 ar5210GetAckCTSRate(struct ath_hal *ah)
499 return ((AH5210(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
503 ar5210SetAckCTSRate(struct ath_hal *ah, u_int high)
505 struct ath_hal_5210 *ahp = AH5210(ah);
508 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
509 ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB;
511 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
512 ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB;
518 ar5210SetCTSTimeout(struct ath_hal *ah, u_int us)
520 struct ath_hal_5210 *ahp = AH5210(ah);
522 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
523 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
525 ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */
528 /* convert to system clocks */
529 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
530 AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
531 ahp->ah_ctstimeout = us;
537 ar5210GetCTSTimeout(struct ath_hal *ah)
539 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
540 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
544 ar5210SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
551 ar5210SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
556 * Control Adaptive Noise Immunity Parameters
559 ar5210AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
565 ar5210AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
566 const struct ieee80211_channel *chan)
571 ar5210MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)
575 #define AR_DIAG_SW_DIS_CRYPTO (AR_DIAG_SW_DIS_ENC | AR_DIAG_SW_DIS_DEC)
578 ar5210GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
579 uint32_t capability, uint32_t *result)
583 case HAL_CAP_CIPHER: /* cipher handled in hardware */
584 return (capability == HAL_CIPHER_WEP ? HAL_OK : HAL_ENOTSUPP);
586 return ath_hal_getcapability(ah, type, capability, result);
591 ar5210SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
592 uint32_t capability, uint32_t setting, HAL_STATUS *status)
596 case HAL_CAP_DIAG: /* hardware diagnostic support */
598 * NB: could split this up into virtual capabilities,
599 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
600 * seems worth the additional complexity.
603 AH_PRIVATE(ah)->ah_diagreg = setting;
605 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
607 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
609 case HAL_CAP_RXORN_FATAL: /* HAL_INT_RXORN treated as fatal */
610 return AH_FALSE; /* NB: disallow */
612 return ath_hal_setcapability(ah, type, capability,
618 ar5210GetDiagState(struct ath_hal *ah, int request,
619 const void *args, uint32_t argsize,
620 void **result, uint32_t *resultsize)
622 #ifdef AH_PRIVATE_DIAG
627 case HAL_DIAG_EEPROM:
630 case HAL_DIAG_EEREAD:
631 if (argsize != sizeof(uint16_t))
633 pcicfg = OS_REG_READ(ah, AR_PCICFG);
634 OS_REG_WRITE(ah, AR_PCICFG, pcicfg | AR_PCICFG_EEPROMSEL);
635 ok = ath_hal_eepromRead(ah, *(const uint16_t *)args, *result);
636 OS_REG_WRITE(ah, AR_PCICFG, pcicfg);
638 *resultsize = sizeof(uint16_t);
642 return ath_hal_getdiagstate(ah, request,
643 args, argsize, result, resultsize);