2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2006 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c 192397 2009-05-19 17:35:15Z sam $
23 #include "ah_internal.h"
25 #include "ar5211/ar5211.h"
26 #include "ar5211/ar5211reg.h"
29 * Checks to see if an interrupt is pending on our NIC
31 * Returns: TRUE if an interrupt is pending
35 ar5211IsInterruptPending(struct ath_hal *ah)
37 return OS_REG_READ(ah, AR_INTPEND) != 0;
41 * Reads the Interrupt Status Register value from the NIC, thus deasserting
42 * the interrupt line, and returns both the masked and unmasked mapped ISR
43 * values. The value returned is mapped to abstract the hw-specific bit
44 * locations in the Interrupt Status Register.
46 * Returns: A hardware-abstracted bitmap of all non-masked-out
47 * interrupts pending, as well as an unmasked value
50 ar5211GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
54 isr = OS_REG_READ(ah, AR_ISR_RAC);
55 if (isr == 0xffffffff) {
60 *masked = isr & HAL_INT_COMMON;
62 if (isr & AR_ISR_HIUERR)
63 *masked |= HAL_INT_FATAL;
64 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
65 *masked |= HAL_INT_RX;
66 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL))
67 *masked |= HAL_INT_TX;
69 * Receive overrun is usually non-fatal on Oahu/Spirit.
70 * BUT on some parts rx could fail and the chip must be reset.
71 * So we force a hardware reset in all cases.
73 if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) {
74 HALDEBUG(ah, HAL_DEBUG_ANY,
75 "%s: receive FIFO overrun interrupt\n", __func__);
76 *masked |= HAL_INT_FATAL;
80 * On fatal errors collect ISR state for debugging.
82 if (*masked & HAL_INT_FATAL) {
83 AH_PRIVATE(ah)->ah_fatalState[0] = isr;
84 AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S);
85 AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S);
86 AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S);
87 AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S);
88 AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S);
89 HALDEBUG(ah, HAL_DEBUG_ANY,
90 "%s: fatal error, ISR_RAC=0x%x ISR_S2_S=0x%x\n",
91 __func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]);
97 ar5211GetInterrupts(struct ath_hal *ah)
99 return AH5211(ah)->ah_maskReg;
103 * Atomically enables NIC interrupts. Interrupts are passed in
104 * via the enumerated bitmask in ints.
107 ar5211SetInterrupts(struct ath_hal *ah, HAL_INT ints)
109 struct ath_hal_5211 *ahp = AH5211(ah);
110 uint32_t omask = ahp->ah_maskReg;
113 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
114 __func__, omask, ints);
117 * Disable interrupts here before reading & modifying
118 * the mask so that the ISR does not modify the mask
121 if (omask & HAL_INT_GLOBAL) {
122 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
123 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
125 (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */
128 mask = ints & HAL_INT_COMMON;
129 if (ints & HAL_INT_TX) {
130 if (ahp->ah_txOkInterruptMask)
132 if (ahp->ah_txErrInterruptMask)
133 mask |= AR_IMR_TXERR;
134 if (ahp->ah_txDescInterruptMask)
135 mask |= AR_IMR_TXDESC;
136 if (ahp->ah_txEolInterruptMask)
137 mask |= AR_IMR_TXEOL;
139 if (ints & HAL_INT_RX)
140 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
141 if (ints & HAL_INT_FATAL) {
143 * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2
144 * so enabling HIUERR enables delivery.
146 mask |= AR_IMR_HIUERR;
149 /* Write the new IMR and store off our SW copy. */
150 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
151 OS_REG_WRITE(ah, AR_IMR, mask);
152 ahp->ah_maskReg = ints;
154 /* Re-enable interrupts as appropriate. */
155 if (ints & HAL_INT_GLOBAL) {
156 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
157 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);