2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $Id: ar5212_keycache.c,v 1.4 2008/11/10 04:08:03 sam Exp $
23 #include "ah_internal.h"
25 #include "ar5212/ar5212.h"
26 #include "ar5212/ar5212reg.h"
27 #include "ar5212/ar5212desc.h"
30 * Note: The key cache hardware requires that each double-word
31 * pair be written in even/odd order (since the destination is
32 * a 64-bit register). Don't reorder the writes in this code
33 * w/o considering this!
37 #define IS_MIC_ENABLED(ah) \
38 (AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
41 * Return the size of the hardware key cache.
44 ar5212GetKeyCacheSize(struct ath_hal *ah)
46 return AH_PRIVATE(ah)->ah_caps.halKeyCacheSize;
50 * Return true if the specific key cache entry is valid.
53 ar5212IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry)
55 if (entry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
56 uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
57 if (val & AR_KEYTABLE_VALID)
64 * Clear the specified key cache entry and any associated MIC entry.
67 ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)
71 if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
72 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
76 keyType = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
78 /* XXX why not clear key type/valid bit first? */
79 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
80 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
81 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
82 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
83 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
84 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
85 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
86 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
87 if (keyType == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) {
88 uint16_t micentry = entry+64; /* MIC goes at slot+64 */
90 HALASSERT(micentry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize);
91 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
92 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
93 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
94 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
95 /* NB: key type and MAC are known to be ok */
101 * Sets the mac part of the specified key cache entry (and any
102 * associated MIC entry) and mark them valid.
105 ar5212SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)
107 uint32_t macHi, macLo;
109 if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
110 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
115 * Set MAC address -- shifted right by 1. MacLo is
116 * the 4 MSBs, and MacHi is the 2 LSBs.
118 if (mac != AH_NULL) {
119 macHi = (mac[5] << 8) | mac[4];
120 macLo = (mac[3] << 24)| (mac[2] << 16)
121 | (mac[1] << 8) | mac[0];
123 macLo |= (macHi & 1) << 31; /* carry */
128 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
129 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
134 * Sets the contents of the specified key cache entry
135 * and any associated MIC entry.
138 ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
139 const HAL_KEYVAL *k, const uint8_t *mac,
142 struct ath_hal_5212 *ahp = AH5212(ah);
143 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
144 uint32_t key0, key1, key2, key3, key4;
146 uint32_t xorMask = xorKey ?
147 (KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0;
149 if (entry >= pCap->halKeyCacheSize) {
150 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
154 switch (k->kv_type) {
155 case HAL_CIPHER_AES_OCB:
156 keyType = AR_KEYTABLE_TYPE_AES;
158 case HAL_CIPHER_AES_CCM:
159 if (!pCap->halCipherAesCcmSupport) {
160 HALDEBUG(ah, HAL_DEBUG_ANY,
161 "%s: AES-CCM not supported by mac rev 0x%x\n",
162 __func__, AH_PRIVATE(ah)->ah_macRev);
165 keyType = AR_KEYTABLE_TYPE_CCM;
167 case HAL_CIPHER_TKIP:
168 keyType = AR_KEYTABLE_TYPE_TKIP;
169 if (IS_MIC_ENABLED(ah) && entry+64 >= pCap->halKeyCacheSize) {
170 HALDEBUG(ah, HAL_DEBUG_ANY,
171 "%s: entry %u inappropriate for TKIP\n",
177 if (k->kv_len < 40 / NBBY) {
178 HALDEBUG(ah, HAL_DEBUG_ANY,
179 "%s: WEP key length %u too small\n",
180 __func__, k->kv_len);
183 if (k->kv_len <= 40 / NBBY)
184 keyType = AR_KEYTABLE_TYPE_40;
185 else if (k->kv_len <= 104 / NBBY)
186 keyType = AR_KEYTABLE_TYPE_104;
188 keyType = AR_KEYTABLE_TYPE_128;
191 keyType = AR_KEYTABLE_TYPE_CLR;
194 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n",
195 __func__, k->kv_type);
199 key0 = LE_READ_4(k->kv_val+0) ^ xorMask;
200 key1 = (LE_READ_2(k->kv_val+4) ^ xorMask) & 0xffff;
201 key2 = LE_READ_4(k->kv_val+6) ^ xorMask;
202 key3 = (LE_READ_2(k->kv_val+10) ^ xorMask) & 0xffff;
203 key4 = LE_READ_4(k->kv_val+12) ^ xorMask;
204 if (k->kv_len <= 104 / NBBY)
208 * Note: key cache hardware requires that each double-word
209 * pair be written in even/odd order (since the destination is
210 * a 64-bit register). Don't reorder these writes w/o
213 if (keyType == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) {
214 uint16_t micentry = entry+64; /* MIC goes at slot+64 */
215 uint32_t mic0, mic1, mic2, mic3, mic4;
218 * Invalidate the encrypt/decrypt key until the MIC
219 * key is installed so pending rx frames will fail
220 * with decrypt errors rather than a MIC error.
222 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
223 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
224 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
225 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
226 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
227 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
228 (void) ar5212SetKeyCacheEntryMac(ah, entry, mac);
232 * Write MIC entry according to new or old key layout.
233 * The MISC_MODE register is assumed already set so
234 * these writes will be handled properly (happens on
235 * attach and at every reset).
238 mic0 = LE_READ_4(k->kv_mic+0);
239 mic2 = LE_READ_4(k->kv_mic+4);
240 if (ahp->ah_miscMode & AR_MISC_MODE_MIC_NEW_LOC_ENABLE) {
242 * Both RX and TX mic values can be combined into
243 * one cache slot entry:
244 * 8*N + 800 31:0 RX Michael key 0
245 * 8*N + 804 15:0 TX Michael key 0 [31:16]
246 * 8*N + 808 31:0 RX Michael key 1
247 * 8*N + 80C 15:0 TX Michael key 0 [15:0]
248 * 8*N + 810 31:0 TX Michael key 1
249 * 8*N + 814 15:0 reserved
250 * 8*N + 818 31:0 reserved
251 * 8*N + 81C 14:0 reserved
255 mic1 = LE_READ_2(k->kv_txmic+2) & 0xffff;
256 mic3 = LE_READ_2(k->kv_txmic+0) & 0xffff;
257 mic4 = LE_READ_4(k->kv_txmic+4);
259 mic1 = mic3 = mic4 = 0;
261 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
262 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
263 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
264 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
265 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
266 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
267 AR_KEYTABLE_TYPE_CLR);
268 /* NB: MIC key is not marked valid and has no MAC address */
269 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
270 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
272 /* correct intentionally corrupted key */
273 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
274 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
276 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
277 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
278 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
279 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
280 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
281 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
283 (void) ar5212SetKeyCacheEntryMac(ah, entry, mac);