sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal_adcdc.c

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c 203158 2010-01-29 10:07:17Z rpaulo $
  18  * $DragonFly$
  19  */
  20 #include "opt_ah.h"
  21
  22 #include "ah.h"
  23 #include "ah_internal.h"
  24 #include "ah_devid.h"
  25
  26 #include "ar5416/ar5416.h"
  27 #include "ar5416/ar5416reg.h"
  28 #include "ar5416/ar5416phy.h"
  29
  30 /* Adc DC Offset Cal aliases */
  31 #define totalAdcDcOffsetIOddPhase(i)    caldata[0][i].s
  32 #define totalAdcDcOffsetIEvenPhase(i)   caldata[1][i].s
  33 #define totalAdcDcOffsetQOddPhase(i)    caldata[2][i].s
  34 #define totalAdcDcOffsetQEvenPhase(i)   caldata[3][i].s
  35
  36 void
  37 ar5416AdcDcCalCollect(struct ath_hal *ah)
  38 {
  39         struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
  40         int i;
  41
  42         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
  43                 cal->totalAdcDcOffsetIOddPhase(i) += (int32_t)
  44                     OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
  45                 cal->totalAdcDcOffsetIEvenPhase(i) += (int32_t)
  46                     OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
  47                 cal->totalAdcDcOffsetQOddPhase(i) += (int32_t)
  48                     OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
  49                 cal->totalAdcDcOffsetQEvenPhase(i) += (int32_t)
  50                     OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
  51
  52                 HALDEBUG(ah, HAL_DEBUG_PERCAL,
  53                     "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
  54                    cal->calSamples, i,
  55                    cal->totalAdcDcOffsetIOddPhase(i),
  56                    cal->totalAdcDcOffsetIEvenPhase(i),
  57                    cal->totalAdcDcOffsetQOddPhase(i),
  58                    cal->totalAdcDcOffsetQEvenPhase(i));
  59         }
  60 }
  61
  62 void
  63 ar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains)
  64 {
  65         struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
  66         const HAL_PERCAL_DATA *calData = cal->cal_curr->calData;
  67         uint32_t numSamples;
  68         int i;
  69
  70         numSamples = (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
  71         for (i = 0; i < numChains; i++) {
  72                 uint32_t iOddMeasOffset = cal->totalAdcDcOffsetIOddPhase(i);
  73                 uint32_t iEvenMeasOffset = cal->totalAdcDcOffsetIEvenPhase(i);
  74                 int32_t qOddMeasOffset = cal->totalAdcDcOffsetQOddPhase(i);
  75                 int32_t qEvenMeasOffset = cal->totalAdcDcOffsetQEvenPhase(i);
  76                 int32_t qDcMismatch, iDcMismatch;
  77                 uint32_t val;
  78
  79                 HALDEBUG(ah, HAL_DEBUG_PERCAL,
  80                     "Starting ADC DC Offset Cal for Chain %d\n", i);
  81
  82                 HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_i = %d\n",
  83                     iOddMeasOffset);
  84                 HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_i = %d\n",
  85                     iEvenMeasOffset);
  86                 HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_q = %d\n",
  87                     qOddMeasOffset);
  88                 HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_q = %d\n",
  89                     qEvenMeasOffset);
  90
  91                 HALASSERT(numSamples);
  92
  93                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
  94                     numSamples) & 0x1ff;
  95                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
  96                     numSamples) & 0x1ff;
  97                 HALDEBUG(ah, HAL_DEBUG_PERCAL,
  98                     " dc_offset_mismatch_i = 0x%08x\n", iDcMismatch);
  99                 HALDEBUG(ah, HAL_DEBUG_PERCAL,
 100                     " dc_offset_mismatch_q = 0x%08x\n", qDcMismatch);
 101
 102                 val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
 103                 val &= 0xc0000fff;
 104                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
 105                 OS_REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 106
 107                 HALDEBUG(ah, HAL_DEBUG_PERCAL,
 108                     "ADC DC Offset Cal done for Chain %d\n", i);
 109         }
 110         OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
 111             AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
 112 }