2 * Copyright (c) 2001 Cubical Solutions Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * capi/iavc/iavc_card.c
26 * The AVM ISDN controllers' card specific support routines.
28 * $FreeBSD: src/sys/i4b/capi/iavc/iavc_card.c,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $
29 * $DragonFly: src/sys/net/i4b/capi/iavc/iavc_card.c,v 1.8 2006/10/25 20:56:03 dillon Exp $
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/systm.h>
36 #include <sys/socket.h>
39 #include <sys/thread2.h>
41 #include <machine/clock.h>
45 #include <net/i4b/include/machine/i4b_debug.h>
46 #include <net/i4b/include/machine/i4b_ioctl.h>
47 #include <net/i4b/include/machine/i4b_trace.h>
49 #include "../../include/i4b_global.h"
50 #include "../../include/i4b_l3l4.h"
51 #include "../../include/i4b_mbuf.h"
57 // AVM B1 (active BRI, PIO mode)
61 b1_detect(iavc_softc_t *sc)
63 if ((iavc_read_port(sc, B1_INSTAT) & 0xfc) ||
64 (iavc_read_port(sc, B1_OUTSTAT) & 0xfc))
67 b1io_outp(sc, B1_INSTAT, 0x02);
68 b1io_outp(sc, B1_OUTSTAT, 0x02);
69 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) != 2 ||
70 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe) != 2)
73 b1io_outp(sc, B1_INSTAT, 0x00);
74 b1io_outp(sc, B1_OUTSTAT, 0x00);
75 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) ||
76 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe))
79 return (0); /* found */
83 b1_disable_irq(iavc_softc_t *sc)
85 b1io_outp(sc, B1_INSTAT, 0x00);
89 b1_reset(iavc_softc_t *sc)
91 b1io_outp(sc, B1_RESET, 0);
94 b1io_outp(sc, B1_RESET, 1);
97 b1io_outp(sc, B1_RESET, 0);
102 // Newer PCI-based B1's, and T1's, supports DMA
106 b1dma_detect(iavc_softc_t *sc)
108 AMCC_WRITE(sc, AMCC_MCSR, 0);
110 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
112 AMCC_WRITE(sc, AMCC_MCSR, 0);
115 AMCC_WRITE(sc, AMCC_RXLEN, 0);
116 AMCC_WRITE(sc, AMCC_TXLEN, 0);
118 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
120 if (AMCC_READ(sc, AMCC_INTCSR) != 0)
123 AMCC_WRITE(sc, AMCC_RXPTR, 0xffffffff);
124 AMCC_WRITE(sc, AMCC_TXPTR, 0xffffffff);
125 if ((AMCC_READ(sc, AMCC_RXPTR) != 0xfffffffc) ||
126 (AMCC_READ(sc, AMCC_TXPTR) != 0xfffffffc))
129 AMCC_WRITE(sc, AMCC_RXPTR, 0);
130 AMCC_WRITE(sc, AMCC_TXPTR, 0);
131 if ((AMCC_READ(sc, AMCC_RXPTR) != 0) ||
132 (AMCC_READ(sc, AMCC_TXPTR) != 0))
135 iavc_write_port(sc, 0x10, 0x00);
136 iavc_write_port(sc, 0x07, 0x00);
138 iavc_write_port(sc, 0x02, 0x02);
139 iavc_write_port(sc, 0x03, 0x02);
141 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x02) ||
142 (iavc_read_port(sc, 0x03) != 0x03))
145 iavc_write_port(sc, 0x02, 0x00);
146 iavc_write_port(sc, 0x03, 0x00);
148 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x00) ||
149 (iavc_read_port(sc, 0x03) != 0x01))
152 return (0); /* found */
156 b1dma_reset(iavc_softc_t *sc)
160 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
161 AMCC_WRITE(sc, AMCC_MCSR, 0);
162 AMCC_WRITE(sc, AMCC_RXLEN, 0);
163 AMCC_WRITE(sc, AMCC_TXLEN, 0);
165 iavc_write_port(sc, 0x10, 0x00); /* XXX magic numbers from */
166 iavc_write_port(sc, 0x07, 0x00); /* XXX the linux driver */
170 AMCC_WRITE(sc, AMCC_MCSR, 0);
172 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
174 AMCC_WRITE(sc, AMCC_MCSR, 0);
179 // AVM T1 (active PRI)
182 /* XXX how do these differ from b1io_{read,write}_reg()? XXX */
185 b1dma_tx_empty(int iobase)
187 return inb(iobase + 3) & 1;
191 b1dma_rx_full(int iobase)
193 return inb(iobase + 2) & 1;
197 b1dma_tolink(iavc_softc_t *sc, void *buf, int len)
200 char *s = (char*) buf;
203 while (!b1dma_tx_empty(sc->sc_iobase) && spin < 100000)
205 if (!b1dma_tx_empty(sc->sc_iobase))
207 t1io_outp(sc, 1, *s++);
213 b1dma_fromlink(iavc_softc_t *sc, void *buf, int len)
216 char *s = (char*) buf;
219 while (!b1dma_rx_full(sc->sc_iobase) && spin < 100000)
221 if (!b1dma_rx_full(sc->sc_iobase))
223 *s++ = t1io_inp(sc, 0);
229 WriteReg(iavc_softc_t *sc, u_int32_t reg, u_int8_t val)
232 if (b1dma_tolink(sc, &cmd, 1) == 0 &&
233 b1dma_tolink(sc, ®, 4) == 0) {
235 return b1dma_tolink(sc, &tmp, 4);
241 ReadReg(iavc_softc_t *sc, u_int32_t reg)
244 if (b1dma_tolink(sc, &cmd, 1) == 0 &&
245 b1dma_tolink(sc, ®, 4) == 0) {
247 if (b1dma_fromlink(sc, &tmp, 4) == 0)
248 return (u_int8_t) tmp;
254 t1_detect(iavc_softc_t *sc)
256 int ret = b1dma_detect(sc);
259 if ((WriteReg(sc, 0x80001000, 0x11) != 0) ||
260 (WriteReg(sc, 0x80101000, 0x22) != 0) ||
261 (WriteReg(sc, 0x80201000, 0x33) != 0) ||
262 (WriteReg(sc, 0x80301000, 0x44) != 0))
265 if ((ReadReg(sc, 0x80001000) != 0x11) ||
266 (ReadReg(sc, 0x80101000) != 0x22) ||
267 (ReadReg(sc, 0x80201000) != 0x33) ||
268 (ReadReg(sc, 0x80301000) != 0x44))
271 if ((WriteReg(sc, 0x80001000, 0x55) != 0) ||
272 (WriteReg(sc, 0x80101000, 0x66) != 0) ||
273 (WriteReg(sc, 0x80201000, 0x77) != 0) ||
274 (WriteReg(sc, 0x80301000, 0x88) != 0))
277 if ((ReadReg(sc, 0x80001000) != 0x55) ||
278 (ReadReg(sc, 0x80101000) != 0x66) ||
279 (ReadReg(sc, 0x80201000) != 0x77) ||
280 (ReadReg(sc, 0x80301000) != 0x88))
283 return 0; /* found */
287 t1_disable_irq(iavc_softc_t *sc)
289 iavc_write_port(sc, T1_IRQMASTER, 0x00);
293 t1_reset(iavc_softc_t *sc)
296 iavc_write_port(sc, B1_INSTAT, 0x00);
297 iavc_write_port(sc, B1_OUTSTAT, 0x00);
298 iavc_write_port(sc, T1_IRQMASTER, 0x00);
299 iavc_write_port(sc, T1_RESETBOARD, 0x0f);