2 * Copyright (c) 1999, 2000 Dave Boyce. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 *---------------------------------------------------------------------------
27 * i4b_iwic - isdn4bsd Winbond W6692 driver
28 * ----------------------------------------
30 * $FreeBSD: src/sys/i4b/layer1/iwic/i4b_iwic_dchan.c,v 1.4.2.1 2001/08/10 14:08:40 obrien Exp $
31 * $DragonFly: src/sys/net/i4b/layer1/iwic/i4b_iwic_dchan.c,v 1.4 2005/06/03 16:50:08 dillon Exp $
33 * last edit-date: [Tue Jan 16 13:20:14 2001]
35 *---------------------------------------------------------------------------*/
41 #if (NIWIC > 0) && (NPCI > 0)
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/socket.h>
47 #include <sys/thread2.h>
51 #include <net/i4b/include/machine/i4b_debug.h>
52 #include <net/i4b/include/machine/i4b_ioctl.h>
53 #include <net/i4b/include/machine/i4b_trace.h>
55 #include "../i4b_l1.h"
57 #include "../../include/i4b_global.h"
58 #include "../../include/i4b_l3l4.h"
59 #include "../../include/i4b_mbuf.h"
62 #include "i4b_w6692.h"
64 #define MAX_DFRAME_LEN 264
66 static void dchan_receive(struct iwic_softc *sc, int ista);
68 /*---------------------------------------------------------------------------*
69 * initialize D-channel variables and registers
70 *---------------------------------------------------------------------------*/
72 iwic_dchan_init(struct iwic_softc *sc)
74 sc->sc_dchan.ibuf = NULL;
75 sc->sc_dchan.rx_count = 0;
77 sc->sc_dchan.obuf = NULL;
78 sc->sc_dchan.obuf2 = NULL;
79 sc->sc_dchan.tx_count = 0;
80 sc->sc_dchan.tx_ready = 0;
82 IWIC_WRITE(sc, D_CTL, D_CTL_SRST);
86 IWIC_WRITE(sc, D_CTL, 0);
88 IWIC_WRITE(sc, SQX, SQX_SCIE);
90 IWIC_WRITE(sc, PCTL, 0x00);
91 IWIC_WRITE(sc, MOCR, 0x00);
92 IWIC_WRITE(sc, GCR, 0x00);
94 IWIC_WRITE(sc, D_CMDR, D_CMDR_RRST | D_CMDR_XRST);
95 IWIC_WRITE(sc, D_MODE, D_MODE_RACT);
97 IWIC_WRITE(sc, D_SAM, 0xff);
98 IWIC_WRITE(sc, D_TAM, 0xff);
100 IWIC_WRITE(sc, D_EXIM, 0x00);
103 /*---------------------------------------------------------------------------*
104 * Extended IRQ handler for the D-channel
105 *---------------------------------------------------------------------------*/
107 iwic_dchan_xirq(struct iwic_softc *sc)
112 irq_stat = IWIC_READ(sc, D_EXIR);
114 if (irq_stat & D_EXIR_RDOV)
116 NDBGL1(L1_I_ERR, "RDOV in state %s", iwic_printstate(sc));
117 IWIC_WRITE(sc, D_CMDR, D_CMDR_RRST);
119 if (irq_stat & D_EXIR_XDUN)
121 NDBGL1(L1_I_ERR, "XDUN in state %s", iwic_printstate(sc));
122 sc->sc_dchan.tx_ready = 0;
124 if (irq_stat & D_EXIR_XCOL)
126 NDBGL1(L1_I_ERR, "XCOL in state %s", iwic_printstate(sc));
127 IWIC_WRITE(sc, D_CMDR, D_CMDR_XRST);
128 sc->sc_dchan.tx_ready = 0;
130 if (irq_stat & D_EXIR_TIN2)
132 NDBGL1(L1_I_ERR, "TIN2 in state %s", iwic_printstate(sc));
134 if (irq_stat & D_EXIR_MOC)
136 stat = IWIC_READ(sc, MOR);
137 NDBGL1(L1_I_ERR, "MOC in state %s, byte = 0x%x", iwic_printstate(sc), stat);
140 if (irq_stat & D_EXIR_ISC)
142 stat = (IWIC_READ(sc, CIR)) & 0x0f;
147 NDBGL1(L1_I_CICO, "rx CE in state %s", iwic_printstate(sc));
148 iwic_next_state(sc, EV_CE);
151 NDBGL1(L1_I_CICO, "rx DRD in state %s", iwic_printstate(sc));
152 iwic_next_state(sc, EV_INFO0);
153 i4b_l1_mph_status_ind(L0IWICUNIT(sc->sc_unit), STI_L1STAT, LAYER_IDLE, NULL);
156 NDBGL1(L1_I_CICO, "rx LD in state %s", iwic_printstate(sc));
157 iwic_next_state(sc, EV_RSY);
160 NDBGL1(L1_I_CICO, "rx ARD in state %s", iwic_printstate(sc));
161 iwic_next_state(sc, EV_INFO2);
164 NDBGL1(L1_I_CICO, "rx TI in state %s", iwic_printstate(sc));
165 iwic_next_state(sc, EV_INFO0);
168 NDBGL1(L1_I_CICO, "rx ATI in state %s", iwic_printstate(sc));
169 iwic_next_state(sc, EV_INFO0);
172 NDBGL1(L1_I_CICO, "rx AI8 in state %s", iwic_printstate(sc));
173 i4b_l1_mph_status_ind(L0IWICUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
174 iwic_next_state(sc, EV_INFO48);
177 NDBGL1(L1_I_CICO, "rx AI10 in state %s", iwic_printstate(sc));
178 i4b_l1_mph_status_ind(L0IWICUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
179 iwic_next_state(sc, EV_INFO410);
182 NDBGL1(L1_I_CICO, "rx DIS in state %s", iwic_printstate(sc));
183 iwic_next_state(sc, EV_DIS);
186 NDBGL1(L1_I_ERR, "ERROR, unknown indication 0x%x in state %s", stat, iwic_printstate(sc));
187 iwic_next_state(sc, EV_INFO0);
192 if (irq_stat & D_EXIR_TEXP)
194 NDBGL1(L1_I_ERR, "TEXP in state %s", iwic_printstate(sc));
197 if (irq_stat & D_EXIR_WEXP)
199 NDBGL1(L1_I_ERR, "WEXP in state %s", iwic_printstate(sc));
203 /*---------------------------------------------------------------------------*
204 * All receiving and transmitting takes place here.
205 *---------------------------------------------------------------------------*/
207 iwic_dchan_xfer_irq(struct iwic_softc *sc, int ista)
209 NDBGL1(L1_I_MSG, "ISTA = 0x%x", ista);
211 if (ista & (ISTA_D_RMR | ISTA_D_RME))
213 /* Receive message ready */
214 dchan_receive(sc, ista);
216 if (ista & ISTA_D_XFR)
218 /* Transmitter ready */
219 sc->sc_dchan.tx_ready = 1;
221 iwic_dchan_transmit(sc);
225 /*---------------------------------------------------------------------------*
227 *---------------------------------------------------------------------------*/
229 iwic_dchan_disable(struct iwic_softc *sc)
233 if (sc->sc_dchan.obuf)
235 if (sc->sc_dchan.free_obuf)
236 i4b_Dfreembuf(sc->sc_dchan.obuf);
237 sc->sc_dchan.obuf = NULL;
240 if (sc->sc_dchan.obuf2)
242 if (sc->sc_dchan.free_obuf2)
243 i4b_Dfreembuf(sc->sc_dchan.obuf2);
244 sc->sc_dchan.obuf2 = NULL;
249 IWIC_WRITE(sc, CIX, CIX_DRC);
252 /*---------------------------------------------------------------------------*
253 * queue D-channel message for transmission
254 *---------------------------------------------------------------------------*/
256 iwic_dchan_data_req(struct iwic_softc *sc, struct mbuf *m, int freeflag)
265 if (sc->sc_dchan.obuf)
267 if (sc->sc_dchan.obuf2)
269 NDBGL1(L1_I_ERR, "no buffer space!");
273 sc->sc_dchan.obuf2 = m;
274 sc->sc_dchan.free_obuf2 = freeflag;
279 sc->sc_dchan.obuf = m;
280 sc->sc_dchan.obuf_ptr = m->m_data;
281 sc->sc_dchan.obuf_len = m->m_len;
282 sc->sc_dchan.free_obuf = freeflag;
285 iwic_dchan_transmit(sc);
292 /*---------------------------------------------------------------------------*
294 *---------------------------------------------------------------------------*/
296 dchan_get_mbuf(struct iwic_softc *sc, int len)
298 sc->sc_dchan.ibuf = i4b_Dgetmbuf(len);
300 if (!sc->sc_dchan.ibuf)
301 panic("dchan_get_mbuf: unable to allocate %d bytes for mbuf!\n", len);
303 sc->sc_dchan.ibuf_ptr = sc->sc_dchan.ibuf->m_data;
304 sc->sc_dchan.ibuf_max_len = sc->sc_dchan.ibuf->m_len;
305 sc->sc_dchan.ibuf_len = 0;
308 /*---------------------------------------------------------------------------*
309 * D-channel receive data interrupt
310 *---------------------------------------------------------------------------*/
312 dchan_receive(struct iwic_softc *sc, int ista)
314 int command = D_CMDR_RACK;
316 if (ista & ISTA_D_RMR)
318 /* Got 64 bytes in FIFO */
320 if (!sc->sc_dchan.ibuf)
322 dchan_get_mbuf(sc, MAX_DFRAME_LEN);
325 else if ((sc->sc_dchan.ibuf_len + MAX_DFRAME_LEN) >
326 sc->sc_dchan.ibuf_max_len)
328 panic("dchan_receive: not enough space in buffer!\n");
331 IWIC_RDDFIFO(sc, sc->sc_dchan.ibuf_ptr, 64);
333 sc->sc_dchan.ibuf_ptr += 64;
334 sc->sc_dchan.ibuf_len += 64;
335 sc->sc_dchan.rx_count += 64;
337 if (ista & ISTA_D_RME)
339 /* Got end of frame */
342 status = IWIC_READ(sc, D_RSTA);
344 if (status & (D_RSTA_RDOV | D_RSTA_CRCE | D_RSTA_RMB))
346 if (status & D_RSTA_RDOV)
347 NDBGL1(L1_I_ERR, "iwic%d: D-channel Receive Data Overflow", sc->sc_unit);
348 if (status & D_RSTA_CRCE)
349 NDBGL1(L1_I_ERR, "iwic%d: D-channel CRC Error", sc->sc_unit);
350 if (status & D_RSTA_RMB)
351 NDBGL1(L1_I_ERR, "iwic%d: D-channel Receive Message Aborted", sc->sc_unit);
352 command |= D_CMDR_RRST;
359 lo = IWIC_READ(sc, D_RBCL);
360 hi = IWIC_READ(sc, D_RBCH);
361 total_frame_len = D_RBC(hi, lo);
365 lo = IWIC_DCHAN_FIFO_LEN;
367 if (!sc->sc_dchan.ibuf)
369 dchan_get_mbuf(sc, lo);
371 else if ((sc->sc_dchan.ibuf_len + lo) >
372 sc->sc_dchan.ibuf_max_len)
374 panic("dchan_receive: buffer not long enough");
377 IWIC_RDDFIFO(sc, sc->sc_dchan.ibuf_ptr, lo);
378 sc->sc_dchan.ibuf_len += lo;
379 sc->sc_dchan.rx_count += lo;
381 sc->sc_dchan.ibuf->m_len = sc->sc_dchan.ibuf_len;
383 if(sc->sc_trace & TRACE_D_RX)
386 hdr.unit = L0IWICUNIT(sc->sc_unit);
389 hdr.count = ++sc->sc_dchan.trace_count;
391 i4b_l1_trace_ind(&hdr, sc->sc_dchan.ibuf->m_len, sc->sc_dchan.ibuf->m_data);
393 i4b_l1_ph_data_ind(L0IWICUNIT(sc->sc_unit), sc->sc_dchan.ibuf);
395 sc->sc_dchan.ibuf = NULL;
398 IWIC_WRITE(sc, D_CMDR, command);
401 /*---------------------------------------------------------------------------*
402 * transmit D-channel frame
403 *---------------------------------------------------------------------------*/
405 iwic_dchan_transmit(struct iwic_softc *sc)
411 if (!sc->sc_dchan.tx_ready)
414 if (!sc->sc_dchan.obuf)
417 if (sc->sc_I430state != ST_F7)
420 ptr = sc->sc_dchan.obuf_ptr;
421 len = min(sc->sc_dchan.obuf_len, IWIC_DCHAN_FIFO_LEN);
423 if(sc->sc_trace & TRACE_D_TX)
426 hdr.unit = L0IWICUNIT(sc->sc_unit);
429 hdr.count = ++sc->sc_dchan.trace_count;
431 i4b_l1_trace_ind(&hdr, len, ptr);
434 IWIC_WRDFIFO(sc, ptr, len);
436 sc->sc_dchan.tx_count += len;
438 if (len < sc->sc_dchan.obuf_len)
440 sc->sc_dchan.obuf_ptr += len;
441 sc->sc_dchan.obuf_len -= len;
448 if (sc->sc_dchan.free_obuf)
449 i4b_Dfreembuf(sc->sc_dchan.obuf);
451 sc->sc_dchan.obuf = NULL;
452 sc->sc_dchan.obuf_ptr = NULL;
453 sc->sc_dchan.obuf_len = 0;
455 if (sc->sc_dchan.obuf2)
457 sc->sc_dchan.obuf = sc->sc_dchan.obuf2;
458 sc->sc_dchan.obuf_ptr = sc->sc_dchan.obuf->m_data;
459 sc->sc_dchan.obuf_len = sc->sc_dchan.obuf->m_len;
460 sc->sc_dchan.free_obuf = sc->sc_dchan.free_obuf2;
462 sc->sc_dchan.obuf2 = NULL;
464 cmd = D_CMDR_XMS | D_CMDR_XME;
466 sc->sc_dchan.tx_ready = 0;
467 IWIC_WRITE(sc, D_CMDR, cmd);
470 #endif /* (NIWIC > 0) && (NPCI > 0) */