2 * Copyright (c) 1990 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz and Don Ahn.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
54 #include "opt_clock.h"
57 #include <sys/param.h>
58 #include <sys/systm.h>
59 #include <sys/eventhandler.h>
61 #include <sys/kernel.h>
66 #include <sys/sysctl.h>
68 #include <sys/systimer.h>
69 #include <sys/globaldata.h>
70 #include <sys/thread2.h>
71 #include <sys/systimer.h>
72 #include <sys/machintr.h>
73 #include <sys/interrupt.h>
75 #include <machine/clock.h>
76 #ifdef CLK_CALIBRATION_LOOP
78 #include <machine/cputypes.h>
79 #include <machine/frame.h>
80 #include <machine/ipl.h>
81 #include <machine/limits.h>
82 #include <machine/md_var.h>
83 #include <machine/psl.h>
84 #include <machine/segments.h>
85 #include <machine/smp.h>
86 #include <machine/specialreg.h>
87 #include <machine/intr_machdep.h>
90 #include <machine_base/apic/ioapic_abi.h>
92 #include <machine_base/icu/icu.h>
93 #include <bus/isa/isa.h>
94 #include <bus/isa/rtc.h>
95 #include <machine_base/isa/timerreg.h>
97 #ifdef SMP /* APIC-IO */
98 /* The interrupt triggered by the 8254 (timer) chip */
99 static void setup_8254_mixed_mode (void);
101 static void i8254_restore(void);
102 static void resettodr_on_shutdown(void *arg __unused);
105 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
106 * can use a simple formula for leap years.
108 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
109 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
112 #define TIMER_FREQ 1193182
115 static uint8_t i8254_walltimer_sel;
116 static uint16_t i8254_walltimer_cntr;
118 int adjkerntz; /* local offset from GMT in seconds */
119 int disable_rtc_set; /* disable resettodr() if != 0 */
121 int64_t tsc_frequency;
123 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
125 enum tstate { RELEASED, ACQUIRED };
126 enum tstate timer0_state;
127 enum tstate timer1_state;
128 enum tstate timer2_state;
130 static int beeping = 0;
131 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
132 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
133 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
134 static int rtc_loaded;
136 static int i8254_cputimer_div;
138 static int i8254_nointr;
139 static int i8254_intr_disable = 1;
140 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
142 static struct callout sysbeepstop_ch;
144 static sysclock_t i8254_cputimer_count(void);
145 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
146 static void i8254_cputimer_destruct(struct cputimer *cputimer);
148 static struct cputimer i8254_cputimer = {
149 SLIST_ENTRY_INITIALIZER,
153 i8254_cputimer_count,
154 cputimer_default_fromhz,
155 cputimer_default_fromus,
156 i8254_cputimer_construct,
157 i8254_cputimer_destruct,
162 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
163 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
164 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
166 static struct cputimer_intr i8254_cputimer_intr = {
168 .reload = i8254_intr_reload,
169 .enable = cputimer_intr_default_enable,
170 .config = i8254_intr_config,
171 .restart = cputimer_intr_default_restart,
172 .pmfixup = cputimer_intr_default_pmfixup,
173 .initclock = i8254_intr_initclock,
174 .next = SLIST_ENTRY_INITIALIZER,
176 .type = CPUTIMER_INTR_8254,
177 .prio = CPUTIMER_INTR_PRIO_8254,
178 .caps = CPUTIMER_INTR_CAP_PS
182 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
183 * counting as of this interrupt. We use timer1 in free-running mode (not
184 * generating any interrupts) as our main counter. Each cpu has timeouts
187 * This code is INTR_MPSAFE and may be called without the BGL held.
190 clkintr(void *dummy, void *frame_arg)
192 static sysclock_t sysclock_count; /* NOTE! Must be static */
193 struct globaldata *gd = mycpu;
195 struct globaldata *gscan;
200 * SWSTROBE mode is a one-shot, the timer is no longer running
205 * XXX the dispatcher needs work. right now we call systimer_intr()
206 * directly or via IPI for any cpu with systimers queued, which is
207 * usually *ALL* of them. We need to use the LAPIC timer for this.
209 sysclock_count = sys_cputimer->count();
211 for (n = 0; n < ncpus; ++n) {
212 gscan = globaldata_find(n);
213 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
216 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
219 systimer_intr(&sysclock_count, 0, frame_arg);
223 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
224 systimer_intr(&sysclock_count, 0, frame_arg);
233 acquire_timer2(int mode)
235 if (timer2_state != RELEASED)
237 timer2_state = ACQUIRED;
240 * This access to the timer registers is as atomic as possible
241 * because it is a single instruction. We could do better if we
244 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
251 if (timer2_state != ACQUIRED)
253 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
254 timer2_state = RELEASED;
262 DB_SHOW_COMMAND(rtc, rtc)
264 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
265 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
266 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
267 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
272 * Return the current cpu timer count as a 32 bit integer.
276 i8254_cputimer_count(void)
278 static __uint16_t cputimer_last;
283 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
284 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
285 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
286 count = -count; /* -> countup */
287 if (count < cputimer_last) /* rollover */
288 i8254_cputimer.base += 0x00010000;
289 ret = i8254_cputimer.base | count;
290 cputimer_last = count;
296 * This function is called whenever the system timebase changes, allowing
297 * us to calculate what is needed to convert a system timebase tick
298 * into an 8254 tick for the interrupt timer. If we can convert to a
299 * simple shift, multiplication, or division, we do so. Otherwise 64
300 * bit arithmatic is required every time the interrupt timer is reloaded.
303 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
309 * Will a simple divide do the trick?
311 div = (timer->freq + (cti->freq / 2)) / cti->freq;
312 freq = cti->freq * div;
314 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
315 i8254_cputimer_div = div;
317 i8254_cputimer_div = 0;
321 * Reload for the next timeout. It is possible for the reload value
322 * to be 0 or negative, indicating that an immediate timer interrupt
323 * is desired. For now make the minimum 2 ticks.
325 * We may have to convert from the system timebase to the 8254 timebase.
328 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
332 if (i8254_cputimer_div)
333 reload /= i8254_cputimer_div;
335 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
341 if (timer0_running) {
342 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
343 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
344 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
345 if (reload < count) {
346 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
347 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
348 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
353 reload = 0; /* full count */
354 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
355 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
356 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
362 * DELAY(usec) - Spin for the specified number of microseconds.
363 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
364 * but do a thread switch in the loop
366 * Relies on timer 1 counting down from (cputimer_freq / hz)
367 * Note: timer had better have been programmed before this is first used!
370 DODELAY(int n, int doswitch)
372 int delta, prev_tick, tick, ticks_left;
377 static int state = 0;
381 for (n1 = 1; n1 <= 10000000; n1 *= 10)
386 kprintf("DELAY(%d)...", n);
389 * Guard against the timer being uninitialized if we are called
390 * early for console i/o.
392 if (timer0_state == RELEASED)
396 * Read the counter first, so that the rest of the setup overhead is
397 * counted. Then calculate the number of hardware timer ticks
398 * required, rounding up to be sure we delay at least the requested
399 * number of microseconds.
401 prev_tick = sys_cputimer->count();
402 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
408 while (ticks_left > 0) {
409 tick = sys_cputimer->count();
413 delta = tick - prev_tick;
418 if (doswitch && ticks_left > 0)
424 kprintf(" %d calls to getit() at %d usec each\n",
425 getit_calls, (n + 5) / getit_calls);
430 * DELAY() never switches.
439 * Returns non-zero if the specified time period has elapsed. Call
440 * first with last_clock set to 0.
443 CHECKTIMEOUT(TOTALDELAY *tdd)
448 if (tdd->started == 0) {
449 if (timer0_state == RELEASED)
451 tdd->last_clock = sys_cputimer->count();
455 delta = sys_cputimer->count() - tdd->last_clock;
456 us = (u_int64_t)delta * (u_int64_t)1000000 /
457 (u_int64_t)sys_cputimer->freq;
458 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
461 return (tdd->us < 0);
466 * DRIVERSLEEP() does not switch if called with a spinlock held or
467 * from a hard interrupt.
470 DRIVERSLEEP(int usec)
472 globaldata_t gd = mycpu;
474 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) {
482 sysbeepstop(void *chan)
484 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
490 sysbeep(int pitch, int period)
492 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
494 if (sysbeep_enable == 0)
497 * Nobody else is using timer2, we do not need the clock lock
499 outb(TIMER_CNTR2, pitch);
500 outb(TIMER_CNTR2, (pitch>>8));
502 /* enable counter2 output to speaker */
503 outb(IO_PPI, inb(IO_PPI) | 3);
505 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
511 * RTC support routines
522 val = inb(IO_RTC + 1);
529 writertc(u_char reg, u_char val)
535 outb(IO_RTC + 1, val);
536 inb(0x84); /* XXX work around wrong order in rtcin() */
543 return(bcd2bin(rtcin(port)));
547 calibrate_clocks(void)
550 u_int count, prev_count, tot_count;
551 int sec, start_sec, timeout;
554 kprintf("Calibrating clock(s) ... ");
555 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
559 /* Read the mc146818A seconds counter. */
561 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
562 sec = rtcin(RTC_SEC);
569 /* Wait for the mC146818A seconds counter to change. */
572 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
573 sec = rtcin(RTC_SEC);
574 if (sec != start_sec)
581 /* Start keeping track of the i8254 counter. */
582 prev_count = sys_cputimer->count();
588 old_tsc = 0; /* shut up gcc */
591 * Wait for the mc146818A seconds counter to change. Read the i8254
592 * counter for each iteration since this is convenient and only
593 * costs a few usec of inaccuracy. The timing of the final reads
594 * of the counters almost matches the timing of the initial reads,
595 * so the main cause of inaccuracy is the varying latency from
596 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
597 * rtcin(RTC_SEC) that returns a changed seconds count. The
598 * maximum inaccuracy from this cause is < 10 usec on 486's.
602 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
603 sec = rtcin(RTC_SEC);
604 count = sys_cputimer->count();
605 tot_count += (int)(count - prev_count);
607 if (sec != start_sec)
614 * Read the cpu cycle counter. The timing considerations are
615 * similar to those for the i8254 clock.
618 tsc_frequency = rdtsc() - old_tsc;
622 kprintf("TSC clock: %llu Hz, ", (long long)tsc_frequency);
623 kprintf("i8254 clock: %u Hz\n", tot_count);
627 kprintf("failed, using default i8254 clock of %u Hz\n",
628 i8254_cputimer.freq);
629 return (i8254_cputimer.freq);
635 timer0_state = ACQUIRED;
640 * Timer0 is our fine-grained variable clock interrupt
642 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
643 outb(TIMER_CNTR0, 2); /* lsb */
644 outb(TIMER_CNTR0, 0); /* msb */
648 cputimer_intr_register(&i8254_cputimer_intr);
649 cputimer_intr_select(&i8254_cputimer_intr, 0);
653 * Timer1 or timer2 is our free-running clock, but only if another
654 * has not been selected.
656 cputimer_register(&i8254_cputimer);
657 cputimer_select(&i8254_cputimer, 0);
661 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
666 * Should we use timer 1 or timer 2 ?
669 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
670 if (which != 1 && which != 2)
675 timer->name = "i8254_timer1";
676 timer->type = CPUTIMER_8254_SEL1;
677 i8254_walltimer_sel = TIMER_SEL1;
678 i8254_walltimer_cntr = TIMER_CNTR1;
679 timer1_state = ACQUIRED;
682 timer->name = "i8254_timer2";
683 timer->type = CPUTIMER_8254_SEL2;
684 i8254_walltimer_sel = TIMER_SEL2;
685 i8254_walltimer_cntr = TIMER_CNTR2;
686 timer2_state = ACQUIRED;
690 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
693 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
694 outb(i8254_walltimer_cntr, 0); /* lsb */
695 outb(i8254_walltimer_cntr, 0); /* msb */
696 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
701 i8254_cputimer_destruct(struct cputimer *timer)
703 switch(timer->type) {
704 case CPUTIMER_8254_SEL1:
705 timer1_state = RELEASED;
707 case CPUTIMER_8254_SEL2:
708 timer2_state = RELEASED;
719 /* Restore all of the RTC's "status" (actually, control) registers. */
720 writertc(RTC_STATUSB, RTCSB_24HR);
721 writertc(RTC_STATUSA, rtc_statusa);
722 writertc(RTC_STATUSB, rtc_statusb);
726 * Restore all the timers.
728 * This function is called to resynchronize our core timekeeping after a
729 * long halt, e.g. from apm_default_resume() and friends. It is also
730 * called if after a BIOS call we have detected munging of the 8254.
731 * It is necessary because cputimer_count() counter's delta may have grown
732 * too large for nanouptime() and friends to handle, or (in the case of 8254
733 * munging) might cause the SYSTIMER code to prematurely trigger.
739 i8254_restore(); /* restore timer_freq and hz */
740 rtc_restore(); /* reenable RTC interrupts */
745 * Initialize 8254 timer 0 early so that it can be used in DELAY().
753 * Can we use the TSC?
755 if (cpu_feature & CPUID_TSC)
761 * Initial RTC state, don't do anything unexpected
763 writertc(RTC_STATUSA, rtc_statusa);
764 writertc(RTC_STATUSB, RTCSB_24HR);
767 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
768 * generate an interrupt, which we will ignore for now.
770 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
771 * (so it counts a full 2^16 and repeats). We will use this timer
775 freq = calibrate_clocks();
776 #ifdef CLK_CALIBRATION_LOOP
779 "Press a key on the console to abort clock calibration\n");
780 while (cncheckc() == -1)
786 * Use the calibrated i8254 frequency if it seems reasonable.
787 * Otherwise use the default, and don't use the calibrated i586
790 delta = freq > i8254_cputimer.freq ?
791 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
792 if (delta < i8254_cputimer.freq / 100) {
793 #ifndef CLK_USE_I8254_CALIBRATION
796 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
797 freq = i8254_cputimer.freq;
801 * Interrupt timer's freq must be adjusted
802 * before we change the cuptimer's frequency.
804 i8254_cputimer_intr.freq = freq;
805 cputimer_set_frequency(&i8254_cputimer, freq);
809 "%d Hz differs from default of %d Hz by more than 1%%\n",
810 freq, i8254_cputimer.freq);
814 #ifndef CLK_USE_TSC_CALIBRATION
815 if (tsc_frequency != 0) {
818 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
822 if (tsc_present && tsc_frequency == 0) {
824 * Calibration of the i586 clock relative to the mc146818A
825 * clock failed. Do a less accurate calibration relative
826 * to the i8254 clock.
828 u_int64_t old_tsc = rdtsc();
831 tsc_frequency = rdtsc() - old_tsc;
832 #ifdef CLK_USE_TSC_CALIBRATION
834 kprintf("TSC clock: %llu Hz (Method B)\n",
840 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
844 * We can not use the TSC in SMP mode, until we figure out a
845 * cheap (impossible), reliable and precise (yeah right!) way
846 * to synchronize the TSCs of all the CPUs.
847 * Curse Intel for leaving the counter out of the I/O APIC.
852 * We can not use the TSC if we support APM. Precise timekeeping
853 * on an APM'ed machine is at best a fools pursuit, since
854 * any and all of the time spent in various SMM code can't
855 * be reliably accounted for. Reading the RTC is your only
856 * source of reliable time info. The i8254 looses too of course
857 * but we need to have some kind of time...
858 * We don't know at this point whether APM is going to be used
859 * or not, nor when it might be activated. Play it safe.
862 #endif /* NAPM > 0 */
864 #endif /* !defined(SMP) */
868 * Sync the time of day back to the RTC on shutdown, but only if
869 * we have already loaded it and have not crashed.
872 resettodr_on_shutdown(void *arg __unused)
874 if (rtc_loaded && panicstr == NULL) {
880 * Initialize the time of day register, based on the time base which is, e.g.
884 inittodr(time_t base)
886 unsigned long sec, days;
897 /* Look if we have a RTC present and the time is valid */
898 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
901 /* wait for time update to complete */
902 /* If RTCSA_TUP is zero, we have at least 244us before next update */
904 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
910 #ifdef USE_RTC_CENTURY
911 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
913 year = readrtc(RTC_YEAR) + 1900;
921 month = readrtc(RTC_MONTH);
922 for (m = 1; m < month; m++)
923 days += daysinmonth[m-1];
924 if ((month > 2) && LEAPYEAR(year))
926 days += readrtc(RTC_DAY) - 1;
927 for (y = 1970; y < year; y++)
928 days += DAYSPERYEAR + LEAPYEAR(y);
929 sec = ((( days * 24 +
930 readrtc(RTC_HRS)) * 60 +
931 readrtc(RTC_MIN)) * 60 +
933 /* sec now contains the number of seconds, since Jan 1 1970,
934 in the local time zone */
936 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
938 y = time_second - sec;
939 if (y <= -2 || y >= 2) {
940 /* badly off, adjust it */
950 kprintf("Invalid time in real time clock.\n");
951 kprintf("Check and reset the date immediately!\n");
955 * Write system time back to RTC
972 /* Disable RTC updates and interrupts. */
973 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
975 /* Calculate local time to put in RTC */
977 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
979 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
980 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
981 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
983 /* We have now the days since 01-01-1970 in tm */
984 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
985 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
987 y++, m = DAYSPERYEAR + LEAPYEAR(y))
990 /* Now we have the years in y and the day-of-the-year in tm */
991 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
992 #ifdef USE_RTC_CENTURY
993 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
999 if (m == 1 && LEAPYEAR(y))
1006 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
1007 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
1009 /* Reenable RTC updates and interrupts. */
1010 writertc(RTC_STATUSB, rtc_statusb);
1017 i8254_ioapic_trial(int irq, struct cputimer_intr *cti)
1023 * Following code assumes the 8254 is the cpu timer,
1024 * so make sure it is.
1026 KKASSERT(sys_cputimer == &i8254_cputimer);
1027 KKASSERT(cti == &i8254_cputimer_intr);
1029 lastcnt = get_interrupt_counter(irq);
1032 * Force an 8254 Timer0 interrupt and wait 1/100s for
1033 * it to happen, then see if we got it.
1035 kprintf("IOAPIC: testing 8254 interrupt delivery\n");
1037 i8254_intr_reload(cti, 2);
1038 base = sys_cputimer->count();
1039 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1042 if (get_interrupt_counter(irq) - lastcnt == 0)
1050 * Start both clocks running. DragonFly note: the stat clock is no longer
1051 * used. Instead, 8254 based systimers are used for all major clock
1055 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1057 #ifdef SMP /* APIC-IO */
1058 int apic_8254_trial = 0;
1059 void *clkdesc = NULL;
1060 int irq = 0, mixed_mode = 0, error;
1063 callout_init(&sysbeepstop_ch);
1065 if (!selected && i8254_intr_disable)
1069 * The stat interrupt mask is different without the
1070 * statistics clock. Also, don't set the interrupt
1071 * flag which would normally cause the RTC to generate
1074 rtc_statusb = RTCSB_24HR;
1076 /* Finish initializing 8254 timer 0. */
1077 #ifdef SMP /* APIC-IO */
1078 if (apic_io_enable) {
1079 if (ioapic_use_old) {
1080 irq = isa_apic_irq(0);
1082 if (apic_int_type(0, 0) == 3)
1083 apic_8254_trial = 1;
1085 /* look for ExtInt on pin 0 */
1086 if (apic_int_type(0, 0) == 3) {
1087 irq = apic_irq(0, 0);
1088 setup_8254_mixed_mode();
1090 panic("APIC_IO: Cannot route 8254 "
1091 "interrupt to CPU");
1095 clkdesc = register_int(irq, clkintr, NULL, "clk",
1097 INTR_EXCL | INTR_CLOCK |
1098 INTR_NOPOLL | INTR_MPSAFE |
1100 machintr_intren(irq);
1102 irq = ioapic_abi_find_irq(0, INTR_TRIGGER_EDGE,
1103 INTR_POLARITY_HIGH);
1106 error = ioapic_abi_extint_irqmap(0);
1108 irq = ioapic_abi_find_irq(0, INTR_TRIGGER_EDGE,
1109 INTR_POLARITY_HIGH);
1116 kprintf("IOAPIC: setup mixed mode for "
1117 "irq 0 failed: %d\n", error);
1120 panic("IOAPIC: setup mixed mode for "
1121 "irq 0 failed: %d\n", error);
1126 clkdesc = register_int(irq, clkintr, NULL, "clk",
1128 INTR_EXCL | INTR_CLOCK |
1129 INTR_NOPOLL | INTR_MPSAFE |
1131 machintr_intren(irq);
1135 register_int(0, clkintr, NULL, "clk", NULL,
1136 INTR_EXCL | INTR_CLOCK |
1137 INTR_NOPOLL | INTR_MPSAFE |
1140 #ifdef SMP /* APIC-IO */
1144 /* Initialize RTC. */
1145 writertc(RTC_STATUSA, rtc_statusa);
1146 writertc(RTC_STATUSB, RTCSB_24HR);
1148 #ifdef SMP /* APIC-IO */
1149 if (apic_io_enable) {
1150 if (ioapic_use_old) {
1151 if (apic_8254_trial) {
1156 * Following code assumes the 8254 is the cpu timer,
1157 * so make sure it is.
1159 KKASSERT(sys_cputimer == &i8254_cputimer);
1160 KKASSERT(cti == &i8254_cputimer_intr);
1162 lastcnt = get_interrupt_counter(irq);
1165 * Force an 8254 Timer0 interrupt and wait 1/100s for
1166 * it to happen, then see if we got it.
1168 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
1169 i8254_intr_reload(cti, 2);
1170 base = sys_cputimer->count();
1171 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1173 if (get_interrupt_counter(irq) - lastcnt == 0) {
1175 * The MP table is broken.
1176 * The 8254 was not connected to the specified pin
1178 * Workaround: Limited variant of mixed mode.
1180 machintr_intrdis(irq);
1181 unregister_int(clkdesc);
1182 kprintf("APIC_IO: Broken MP table detected: "
1183 "8254 is not connected to "
1184 "IOAPIC #%d intpin %d\n",
1185 int_to_apicintpin[irq].ioapic,
1186 int_to_apicintpin[irq].int_pin);
1188 * Revoke current ISA IRQ 0 assignment and
1189 * configure a fallback interrupt routing from
1190 * the 8254 Timer via the 8259 PIC to the
1191 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1192 * We reuse the low level interrupt handler number.
1194 if (apic_irq(0, 0) < 0) {
1195 revoke_apic_irq(irq);
1196 assign_apic_irq(0, 0, irq);
1198 irq = apic_irq(0, 0);
1199 setup_8254_mixed_mode();
1200 register_int(irq, clkintr, NULL, "clk",
1202 INTR_EXCL | INTR_CLOCK |
1203 INTR_NOPOLL | INTR_MPSAFE |
1205 machintr_intren(irq);
1208 if (apic_int_type(0, 0) != 3 ||
1209 int_to_apicintpin[irq].ioapic != 0 ||
1210 int_to_apicintpin[irq].int_pin != 0) {
1211 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1212 int_to_apicintpin[irq].ioapic,
1213 int_to_apicintpin[irq].int_pin);
1216 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1218 } else { /* !ioapic_use_old */
1219 error = i8254_ioapic_trial(irq, cti);
1223 kprintf("IOAPIC: mixed mode for irq %d "
1224 "trial failed: %d\n", irq, error);
1227 panic("IOAPIC: mixed mode for irq %d "
1228 "trial failed: %d\n", irq, error);
1231 kprintf("IOAPIC: warning 8254 is not connected "
1232 "to the correct pin, try mixed mode\n");
1233 machintr_intrdis(irq);
1234 unregister_int(clkdesc);
1235 goto mixed_mode_setup;
1238 } /* ioapic_use_old */
1244 i8254_nointr = 1; /* don't try to register again */
1245 cputimer_intr_deregister(cti);
1248 #ifdef SMP /* APIC-IO */
1251 setup_8254_mixed_mode(void)
1254 * Allow 8254 timer to INTerrupt 8259:
1255 * re-initialize master 8259:
1256 * reset; prog 4 bytes, single ICU, edge triggered
1258 outb(IO_ICU1, 0x13);
1259 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
1260 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1261 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1262 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1264 /* program IO APIC for type 3 INT on INT0 */
1265 if (ext_int_setup(0, 0) < 0)
1266 panic("8254 redirect via APIC pin0 impossible!");
1271 setstatclockrate(int newhz)
1273 if (newhz == RTC_PROFRATE)
1274 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1276 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1277 writertc(RTC_STATUSA, rtc_statusa);
1282 tsc_get_timecount(struct timecounter *tc)
1288 #ifdef KERN_TIMESTAMP
1289 #define KERN_TIMESTAMP_SIZE 16384
1290 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1291 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1292 sizeof(tsc), "LU", "Kernel timestamps");
1298 tsc[i] = (u_int32_t)rdtsc();
1301 if (i >= KERN_TIMESTAMP_SIZE)
1303 tsc[i] = 0; /* mark last entry */
1305 #endif /* KERN_TIMESTAMP */
1312 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1319 if (sys_cputimer == &i8254_cputimer)
1320 count = sys_cputimer->count();
1328 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1329 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1332 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1333 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1335 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1336 0, 0, hw_i8254_timestamp, "A", "");
1338 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1339 &tsc_present, 0, "TSC Available");
1340 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1341 &tsc_frequency, 0, "TSC Frequency");