2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/isa/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_BASE2 (0xe0000)
78 #define BIOS_SIZE (0x10000)
79 #define BIOS_COUNT (BIOS_SIZE/4)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define PROCENTRY_FLAG_EN 0x01
87 #define PROCENTRY_FLAG_BP 0x02
88 #define IOAPICENTRY_FLAG_EN 0x01
91 /* MP Floating Pointer Structure */
92 typedef struct MPFPS {
105 /* MP Configuration Table Header */
106 typedef struct MPCTH {
108 u_short base_table_length;
112 u_char product_id[12];
113 u_int32_t oem_table_pointer;
114 u_short oem_table_size;
116 u_int32_t apic_address;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
123 typedef struct PROCENTRY {
128 u_int32_t cpu_signature;
129 u_int32_t feature_flags;
134 typedef struct BUSENTRY {
140 typedef struct IOAPICENTRY {
145 u_int32_t apic_address;
146 } *io_apic_entry_ptr;
148 typedef struct INTENTRY {
158 /* descriptions of MP basetable entries */
159 typedef struct BASETABLE_ENTRY {
168 vm_size_t mp_cth_mapsz;
171 typedef int (*mptable_iter_func)(void *, const void *, int);
174 * this code MUST be enabled here and in mpboot.s.
175 * it follows the very early stages of AP boot by placing values in CMOS ram.
176 * it NORMALLY will never be needed and thus the primitive method for enabling.
179 #if defined(CHECK_POINTS)
180 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
181 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
183 #define CHECK_INIT(D); \
184 CHECK_WRITE(0x34, (D)); \
185 CHECK_WRITE(0x35, (D)); \
186 CHECK_WRITE(0x36, (D)); \
187 CHECK_WRITE(0x37, (D)); \
188 CHECK_WRITE(0x38, (D)); \
189 CHECK_WRITE(0x39, (D));
191 #define CHECK_PRINT(S); \
192 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
201 #else /* CHECK_POINTS */
203 #define CHECK_INIT(D)
204 #define CHECK_PRINT(S)
206 #endif /* CHECK_POINTS */
209 * Values to send to the POST hardware.
211 #define MP_BOOTADDRESS_POST 0x10
212 #define MP_PROBE_POST 0x11
213 #define MPTABLE_PASS1_POST 0x12
215 #define MP_START_POST 0x13
216 #define MP_ENABLE_POST 0x14
217 #define MPTABLE_PASS2_POST 0x15
219 #define START_ALL_APS_POST 0x16
220 #define INSTALL_AP_TRAMP_POST 0x17
221 #define START_AP_POST 0x18
223 #define MP_ANNOUNCE_POST 0x19
225 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
226 int current_postcode;
228 /** XXX FIXME: what system files declare these??? */
229 extern struct region_descriptor r_gdt, r_idt;
231 int mp_naps; /* # of Applications processors */
233 static int mp_nbusses; /* # of busses */
234 int mp_napics; /* # of IO APICs */
237 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
238 u_int32_t *io_apic_versions;
242 u_int32_t cpu_apic_versions[MAXCPU];
244 extern int64_t tsc_offsets[];
246 extern u_long ebda_addr;
249 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
253 * APIC ID logical/physical mapping structures.
254 * We oversize these to simplify boot-time config.
256 int cpu_num_to_apic_id[NAPICID];
258 int io_num_to_apic_id[NAPICID];
260 int apic_id_to_logical[NAPICID];
262 /* AP uses this during bootstrap. Do not staticize. */
267 * SMP page table page. Setup by locore to point to a page table
268 * page from which we allocate per-cpu privatespace areas io_apics,
272 #define IO_MAPPING_START_INDEX \
273 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
275 extern pt_entry_t *SMPpt;
277 struct pcb stoppcbs[MAXCPU];
279 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
281 static basetable_entry basetable_entry_types[] =
283 {0, 20, "Processor"},
291 * Local data and functions.
294 static u_int boot_address;
295 static u_int base_memory;
296 static int mp_finish;
298 static void mp_enable(u_int boot_addr);
300 static int mptable_iterate_entries(const mpcth_t,
301 mptable_iter_func, void *);
302 static int mptable_probe(void);
303 static int mptable_search(void);
304 static int mptable_check(vm_paddr_t);
305 static long mptable_search_sig(u_int32_t target, int count);
306 static int mptable_hyperthread_fixup(u_int, int);
308 static void mptable_pass1(struct mptable_pos *);
309 static void mptable_pass2(struct mptable_pos *);
310 static void mptable_default(int type);
311 static void mptable_fix(void);
313 static int mptable_map(struct mptable_pos *, vm_paddr_t);
314 static void mptable_unmap(struct mptable_pos *);
315 static void mptable_imcr(struct mptable_pos *);
317 static int mptable_lapic_probe(struct lapic_enumerator *);
318 static void mptable_lapic_enumerate(struct lapic_enumerator *);
319 static void mptable_lapic_default(void);
322 static void setup_apic_irq_mapping(void);
323 static int apic_int_is_bus_type(int intr, int bus_type);
325 static int start_all_aps(u_int boot_addr);
327 static void install_ap_tramp(u_int boot_addr);
329 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
330 static int smitest(void);
332 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
333 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
334 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
335 static u_int bootMP_size;
338 * Calculate usable address in base memory for AP trampoline code.
341 mp_bootaddress(u_int basemem)
343 POSTCODE(MP_BOOTADDRESS_POST);
345 base_memory = basemem;
347 bootMP_size = mptramp_end - mptramp_start;
348 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
349 if (((basemem * 1024) - boot_address) < bootMP_size)
350 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
351 /* 3 levels of page table pages */
352 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
354 return mptramp_pagetables;
363 mpfps_paddr = mptable_search();
364 if (mptable_check(mpfps_paddr))
371 * Look for an Intel MP spec table (ie, SMP capable hardware).
380 * Make sure our SMPpt[] page table is big enough to hold all the
383 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
385 POSTCODE(MP_PROBE_POST);
387 /* see if EBDA exists */
388 if (ebda_addr != 0) {
389 /* search first 1K of EBDA */
390 target = (u_int32_t)ebda_addr;
391 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
394 /* last 1K of base memory, effective 'top of base' passed in */
395 target = (u_int32_t)(base_memory - 0x400);
396 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
400 /* search the BIOS */
401 target = (u_int32_t)BIOS_BASE;
402 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
405 /* search the extended BIOS */
406 target = (u_int32_t)BIOS_BASE2;
407 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
414 struct mptable_check_cbarg {
420 mptable_check_callback(void *xarg, const void *pos, int type)
422 const struct PROCENTRY *ent;
423 struct mptable_check_cbarg *arg = xarg;
429 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
433 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
434 if (arg->found_bsp) {
435 kprintf("more than one BSP in base MP table\n");
444 mptable_check(vm_paddr_t mpfps_paddr)
446 struct mptable_pos mpt;
447 struct mptable_check_cbarg arg;
451 if (mpfps_paddr == 0)
454 error = mptable_map(&mpt, mpfps_paddr);
458 if (mpt.mp_fps->mpfb1 != 0)
466 if (cth->apic_address == 0)
469 bzero(&arg, sizeof(arg));
470 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
472 if (arg.cpu_count == 0) {
473 kprintf("MP table contains no processor entries\n");
475 } else if (!arg.found_bsp) {
476 kprintf("MP table does not contains BSP entry\n");
486 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
488 int count, total_size;
489 const void *position;
491 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
492 total_size = cth->base_table_length - sizeof(struct MPCTH);
493 position = (const uint8_t *)cth + sizeof(struct MPCTH);
494 count = cth->entry_count;
499 KKASSERT(total_size >= 0);
500 if (total_size == 0) {
501 kprintf("invalid base MP table, "
502 "entry count and length mismatch\n");
506 type = *(const uint8_t *)position;
508 case 0: /* processor_entry */
509 case 1: /* bus_entry */
510 case 2: /* io_apic_entry */
511 case 3: /* int_entry */
512 case 4: /* int_entry */
515 kprintf("unknown base MP table entry type %d\n", type);
519 if (total_size < basetable_entry_types[type].length) {
520 kprintf("invalid base MP table length, "
521 "does not contain all entries\n");
524 total_size -= basetable_entry_types[type].length;
526 error = func(arg, position, type);
530 position = (const uint8_t *)position +
531 basetable_entry_types[type].length;
538 * Startup the SMP processors.
543 POSTCODE(MP_START_POST);
544 mp_enable(boot_address);
549 * Print various information about the SMP system hardware and setup.
556 POSTCODE(MP_ANNOUNCE_POST);
558 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
559 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
560 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
561 for (x = 1; x <= mp_naps; ++x) {
562 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
563 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
567 for (x = 0; x < mp_napics; ++x) {
568 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
569 kprintf(", version: 0x%08x", io_apic_versions[x]);
570 kprintf(", at 0x%08lx\n", io_apic_address[x]);
573 kprintf(" Warning: APIC I/O disabled\n");
578 * AP cpu's call this to sync up protected mode.
580 * WARNING! %gs is not set up on entry. This routine sets up %gs.
586 int x, myid = bootAP;
588 struct mdglobaldata *md;
589 struct privatespace *ps;
591 ps = &CPU_prvspace[myid];
593 gdt_segs[GPROC0_SEL].ssd_base =
594 (long) &ps->mdglobaldata.gd_common_tss;
595 ps->mdglobaldata.mi.gd_prvspace = ps;
597 /* We fill the 32-bit segment descriptors */
598 for (x = 0; x < NGDT; x++) {
599 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
600 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
602 /* And now a 64-bit one */
603 ssdtosyssd(&gdt_segs[GPROC0_SEL],
604 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
606 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
607 r_gdt.rd_base = (long) &gdt[myid * NGDT];
608 lgdt(&r_gdt); /* does magic intra-segment return */
610 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
611 wrmsr(MSR_FSBASE, 0); /* User value */
612 wrmsr(MSR_GSBASE, (u_int64_t)ps);
613 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
619 mdcpu->gd_currentldt = _default_ldt;
622 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
623 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
625 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
627 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
629 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
631 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
632 md->gd_common_tssd = *md->gd_tss_gdt;
634 /* double fault stack */
635 md->gd_common_tss.tss_ist1 =
636 (long)&md->mi.gd_prvspace->idlestack[
637 sizeof(md->mi.gd_prvspace->idlestack)];
642 * Set to a known state:
643 * Set by mpboot.s: CR0_PG, CR0_PE
644 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
647 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
650 /* Set up the fast syscall stuff */
651 msr = rdmsr(MSR_EFER) | EFER_SCE;
652 wrmsr(MSR_EFER, msr);
653 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
654 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
655 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
656 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
657 wrmsr(MSR_STAR, msr);
658 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
660 pmap_set_opt(); /* PSE/4MB pages, etc */
662 /* Initialize the PAT MSR. */
666 /* set up CPU registers and state */
669 /* set up SSE/NX registers */
672 /* set up FPU state on the AP */
673 npxinit(__INITIAL_NPXCW__);
675 /* disable the APIC, just to be SURE */
676 lapic->svr &= ~APIC_SVR_ENABLE;
678 /* data returned to BSP */
679 cpu_apic_versions[0] = lapic->version;
682 /*******************************************************************
683 * local functions and data
687 * start the SMP system
690 mp_enable(u_int boot_addr)
696 vm_paddr_t mpfps_paddr;
697 struct mptable_pos mpt;
699 POSTCODE(MP_ENABLE_POST);
703 mpfps_paddr = mptable_probe();
705 mptable_map(&mpt, mpfps_paddr);
712 panic("no MP table, disable APIC_IO!\n");
714 mptable_map(&mpt, mpfps_paddr);
717 * Examine the MP table for needed info
724 /* Post scan cleanup */
727 setup_apic_irq_mapping();
729 /* fill the LOGICAL io_apic_versions table */
730 for (apic = 0; apic < mp_napics; ++apic) {
731 ux = io_apic_read(apic, IOAPIC_VER);
732 io_apic_versions[apic] = ux;
733 io_apic_set_id(apic, IO_TO_ID(apic));
736 /* program each IO APIC in the system */
737 for (apic = 0; apic < mp_napics; ++apic)
738 if (io_apic_setup(apic) < 0)
739 panic("IO APIC setup failure");
744 * These are required for SMP operation
747 /* install a 'Spurious INTerrupt' vector */
748 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
749 SDT_SYSIGT, SEL_KPL, 0);
751 /* install an inter-CPU IPI for TLB invalidation */
752 setidt(XINVLTLB_OFFSET, Xinvltlb,
753 SDT_SYSIGT, SEL_KPL, 0);
755 /* install an inter-CPU IPI for IPIQ messaging */
756 setidt(XIPIQ_OFFSET, Xipiq,
757 SDT_SYSIGT, SEL_KPL, 0);
759 /* install a timer vector */
760 setidt(XTIMER_OFFSET, Xtimer,
761 SDT_SYSIGT, SEL_KPL, 0);
763 /* install an inter-CPU IPI for CPU stop/restart */
764 setidt(XCPUSTOP_OFFSET, Xcpustop,
765 SDT_SYSIGT, SEL_KPL, 0);
767 /* start each Application Processor */
768 start_all_aps(boot_addr);
773 * look for the MP spec signature
776 /* string defined by the Intel MP Spec as identifying the MP table */
777 #define MP_SIG 0x5f504d5f /* _MP_ */
778 #define NEXT(X) ((X) += 4)
780 mptable_search_sig(u_int32_t target, int count)
786 KKASSERT(target != 0);
788 map_size = count * sizeof(u_int32_t);
789 addr = pmap_mapdev((vm_paddr_t)target, map_size);
792 for (x = 0; x < count; NEXT(x)) {
793 if (addr[x] == MP_SIG) {
794 /* make array index a byte index */
795 ret = target + (x * sizeof(u_int32_t));
800 pmap_unmapdev((vm_offset_t)addr, map_size);
805 typedef struct BUSDATA {
807 enum busTypes bus_type;
810 typedef struct INTDATA {
820 typedef struct BUSTYPENAME {
827 static bus_type_name bus_type_table[] =
833 {UNKNOWN_BUSTYPE, "---"},
836 {UNKNOWN_BUSTYPE, "---"},
837 {UNKNOWN_BUSTYPE, "---"},
838 {UNKNOWN_BUSTYPE, "---"},
839 {UNKNOWN_BUSTYPE, "---"},
840 {UNKNOWN_BUSTYPE, "---"},
842 {UNKNOWN_BUSTYPE, "---"},
843 {UNKNOWN_BUSTYPE, "---"},
844 {UNKNOWN_BUSTYPE, "---"},
845 {UNKNOWN_BUSTYPE, "---"},
847 {UNKNOWN_BUSTYPE, "---"}
850 /* from MP spec v1.4, table 5-1 */
851 static int default_data[7][5] =
853 /* nbus, id0, type0, id1, type1 */
854 {1, 0, ISA, 255, 255},
855 {1, 0, EISA, 255, 255},
856 {1, 0, EISA, 255, 255},
857 {1, 0, MCA, 255, 255},
859 {2, 0, EISA, 1, PCI},
864 static bus_datum *bus_data;
866 /* the IO INT data, one entry per possible APIC INTerrupt */
867 static io_int *io_apic_ints;
872 static int processor_entry (const struct PROCENTRY *entry, int cpu);
874 static int bus_entry (const struct BUSENTRY *entry, int bus);
875 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
876 static int int_entry (const struct INTENTRY *entry, int intr);
877 static int lookup_bus_type (char *name);
883 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
885 const struct IOAPICENTRY *ioapic_ent;
888 case 1: /* bus_entry */
892 case 2: /* io_apic_entry */
894 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
895 io_apic_address[mp_napics++] =
896 (vm_offset_t)ioapic_ent->apic_address;
900 case 3: /* int_entry */
908 * 1st pass on motherboard's Intel MP specification table.
917 mptable_pass1(struct mptable_pos *mpt)
922 POSTCODE(MPTABLE_PASS1_POST);
925 KKASSERT(fps != NULL);
927 /* clear various tables */
928 for (x = 0; x < NAPICID; ++x)
929 io_apic_address[x] = ~0; /* IO APIC address table */
935 /* check for use of 'default' configuration */
936 if (fps->mpfb1 != 0) {
937 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
938 mp_nbusses = default_data[fps->mpfb1 - 1][0];
944 error = mptable_iterate_entries(mpt->mp_cth,
945 mptable_ioapic_pass1_callback, NULL);
947 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
951 struct mptable_ioapic2_cbarg {
958 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
960 struct mptable_ioapic2_cbarg *arg = xarg;
964 if (bus_entry(pos, arg->bus))
969 if (io_apic_entry(pos, arg->apic))
974 if (int_entry(pos, arg->intr))
982 * 2nd pass on motherboard's Intel MP specification table.
985 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
986 * IO_TO_ID(N), logical IO to APIC ID table
991 mptable_pass2(struct mptable_pos *mpt)
993 struct mptable_ioapic2_cbarg arg;
997 POSTCODE(MPTABLE_PASS2_POST);
1000 KKASSERT(fps != NULL);
1002 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
1003 M_DEVBUF, M_WAITOK);
1004 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
1005 M_DEVBUF, M_WAITOK | M_ZERO);
1006 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
1007 M_DEVBUF, M_WAITOK);
1008 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
1009 M_DEVBUF, M_WAITOK);
1011 for (x = 0; x < mp_napics; x++)
1012 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
1014 /* clear various tables */
1015 for (x = 0; x < NAPICID; ++x) {
1016 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1017 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1020 /* clear bus data table */
1021 for (x = 0; x < mp_nbusses; ++x)
1022 bus_data[x].bus_id = 0xff;
1024 /* clear IO APIC INT table */
1025 for (x = 0; x < (nintrs + 1); ++x) {
1026 io_apic_ints[x].int_type = 0xff;
1027 io_apic_ints[x].int_vector = 0xff;
1030 /* check for use of 'default' configuration */
1031 if (fps->mpfb1 != 0) {
1032 mptable_default(fps->mpfb1);
1036 bzero(&arg, sizeof(arg));
1037 error = mptable_iterate_entries(mpt->mp_cth,
1038 mptable_ioapic_pass2_callback, &arg);
1040 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1046 * Check if we should perform a hyperthreading "fix-up" to
1047 * enumerate any logical CPU's that aren't already listed
1050 * XXX: We assume that all of the physical CPUs in the
1051 * system have the same number of logical CPUs.
1053 * XXX: We assume that APIC ID's are allocated such that
1054 * the APIC ID's for a physical processor are aligned
1055 * with the number of logical CPU's in the processor.
1058 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1060 int i, id, lcpus_max, logical_cpus;
1062 if ((cpu_feature & CPUID_HTT) == 0)
1065 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1069 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1071 * INSTRUCTION SET REFERENCE, A-M (#253666)
1072 * Page 3-181, Table 3-20
1073 * "The nearest power-of-2 integer that is not smaller
1074 * than EBX[23:16] is the number of unique initial APIC
1075 * IDs reserved for addressing different logical
1076 * processors in a physical package."
1078 for (i = 0; ; ++i) {
1079 if ((1 << i) >= lcpus_max) {
1086 KKASSERT(cpu_count != 0);
1087 if (cpu_count == lcpus_max) {
1088 /* We have nothing to fix */
1090 } else if (cpu_count == 1) {
1091 /* XXX this may be incorrect */
1092 logical_cpus = lcpus_max;
1094 int cur, prev, dist;
1097 * Calculate the distances between two nearest
1098 * APIC IDs. If all such distances are same,
1099 * then it is the number of missing cpus that
1100 * we are going to fill later.
1102 dist = cur = prev = -1;
1103 for (id = 0; id < MAXCPU; ++id) {
1104 if ((id_mask & 1 << id) == 0)
1109 int new_dist = cur - prev;
1115 * Make sure that all distances
1116 * between two nearest APIC IDs
1119 if (dist != new_dist)
1127 /* Must be power of 2 */
1128 if (dist & (dist - 1))
1131 /* Can't exceed CPU package capacity */
1132 if (dist > lcpus_max)
1133 logical_cpus = lcpus_max;
1135 logical_cpus = dist;
1139 * For each APIC ID of a CPU that is set in the mask,
1140 * scan the other candidate APIC ID's for this
1141 * physical processor. If any of those ID's are
1142 * already in the table, then kill the fixup.
1144 for (id = 0; id < MAXCPU; id++) {
1145 if ((id_mask & 1 << id) == 0)
1147 /* First, make sure we are on a logical_cpus boundary. */
1148 if (id % logical_cpus != 0)
1150 for (i = id + 1; i < id + logical_cpus; i++)
1151 if ((id_mask & 1 << i) != 0)
1154 return logical_cpus;
1158 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1162 vm_size_t cth_mapsz = 0;
1164 bzero(mpt, sizeof(*mpt));
1166 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1167 if (fps->pap != 0) {
1169 * Map configuration table header to get
1170 * the base table size
1172 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1173 cth_mapsz = cth->base_table_length;
1174 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1176 if (cth_mapsz < sizeof(*cth)) {
1177 kprintf("invalid base MP table length %d\n",
1179 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1184 * Map the base table
1186 cth = pmap_mapdev(fps->pap, cth_mapsz);
1191 mpt->mp_cth_mapsz = cth_mapsz;
1197 mptable_unmap(struct mptable_pos *mpt)
1199 if (mpt->mp_cth != NULL) {
1200 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1202 mpt->mp_cth_mapsz = 0;
1204 if (mpt->mp_fps != NULL) {
1205 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1213 assign_apic_irq(int apic, int intpin, int irq)
1217 if (int_to_apicintpin[irq].ioapic != -1)
1218 panic("assign_apic_irq: inconsistent table");
1220 int_to_apicintpin[irq].ioapic = apic;
1221 int_to_apicintpin[irq].int_pin = intpin;
1222 int_to_apicintpin[irq].apic_address = ioapic[apic];
1223 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1225 for (x = 0; x < nintrs; x++) {
1226 if ((io_apic_ints[x].int_type == 0 ||
1227 io_apic_ints[x].int_type == 3) &&
1228 io_apic_ints[x].int_vector == 0xff &&
1229 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1230 io_apic_ints[x].dst_apic_int == intpin)
1231 io_apic_ints[x].int_vector = irq;
1236 revoke_apic_irq(int irq)
1242 if (int_to_apicintpin[irq].ioapic == -1)
1243 panic("revoke_apic_irq: inconsistent table");
1245 oldapic = int_to_apicintpin[irq].ioapic;
1246 oldintpin = int_to_apicintpin[irq].int_pin;
1248 int_to_apicintpin[irq].ioapic = -1;
1249 int_to_apicintpin[irq].int_pin = 0;
1250 int_to_apicintpin[irq].apic_address = NULL;
1251 int_to_apicintpin[irq].redirindex = 0;
1253 for (x = 0; x < nintrs; x++) {
1254 if ((io_apic_ints[x].int_type == 0 ||
1255 io_apic_ints[x].int_type == 3) &&
1256 io_apic_ints[x].int_vector != 0xff &&
1257 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1258 io_apic_ints[x].dst_apic_int == oldintpin)
1259 io_apic_ints[x].int_vector = 0xff;
1267 allocate_apic_irq(int intr)
1273 if (io_apic_ints[intr].int_vector != 0xff)
1274 return; /* Interrupt handler already assigned */
1276 if (io_apic_ints[intr].int_type != 0 &&
1277 (io_apic_ints[intr].int_type != 3 ||
1278 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1279 io_apic_ints[intr].dst_apic_int == 0)))
1280 return; /* Not INT or ExtInt on != (0, 0) */
1283 while (irq < APIC_INTMAPSIZE &&
1284 int_to_apicintpin[irq].ioapic != -1)
1287 if (irq >= APIC_INTMAPSIZE)
1288 return; /* No free interrupt handlers */
1290 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1291 intpin = io_apic_ints[intr].dst_apic_int;
1293 assign_apic_irq(apic, intpin, irq);
1298 swap_apic_id(int apic, int oldid, int newid)
1305 return; /* Nothing to do */
1307 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1308 apic, oldid, newid);
1310 /* Swap physical APIC IDs in interrupt entries */
1311 for (x = 0; x < nintrs; x++) {
1312 if (io_apic_ints[x].dst_apic_id == oldid)
1313 io_apic_ints[x].dst_apic_id = newid;
1314 else if (io_apic_ints[x].dst_apic_id == newid)
1315 io_apic_ints[x].dst_apic_id = oldid;
1318 /* Swap physical APIC IDs in IO_TO_ID mappings */
1319 for (oapic = 0; oapic < mp_napics; oapic++)
1320 if (IO_TO_ID(oapic) == newid)
1323 if (oapic < mp_napics) {
1324 kprintf("Changing APIC ID for IO APIC #%d from "
1325 "%d to %d in MP table\n",
1326 oapic, newid, oldid);
1327 IO_TO_ID(oapic) = oldid;
1329 IO_TO_ID(apic) = newid;
1334 fix_id_to_io_mapping(void)
1338 for (x = 0; x < NAPICID; x++)
1341 for (x = 0; x <= mp_naps; x++)
1342 if (CPU_TO_ID(x) < NAPICID)
1343 ID_TO_IO(CPU_TO_ID(x)) = x;
1345 for (x = 0; x < mp_napics; x++)
1346 if (IO_TO_ID(x) < NAPICID)
1347 ID_TO_IO(IO_TO_ID(x)) = x;
1352 first_free_apic_id(void)
1356 for (freeid = 0; freeid < NAPICID; freeid++) {
1357 for (x = 0; x <= mp_naps; x++)
1358 if (CPU_TO_ID(x) == freeid)
1362 for (x = 0; x < mp_napics; x++)
1363 if (IO_TO_ID(x) == freeid)
1374 io_apic_id_acceptable(int apic, int id)
1376 int cpu; /* Logical CPU number */
1377 int oapic; /* Logical IO APIC number for other IO APIC */
1380 return 0; /* Out of range */
1382 for (cpu = 0; cpu <= mp_naps; cpu++)
1383 if (CPU_TO_ID(cpu) == id)
1384 return 0; /* Conflict with CPU */
1386 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1387 if (IO_TO_ID(oapic) == id)
1388 return 0; /* Conflict with other APIC */
1390 return 1; /* ID is acceptable for IO APIC */
1395 io_apic_find_int_entry(int apic, int pin)
1399 /* search each of the possible INTerrupt sources */
1400 for (x = 0; x < nintrs; ++x) {
1401 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1402 (pin == io_apic_ints[x].dst_apic_int))
1403 return (&io_apic_ints[x]);
1409 * parse an Intel MP specification table
1416 int apic; /* IO APIC unit number */
1417 int freeid; /* Free physical APIC ID */
1418 int physid; /* Current physical IO APIC ID */
1420 int bus_0 = 0; /* Stop GCC warning */
1421 int bus_pci = 0; /* Stop GCC warning */
1425 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1426 * did it wrong. The MP spec says that when more than 1 PCI bus
1427 * exists the BIOS must begin with bus entries for the PCI bus and use
1428 * actual PCI bus numbering. This implies that when only 1 PCI bus
1429 * exists the BIOS can choose to ignore this ordering, and indeed many
1430 * MP motherboards do ignore it. This causes a problem when the PCI
1431 * sub-system makes requests of the MP sub-system based on PCI bus
1432 * numbers. So here we look for the situation and renumber the
1433 * busses and associated INTs in an effort to "make it right".
1436 /* find bus 0, PCI bus, count the number of PCI busses */
1437 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1438 if (bus_data[x].bus_id == 0) {
1441 if (bus_data[x].bus_type == PCI) {
1447 * bus_0 == slot of bus with ID of 0
1448 * bus_pci == slot of last PCI bus encountered
1451 /* check the 1 PCI bus case for sanity */
1452 /* if it is number 0 all is well */
1453 if (num_pci_bus == 1 &&
1454 bus_data[bus_pci].bus_id != 0) {
1456 /* mis-numbered, swap with whichever bus uses slot 0 */
1458 /* swap the bus entry types */
1459 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1460 bus_data[bus_0].bus_type = PCI;
1462 /* swap each relavant INTerrupt entry */
1463 id = bus_data[bus_pci].bus_id;
1464 for (x = 0; x < nintrs; ++x) {
1465 if (io_apic_ints[x].src_bus_id == id) {
1466 io_apic_ints[x].src_bus_id = 0;
1468 else if (io_apic_ints[x].src_bus_id == 0) {
1469 io_apic_ints[x].src_bus_id = id;
1474 /* Assign IO APIC IDs.
1476 * First try the existing ID. If a conflict is detected, try
1477 * the ID in the MP table. If a conflict is still detected, find
1480 * We cannot use the ID_TO_IO table before all conflicts has been
1481 * resolved and the table has been corrected.
1483 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1485 /* First try to use the value set by the BIOS */
1486 physid = io_apic_get_id(apic);
1487 if (io_apic_id_acceptable(apic, physid)) {
1488 if (IO_TO_ID(apic) != physid)
1489 swap_apic_id(apic, IO_TO_ID(apic), physid);
1493 /* Then check if the value in the MP table is acceptable */
1494 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1497 /* Last resort, find a free APIC ID and use it */
1498 freeid = first_free_apic_id();
1499 if (freeid >= NAPICID)
1500 panic("No free physical APIC IDs found");
1502 if (io_apic_id_acceptable(apic, freeid)) {
1503 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1506 panic("Free physical APIC ID not usable");
1508 fix_id_to_io_mapping();
1510 /* detect and fix broken Compaq MP table */
1511 if (apic_int_type(0, 0) == -1) {
1512 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1513 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1514 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1515 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1516 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1517 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1519 } else if (apic_int_type(0, 0) == 0) {
1520 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1521 for (x = 0; x < nintrs; ++x)
1522 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1523 (0 == io_apic_ints[x].dst_apic_int)) {
1524 io_apic_ints[x].int_type = 3;
1525 io_apic_ints[x].int_vector = 0xff;
1531 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1532 * controllers universally come in pairs. If IRQ 14 is specified
1533 * as an ISA interrupt, then IRQ 15 had better be too.
1535 * [ Shuttle XPC / AMD Athlon X2 ]
1536 * The MPTable is missing an entry for IRQ 15. Note that the
1537 * ACPI table has an entry for both 14 and 15.
1539 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1540 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1541 io14 = io_apic_find_int_entry(0, 14);
1542 io_apic_ints[nintrs] = *io14;
1543 io_apic_ints[nintrs].src_bus_irq = 15;
1544 io_apic_ints[nintrs].dst_apic_int = 15;
1549 /* Assign low level interrupt handlers */
1551 setup_apic_irq_mapping(void)
1557 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1558 int_to_apicintpin[x].ioapic = -1;
1559 int_to_apicintpin[x].int_pin = 0;
1560 int_to_apicintpin[x].apic_address = NULL;
1561 int_to_apicintpin[x].redirindex = 0;
1563 /* Default to masked */
1564 int_to_apicintpin[x].flags = AIMI_FLAG_MASKED;
1567 /* First assign ISA/EISA interrupts */
1568 for (x = 0; x < nintrs; x++) {
1569 int_vector = io_apic_ints[x].src_bus_irq;
1570 if (int_vector < APIC_INTMAPSIZE &&
1571 io_apic_ints[x].int_vector == 0xff &&
1572 int_to_apicintpin[int_vector].ioapic == -1 &&
1573 (apic_int_is_bus_type(x, ISA) ||
1574 apic_int_is_bus_type(x, EISA)) &&
1575 io_apic_ints[x].int_type == 0) {
1576 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1577 io_apic_ints[x].dst_apic_int,
1582 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1583 for (x = 0; x < nintrs; x++) {
1584 if (io_apic_ints[x].dst_apic_int == 0 &&
1585 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1586 io_apic_ints[x].int_vector == 0xff &&
1587 int_to_apicintpin[0].ioapic == -1 &&
1588 io_apic_ints[x].int_type == 3) {
1589 assign_apic_irq(0, 0, 0);
1594 /* Assign PCI interrupts */
1595 for (x = 0; x < nintrs; ++x) {
1596 if (io_apic_ints[x].int_type == 0 &&
1597 io_apic_ints[x].int_vector == 0xff &&
1598 apic_int_is_bus_type(x, PCI))
1599 allocate_apic_irq(x);
1606 mp_set_cpuids(int cpu_id, int apic_id)
1608 CPU_TO_ID(cpu_id) = apic_id;
1609 ID_TO_CPU(apic_id) = cpu_id;
1613 processor_entry(const struct PROCENTRY *entry, int cpu)
1617 /* check for usability */
1618 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1621 /* check for BSP flag */
1622 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1623 mp_set_cpuids(0, entry->apic_id);
1624 return 0; /* its already been counted */
1627 /* add another AP to list, if less than max number of CPUs */
1628 else if (cpu < MAXCPU) {
1629 mp_set_cpuids(cpu, entry->apic_id);
1639 bus_entry(const struct BUSENTRY *entry, int bus)
1644 /* encode the name into an index */
1645 for (x = 0; x < 6; ++x) {
1646 if ((c = entry->bus_type[x]) == ' ')
1652 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1653 panic("unknown bus type: '%s'", name);
1655 bus_data[bus].bus_id = entry->bus_id;
1656 bus_data[bus].bus_type = x;
1662 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1664 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1667 IO_TO_ID(apic) = entry->apic_id;
1668 ID_TO_IO(entry->apic_id) = apic;
1674 lookup_bus_type(char *name)
1678 for (x = 0; x < MAX_BUSTYPE; ++x)
1679 if (strcmp(bus_type_table[x].name, name) == 0)
1680 return bus_type_table[x].type;
1682 return UNKNOWN_BUSTYPE;
1686 int_entry(const struct INTENTRY *entry, int intr)
1690 io_apic_ints[intr].int_type = entry->int_type;
1691 io_apic_ints[intr].int_flags = entry->int_flags;
1692 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1693 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1694 if (entry->dst_apic_id == 255) {
1695 /* This signal goes to all IO APICS. Select an IO APIC
1696 with sufficient number of interrupt pins */
1697 for (apic = 0; apic < mp_napics; apic++)
1698 if (((io_apic_read(apic, IOAPIC_VER) &
1699 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1700 entry->dst_apic_int)
1702 if (apic < mp_napics)
1703 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1705 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1707 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1708 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1714 apic_int_is_bus_type(int intr, int bus_type)
1718 for (bus = 0; bus < mp_nbusses; ++bus)
1719 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1720 && ((int) bus_data[bus].bus_type == bus_type))
1727 * Given a traditional ISA INT mask, return an APIC mask.
1730 isa_apic_mask(u_int isa_mask)
1735 #if defined(SKIP_IRQ15_REDIRECT)
1736 if (isa_mask == (1 << 15)) {
1737 kprintf("skipping ISA IRQ15 redirect\n");
1740 #endif /* SKIP_IRQ15_REDIRECT */
1742 isa_irq = ffs(isa_mask); /* find its bit position */
1743 if (isa_irq == 0) /* doesn't exist */
1745 --isa_irq; /* make it zero based */
1747 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1751 return (1 << apic_pin); /* convert pin# to a mask */
1755 * Determine which APIC pin an ISA/EISA INT is attached to.
1757 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1758 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1759 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1760 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1762 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1764 isa_apic_irq(int isa_irq)
1768 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1769 if (INTTYPE(intr) == 0) { /* standard INT */
1770 if (SRCBUSIRQ(intr) == isa_irq) {
1771 if (apic_int_is_bus_type(intr, ISA) ||
1772 apic_int_is_bus_type(intr, EISA)) {
1773 if (INTIRQ(intr) == 0xff)
1774 return -1; /* unassigned */
1775 return INTIRQ(intr); /* found */
1780 return -1; /* NOT found */
1785 * Determine which APIC pin a PCI INT is attached to.
1787 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1788 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1789 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1791 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1795 --pciInt; /* zero based */
1797 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1798 if ((INTTYPE(intr) == 0) /* standard INT */
1799 && (SRCBUSID(intr) == pciBus)
1800 && (SRCBUSDEVICE(intr) == pciDevice)
1801 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1802 if (apic_int_is_bus_type(intr, PCI)) {
1803 if (INTIRQ(intr) == 0xff) {
1804 kprintf("IOAPIC: pci_apic_irq() "
1806 return -1; /* unassigned */
1808 return INTIRQ(intr); /* exact match */
1813 return -1; /* NOT found */
1817 next_apic_irq(int irq)
1824 for (intr = 0; intr < nintrs; intr++) {
1825 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1827 bus = SRCBUSID(intr);
1828 bustype = apic_bus_type(bus);
1829 if (bustype != ISA &&
1835 if (intr >= nintrs) {
1838 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1839 if (INTTYPE(ointr) != 0)
1841 if (bus != SRCBUSID(ointr))
1843 if (bustype == PCI) {
1844 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1846 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1849 if (bustype == ISA || bustype == EISA) {
1850 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1853 if (INTPIN(intr) == INTPIN(ointr))
1857 if (ointr >= nintrs) {
1860 return INTIRQ(ointr);
1875 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1878 * Exactly what this means is unclear at this point. It is a solution
1879 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1880 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1881 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1885 undirect_isa_irq(int rirq)
1889 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1890 /** FIXME: tickle the MB redirector chip */
1894 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1901 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1904 undirect_pci_irq(int rirq)
1908 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1910 /** FIXME: tickle the MB redirector chip */
1914 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1924 * given a bus ID, return:
1925 * the bus type if found
1929 apic_bus_type(int id)
1933 for (x = 0; x < mp_nbusses; ++x)
1934 if (bus_data[x].bus_id == id)
1935 return bus_data[x].bus_type;
1941 * given a LOGICAL APIC# and pin#, return:
1942 * the associated src bus ID if found
1946 apic_src_bus_id(int apic, int pin)
1950 /* search each of the possible INTerrupt sources */
1951 for (x = 0; x < nintrs; ++x)
1952 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1953 (pin == io_apic_ints[x].dst_apic_int))
1954 return (io_apic_ints[x].src_bus_id);
1956 return -1; /* NOT found */
1960 * given a LOGICAL APIC# and pin#, return:
1961 * the associated src bus IRQ if found
1965 apic_src_bus_irq(int apic, int pin)
1969 for (x = 0; x < nintrs; x++)
1970 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1971 (pin == io_apic_ints[x].dst_apic_int))
1972 return (io_apic_ints[x].src_bus_irq);
1974 return -1; /* NOT found */
1979 * given a LOGICAL APIC# and pin#, return:
1980 * the associated INTerrupt type if found
1984 apic_int_type(int apic, int pin)
1988 /* search each of the possible INTerrupt sources */
1989 for (x = 0; x < nintrs; ++x) {
1990 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1991 (pin == io_apic_ints[x].dst_apic_int))
1992 return (io_apic_ints[x].int_type);
1994 return -1; /* NOT found */
1998 * Return the IRQ associated with an APIC pin
2001 apic_irq(int apic, int pin)
2006 for (x = 0; x < nintrs; ++x) {
2007 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2008 (pin == io_apic_ints[x].dst_apic_int)) {
2009 res = io_apic_ints[x].int_vector;
2012 if (apic != int_to_apicintpin[res].ioapic)
2013 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2014 if (pin != int_to_apicintpin[res].int_pin)
2015 panic("apic_irq inconsistent table (2)");
2024 * given a LOGICAL APIC# and pin#, return:
2025 * the associated trigger mode if found
2029 apic_trigger(int apic, int pin)
2033 /* search each of the possible INTerrupt sources */
2034 for (x = 0; x < nintrs; ++x)
2035 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2036 (pin == io_apic_ints[x].dst_apic_int))
2037 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2039 return -1; /* NOT found */
2044 * given a LOGICAL APIC# and pin#, return:
2045 * the associated 'active' level if found
2049 apic_polarity(int apic, int pin)
2053 /* search each of the possible INTerrupt sources */
2054 for (x = 0; x < nintrs; ++x)
2055 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2056 (pin == io_apic_ints[x].dst_apic_int))
2057 return (io_apic_ints[x].int_flags & 0x03);
2059 return -1; /* NOT found */
2063 * set data according to MP defaults
2064 * FIXME: probably not complete yet...
2067 mptable_default(int type)
2073 kprintf(" MP default config type: %d\n", type);
2076 kprintf(" bus: ISA, APIC: 82489DX\n");
2079 kprintf(" bus: EISA, APIC: 82489DX\n");
2082 kprintf(" bus: EISA, APIC: 82489DX\n");
2085 kprintf(" bus: MCA, APIC: 82489DX\n");
2088 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2091 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2094 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2097 kprintf(" future type\n");
2103 /* one and only IO APIC */
2104 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2107 * sanity check, refer to MP spec section 3.6.6, last paragraph
2108 * necessary as some hardware isn't properly setting up the IO APIC
2110 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2111 if (io_apic_id != 2) {
2113 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2114 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2115 io_apic_set_id(0, 2);
2118 IO_TO_ID(0) = io_apic_id;
2119 ID_TO_IO(io_apic_id) = 0;
2121 /* fill out bus entries */
2130 bus_data[0].bus_id = default_data[type - 1][1];
2131 bus_data[0].bus_type = default_data[type - 1][2];
2132 bus_data[1].bus_id = default_data[type - 1][3];
2133 bus_data[1].bus_type = default_data[type - 1][4];
2136 /* case 4: case 7: MCA NOT supported */
2137 default: /* illegal/reserved */
2138 panic("BAD default MP config: %d", type);
2142 /* general cases from MP v1.4, table 5-2 */
2143 for (pin = 0; pin < 16; ++pin) {
2144 io_apic_ints[pin].int_type = 0;
2145 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2146 io_apic_ints[pin].src_bus_id = 0;
2147 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2148 io_apic_ints[pin].dst_apic_id = io_apic_id;
2149 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2152 /* special cases from MP v1.4, table 5-2 */
2154 io_apic_ints[2].int_type = 0xff; /* N/C */
2155 io_apic_ints[13].int_type = 0xff; /* N/C */
2156 #if !defined(APIC_MIXED_MODE)
2158 panic("sorry, can't support type 2 default yet");
2159 #endif /* APIC_MIXED_MODE */
2162 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2165 io_apic_ints[0].int_type = 0xff; /* N/C */
2167 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2170 #endif /* APIC_IO */
2173 * Map a physical memory address representing I/O into KVA. The I/O
2174 * block is assumed not to cross a page boundary.
2177 permanent_io_mapping(vm_paddr_t pa)
2179 KKASSERT(pa < 0x100000000LL);
2181 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2185 * start each AP in our list
2188 start_all_aps(u_int boot_addr)
2190 vm_offset_t va = boot_address + KERNBASE;
2191 u_int64_t *pt4, *pt3, *pt2;
2197 u_char mpbiosreason;
2198 u_long mpbioswarmvec;
2199 struct mdglobaldata *gd;
2200 struct privatespace *ps;
2202 POSTCODE(START_ALL_APS_POST);
2204 /* Initialize BSP's local APIC */
2205 apic_initialize(TRUE);
2207 /* install the AP 1st level boot code */
2208 pmap_kenter(va, boot_address);
2209 cpu_invlpg((void *)va); /* JG XXX */
2210 bcopy(mptramp_start, (void *)va, bootMP_size);
2212 /* Locate the page tables, they'll be below the trampoline */
2213 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2214 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2215 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2217 /* Create the initial 1GB replicated page tables */
2218 for (i = 0; i < 512; i++) {
2219 /* Each slot of the level 4 pages points to the same level 3 page */
2220 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2221 pt4[i] |= PG_V | PG_RW | PG_U;
2223 /* Each slot of the level 3 pages points to the same level 2 page */
2224 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2225 pt3[i] |= PG_V | PG_RW | PG_U;
2227 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2228 pt2[i] = i * (2 * 1024 * 1024);
2229 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2232 /* save the current value of the warm-start vector */
2233 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2234 outb(CMOS_REG, BIOS_RESET);
2235 mpbiosreason = inb(CMOS_DATA);
2237 /* setup a vector to our boot code */
2238 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2239 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2240 outb(CMOS_REG, BIOS_RESET);
2241 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2244 * If we have a TSC we can figure out the SMI interrupt rate.
2245 * The SMI does not necessarily use a constant rate. Spend
2246 * up to 250ms trying to figure it out.
2249 if (cpu_feature & CPUID_TSC) {
2250 set_apic_timer(275000);
2251 smilast = read_apic_timer();
2252 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2253 smicount = smitest();
2254 if (smibest == 0 || smilast - smicount < smibest)
2255 smibest = smilast - smicount;
2258 if (smibest > 250000)
2261 smibest = smibest * (int64_t)1000000 /
2262 get_apic_timer_frequency();
2266 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2267 1000000 / smibest, smibest);
2270 for (x = 1; x <= mp_naps; ++x) {
2272 /* This is a bit verbose, it will go away soon. */
2274 /* first page of AP's private space */
2275 pg = x * x86_64_btop(sizeof(struct privatespace));
2277 /* allocate new private data page(s) */
2278 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2279 MDGLOBALDATA_BASEALLOC_SIZE);
2281 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2282 bzero(gd, sizeof(*gd));
2283 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2285 /* prime data page for it to use */
2286 mi_gdinit(&gd->mi, x);
2288 gd->gd_CMAP1 = &SMPpt[pg + 0];
2289 gd->gd_CMAP2 = &SMPpt[pg + 1];
2290 gd->gd_CMAP3 = &SMPpt[pg + 2];
2291 gd->gd_PMAP1 = &SMPpt[pg + 3];
2292 gd->gd_CADDR1 = ps->CPAGE1;
2293 gd->gd_CADDR2 = ps->CPAGE2;
2294 gd->gd_CADDR3 = ps->CPAGE3;
2295 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2296 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2297 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2299 /* setup a vector to our boot code */
2300 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2301 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2302 outb(CMOS_REG, BIOS_RESET);
2303 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2306 * Setup the AP boot stack
2308 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2311 /* attempt to start the Application Processor */
2312 CHECK_INIT(99); /* setup checkpoints */
2313 if (!start_ap(gd, boot_addr, smibest)) {
2314 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2315 CHECK_PRINT("trace"); /* show checkpoints */
2316 /* better panic as the AP may be running loose */
2317 kprintf("panic y/n? [y] ");
2318 if (cngetc() != 'n')
2321 CHECK_PRINT("trace"); /* show checkpoints */
2323 /* record its version info */
2324 cpu_apic_versions[x] = cpu_apic_versions[0];
2327 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2330 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2331 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2334 ncpus2_shift = shift;
2335 ncpus2 = 1 << shift;
2336 ncpus2_mask = ncpus2 - 1;
2338 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2339 if ((1 << shift) < ncpus)
2341 ncpus_fit = 1 << shift;
2342 ncpus_fit_mask = ncpus_fit - 1;
2344 /* build our map of 'other' CPUs */
2345 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2346 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2347 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2349 /* fill in our (BSP) APIC version */
2350 cpu_apic_versions[0] = lapic->version;
2352 /* restore the warmstart vector */
2353 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2354 outb(CMOS_REG, BIOS_RESET);
2355 outb(CMOS_DATA, mpbiosreason);
2358 * NOTE! The idlestack for the BSP was setup by locore. Finish
2359 * up, clean out the P==V mapping we did earlier.
2363 /* number of APs actually started */
2369 * load the 1st level AP boot code into base memory.
2372 /* targets for relocation */
2373 extern void bigJump(void);
2374 extern void bootCodeSeg(void);
2375 extern void bootDataSeg(void);
2376 extern void MPentry(void);
2377 extern u_int MP_GDT;
2378 extern u_int mp_gdtbase;
2383 install_ap_tramp(u_int boot_addr)
2386 int size = *(int *) ((u_long) & bootMP_size);
2387 u_char *src = (u_char *) ((u_long) bootMP);
2388 u_char *dst = (u_char *) boot_addr + KERNBASE;
2389 u_int boot_base = (u_int) bootMP;
2394 POSTCODE(INSTALL_AP_TRAMP_POST);
2396 for (x = 0; x < size; ++x)
2400 * modify addresses in code we just moved to basemem. unfortunately we
2401 * need fairly detailed info about mpboot.s for this to work. changes
2402 * to mpboot.s might require changes here.
2405 /* boot code is located in KERNEL space */
2406 dst = (u_char *) boot_addr + KERNBASE;
2408 /* modify the lgdt arg */
2409 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2410 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2412 /* modify the ljmp target for MPentry() */
2413 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2414 *dst32 = ((u_int) MPentry - KERNBASE);
2416 /* modify the target for boot code segment */
2417 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2418 dst8 = (u_int8_t *) (dst16 + 1);
2419 *dst16 = (u_int) boot_addr & 0xffff;
2420 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2422 /* modify the target for boot data segment */
2423 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2424 dst8 = (u_int8_t *) (dst16 + 1);
2425 *dst16 = (u_int) boot_addr & 0xffff;
2426 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2432 * This function starts the AP (application processor) identified
2433 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2434 * to accomplish this. This is necessary because of the nuances
2435 * of the different hardware we might encounter. It ain't pretty,
2436 * but it seems to work.
2438 * NOTE: eventually an AP gets to ap_init(), which is called just
2439 * before the AP goes into the LWKT scheduler's idle loop.
2442 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2446 u_long icr_lo, icr_hi;
2448 POSTCODE(START_AP_POST);
2450 /* get the PHYSICAL APIC ID# */
2451 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2453 /* calculate the vector */
2454 vector = (boot_addr >> 12) & 0xff;
2456 /* We don't want anything interfering */
2459 /* Make sure the target cpu sees everything */
2463 * Try to detect when a SMI has occurred, wait up to 200ms.
2465 * If a SMI occurs during an AP reset but before we issue
2466 * the STARTUP command, the AP may brick. To work around
2467 * this problem we hold off doing the AP startup until
2468 * after we have detected the SMI. Hopefully another SMI
2469 * will not occur before we finish the AP startup.
2471 * Retries don't seem to help. SMIs have a window of opportunity
2472 * and if USB->legacy keyboard emulation is enabled in the BIOS
2473 * the interrupt rate can be quite high.
2475 * NOTE: Don't worry about the L1 cache load, it might bloat
2476 * ldelta a little but ndelta will be so huge when the SMI
2477 * occurs the detection logic will still work fine.
2480 set_apic_timer(200000);
2485 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2486 * and running the target CPU. OR this INIT IPI might be latched (P5
2487 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2490 * see apic/apicreg.h for icr bit definitions.
2492 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2496 * Setup the address for the target AP. We can setup
2497 * icr_hi once and then just trigger operations with
2500 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2501 icr_hi |= (physical_cpu << 24);
2502 icr_lo = lapic->icr_lo & 0xfff00000;
2503 lapic->icr_hi = icr_hi;
2506 * Do an INIT IPI: assert RESET
2508 * Use edge triggered mode to assert INIT
2510 lapic->icr_lo = icr_lo | 0x00004500;
2511 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2515 * The spec calls for a 10ms delay but we may have to use a
2516 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2517 * interrupt. We have other loops here too and dividing by 2
2518 * doesn't seem to be enough even after subtracting 350us,
2519 * so we divide by 4.
2521 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2522 * interrupt was detected we use the full 10ms.
2526 else if (smibest < 150 * 4 + 350)
2528 else if ((smibest - 350) / 4 < 10000)
2529 u_sleep((smibest - 350) / 4);
2534 * Do an INIT IPI: deassert RESET
2536 * Use level triggered mode to deassert. It is unclear
2537 * why we need to do this.
2539 lapic->icr_lo = icr_lo | 0x00008500;
2540 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2542 u_sleep(150); /* wait 150us */
2545 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2546 * latched, (P5 bug) this 1st STARTUP would then terminate
2547 * immediately, and the previously started INIT IPI would continue. OR
2548 * the previous INIT IPI has already run. and this STARTUP IPI will
2549 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2552 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2553 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2555 u_sleep(200); /* wait ~200uS */
2558 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2559 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2560 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2561 * recognized after hardware RESET or INIT IPI.
2563 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2564 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2567 /* Resume normal operation */
2570 /* wait for it to start, see ap_init() */
2571 set_apic_timer(5000000);/* == 5 seconds */
2572 while (read_apic_timer()) {
2573 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2574 return 1; /* return SUCCESS */
2577 return 0; /* return FAILURE */
2592 while (read_apic_timer()) {
2594 for (count = 0; count < 100; ++count)
2595 ntsc = rdtsc(); /* force loop to occur */
2597 ndelta = ntsc - ltsc;
2598 if (ldelta > ndelta)
2600 if (ndelta > ldelta * 2)
2603 ldelta = ntsc - ltsc;
2606 return(read_apic_timer());
2610 * Synchronously flush the TLB on all other CPU's. The current cpu's
2611 * TLB is not flushed. If the caller wishes to flush the current cpu's
2612 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
2614 * NOTE: If for some reason we were unable to start all cpus we cannot
2615 * safely use broadcast IPIs.
2618 static cpumask_t smp_invltlb_req;
2620 #define SMP_INVLTLB_DEBUG
2626 struct mdglobaldata *md = mdcpu;
2627 #ifdef SMP_INVLTLB_DEBUG
2632 crit_enter_gd(&md->mi);
2633 md->gd_invltlb_ret = 0;
2634 ++md->mi.gd_cnt.v_smpinvltlb;
2635 atomic_set_int(&smp_invltlb_req, md->mi.gd_cpumask);
2636 #ifdef SMP_INVLTLB_DEBUG
2639 if (smp_startup_mask == smp_active_mask) {
2640 all_but_self_ipi(XINVLTLB_OFFSET);
2642 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2643 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2646 #ifdef SMP_INVLTLB_DEBUG
2648 kprintf("smp_invltlb: ipi sent\n");
2650 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2651 (smp_active_mask & ~md->mi.gd_cpumask)) {
2654 #ifdef SMP_INVLTLB_DEBUG
2656 if (++count == 400000000) {
2657 print_backtrace(-1);
2658 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2659 "rflags %016jx retry",
2660 (long)md->gd_invltlb_ret,
2661 (long)smp_invltlb_req,
2662 (intmax_t)read_rflags());
2663 __asm __volatile ("sti");
2666 lwkt_process_ipiq();
2668 int bcpu = bsfl(~md->gd_invltlb_ret & ~md->mi.gd_cpumask & smp_active_mask);
2671 kprintf("bcpu %d\n", bcpu);
2672 xgd = globaldata_find(bcpu);
2673 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2676 Debugger("giving up");
2682 atomic_clear_int(&smp_invltlb_req, md->mi.gd_cpumask);
2683 crit_exit_gd(&md->mi);
2690 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2691 * bother to bump the critical section count or nested interrupt count
2692 * so only do very low level operations here.
2695 smp_invltlb_intr(void)
2697 struct mdglobaldata *md = mdcpu;
2698 struct mdglobaldata *omd;
2703 mask = smp_invltlb_req;
2707 mask &= ~(1 << cpu);
2708 omd = (struct mdglobaldata *)globaldata_find(cpu);
2709 atomic_set_int(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2716 * When called the executing CPU will send an IPI to all other CPUs
2717 * requesting that they halt execution.
2719 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2721 * - Signals all CPUs in map to stop.
2722 * - Waits for each to stop.
2729 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2730 * from executing at same time.
2733 stop_cpus(u_int map)
2735 map &= smp_active_mask;
2737 /* send the Xcpustop IPI to all CPUs in map */
2738 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2740 while ((stopped_cpus & map) != map)
2748 * Called by a CPU to restart stopped CPUs.
2750 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2752 * - Signals all CPUs in map to restart.
2753 * - Waits for each to restart.
2761 restart_cpus(u_int map)
2763 /* signal other cpus to restart */
2764 started_cpus = map & smp_active_mask;
2766 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2773 * This is called once the mpboot code has gotten us properly relocated
2774 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2775 * and when it returns the scheduler will call the real cpu_idle() main
2776 * loop for the idlethread. Interrupts are disabled on entry and should
2777 * remain disabled at return.
2785 * Adjust smp_startup_mask to signal the BSP that we have started
2786 * up successfully. Note that we do not yet hold the BGL. The BSP
2787 * is waiting for our signal.
2789 * We can't set our bit in smp_active_mask yet because we are holding
2790 * interrupts physically disabled and remote cpus could deadlock
2791 * trying to send us an IPI.
2793 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2797 * Interlock for finalization. Wait until mp_finish is non-zero,
2798 * then get the MP lock.
2800 * Note: We are in a critical section.
2802 * Note: We have to synchronize td_mpcount to our desired MP state
2803 * before calling cpu_try_mplock().
2805 * Note: we are the idle thread, we can only spin.
2807 * Note: The load fence is memory volatile and prevents the compiler
2808 * from improperly caching mp_finish, and the cpu from improperly
2811 while (mp_finish == 0)
2813 ++curthread->td_mpcount;
2814 while (cpu_try_mplock() == 0)
2817 if (cpu_feature & CPUID_TSC) {
2819 * The BSP is constantly updating tsc0_offset, figure out the
2820 * relative difference to synchronize ktrdump.
2822 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2825 /* BSP may have changed PTD while we're waiting for the lock */
2828 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2832 /* Build our map of 'other' CPUs. */
2833 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2835 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2837 /* A quick check from sanity claus */
2838 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2839 if (mycpu->gd_cpuid != apic_id) {
2840 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2841 kprintf("SMP: apic_id = %d\n", apic_id);
2843 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2845 panic("cpuid mismatch! boom!!");
2848 /* Initialize AP's local APIC for irq's */
2849 apic_initialize(FALSE);
2851 /* Set memory range attributes for this CPU to match the BSP */
2852 mem_range_AP_init();
2855 * Once we go active we must process any IPIQ messages that may
2856 * have been queued, because no actual IPI will occur until we
2857 * set our bit in the smp_active_mask. If we don't the IPI
2858 * message interlock could be left set which would also prevent
2861 * The idle loop doesn't expect the BGL to be held and while
2862 * lwkt_switch() normally cleans things up this is a special case
2863 * because we returning almost directly into the idle loop.
2865 * The idle thread is never placed on the runq, make sure
2866 * nothing we've done put it there.
2868 KKASSERT(curthread->td_mpcount == 1);
2869 smp_active_mask |= 1 << mycpu->gd_cpuid;
2872 * Enable interrupts here. idle_restore will also do it, but
2873 * doing it here lets us clean up any strays that got posted to
2874 * the CPU during the AP boot while we are still in a critical
2877 __asm __volatile("sti; pause; pause"::);
2878 mdcpu->gd_fpending = 0;
2880 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2881 lwkt_process_ipiq();
2884 * Releasing the mp lock lets the BSP finish up the SMP init
2887 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2891 * Get SMP fully working before we start initializing devices.
2899 kprintf("Finish MP startup\n");
2900 if (cpu_feature & CPUID_TSC)
2901 tsc0_offset = rdtsc();
2904 while (smp_active_mask != smp_startup_mask) {
2906 if (cpu_feature & CPUID_TSC)
2907 tsc0_offset = rdtsc();
2909 while (try_mplock() == 0)
2912 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2915 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2918 cpu_send_ipiq(int dcpu)
2920 if ((1 << dcpu) & smp_active_mask)
2921 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2924 #if 0 /* single_apic_ipi_passive() not working yet */
2926 * Returns 0 on failure, 1 on success
2929 cpu_send_ipiq_passive(int dcpu)
2932 if ((1 << dcpu) & smp_active_mask) {
2933 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2934 APIC_DELMODE_FIXED);
2940 struct mptable_lapic_cbarg1 {
2943 u_int ht_apicid_mask;
2947 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2949 const struct PROCENTRY *ent;
2950 struct mptable_lapic_cbarg1 *arg = xarg;
2956 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2960 if (ent->apic_id < 32) {
2961 arg->ht_apicid_mask |= 1 << ent->apic_id;
2962 } else if (arg->ht_fixup) {
2963 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2969 struct mptable_lapic_cbarg2 {
2976 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2978 const struct PROCENTRY *ent;
2979 struct mptable_lapic_cbarg2 *arg = xarg;
2985 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2986 KKASSERT(!arg->found_bsp);
2990 if (processor_entry(ent, arg->cpu))
2993 if (arg->logical_cpus) {
2994 struct PROCENTRY proc;
2998 * Create fake mptable processor entries
2999 * and feed them to processor_entry() to
3000 * enumerate the logical CPUs.
3002 bzero(&proc, sizeof(proc));
3004 proc.cpu_flags = PROCENTRY_FLAG_EN;
3005 proc.apic_id = ent->apic_id;
3007 for (i = 1; i < arg->logical_cpus; i++) {
3009 processor_entry(&proc, arg->cpu);
3017 mptable_imcr(struct mptable_pos *mpt)
3019 /* record whether PIC or virtual-wire mode */
3020 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
3021 mpt->mp_fps->mpfb2 & 0x80);
3024 struct mptable_lapic_enumerator {
3025 struct lapic_enumerator enumerator;
3026 vm_paddr_t mpfps_paddr;
3030 mptable_lapic_default(void)
3032 int ap_apicid, bsp_apicid;
3034 mp_naps = 1; /* exclude BSP */
3036 /* Map local apic before the id field is accessed */
3037 lapic_init(DEFAULT_APIC_BASE);
3039 bsp_apicid = APIC_ID(lapic->id);
3040 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3043 mp_set_cpuids(0, bsp_apicid);
3044 /* one and only AP */
3045 mp_set_cpuids(1, ap_apicid);
3051 * ID_TO_CPU(N), APIC ID to logical CPU table
3052 * CPU_TO_ID(N), logical CPU to APIC ID table
3055 mptable_lapic_enumerate(struct lapic_enumerator *e)
3057 struct mptable_pos mpt;
3058 struct mptable_lapic_cbarg1 arg1;
3059 struct mptable_lapic_cbarg2 arg2;
3061 int error, logical_cpus = 0;
3062 vm_offset_t lapic_addr;
3063 vm_paddr_t mpfps_paddr;
3065 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
3066 KKASSERT(mpfps_paddr != 0);
3068 error = mptable_map(&mpt, mpfps_paddr);
3070 panic("mptable_lapic_enumerate mptable_map failed\n");
3072 KKASSERT(mpt.mp_fps != NULL);
3075 * Check for use of 'default' configuration
3077 if (mpt.mp_fps->mpfb1 != 0) {
3078 mptable_lapic_default();
3079 mptable_unmap(&mpt);
3084 KKASSERT(cth != NULL);
3086 /* Save local apic address */
3087 lapic_addr = (vm_offset_t)cth->apic_address;
3088 KKASSERT(lapic_addr != 0);
3091 * Find out how many CPUs do we have
3093 bzero(&arg1, sizeof(arg1));
3094 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3096 error = mptable_iterate_entries(cth,
3097 mptable_lapic_pass1_callback, &arg1);
3099 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3100 KKASSERT(arg1.cpu_count != 0);
3102 /* See if we need to fixup HT logical CPUs. */
3103 if (arg1.ht_fixup) {
3104 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3106 if (logical_cpus != 0)
3107 arg1.cpu_count *= logical_cpus;
3109 mp_naps = arg1.cpu_count;
3111 /* Qualify the numbers again, after possible HT fixup */
3112 if (mp_naps > MAXCPU) {
3113 kprintf("Warning: only using %d of %d available CPUs!\n",
3118 --mp_naps; /* subtract the BSP */
3121 * Link logical CPU id to local apic id
3123 bzero(&arg2, sizeof(arg2));
3125 arg2.logical_cpus = logical_cpus;
3127 error = mptable_iterate_entries(cth,
3128 mptable_lapic_pass2_callback, &arg2);
3130 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3131 KKASSERT(arg2.found_bsp);
3133 /* Map local apic */
3134 lapic_init(lapic_addr);
3136 mptable_unmap(&mpt);
3140 mptable_lapic_probe(struct lapic_enumerator *e)
3142 vm_paddr_t mpfps_paddr;
3144 mpfps_paddr = mptable_probe();
3145 if (mpfps_paddr == 0)
3148 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3152 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3154 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3155 .lapic_probe = mptable_lapic_probe,
3156 .lapic_enumerate = mptable_lapic_enumerate
3161 mptable_apic_register(void)
3163 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
3165 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);