2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
164 vm_size_t mp_cth_mapsz;
167 typedef int (*mptable_iter_func)(void *, const void *, int);
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
175 #if defined(CHECK_POINTS)
176 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
179 #define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
187 #define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
197 #else /* CHECK_POINTS */
199 #define CHECK_INIT(D)
200 #define CHECK_PRINT(S)
202 #endif /* CHECK_POINTS */
205 * Values to send to the POST hardware.
207 #define MP_BOOTADDRESS_POST 0x10
208 #define MP_PROBE_POST 0x11
209 #define MPTABLE_PASS1_POST 0x12
211 #define MP_START_POST 0x13
212 #define MP_ENABLE_POST 0x14
213 #define MPTABLE_PASS2_POST 0x15
215 #define START_ALL_APS_POST 0x16
216 #define INSTALL_AP_TRAMP_POST 0x17
217 #define START_AP_POST 0x18
219 #define MP_ANNOUNCE_POST 0x19
221 static int madt_probe_test;
222 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
224 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
225 int current_postcode;
227 /** XXX FIXME: what system files declare these??? */
228 extern struct region_descriptor r_gdt, r_idt;
230 int mp_naps; /* # of Applications processors */
232 static int mp_nbusses; /* # of busses */
233 int mp_napics; /* # of IO APICs */
236 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
237 u_int32_t *io_apic_versions;
241 u_int32_t cpu_apic_versions[MAXCPU];
243 extern int64_t tsc_offsets[];
245 extern u_long ebda_addr;
248 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
252 * APIC ID logical/physical mapping structures.
253 * We oversize these to simplify boot-time config.
255 int cpu_num_to_apic_id[NAPICID];
257 int io_num_to_apic_id[NAPICID];
259 int apic_id_to_logical[NAPICID];
261 /* AP uses this during bootstrap. Do not staticize. */
265 /* Hotwire a 0->4MB V==P mapping */
266 extern pt_entry_t *KPTphys;
269 * SMP page table page. Setup by locore to point to a page table
270 * page from which we allocate per-cpu privatespace areas io_apics,
274 #define IO_MAPPING_START_INDEX \
275 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
277 extern pt_entry_t *SMPpt;
278 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
280 struct pcb stoppcbs[MAXCPU];
282 static basetable_entry basetable_entry_types[] =
284 {0, 20, "Processor"},
292 * Local data and functions.
295 static u_int boot_address;
296 static u_int base_memory;
297 static int mp_finish;
299 static void mp_enable(u_int boot_addr);
301 static int mptable_iterate_entries(const mpcth_t,
302 mptable_iter_func, void *);
303 static int mptable_probe(void);
304 static int mptable_search(void);
305 static int mptable_check(vm_paddr_t);
306 static int mptable_search_sig(u_int32_t target, int count);
307 static int mptable_hyperthread_fixup(u_int, int);
308 static void mptable_pass1(struct mptable_pos *);
309 static void mptable_pass2(struct mptable_pos *);
310 static void mptable_default(int type);
311 static void mptable_fix(void);
312 static int mptable_map(struct mptable_pos *, vm_paddr_t);
313 static void mptable_unmap(struct mptable_pos *);
314 static void mptable_lapic_enumerate(struct mptable_pos *);
315 static void mptable_lapic_default(void);
316 static void mptable_imcr(struct mptable_pos *);
319 static void setup_apic_irq_mapping(void);
320 static int apic_int_is_bus_type(int intr, int bus_type);
322 static int start_all_aps(u_int boot_addr);
323 static void install_ap_tramp(u_int boot_addr);
324 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
326 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
327 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
328 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
331 * Calculate usable address in base memory for AP trampoline code.
334 mp_bootaddress(u_int basemem)
336 POSTCODE(MP_BOOTADDRESS_POST);
338 base_memory = basemem;
340 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
341 if ((base_memory - boot_address) < bootMP_size)
342 boot_address -= 4096; /* not enough, lower by 4k */
353 mpfps_paddr = mptable_search();
354 if (mptable_check(mpfps_paddr))
361 * Look for an Intel MP spec table (ie, SMP capable hardware).
370 * Make sure our SMPpt[] page table is big enough to hold all the
373 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
375 POSTCODE(MP_PROBE_POST);
377 /* see if EBDA exists */
378 if (ebda_addr != 0) {
379 /* search first 1K of EBDA */
380 target = (u_int32_t)ebda_addr;
381 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
384 /* last 1K of base memory, effective 'top of base' passed in */
385 target = (u_int32_t)(base_memory - 0x400);
386 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
390 /* search the BIOS */
391 target = (u_int32_t)BIOS_BASE;
392 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
399 struct mptable_check_cbarg {
405 mptable_check_callback(void *xarg, const void *pos, int type)
407 const struct PROCENTRY *ent;
408 struct mptable_check_cbarg *arg = xarg;
414 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
418 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
419 if (arg->found_bsp) {
420 kprintf("more than one BSP in base MP table\n");
429 mptable_check(vm_paddr_t mpfps_paddr)
431 struct mptable_pos mpt;
432 struct mptable_check_cbarg arg;
436 if (mpfps_paddr == 0)
439 error = mptable_map(&mpt, mpfps_paddr);
443 if (mpt.mp_fps->mpfb1 != 0)
451 if (cth->apic_address == 0)
454 bzero(&arg, sizeof(arg));
455 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
457 if (arg.cpu_count == 0) {
458 kprintf("MP table contains no processor entries\n");
460 } else if (!arg.found_bsp) {
461 kprintf("MP table does not contains BSP entry\n");
471 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
473 int count, total_size;
474 const void *position;
476 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
477 total_size = cth->base_table_length - sizeof(struct MPCTH);
478 position = (const uint8_t *)cth + sizeof(struct MPCTH);
479 count = cth->entry_count;
484 KKASSERT(total_size >= 0);
485 if (total_size == 0) {
486 kprintf("invalid base MP table, "
487 "entry count and length mismatch\n");
491 type = *(const uint8_t *)position;
493 case 0: /* processor_entry */
494 case 1: /* bus_entry */
495 case 2: /* io_apic_entry */
496 case 3: /* int_entry */
497 case 4: /* int_entry */
500 kprintf("unknown base MP table entry type %d\n", type);
504 if (total_size < basetable_entry_types[type].length) {
505 kprintf("invalid base MP table length, "
506 "does not contain all entries\n");
509 total_size -= basetable_entry_types[type].length;
511 error = func(arg, position, type);
515 position = (const uint8_t *)position +
516 basetable_entry_types[type].length;
523 * Startup the SMP processors.
528 POSTCODE(MP_START_POST);
529 mp_enable(boot_address);
534 * Print various information about the SMP system hardware and setup.
541 POSTCODE(MP_ANNOUNCE_POST);
543 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
544 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
545 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
546 for (x = 1; x <= mp_naps; ++x) {
547 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
548 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
552 for (x = 0; x < mp_napics; ++x) {
553 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
554 kprintf(", version: 0x%08x", io_apic_versions[x]);
555 kprintf(", at 0x%08x\n", io_apic_address[x]);
558 kprintf(" Warning: APIC I/O disabled\n");
563 * AP cpu's call this to sync up protected mode.
565 * WARNING! We must ensure that the cpu is sufficiently initialized to
566 * be able to use to the FP for our optimized bzero/bcopy code before
567 * we enter more mainstream C code.
569 * WARNING! %fs is not set up on entry. This routine sets up %fs.
575 int x, myid = bootAP;
577 struct mdglobaldata *md;
578 struct privatespace *ps;
580 ps = &CPU_prvspace[myid];
582 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
583 gdt_segs[GPROC0_SEL].ssd_base =
584 (int) &ps->mdglobaldata.gd_common_tss;
585 ps->mdglobaldata.mi.gd_prvspace = ps;
587 for (x = 0; x < NGDT; x++) {
588 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
591 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
592 r_gdt.rd_base = (int) &gdt[myid * NGDT];
593 lgdt(&r_gdt); /* does magic intra-segment return */
598 mdcpu->gd_currentldt = _default_ldt;
600 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
601 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
603 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
605 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
606 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
607 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
608 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
609 md->gd_common_tssd = *md->gd_tss_gdt;
613 * Set to a known state:
614 * Set by mpboot.s: CR0_PG, CR0_PE
615 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
618 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
620 pmap_set_opt(); /* PSE/4MB pages, etc */
622 /* set up CPU registers and state */
625 /* set up FPU state on the AP */
626 npxinit(__INITIAL_NPXCW__);
628 /* set up SSE registers */
632 /*******************************************************************
633 * local functions and data
637 * start the SMP system
640 mp_enable(u_int boot_addr)
646 vm_paddr_t mpfps_paddr;
647 struct mptable_pos mpt;
649 POSTCODE(MP_ENABLE_POST);
652 * Enumerate Local APIC
657 mpfps_paddr = mptable_probe();
659 mptable_map(&mpt, mpfps_paddr);
660 mptable_lapic_enumerate(&mpt);
663 vm_paddr_t madt_paddr;
664 vm_offset_t lapic_addr;
667 madt_paddr = madt_probe();
669 panic("mp_enable: madt_probe failed\n");
671 lapic_addr = madt_pass1(madt_paddr);
673 panic("mp_enable: no local apic (madt)!\n");
675 lapic_init(lapic_addr);
677 bsp_apic_id = APIC_ID(lapic.id);
678 if (madt_pass2(madt_paddr, bsp_apic_id))
679 panic("mp_enable: madt_pass2 failed\n");
682 mpfps_paddr = mptable_probe();
684 mptable_map(&mpt, mpfps_paddr);
691 panic("no MP table, disable APIC_IO!\n");
693 mptable_map(&mpt, mpfps_paddr);
696 * Examine the MP table for needed info
703 /* Post scan cleanup */
706 setup_apic_irq_mapping();
708 /* fill the LOGICAL io_apic_versions table */
709 for (apic = 0; apic < mp_napics; ++apic) {
710 ux = io_apic_read(apic, IOAPIC_VER);
711 io_apic_versions[apic] = ux;
712 io_apic_set_id(apic, IO_TO_ID(apic));
715 /* program each IO APIC in the system */
716 for (apic = 0; apic < mp_napics; ++apic)
717 if (io_apic_setup(apic) < 0)
718 panic("IO APIC setup failure");
723 * These are required for SMP operation
726 /* install a 'Spurious INTerrupt' vector */
727 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
728 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
730 /* install an inter-CPU IPI for TLB invalidation */
731 setidt(XINVLTLB_OFFSET, Xinvltlb,
732 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
734 /* install an inter-CPU IPI for IPIQ messaging */
735 setidt(XIPIQ_OFFSET, Xipiq,
736 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
738 /* install a timer vector */
739 setidt(XTIMER_OFFSET, Xtimer,
740 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
742 /* install an inter-CPU IPI for CPU stop/restart */
743 setidt(XCPUSTOP_OFFSET, Xcpustop,
744 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
746 /* start each Application Processor */
747 start_all_aps(boot_addr);
752 * look for the MP spec signature
755 /* string defined by the Intel MP Spec as identifying the MP table */
756 #define MP_SIG 0x5f504d5f /* _MP_ */
757 #define NEXT(X) ((X) += 4)
759 mptable_search_sig(u_int32_t target, int count)
765 KKASSERT(target != 0);
767 map_size = count * sizeof(u_int32_t);
768 addr = pmap_mapdev((vm_paddr_t)target, map_size);
771 for (x = 0; x < count; NEXT(x)) {
772 if (addr[x] == MP_SIG) {
773 /* make array index a byte index */
774 ret = target + (x * sizeof(u_int32_t));
779 pmap_unmapdev((vm_offset_t)addr, map_size);
784 typedef struct BUSDATA {
786 enum busTypes bus_type;
789 typedef struct INTDATA {
799 typedef struct BUSTYPENAME {
804 static bus_type_name bus_type_table[] =
810 {UNKNOWN_BUSTYPE, "---"},
813 {UNKNOWN_BUSTYPE, "---"},
814 {UNKNOWN_BUSTYPE, "---"},
815 {UNKNOWN_BUSTYPE, "---"},
816 {UNKNOWN_BUSTYPE, "---"},
817 {UNKNOWN_BUSTYPE, "---"},
819 {UNKNOWN_BUSTYPE, "---"},
820 {UNKNOWN_BUSTYPE, "---"},
821 {UNKNOWN_BUSTYPE, "---"},
822 {UNKNOWN_BUSTYPE, "---"},
824 {UNKNOWN_BUSTYPE, "---"}
826 /* from MP spec v1.4, table 5-1 */
827 static int default_data[7][5] =
829 /* nbus, id0, type0, id1, type1 */
830 {1, 0, ISA, 255, 255},
831 {1, 0, EISA, 255, 255},
832 {1, 0, EISA, 255, 255},
833 {1, 0, MCA, 255, 255},
835 {2, 0, EISA, 1, PCI},
843 static bus_datum *bus_data;
845 /* the IO INT data, one entry per possible APIC INTerrupt */
846 static io_int *io_apic_ints;
851 static int processor_entry (const struct PROCENTRY *entry, int cpu);
853 static int bus_entry (const struct BUSENTRY *entry, int bus);
854 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
855 static int int_entry (const struct INTENTRY *entry, int intr);
857 static int lookup_bus_type (char *name);
862 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
864 const struct IOAPICENTRY *ioapic_ent;
867 case 1: /* bus_entry */
871 case 2: /* io_apic_entry */
873 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
874 io_apic_address[mp_napics++] =
875 (vm_offset_t)ioapic_ent->apic_address;
879 case 3: /* int_entry */
889 * 1st pass on motherboard's Intel MP specification table.
898 mptable_pass1(struct mptable_pos *mpt)
904 POSTCODE(MPTABLE_PASS1_POST);
907 KKASSERT(fps != NULL);
909 /* clear various tables */
910 for (x = 0; x < NAPICID; ++x)
911 io_apic_address[x] = ~0; /* IO APIC address table */
917 /* check for use of 'default' configuration */
918 if (fps->mpfb1 != 0) {
919 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
920 mp_nbusses = default_data[fps->mpfb1 - 1][0];
926 error = mptable_iterate_entries(mpt->mp_cth,
927 mptable_ioapic_pass1_callback, NULL);
929 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
936 struct mptable_ioapic2_cbarg {
943 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
945 struct mptable_ioapic2_cbarg *arg = xarg;
949 if (bus_entry(pos, arg->bus))
954 if (io_apic_entry(pos, arg->apic))
959 if (int_entry(pos, arg->intr))
969 * 2nd pass on motherboard's Intel MP specification table.
972 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
973 * IO_TO_ID(N), logical IO to APIC ID table
978 mptable_pass2(struct mptable_pos *mpt)
981 struct mptable_ioapic2_cbarg arg;
985 POSTCODE(MPTABLE_PASS2_POST);
988 KKASSERT(fps != NULL);
990 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
992 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
993 M_DEVBUF, M_WAITOK | M_ZERO);
994 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
996 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
999 for (x = 0; x < mp_napics; x++)
1000 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
1002 /* clear various tables */
1003 for (x = 0; x < NAPICID; ++x) {
1004 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1005 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1008 /* clear bus data table */
1009 for (x = 0; x < mp_nbusses; ++x)
1010 bus_data[x].bus_id = 0xff;
1012 /* clear IO APIC INT table */
1013 for (x = 0; x < (nintrs + 1); ++x) {
1014 io_apic_ints[x].int_type = 0xff;
1015 io_apic_ints[x].int_vector = 0xff;
1018 /* check for use of 'default' configuration */
1019 if (fps->mpfb1 != 0) {
1020 mptable_default(fps->mpfb1);
1024 bzero(&arg, sizeof(arg));
1025 error = mptable_iterate_entries(mpt->mp_cth,
1026 mptable_ioapic_pass2_callback, &arg);
1028 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1033 * Check if we should perform a hyperthreading "fix-up" to
1034 * enumerate any logical CPU's that aren't already listed
1037 * XXX: We assume that all of the physical CPUs in the
1038 * system have the same number of logical CPUs.
1040 * XXX: We assume that APIC ID's are allocated such that
1041 * the APIC ID's for a physical processor are aligned
1042 * with the number of logical CPU's in the processor.
1045 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1047 int i, id, lcpus_max, logical_cpus;
1049 if ((cpu_feature & CPUID_HTT) == 0)
1052 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1056 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1058 * INSTRUCTION SET REFERENCE, A-M (#253666)
1059 * Page 3-181, Table 3-20
1060 * "The nearest power-of-2 integer that is not smaller
1061 * than EBX[23:16] is the number of unique initial APIC
1062 * IDs reserved for addressing different logical
1063 * processors in a physical package."
1065 for (i = 0; ; ++i) {
1066 if ((1 << i) >= lcpus_max) {
1073 KKASSERT(cpu_count != 0);
1074 if (cpu_count == lcpus_max) {
1075 /* We have nothing to fix */
1077 } else if (cpu_count == 1) {
1078 /* XXX this may be incorrect */
1079 logical_cpus = lcpus_max;
1081 int cur, prev, dist;
1084 * Calculate the distances between two nearest
1085 * APIC IDs. If all such distances are same,
1086 * then it is the number of missing cpus that
1087 * we are going to fill later.
1089 dist = cur = prev = -1;
1090 for (id = 0; id < MAXCPU; ++id) {
1091 if ((id_mask & 1 << id) == 0)
1096 int new_dist = cur - prev;
1102 * Make sure that all distances
1103 * between two nearest APIC IDs
1106 if (dist != new_dist)
1114 /* Must be power of 2 */
1115 if (dist & (dist - 1))
1118 /* Can't exceed CPU package capacity */
1119 if (dist > lcpus_max)
1120 logical_cpus = lcpus_max;
1122 logical_cpus = dist;
1126 * For each APIC ID of a CPU that is set in the mask,
1127 * scan the other candidate APIC ID's for this
1128 * physical processor. If any of those ID's are
1129 * already in the table, then kill the fixup.
1131 for (id = 0; id < MAXCPU; id++) {
1132 if ((id_mask & 1 << id) == 0)
1134 /* First, make sure we are on a logical_cpus boundary. */
1135 if (id % logical_cpus != 0)
1137 for (i = id + 1; i < id + logical_cpus; i++)
1138 if ((id_mask & 1 << i) != 0)
1141 return logical_cpus;
1145 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1149 vm_size_t cth_mapsz = 0;
1151 bzero(mpt, sizeof(*mpt));
1153 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1154 if (fps->pap != 0) {
1156 * Map configuration table header to get
1157 * the base table size
1159 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1160 cth_mapsz = cth->base_table_length;
1161 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1163 if (cth_mapsz < sizeof(*cth)) {
1164 kprintf("invalid base MP table length %d\n",
1166 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1171 * Map the base table
1173 cth = pmap_mapdev(fps->pap, cth_mapsz);
1178 mpt->mp_cth_mapsz = cth_mapsz;
1184 mptable_unmap(struct mptable_pos *mpt)
1186 if (mpt->mp_cth != NULL) {
1187 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1189 mpt->mp_cth_mapsz = 0;
1191 if (mpt->mp_fps != NULL) {
1192 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1200 assign_apic_irq(int apic, int intpin, int irq)
1204 if (int_to_apicintpin[irq].ioapic != -1)
1205 panic("assign_apic_irq: inconsistent table");
1207 int_to_apicintpin[irq].ioapic = apic;
1208 int_to_apicintpin[irq].int_pin = intpin;
1209 int_to_apicintpin[irq].apic_address = ioapic[apic];
1210 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1212 for (x = 0; x < nintrs; x++) {
1213 if ((io_apic_ints[x].int_type == 0 ||
1214 io_apic_ints[x].int_type == 3) &&
1215 io_apic_ints[x].int_vector == 0xff &&
1216 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1217 io_apic_ints[x].dst_apic_int == intpin)
1218 io_apic_ints[x].int_vector = irq;
1223 revoke_apic_irq(int irq)
1229 if (int_to_apicintpin[irq].ioapic == -1)
1230 panic("revoke_apic_irq: inconsistent table");
1232 oldapic = int_to_apicintpin[irq].ioapic;
1233 oldintpin = int_to_apicintpin[irq].int_pin;
1235 int_to_apicintpin[irq].ioapic = -1;
1236 int_to_apicintpin[irq].int_pin = 0;
1237 int_to_apicintpin[irq].apic_address = NULL;
1238 int_to_apicintpin[irq].redirindex = 0;
1240 for (x = 0; x < nintrs; x++) {
1241 if ((io_apic_ints[x].int_type == 0 ||
1242 io_apic_ints[x].int_type == 3) &&
1243 io_apic_ints[x].int_vector != 0xff &&
1244 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1245 io_apic_ints[x].dst_apic_int == oldintpin)
1246 io_apic_ints[x].int_vector = 0xff;
1254 allocate_apic_irq(int intr)
1260 if (io_apic_ints[intr].int_vector != 0xff)
1261 return; /* Interrupt handler already assigned */
1263 if (io_apic_ints[intr].int_type != 0 &&
1264 (io_apic_ints[intr].int_type != 3 ||
1265 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1266 io_apic_ints[intr].dst_apic_int == 0)))
1267 return; /* Not INT or ExtInt on != (0, 0) */
1270 while (irq < APIC_INTMAPSIZE &&
1271 int_to_apicintpin[irq].ioapic != -1)
1274 if (irq >= APIC_INTMAPSIZE)
1275 return; /* No free interrupt handlers */
1277 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1278 intpin = io_apic_ints[intr].dst_apic_int;
1280 assign_apic_irq(apic, intpin, irq);
1281 io_apic_setup_intpin(apic, intpin);
1286 swap_apic_id(int apic, int oldid, int newid)
1293 return; /* Nothing to do */
1295 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1296 apic, oldid, newid);
1298 /* Swap physical APIC IDs in interrupt entries */
1299 for (x = 0; x < nintrs; x++) {
1300 if (io_apic_ints[x].dst_apic_id == oldid)
1301 io_apic_ints[x].dst_apic_id = newid;
1302 else if (io_apic_ints[x].dst_apic_id == newid)
1303 io_apic_ints[x].dst_apic_id = oldid;
1306 /* Swap physical APIC IDs in IO_TO_ID mappings */
1307 for (oapic = 0; oapic < mp_napics; oapic++)
1308 if (IO_TO_ID(oapic) == newid)
1311 if (oapic < mp_napics) {
1312 kprintf("Changing APIC ID for IO APIC #%d from "
1313 "%d to %d in MP table\n",
1314 oapic, newid, oldid);
1315 IO_TO_ID(oapic) = oldid;
1317 IO_TO_ID(apic) = newid;
1322 fix_id_to_io_mapping(void)
1326 for (x = 0; x < NAPICID; x++)
1329 for (x = 0; x <= mp_naps; x++)
1330 if (CPU_TO_ID(x) < NAPICID)
1331 ID_TO_IO(CPU_TO_ID(x)) = x;
1333 for (x = 0; x < mp_napics; x++)
1334 if (IO_TO_ID(x) < NAPICID)
1335 ID_TO_IO(IO_TO_ID(x)) = x;
1340 first_free_apic_id(void)
1344 for (freeid = 0; freeid < NAPICID; freeid++) {
1345 for (x = 0; x <= mp_naps; x++)
1346 if (CPU_TO_ID(x) == freeid)
1350 for (x = 0; x < mp_napics; x++)
1351 if (IO_TO_ID(x) == freeid)
1362 io_apic_id_acceptable(int apic, int id)
1364 int cpu; /* Logical CPU number */
1365 int oapic; /* Logical IO APIC number for other IO APIC */
1368 return 0; /* Out of range */
1370 for (cpu = 0; cpu <= mp_naps; cpu++)
1371 if (CPU_TO_ID(cpu) == id)
1372 return 0; /* Conflict with CPU */
1374 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1375 if (IO_TO_ID(oapic) == id)
1376 return 0; /* Conflict with other APIC */
1378 return 1; /* ID is acceptable for IO APIC */
1383 io_apic_find_int_entry(int apic, int pin)
1387 /* search each of the possible INTerrupt sources */
1388 for (x = 0; x < nintrs; ++x) {
1389 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1390 (pin == io_apic_ints[x].dst_apic_int))
1391 return (&io_apic_ints[x]);
1399 * parse an Intel MP specification table
1407 int apic; /* IO APIC unit number */
1408 int freeid; /* Free physical APIC ID */
1409 int physid; /* Current physical IO APIC ID */
1411 int bus_0 = 0; /* Stop GCC warning */
1412 int bus_pci = 0; /* Stop GCC warning */
1416 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1417 * did it wrong. The MP spec says that when more than 1 PCI bus
1418 * exists the BIOS must begin with bus entries for the PCI bus and use
1419 * actual PCI bus numbering. This implies that when only 1 PCI bus
1420 * exists the BIOS can choose to ignore this ordering, and indeed many
1421 * MP motherboards do ignore it. This causes a problem when the PCI
1422 * sub-system makes requests of the MP sub-system based on PCI bus
1423 * numbers. So here we look for the situation and renumber the
1424 * busses and associated INTs in an effort to "make it right".
1427 /* find bus 0, PCI bus, count the number of PCI busses */
1428 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1429 if (bus_data[x].bus_id == 0) {
1432 if (bus_data[x].bus_type == PCI) {
1438 * bus_0 == slot of bus with ID of 0
1439 * bus_pci == slot of last PCI bus encountered
1442 /* check the 1 PCI bus case for sanity */
1443 /* if it is number 0 all is well */
1444 if (num_pci_bus == 1 &&
1445 bus_data[bus_pci].bus_id != 0) {
1447 /* mis-numbered, swap with whichever bus uses slot 0 */
1449 /* swap the bus entry types */
1450 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1451 bus_data[bus_0].bus_type = PCI;
1453 /* swap each relavant INTerrupt entry */
1454 id = bus_data[bus_pci].bus_id;
1455 for (x = 0; x < nintrs; ++x) {
1456 if (io_apic_ints[x].src_bus_id == id) {
1457 io_apic_ints[x].src_bus_id = 0;
1459 else if (io_apic_ints[x].src_bus_id == 0) {
1460 io_apic_ints[x].src_bus_id = id;
1465 /* Assign IO APIC IDs.
1467 * First try the existing ID. If a conflict is detected, try
1468 * the ID in the MP table. If a conflict is still detected, find
1471 * We cannot use the ID_TO_IO table before all conflicts has been
1472 * resolved and the table has been corrected.
1474 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1476 /* First try to use the value set by the BIOS */
1477 physid = io_apic_get_id(apic);
1478 if (io_apic_id_acceptable(apic, physid)) {
1479 if (IO_TO_ID(apic) != physid)
1480 swap_apic_id(apic, IO_TO_ID(apic), physid);
1484 /* Then check if the value in the MP table is acceptable */
1485 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1488 /* Last resort, find a free APIC ID and use it */
1489 freeid = first_free_apic_id();
1490 if (freeid >= NAPICID)
1491 panic("No free physical APIC IDs found");
1493 if (io_apic_id_acceptable(apic, freeid)) {
1494 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1497 panic("Free physical APIC ID not usable");
1499 fix_id_to_io_mapping();
1501 /* detect and fix broken Compaq MP table */
1502 if (apic_int_type(0, 0) == -1) {
1503 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1504 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1505 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1506 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1507 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1508 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1510 } else if (apic_int_type(0, 0) == 0) {
1511 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1512 for (x = 0; x < nintrs; ++x)
1513 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1514 (0 == io_apic_ints[x].dst_apic_int)) {
1515 io_apic_ints[x].int_type = 3;
1516 io_apic_ints[x].int_vector = 0xff;
1522 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1523 * controllers universally come in pairs. If IRQ 14 is specified
1524 * as an ISA interrupt, then IRQ 15 had better be too.
1526 * [ Shuttle XPC / AMD Athlon X2 ]
1527 * The MPTable is missing an entry for IRQ 15. Note that the
1528 * ACPI table has an entry for both 14 and 15.
1530 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1531 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1532 io14 = io_apic_find_int_entry(0, 14);
1533 io_apic_ints[nintrs] = *io14;
1534 io_apic_ints[nintrs].src_bus_irq = 15;
1535 io_apic_ints[nintrs].dst_apic_int = 15;
1543 /* Assign low level interrupt handlers */
1545 setup_apic_irq_mapping(void)
1551 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1552 int_to_apicintpin[x].ioapic = -1;
1553 int_to_apicintpin[x].int_pin = 0;
1554 int_to_apicintpin[x].apic_address = NULL;
1555 int_to_apicintpin[x].redirindex = 0;
1558 /* First assign ISA/EISA interrupts */
1559 for (x = 0; x < nintrs; x++) {
1560 int_vector = io_apic_ints[x].src_bus_irq;
1561 if (int_vector < APIC_INTMAPSIZE &&
1562 io_apic_ints[x].int_vector == 0xff &&
1563 int_to_apicintpin[int_vector].ioapic == -1 &&
1564 (apic_int_is_bus_type(x, ISA) ||
1565 apic_int_is_bus_type(x, EISA)) &&
1566 io_apic_ints[x].int_type == 0) {
1567 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1568 io_apic_ints[x].dst_apic_int,
1573 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1574 for (x = 0; x < nintrs; x++) {
1575 if (io_apic_ints[x].dst_apic_int == 0 &&
1576 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1577 io_apic_ints[x].int_vector == 0xff &&
1578 int_to_apicintpin[0].ioapic == -1 &&
1579 io_apic_ints[x].int_type == 3) {
1580 assign_apic_irq(0, 0, 0);
1584 /* PCI interrupt assignment is deferred */
1590 mp_set_cpuids(int cpu_id, int apic_id)
1592 CPU_TO_ID(cpu_id) = apic_id;
1593 ID_TO_CPU(apic_id) = cpu_id;
1597 processor_entry(const struct PROCENTRY *entry, int cpu)
1601 /* check for usability */
1602 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1605 /* check for BSP flag */
1606 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1607 mp_set_cpuids(0, entry->apic_id);
1608 return 0; /* its already been counted */
1611 /* add another AP to list, if less than max number of CPUs */
1612 else if (cpu < MAXCPU) {
1613 mp_set_cpuids(cpu, entry->apic_id);
1623 bus_entry(const struct BUSENTRY *entry, int bus)
1628 /* encode the name into an index */
1629 for (x = 0; x < 6; ++x) {
1630 if ((c = entry->bus_type[x]) == ' ')
1636 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1637 panic("unknown bus type: '%s'", name);
1639 bus_data[bus].bus_id = entry->bus_id;
1640 bus_data[bus].bus_type = x;
1646 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1648 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1651 IO_TO_ID(apic) = entry->apic_id;
1652 ID_TO_IO(entry->apic_id) = apic;
1660 lookup_bus_type(char *name)
1664 for (x = 0; x < MAX_BUSTYPE; ++x)
1665 if (strcmp(bus_type_table[x].name, name) == 0)
1666 return bus_type_table[x].type;
1668 return UNKNOWN_BUSTYPE;
1674 int_entry(const struct INTENTRY *entry, int intr)
1678 io_apic_ints[intr].int_type = entry->int_type;
1679 io_apic_ints[intr].int_flags = entry->int_flags;
1680 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1681 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1682 if (entry->dst_apic_id == 255) {
1683 /* This signal goes to all IO APICS. Select an IO APIC
1684 with sufficient number of interrupt pins */
1685 for (apic = 0; apic < mp_napics; apic++)
1686 if (((io_apic_read(apic, IOAPIC_VER) &
1687 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1688 entry->dst_apic_int)
1690 if (apic < mp_napics)
1691 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1693 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1695 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1696 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1702 apic_int_is_bus_type(int intr, int bus_type)
1706 for (bus = 0; bus < mp_nbusses; ++bus)
1707 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1708 && ((int) bus_data[bus].bus_type == bus_type))
1715 * Given a traditional ISA INT mask, return an APIC mask.
1718 isa_apic_mask(u_int isa_mask)
1723 #if defined(SKIP_IRQ15_REDIRECT)
1724 if (isa_mask == (1 << 15)) {
1725 kprintf("skipping ISA IRQ15 redirect\n");
1728 #endif /* SKIP_IRQ15_REDIRECT */
1730 isa_irq = ffs(isa_mask); /* find its bit position */
1731 if (isa_irq == 0) /* doesn't exist */
1733 --isa_irq; /* make it zero based */
1735 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1739 return (1 << apic_pin); /* convert pin# to a mask */
1743 * Determine which APIC pin an ISA/EISA INT is attached to.
1745 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1746 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1747 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1748 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1750 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1752 isa_apic_irq(int isa_irq)
1756 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1757 if (INTTYPE(intr) == 0) { /* standard INT */
1758 if (SRCBUSIRQ(intr) == isa_irq) {
1759 if (apic_int_is_bus_type(intr, ISA) ||
1760 apic_int_is_bus_type(intr, EISA)) {
1761 if (INTIRQ(intr) == 0xff)
1762 return -1; /* unassigned */
1763 return INTIRQ(intr); /* found */
1768 return -1; /* NOT found */
1773 * Determine which APIC pin a PCI INT is attached to.
1775 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1776 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1777 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1779 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1783 --pciInt; /* zero based */
1785 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1786 if ((INTTYPE(intr) == 0) /* standard INT */
1787 && (SRCBUSID(intr) == pciBus)
1788 && (SRCBUSDEVICE(intr) == pciDevice)
1789 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1790 if (apic_int_is_bus_type(intr, PCI)) {
1791 if (INTIRQ(intr) == 0xff)
1792 allocate_apic_irq(intr);
1793 if (INTIRQ(intr) == 0xff)
1794 return -1; /* unassigned */
1795 return INTIRQ(intr); /* exact match */
1800 return -1; /* NOT found */
1804 next_apic_irq(int irq)
1811 for (intr = 0; intr < nintrs; intr++) {
1812 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1814 bus = SRCBUSID(intr);
1815 bustype = apic_bus_type(bus);
1816 if (bustype != ISA &&
1822 if (intr >= nintrs) {
1825 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1826 if (INTTYPE(ointr) != 0)
1828 if (bus != SRCBUSID(ointr))
1830 if (bustype == PCI) {
1831 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1833 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1836 if (bustype == ISA || bustype == EISA) {
1837 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1840 if (INTPIN(intr) == INTPIN(ointr))
1844 if (ointr >= nintrs) {
1847 return INTIRQ(ointr);
1862 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1865 * Exactly what this means is unclear at this point. It is a solution
1866 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1867 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1868 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1872 undirect_isa_irq(int rirq)
1876 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1877 /** FIXME: tickle the MB redirector chip */
1881 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1888 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1891 undirect_pci_irq(int rirq)
1895 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1897 /** FIXME: tickle the MB redirector chip */
1901 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1911 * given a bus ID, return:
1912 * the bus type if found
1916 apic_bus_type(int id)
1920 for (x = 0; x < mp_nbusses; ++x)
1921 if (bus_data[x].bus_id == id)
1922 return bus_data[x].bus_type;
1928 * given a LOGICAL APIC# and pin#, return:
1929 * the associated src bus ID if found
1933 apic_src_bus_id(int apic, int pin)
1937 /* search each of the possible INTerrupt sources */
1938 for (x = 0; x < nintrs; ++x)
1939 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1940 (pin == io_apic_ints[x].dst_apic_int))
1941 return (io_apic_ints[x].src_bus_id);
1943 return -1; /* NOT found */
1947 * given a LOGICAL APIC# and pin#, return:
1948 * the associated src bus IRQ if found
1952 apic_src_bus_irq(int apic, int pin)
1956 for (x = 0; x < nintrs; x++)
1957 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1958 (pin == io_apic_ints[x].dst_apic_int))
1959 return (io_apic_ints[x].src_bus_irq);
1961 return -1; /* NOT found */
1966 * given a LOGICAL APIC# and pin#, return:
1967 * the associated INTerrupt type if found
1971 apic_int_type(int apic, int pin)
1975 /* search each of the possible INTerrupt sources */
1976 for (x = 0; x < nintrs; ++x) {
1977 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1978 (pin == io_apic_ints[x].dst_apic_int))
1979 return (io_apic_ints[x].int_type);
1981 return -1; /* NOT found */
1985 * Return the IRQ associated with an APIC pin
1988 apic_irq(int apic, int pin)
1993 for (x = 0; x < nintrs; ++x) {
1994 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1995 (pin == io_apic_ints[x].dst_apic_int)) {
1996 res = io_apic_ints[x].int_vector;
1999 if (apic != int_to_apicintpin[res].ioapic)
2000 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2001 if (pin != int_to_apicintpin[res].int_pin)
2002 panic("apic_irq inconsistent table (2)");
2011 * given a LOGICAL APIC# and pin#, return:
2012 * the associated trigger mode if found
2016 apic_trigger(int apic, int pin)
2020 /* search each of the possible INTerrupt sources */
2021 for (x = 0; x < nintrs; ++x)
2022 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2023 (pin == io_apic_ints[x].dst_apic_int))
2024 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2026 return -1; /* NOT found */
2031 * given a LOGICAL APIC# and pin#, return:
2032 * the associated 'active' level if found
2036 apic_polarity(int apic, int pin)
2040 /* search each of the possible INTerrupt sources */
2041 for (x = 0; x < nintrs; ++x)
2042 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2043 (pin == io_apic_ints[x].dst_apic_int))
2044 return (io_apic_ints[x].int_flags & 0x03);
2046 return -1; /* NOT found */
2052 * set data according to MP defaults
2053 * FIXME: probably not complete yet...
2056 mptable_default(int type)
2058 #if defined(APIC_IO)
2063 kprintf(" MP default config type: %d\n", type);
2066 kprintf(" bus: ISA, APIC: 82489DX\n");
2069 kprintf(" bus: EISA, APIC: 82489DX\n");
2072 kprintf(" bus: EISA, APIC: 82489DX\n");
2075 kprintf(" bus: MCA, APIC: 82489DX\n");
2078 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2081 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2084 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2087 kprintf(" future type\n");
2093 /* one and only IO APIC */
2094 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2097 * sanity check, refer to MP spec section 3.6.6, last paragraph
2098 * necessary as some hardware isn't properly setting up the IO APIC
2100 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2101 if (io_apic_id != 2) {
2103 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2104 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2105 io_apic_set_id(0, 2);
2108 IO_TO_ID(0) = io_apic_id;
2109 ID_TO_IO(io_apic_id) = 0;
2111 /* fill out bus entries */
2120 bus_data[0].bus_id = default_data[type - 1][1];
2121 bus_data[0].bus_type = default_data[type - 1][2];
2122 bus_data[1].bus_id = default_data[type - 1][3];
2123 bus_data[1].bus_type = default_data[type - 1][4];
2126 /* case 4: case 7: MCA NOT supported */
2127 default: /* illegal/reserved */
2128 panic("BAD default MP config: %d", type);
2132 /* general cases from MP v1.4, table 5-2 */
2133 for (pin = 0; pin < 16; ++pin) {
2134 io_apic_ints[pin].int_type = 0;
2135 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2136 io_apic_ints[pin].src_bus_id = 0;
2137 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2138 io_apic_ints[pin].dst_apic_id = io_apic_id;
2139 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2142 /* special cases from MP v1.4, table 5-2 */
2144 io_apic_ints[2].int_type = 0xff; /* N/C */
2145 io_apic_ints[13].int_type = 0xff; /* N/C */
2146 #if !defined(APIC_MIXED_MODE)
2148 panic("sorry, can't support type 2 default yet");
2149 #endif /* APIC_MIXED_MODE */
2152 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2155 io_apic_ints[0].int_type = 0xff; /* N/C */
2157 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2158 #endif /* APIC_IO */
2162 * Map a physical memory address representing I/O into KVA. The I/O
2163 * block is assumed not to cross a page boundary.
2166 permanent_io_mapping(vm_paddr_t pa)
2172 KKASSERT(pa < 0x100000000LL);
2174 pgeflag = 0; /* not used for SMP yet */
2177 * If the requested physical address has already been incidently
2178 * mapped, just use the existing mapping. Otherwise create a new
2181 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2182 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2183 ((vm_offset_t)pa & PG_FRAME)) {
2187 if (i == SMPpt_alloc_index) {
2188 if (i == NPTEPG - 2) {
2189 panic("permanent_io_mapping: We ran out of space"
2192 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2193 ((vm_offset_t)pa & PG_FRAME));
2194 ++SMPpt_alloc_index;
2196 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2197 ((vm_offset_t)pa & PAGE_MASK);
2198 return ((void *)vaddr);
2202 * start each AP in our list
2205 start_all_aps(u_int boot_addr)
2209 u_char mpbiosreason;
2210 u_long mpbioswarmvec;
2211 struct mdglobaldata *gd;
2212 struct privatespace *ps;
2216 POSTCODE(START_ALL_APS_POST);
2218 /* Initialize BSP's local APIC */
2219 apic_initialize(TRUE);
2221 /* install the AP 1st level boot code */
2222 install_ap_tramp(boot_addr);
2225 /* save the current value of the warm-start vector */
2226 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2227 outb(CMOS_REG, BIOS_RESET);
2228 mpbiosreason = inb(CMOS_DATA);
2230 /* set up temporary P==V mapping for AP boot */
2231 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2232 kptbase = (uintptr_t)(void *)KPTphys;
2233 for (x = 0; x < NKPT; x++) {
2234 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2235 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2240 for (x = 1; x <= mp_naps; ++x) {
2242 /* This is a bit verbose, it will go away soon. */
2244 /* first page of AP's private space */
2245 pg = x * i386_btop(sizeof(struct privatespace));
2247 /* allocate new private data page(s) */
2248 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2249 MDGLOBALDATA_BASEALLOC_SIZE);
2250 /* wire it into the private page table page */
2251 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2252 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2253 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2255 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2257 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2258 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2259 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2260 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2262 /* allocate and set up an idle stack data page */
2263 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2264 for (i = 0; i < UPAGES; i++) {
2265 SMPpt[pg + 4 + i] = (pt_entry_t)
2266 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2269 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2270 bzero(gd, sizeof(*gd));
2271 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2273 /* prime data page for it to use */
2274 mi_gdinit(&gd->mi, x);
2276 gd->gd_CMAP1 = &SMPpt[pg + 0];
2277 gd->gd_CMAP2 = &SMPpt[pg + 1];
2278 gd->gd_CMAP3 = &SMPpt[pg + 2];
2279 gd->gd_PMAP1 = &SMPpt[pg + 3];
2280 gd->gd_CADDR1 = ps->CPAGE1;
2281 gd->gd_CADDR2 = ps->CPAGE2;
2282 gd->gd_CADDR3 = ps->CPAGE3;
2283 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2284 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2285 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2287 /* setup a vector to our boot code */
2288 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2289 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2290 outb(CMOS_REG, BIOS_RESET);
2291 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2294 * Setup the AP boot stack
2296 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2299 /* attempt to start the Application Processor */
2300 CHECK_INIT(99); /* setup checkpoints */
2301 if (!start_ap(gd, boot_addr)) {
2302 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2303 CHECK_PRINT("trace"); /* show checkpoints */
2304 /* better panic as the AP may be running loose */
2305 kprintf("panic y/n? [y] ");
2306 if (cngetc() != 'n')
2309 CHECK_PRINT("trace"); /* show checkpoints */
2311 /* record its version info */
2312 cpu_apic_versions[x] = cpu_apic_versions[0];
2315 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2318 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2319 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2322 ncpus2_shift = shift;
2323 ncpus2 = 1 << shift;
2324 ncpus2_mask = ncpus2 - 1;
2326 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2327 if ((1 << shift) < ncpus)
2329 ncpus_fit = 1 << shift;
2330 ncpus_fit_mask = ncpus_fit - 1;
2332 /* build our map of 'other' CPUs */
2333 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2334 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2335 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2337 /* fill in our (BSP) APIC version */
2338 cpu_apic_versions[0] = lapic.version;
2340 /* restore the warmstart vector */
2341 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2342 outb(CMOS_REG, BIOS_RESET);
2343 outb(CMOS_DATA, mpbiosreason);
2346 * NOTE! The idlestack for the BSP was setup by locore. Finish
2347 * up, clean out the P==V mapping we did earlier.
2349 for (x = 0; x < NKPT; x++)
2353 /* number of APs actually started */
2359 * load the 1st level AP boot code into base memory.
2362 /* targets for relocation */
2363 extern void bigJump(void);
2364 extern void bootCodeSeg(void);
2365 extern void bootDataSeg(void);
2366 extern void MPentry(void);
2367 extern u_int MP_GDT;
2368 extern u_int mp_gdtbase;
2371 install_ap_tramp(u_int boot_addr)
2374 int size = *(int *) ((u_long) & bootMP_size);
2375 u_char *src = (u_char *) ((u_long) bootMP);
2376 u_char *dst = (u_char *) boot_addr + KERNBASE;
2377 u_int boot_base = (u_int) bootMP;
2382 POSTCODE(INSTALL_AP_TRAMP_POST);
2384 for (x = 0; x < size; ++x)
2388 * modify addresses in code we just moved to basemem. unfortunately we
2389 * need fairly detailed info about mpboot.s for this to work. changes
2390 * to mpboot.s might require changes here.
2393 /* boot code is located in KERNEL space */
2394 dst = (u_char *) boot_addr + KERNBASE;
2396 /* modify the lgdt arg */
2397 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2398 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2400 /* modify the ljmp target for MPentry() */
2401 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2402 *dst32 = ((u_int) MPentry - KERNBASE);
2404 /* modify the target for boot code segment */
2405 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2406 dst8 = (u_int8_t *) (dst16 + 1);
2407 *dst16 = (u_int) boot_addr & 0xffff;
2408 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2410 /* modify the target for boot data segment */
2411 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2412 dst8 = (u_int8_t *) (dst16 + 1);
2413 *dst16 = (u_int) boot_addr & 0xffff;
2414 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2419 * this function starts the AP (application processor) identified
2420 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2421 * to accomplish this. This is necessary because of the nuances
2422 * of the different hardware we might encounter. It ain't pretty,
2423 * but it seems to work.
2425 * NOTE: eventually an AP gets to ap_init(), which is called just
2426 * before the AP goes into the LWKT scheduler's idle loop.
2429 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2433 u_long icr_lo, icr_hi;
2435 POSTCODE(START_AP_POST);
2437 /* get the PHYSICAL APIC ID# */
2438 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2440 /* calculate the vector */
2441 vector = (boot_addr >> 12) & 0xff;
2443 /* Make sure the target cpu sees everything */
2447 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2448 * and running the target CPU. OR this INIT IPI might be latched (P5
2449 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2453 /* setup the address for the target AP */
2454 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2455 icr_hi |= (physical_cpu << 24);
2456 lapic.icr_hi = icr_hi;
2458 /* do an INIT IPI: assert RESET */
2459 icr_lo = lapic.icr_lo & 0xfff00000;
2460 lapic.icr_lo = icr_lo | 0x0000c500;
2462 /* wait for pending status end */
2463 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2466 /* do an INIT IPI: deassert RESET */
2467 lapic.icr_lo = icr_lo | 0x00008500;
2469 /* wait for pending status end */
2470 u_sleep(10000); /* wait ~10mS */
2471 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2475 * next we do a STARTUP IPI: the previous INIT IPI might still be
2476 * latched, (P5 bug) this 1st STARTUP would then terminate
2477 * immediately, and the previously started INIT IPI would continue. OR
2478 * the previous INIT IPI has already run. and this STARTUP IPI will
2479 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2483 /* do a STARTUP IPI */
2484 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2485 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2487 u_sleep(200); /* wait ~200uS */
2490 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2491 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2492 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2493 * recognized after hardware RESET or INIT IPI.
2496 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2497 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2499 u_sleep(200); /* wait ~200uS */
2501 /* wait for it to start, see ap_init() */
2502 set_apic_timer(5000000);/* == 5 seconds */
2503 while (read_apic_timer()) {
2504 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2505 return 1; /* return SUCCESS */
2507 return 0; /* return FAILURE */
2512 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2514 * If for some reason we were unable to start all cpus we cannot safely
2515 * use broadcast IPIs.
2521 if (smp_startup_mask == smp_active_mask) {
2522 all_but_self_ipi(XINVLTLB_OFFSET);
2524 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2525 APIC_DELMODE_FIXED);
2531 * When called the executing CPU will send an IPI to all other CPUs
2532 * requesting that they halt execution.
2534 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2536 * - Signals all CPUs in map to stop.
2537 * - Waits for each to stop.
2544 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2545 * from executing at same time.
2548 stop_cpus(u_int map)
2550 map &= smp_active_mask;
2552 /* send the Xcpustop IPI to all CPUs in map */
2553 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2555 while ((stopped_cpus & map) != map)
2563 * Called by a CPU to restart stopped CPUs.
2565 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2567 * - Signals all CPUs in map to restart.
2568 * - Waits for each to restart.
2576 restart_cpus(u_int map)
2578 /* signal other cpus to restart */
2579 started_cpus = map & smp_active_mask;
2581 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2588 * This is called once the mpboot code has gotten us properly relocated
2589 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2590 * and when it returns the scheduler will call the real cpu_idle() main
2591 * loop for the idlethread. Interrupts are disabled on entry and should
2592 * remain disabled at return.
2600 * Adjust smp_startup_mask to signal the BSP that we have started
2601 * up successfully. Note that we do not yet hold the BGL. The BSP
2602 * is waiting for our signal.
2604 * We can't set our bit in smp_active_mask yet because we are holding
2605 * interrupts physically disabled and remote cpus could deadlock
2606 * trying to send us an IPI.
2608 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2612 * Interlock for finalization. Wait until mp_finish is non-zero,
2613 * then get the MP lock.
2615 * Note: We are in a critical section.
2617 * Note: We have to synchronize td_mpcount to our desired MP state
2618 * before calling cpu_try_mplock().
2620 * Note: we are the idle thread, we can only spin.
2622 * Note: The load fence is memory volatile and prevents the compiler
2623 * from improperly caching mp_finish, and the cpu from improperly
2626 while (mp_finish == 0)
2628 ++curthread->td_mpcount;
2629 while (cpu_try_mplock() == 0)
2632 if (cpu_feature & CPUID_TSC) {
2634 * The BSP is constantly updating tsc0_offset, figure out the
2635 * relative difference to synchronize ktrdump.
2637 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2640 /* BSP may have changed PTD while we're waiting for the lock */
2643 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2647 /* Build our map of 'other' CPUs. */
2648 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2650 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2652 /* A quick check from sanity claus */
2653 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2654 if (mycpu->gd_cpuid != apic_id) {
2655 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2656 kprintf("SMP: apic_id = %d\n", apic_id);
2657 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2658 panic("cpuid mismatch! boom!!");
2661 /* Initialize AP's local APIC for irq's */
2662 apic_initialize(FALSE);
2664 /* Set memory range attributes for this CPU to match the BSP */
2665 mem_range_AP_init();
2668 * Once we go active we must process any IPIQ messages that may
2669 * have been queued, because no actual IPI will occur until we
2670 * set our bit in the smp_active_mask. If we don't the IPI
2671 * message interlock could be left set which would also prevent
2674 * The idle loop doesn't expect the BGL to be held and while
2675 * lwkt_switch() normally cleans things up this is a special case
2676 * because we returning almost directly into the idle loop.
2678 * The idle thread is never placed on the runq, make sure
2679 * nothing we've done put it there.
2681 KKASSERT(curthread->td_mpcount == 1);
2682 smp_active_mask |= 1 << mycpu->gd_cpuid;
2685 * Enable interrupts here. idle_restore will also do it, but
2686 * doing it here lets us clean up any strays that got posted to
2687 * the CPU during the AP boot while we are still in a critical
2690 __asm __volatile("sti; pause; pause"::);
2691 mdcpu->gd_fpending = 0;
2692 mdcpu->gd_ipending = 0;
2694 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2695 lwkt_process_ipiq();
2698 * Releasing the mp lock lets the BSP finish up the SMP init
2701 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2705 * Get SMP fully working before we start initializing devices.
2713 kprintf("Finish MP startup\n");
2714 if (cpu_feature & CPUID_TSC)
2715 tsc0_offset = rdtsc();
2718 while (smp_active_mask != smp_startup_mask) {
2720 if (cpu_feature & CPUID_TSC)
2721 tsc0_offset = rdtsc();
2723 while (try_mplock() == 0)
2726 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2729 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2732 cpu_send_ipiq(int dcpu)
2734 if ((1 << dcpu) & smp_active_mask)
2735 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2738 #if 0 /* single_apic_ipi_passive() not working yet */
2740 * Returns 0 on failure, 1 on success
2743 cpu_send_ipiq_passive(int dcpu)
2746 if ((1 << dcpu) & smp_active_mask) {
2747 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2748 APIC_DELMODE_FIXED);
2754 struct mptable_lapic_cbarg1 {
2757 u_int ht_apicid_mask;
2761 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2763 const struct PROCENTRY *ent;
2764 struct mptable_lapic_cbarg1 *arg = xarg;
2770 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2774 if (ent->apic_id < 32) {
2775 arg->ht_apicid_mask |= 1 << ent->apic_id;
2776 } else if (arg->ht_fixup) {
2777 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2783 struct mptable_lapic_cbarg2 {
2790 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2792 const struct PROCENTRY *ent;
2793 struct mptable_lapic_cbarg2 *arg = xarg;
2799 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2800 KKASSERT(!arg->found_bsp);
2804 if (processor_entry(ent, arg->cpu))
2807 if (arg->logical_cpus) {
2808 struct PROCENTRY proc;
2812 * Create fake mptable processor entries
2813 * and feed them to processor_entry() to
2814 * enumerate the logical CPUs.
2816 bzero(&proc, sizeof(proc));
2818 proc.cpu_flags = PROCENTRY_FLAG_EN;
2819 proc.apic_id = ent->apic_id;
2821 for (i = 1; i < arg->logical_cpus; i++) {
2823 processor_entry(&proc, arg->cpu);
2831 mptable_lapic_default(void)
2833 int ap_apicid, bsp_apicid;
2835 mp_naps = 1; /* exclude BSP */
2837 /* Map local apic before the id field is accessed */
2838 lapic_init(DEFAULT_APIC_BASE);
2840 bsp_apicid = APIC_ID(lapic.id);
2841 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2844 mp_set_cpuids(0, bsp_apicid);
2845 /* one and only AP */
2846 mp_set_cpuids(1, ap_apicid);
2852 * ID_TO_CPU(N), APIC ID to logical CPU table
2853 * CPU_TO_ID(N), logical CPU to APIC ID table
2856 mptable_lapic_enumerate(struct mptable_pos *mpt)
2858 struct mptable_lapic_cbarg1 arg1;
2859 struct mptable_lapic_cbarg2 arg2;
2861 int error, logical_cpus = 0;
2862 vm_offset_t lapic_addr;
2864 KKASSERT(mpt->mp_fps != NULL);
2867 * Check for use of 'default' configuration
2869 if (mpt->mp_fps->mpfb1 != 0) {
2870 mptable_lapic_default();
2875 KKASSERT(cth != NULL);
2877 /* Save local apic address */
2878 lapic_addr = (vm_offset_t)cth->apic_address;
2879 KKASSERT(lapic_addr != 0);
2882 * Find out how many CPUs do we have
2884 bzero(&arg1, sizeof(arg1));
2885 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2887 error = mptable_iterate_entries(cth,
2888 mptable_lapic_pass1_callback, &arg1);
2890 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2891 KKASSERT(arg1.cpu_count != 0);
2893 /* See if we need to fixup HT logical CPUs. */
2894 if (arg1.ht_fixup) {
2895 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2897 if (logical_cpus != 0)
2898 arg1.cpu_count *= logical_cpus;
2900 mp_naps = arg1.cpu_count;
2902 /* Qualify the numbers again, after possible HT fixup */
2903 if (mp_naps > MAXCPU) {
2904 kprintf("Warning: only using %d of %d available CPUs!\n",
2909 --mp_naps; /* subtract the BSP */
2912 * Link logical CPU id to local apic id
2914 bzero(&arg2, sizeof(arg2));
2916 arg2.logical_cpus = logical_cpus;
2918 error = mptable_iterate_entries(cth,
2919 mptable_lapic_pass2_callback, &arg2);
2921 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2922 KKASSERT(arg2.found_bsp);
2924 /* Map local apic */
2925 lapic_init(lapic_addr);
2929 mptable_imcr(struct mptable_pos *mpt)
2931 /* record whether PIC or virtual-wire mode */
2932 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2933 mpt->mp_fps->mpfb2 & 0x80);