2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved.
3 * Copyright (c) 2008 Jordan Gordeev.
5 * This code is derived from software contributed to The DragonFly Project
6 * by Matthew Dillon <dillon@backplane.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * Copyright (c) 1990 The Regents of the University of California.
36 * All rights reserved.
38 * This code is derived from software contributed to Berkeley by
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by the University of
52 * California, Berkeley and its contributors.
53 * 4. Neither the name of the University nor the names of its contributors
54 * may be used to endorse or promote products derived from this software
55 * without specific prior written permission.
57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $
72 //#include "use_npx.h"
74 #include <sys/rtprio.h>
76 #include <machine/asmacros.h>
77 #include <machine/segments.h>
79 #include <machine/pmap.h>
81 #include <machine_base/apic/apicreg.h>
83 #include <machine/lock.h>
87 #define MPLOCKED lock ;
92 .globl lwkt_switch_return
94 #if defined(SWTCH_OPTIM_STATS)
95 .globl swtch_optim_stats, tlb_flush_count
96 swtch_optim_stats: .long 0 /* number of _swtch_optims */
97 tlb_flush_count: .long 0
104 * cpu_heavy_switch(struct thread *next_thread)
106 * Switch from the current thread to a new thread. This entry
107 * is normally called via the thread->td_switch function, and will
108 * only be called when the current thread is a heavy weight process.
110 * Some instructions have been reordered to reduce pipeline stalls.
112 * YYY disable interrupts once giant is removed.
114 ENTRY(cpu_heavy_switch)
116 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15).
118 movq PCPU(curthread),%rcx
119 /* On top of the stack is the return adress. */
120 movq (%rsp),%rax /* (reorder optimization) */
121 movq TD_PCB(%rcx),%rdx /* RDX = PCB */
122 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */
123 movq %rbx,PCB_RBX(%rdx)
124 movq %rsp,PCB_RSP(%rdx)
125 movq %rbp,PCB_RBP(%rdx)
126 movq %r12,PCB_R12(%rdx)
127 movq %r13,PCB_R13(%rdx)
128 movq %r14,PCB_R14(%rdx)
129 movq %r15,PCB_R15(%rdx)
132 * Clear the cpu bit in the pmap active mask. The restore
133 * function will set the bit in the pmap active mask.
135 * Special case: when switching between threads sharing the
136 * same vmspace if we avoid clearing the bit we do not have
137 * to reload %cr3 (if we clear the bit we could race page
138 * table ops done by other threads and would have to reload
139 * %cr3, because those ops will not know to IPI us).
141 movq %rcx,%rbx /* RBX = oldthread */
142 movq TD_LWP(%rcx),%rcx /* RCX = oldlwp */
143 movq TD_LWP(%rdi),%r13 /* R13 = newlwp */
144 movq LWP_VMSPACE(%rcx), %rcx /* RCX = oldvmspace */
145 testq %r13,%r13 /* might not be a heavy */
147 cmpq LWP_VMSPACE(%r13),%rcx /* same vmspace? */
150 movslq PCPU(cpuid), %rax
151 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx)
155 * Push the LWKT switch restore function, which resumes a heavy
156 * weight process. Note that the LWKT switcher is based on
157 * TD_SP, while the heavy weight process switcher is based on
158 * PCB_RSP. TD_SP is usually two ints pushed relative to
159 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore.
163 movq $cpu_heavy_restore, %rax
165 movq %rsp,TD_SP(%rbx)
168 * Save debug regs if necessary
170 movq PCB_FLAGS(%rdx),%rax
171 andq $PCB_DBREGS,%rax
172 jz 1f /* no, skip over */
173 movq %dr7,%rax /* yes, do the save */
174 movq %rax,PCB_DR7(%rdx)
175 /* JG correct value? */
176 andq $0x0000fc00, %rax /* disable all watchpoints */
179 movq %rax,PCB_DR6(%rdx)
181 movq %rax,PCB_DR3(%rdx)
183 movq %rax,PCB_DR2(%rdx)
185 movq %rax,PCB_DR1(%rdx)
187 movq %rax,PCB_DR0(%rdx)
192 * Save the FP state if we have used the FP. Note that calling
193 * npxsave will NULL out PCPU(npxthread).
195 cmpq %rbx,PCPU(npxthread)
197 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */
198 movq TD_SAVEFPU(%rbx),%rdi
199 call npxsave /* do it in a big C function */
200 movq %r12,%rdi /* restore %rdi */
205 * Switch to the next thread, which was passed as an argument
206 * to cpu_heavy_switch(). The argument is in %rdi.
207 * Set the current thread, load the stack pointer,
208 * and 'ret' into the switch-restore function.
210 * The switch restore function expects the new thread to be in %rax
211 * and the old one to be in %rbx.
213 * There is a one-instruction window where curthread is the new
214 * thread but %rsp still points to the old thread's stack, but
215 * we are protected by a critical section so it is ok.
217 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */
218 movq %rax,PCPU(curthread)
219 movq TD_SP(%rax),%rsp
223 * cpu_exit_switch(struct thread *next)
225 * The switch function is changed to this when a thread is going away
226 * for good. We have to ensure that the MMU state is not cached, and
227 * we don't bother saving the existing thread state before switching.
229 * At this point we are in a critical section and this cpu owns the
230 * thread's token, which serves as an interlock until the switchout is
233 ENTRY(cpu_exit_switch)
235 * Get us out of the vmspace
243 /* JG no increment of statistics counters? see cpu_heavy_restore */
246 movq PCPU(curthread),%rbx
249 * If this is a process/lwp, deactivate the pmap after we've
252 movq TD_LWP(%rbx),%rcx
255 movslq PCPU(cpuid), %rax
256 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */
257 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx)
260 * Switch to the next thread. RET into the restore function, which
261 * expects the new thread in RAX and the old in RBX.
263 * There is a one-instruction window where curthread is the new
264 * thread but %rsp still points to the old thread's stack, but
265 * we are protected by a critical section so it is ok.
269 movq %rax,PCPU(curthread)
270 movq TD_SP(%rax),%rsp
274 * cpu_heavy_restore() (current thread in %rax on entry, old thread in %rbx)
276 * Restore the thread after an LWKT switch. This entry is normally
277 * called via the LWKT switch restore function, which was pulled
278 * off the thread stack and jumped to.
280 * This entry is only called if the thread was previously saved
281 * using cpu_heavy_switch() (the heavy weight process thread switcher),
282 * or when a new process is initially scheduled.
284 * NOTE: The lwp may be in any state, not necessarily LSRUN, because
285 * a preemption switch may interrupt the process and then return via
288 * YYY theoretically we do not have to restore everything here, a lot
289 * of this junk can wait until we return to usermode. But for now
290 * we restore everything.
292 * YYY the PCB crap is really crap, it makes startup a bitch because
293 * we can't switch away.
295 * YYY note: spl check is done in mi_switch when it splx()'s.
298 ENTRY(cpu_heavy_restore)
299 movq TD_PCB(%rax),%rdx /* RDX = PCB */
300 movq %rdx, PCPU(common_tss) + TSS_RSP0
303 #if defined(SWTCH_OPTIM_STATS)
304 incl _swtch_optim_stats
307 * Tell the pmap that our cpu is using the VMSPACE now. We cannot
308 * safely test/reload %cr3 until after we have set the bit in the
311 * We must do an interlocked test of the CPULOCK_EXCL at the same
312 * time. If found to be set we will have to wait for it to clear
313 * and then do a forced reload of %cr3 (even if the value matches).
315 * XXX When switching between two LWPs sharing the same vmspace
316 * the cpu_heavy_switch() code currently avoids clearing the
317 * cpu bit in PM_ACTIVE. So if the bit is already set we can
318 * avoid checking for the interlock via CPULOCK_EXCL. We currently
319 * do not perform this optimization.
321 movq TD_LWP(%rax),%rcx
322 movq LWP_VMSPACE(%rcx),%rcx /* RCX = vmspace */
323 movq PCPU(cpumask),%rsi /* new contents */
324 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE(%rcx)
325 movl VM_PMAP+PM_ACTIVE_LOCK(%rcx),%esi
326 testl $CPULOCK_EXCL,%esi
329 movq %rax,%r12 /* save newthread ptr */
330 movq %rcx,%rdi /* (found to be set) */
331 call pmap_interlock_wait /* pmap_interlock_wait(%rdi:vm) */
335 * Need unconditional load cr3
337 movq TD_PCB(%rax),%rdx /* RDX = PCB */
338 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */
339 jmp 2f /* unconditional reload */
342 * Restore the MMU address space. If it is the same as the last
343 * thread we don't have to invalidate the tlb (i.e. reload cr3).
344 * YYY which naturally also means that the PM_ACTIVE bit had better
345 * already have been set before we set it above, check? YYY
347 movq TD_PCB(%rax),%rdx /* RDX = PCB */
348 movq %cr3,%rsi /* RSI = current CR3 */
349 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */
353 #if defined(SWTCH_OPTIM_STATS)
354 decl _swtch_optim_stats
355 incl _tlb_flush_count
361 * NOTE: %rbx is the previous thread and %rax is the new thread.
362 * %rbx is retained throughout so we can return it.
364 * lwkt_switch[_return] is responsible for handling TDF_RUNNING.
368 * Deal with the PCB extension, restore the private tss
370 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */
371 movq $1,%rcx /* maybe mark use of a private tss */
378 * Going back to the common_tss. We may need to update TSS_RSP0
379 * which sets the top of the supervisor stack when entering from
380 * usermode. The PCB is at the top of the stack but we need another
381 * 16 bytes to take vm86 into account.
384 /*leaq -TF_SIZE(%rdx),%rcx*/
385 movq %rcx, PCPU(common_tss) + TSS_RSP0
388 cmpl $0,PCPU(private_tss) /* don't have to reload if */
389 je 3f /* already using the common TSS */
392 subq %rcx,%rcx /* unmark use of private tss */
395 * Get the address of the common TSS descriptor for the ltr.
396 * There is no way to get the address of a segment-accessed variable
397 * so we store a self-referential pointer at the base of the per-cpu
398 * data area and add the appropriate offset.
401 movq $gd_common_tssd, %rdi
402 /* JG name for "%gs:0"? */
406 * Move the correct TSS descriptor into the GDT slot, then reload
411 movl %rcx,PCPU(private_tss) /* mark/unmark private tss */
412 movq PCPU(tss_gdt), %rbx /* entry in GDT */
415 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */
421 * Restore the user %gs and %fs
423 movq PCB_FSBASE(%rdx),%r9
424 cmpq PCPU(user_fs),%r9
427 movq %r9,PCPU(user_fs)
428 movl $MSR_FSBASE,%ecx
429 movl PCB_FSBASE(%r10),%eax
430 movl PCB_FSBASE+4(%r10),%edx
434 movq PCB_GSBASE(%rdx),%r9
435 cmpq PCPU(user_gs),%r9
438 movq %r9,PCPU(user_gs)
439 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */
440 movl PCB_GSBASE(%r10),%eax
441 movl PCB_GSBASE+4(%r10),%edx
447 * Restore general registers. %rbx is restored later.
449 movq PCB_RSP(%rdx), %rsp
450 movq PCB_RBP(%rdx), %rbp
451 movq PCB_R12(%rdx), %r12
452 movq PCB_R13(%rdx), %r13
453 movq PCB_R14(%rdx), %r14
454 movq PCB_R15(%rdx), %r15
455 movq PCB_RIP(%rdx), %rax
462 * Restore the user LDT if we have one
464 cmpl $0, PCB_USERLDT(%edx)
466 movl _default_ldt,%eax
467 cmpl PCPU(currentldt),%eax
470 movl %eax,PCPU(currentldt)
479 * Restore the user TLS if we have one
487 * Restore the DEBUG register state if necessary.
489 movq PCB_FLAGS(%rdx),%rax
490 andq $PCB_DBREGS,%rax
491 jz 1f /* no, skip over */
492 movq PCB_DR6(%rdx),%rax /* yes, do the restore */
494 movq PCB_DR3(%rdx),%rax
496 movq PCB_DR2(%rdx),%rax
498 movq PCB_DR1(%rdx),%rax
500 movq PCB_DR0(%rdx),%rax
502 movq %dr7,%rax /* load dr7 so as not to disturb */
503 /* JG correct value? */
504 andq $0x0000fc00,%rax /* reserved bits */
505 /* JG we've got more registers on x86_64 */
506 movq PCB_DR7(%rdx),%rcx
507 /* JG correct value? */
508 andq $~0x0000fc00,%rcx
513 * Clear the QUICKRET flag when restoring a user process context
514 * so we don't try to do a quick syscall return.
517 andl $~RQF_QUICKRET,PCPU(reqflags)
519 movq PCB_RBX(%rdx),%rbx
523 * savectx(struct pcb *pcb)
525 * Update pcb, saving current processor state.
529 /* JG use %rdi instead of %rcx everywhere? */
532 /* caller's return address - child won't execute this routine */
534 movq %rax,PCB_RIP(%rcx)
537 movq %rax,PCB_CR3(%rcx)
539 movq %rbx,PCB_RBX(%rcx)
540 movq %rsp,PCB_RSP(%rcx)
541 movq %rbp,PCB_RBP(%rcx)
542 movq %r12,PCB_R12(%rcx)
543 movq %r13,PCB_R13(%rcx)
544 movq %r14,PCB_R14(%rcx)
545 movq %r15,PCB_R15(%rcx)
549 * If npxthread == NULL, then the npx h/w state is irrelevant and the
550 * state had better already be in the pcb. This is true for forks
551 * but not for dumps (the old book-keeping with FP flags in the pcb
552 * always lost for dumps because the dump pcb has 0 flags).
554 * If npxthread != NULL, then we have to save the npx h/w state to
555 * npxthread's pcb and copy it to the requested pcb, or save to the
556 * requested pcb and reload. Copying is easier because we would
557 * have to handle h/w bugs for reloading. We used to lose the
558 * parent's npx state for forks by forgetting to reload.
560 movq PCPU(npxthread),%rax
564 pushq %rcx /* target pcb */
565 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */
574 movq $PCB_SAVEFPU_SIZE,%rdx
575 leaq PCB_SAVEFPU(%rcx),%rcx
585 * cpu_idle_restore() (current thread in %rax on entry) (one-time execution)
587 * Don't bother setting up any regs other than %rbp so backtraces
588 * don't die. This restore function is used to bootstrap into the
589 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for
592 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3.
593 * This only occurs during system boot so no special handling is
594 * required for migration.
596 * If we are an AP we have to call ap_init() before jumping to
597 * cpu_idle(). ap_init() will synchronize with the BP and finish
598 * setting up various ncpu-dependant globaldata fields. This may
599 * happen on UP as well as SMP if we happen to be simulating multiple
602 ENTRY(cpu_idle_restore)
612 andl $~TDF_RUNNING,TD_FLAGS(%rbx)
613 orl $TDF_RUNNING,TD_FLAGS(%rax) /* manual, no switch_return */
616 * ap_init can decide to enable interrupts early, but otherwise, or if
617 * we are UP, do it here.
623 * cpu 0's idle thread entry for the first time must use normal
624 * lwkt_switch_return() semantics or a pending cpu migration on
625 * thread0 will deadlock.
631 call lwkt_switch_return
636 * cpu_kthread_restore() (current thread is %rax on entry, previous is %rbx)
637 * (one-time execution)
639 * Don't bother setting up any regs other then %rbp so backtraces
640 * don't die. This restore function is used to bootstrap into an
641 * LWKT based kernel thread only. cpu_lwkt_switch() will be used
644 * Because this switch target does not 'return' to lwkt_switch()
645 * we have to call lwkt_switch_return(otd) to clean up otd.
648 * Since all of our context is on the stack we are reentrant and
649 * we can release our critical section and enable interrupts early.
651 ENTRY(cpu_kthread_restore)
654 movq TD_PCB(%rax),%r13
659 * rax and rbx come from the switchout code. Call
660 * lwkt_switch_return(otd).
662 * NOTE: unlike i386, %rsi and %rdi are not call-saved regs.
666 call lwkt_switch_return
668 decl TD_CRITCOUNT(%rax)
669 movq PCB_R12(%r13),%rdi /* argument to RBX function */
670 movq PCB_RBX(%r13),%rax /* thread function */
671 /* note: top of stack return address inherited by function */
675 * cpu_lwkt_switch(struct thread *)
677 * Standard LWKT switching function. Only non-scratch registers are
678 * saved and we don't bother with the MMU state or anything else.
680 * This function is always called while in a critical section.
682 * There is a one-instruction window where curthread is the new
683 * thread but %rsp still points to the old thread's stack, but
684 * we are protected by a critical section so it is ok.
686 ENTRY(cpu_lwkt_switch)
687 pushq %rbp /* JG note: GDB hacked to locate ebp rel to td_sp */
689 movq PCPU(curthread),%rbx /* becomes old thread in restore */
699 * Save the FP state if we have used the FP. Note that calling
700 * npxsave will NULL out PCPU(npxthread).
702 * We have to deal with the FP state for LWKT threads in case they
703 * happen to get preempted or block while doing an optimized
704 * bzero/bcopy/memcpy.
706 cmpq %rbx,PCPU(npxthread)
708 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */
709 movq TD_SAVEFPU(%rbx),%rdi
710 call npxsave /* do it in a big C function */
711 movq %r12,%rdi /* restore %rdi */
715 movq %rdi,%rax /* switch to this thread */
716 pushq $cpu_lwkt_restore
717 movq %rsp,TD_SP(%rbx)
719 * %rax contains new thread, %rbx contains old thread.
721 movq %rax,PCPU(curthread)
722 movq TD_SP(%rax),%rsp
726 * cpu_lwkt_restore() (current thread in %rax on entry)
728 * Standard LWKT restore function. This function is always called
729 * while in a critical section.
731 * Warning: due to preemption the restore function can be used to
732 * 'return' to the original thread. Interrupt disablement must be
733 * protected through the switch so we cannot run splz here.
735 * YYY we theoretically do not need to load KPML4phys into cr3, but if
736 * so we need a way to detect when the PTD we are using is being
737 * deleted due to a process exiting.
739 ENTRY(cpu_lwkt_restore)
740 movq KPML4phys,%rcx /* YYY borrow but beware desched/cpuchg/exit */
749 * Safety, clear RSP0 in the tss so it isn't pointing at the
750 * previous thread's kstack (if a heavy weight user thread).
751 * RSP0 should only be used in ring 3 transitions and kernel
752 * threads run in ring 0 so there should be none.
755 movq %rdx, PCPU(common_tss) + TSS_RSP0
758 * NOTE: %rbx is the previous thread and %rax is the new thread.
759 * %rbx is retained throughout so we can return it.
761 * lwkt_switch[_return] is responsible for handling TDF_RUNNING.