2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 * $DragonFly: src/sys/platform/pc32/isa/clock.c,v 1.55 2008/08/02 01:14:43 dillon Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
53 #include "opt_clock.h"
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/eventhandler.h>
59 #include <sys/kernel.h>
64 #include <sys/sysctl.h>
66 #include <sys/systimer.h>
67 #include <sys/globaldata.h>
68 #include <sys/thread2.h>
69 #include <sys/systimer.h>
70 #include <sys/machintr.h>
72 #include <machine/clock.h>
73 #ifdef CLK_CALIBRATION_LOOP
75 #include <machine/cputypes.h>
76 #include <machine/frame.h>
77 #include <machine/ipl.h>
78 #include <machine/limits.h>
79 #include <machine/md_var.h>
80 #include <machine/psl.h>
81 #include <machine/segments.h>
82 #include <machine/smp.h>
83 #include <machine/specialreg.h>
85 #include <machine_base/icu/icu.h>
86 #include <bus/isa/isa.h>
87 #include <bus/isa/rtc.h>
88 #include <machine_base/isa/timerreg.h>
90 #include <machine_base/isa/intr_machdep.h>
93 /* The interrupt triggered by the 8254 (timer) chip */
95 static void setup_8254_mixed_mode (void);
97 static void i8254_restore(void);
98 static void resettodr_on_shutdown(void *arg __unused);
101 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
102 * can use a simple formula for leap years.
104 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
105 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
108 #define TIMER_FREQ 1193182
111 static uint8_t i8254_walltimer_sel;
112 static uint16_t i8254_walltimer_cntr;
114 int adjkerntz; /* local offset from GMT in seconds */
115 int disable_rtc_set; /* disable resettodr() if != 0 */
116 int statclock_disable = 1; /* we don't use the statclock right now */
118 int64_t tsc_frequency;
120 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
122 enum tstate { RELEASED, ACQUIRED };
123 enum tstate timer0_state;
124 enum tstate timer1_state;
125 enum tstate timer2_state;
127 static int beeping = 0;
128 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
129 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
130 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
131 static int rtc_loaded;
133 static int i8254_cputimer_div;
135 static int i8254_nointr;
136 static int i8254_intr_disable = 0;
137 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
139 static struct callout sysbeepstop_ch;
141 static sysclock_t i8254_cputimer_count(void);
142 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
143 static void i8254_cputimer_destruct(struct cputimer *cputimer);
145 static struct cputimer i8254_cputimer = {
146 SLIST_ENTRY_INITIALIZER,
150 i8254_cputimer_count,
151 cputimer_default_fromhz,
152 cputimer_default_fromus,
153 i8254_cputimer_construct,
154 i8254_cputimer_destruct,
159 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
160 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
161 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
163 static struct cputimer_intr i8254_cputimer_intr = {
165 .reload = i8254_intr_reload,
166 .enable = cputimer_intr_default_enable,
167 .config = i8254_intr_config,
168 .restart = cputimer_intr_default_restart,
169 .pmfixup = cputimer_intr_default_pmfixup,
170 .initclock = i8254_intr_initclock,
171 .next = SLIST_ENTRY_INITIALIZER,
173 .type = CPUTIMER_INTR_8254,
174 .prio = CPUTIMER_INTR_PRIO_8254,
175 .caps = CPUTIMER_INTR_CAP_PS
179 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
180 * counting as of this interrupt. We use timer1 in free-running mode (not
181 * generating any interrupts) as our main counter. Each cpu has timeouts
184 * This code is INTR_MPSAFE and may be called without the BGL held.
187 clkintr(void *dummy, void *frame_arg)
189 static sysclock_t sysclock_count; /* NOTE! Must be static */
190 struct globaldata *gd = mycpu;
192 struct globaldata *gscan;
197 * SWSTROBE mode is a one-shot, the timer is no longer running
202 * XXX the dispatcher needs work. right now we call systimer_intr()
203 * directly or via IPI for any cpu with systimers queued, which is
204 * usually *ALL* of them. We need to use the LAPIC timer for this.
206 sysclock_count = sys_cputimer->count();
208 for (n = 0; n < ncpus; ++n) {
209 gscan = globaldata_find(n);
210 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
213 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
216 systimer_intr(&sysclock_count, 0, frame_arg);
220 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
221 systimer_intr(&sysclock_count, 0, frame_arg);
230 acquire_timer2(int mode)
232 if (timer2_state != RELEASED)
234 timer2_state = ACQUIRED;
237 * This access to the timer registers is as atomic as possible
238 * because it is a single instruction. We could do better if we
241 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
248 if (timer2_state != ACQUIRED)
250 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
251 timer2_state = RELEASED;
256 * This routine receives statistical clock interrupts from the RTC.
257 * As explained above, these occur at 128 interrupts per second.
258 * When profiling, we receive interrupts at a rate of 1024 Hz.
260 * This does not actually add as much overhead as it sounds, because
261 * when the statistical clock is active, the hardclock driver no longer
262 * needs to keep (inaccurate) statistics on its own. This decouples
263 * statistics gathering from scheduling interrupts.
265 * The RTC chip requires that we read status register C (RTC_INTR)
266 * to acknowledge an interrupt, before it will generate the next one.
267 * Under high interrupt load, rtcintr() can be indefinitely delayed and
268 * the clock can tick immediately after the read from RTC_INTR. In this
269 * case, the mc146818A interrupt signal will not drop for long enough
270 * to register with the 8259 PIC. If an interrupt is missed, the stat
271 * clock will halt, considerably degrading system performance. This is
272 * why we use 'while' rather than a more straightforward 'if' below.
273 * Stat clock ticks can still be lost, causing minor loss of accuracy
274 * in the statistics, but the stat clock will no longer stop.
277 rtcintr(void *dummy, void *frame)
279 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
281 /* statclock(frame); no longer used */
288 DB_SHOW_COMMAND(rtc, rtc)
290 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
291 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
292 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
293 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
298 * Return the current cpu timer count as a 32 bit integer.
302 i8254_cputimer_count(void)
304 static __uint16_t cputimer_last;
309 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
310 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
311 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
312 count = -count; /* -> countup */
313 if (count < cputimer_last) /* rollover */
314 i8254_cputimer.base += 0x00010000;
315 ret = i8254_cputimer.base | count;
316 cputimer_last = count;
322 * This function is called whenever the system timebase changes, allowing
323 * us to calculate what is needed to convert a system timebase tick
324 * into an 8254 tick for the interrupt timer. If we can convert to a
325 * simple shift, multiplication, or division, we do so. Otherwise 64
326 * bit arithmatic is required every time the interrupt timer is reloaded.
329 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
335 * Will a simple divide do the trick?
337 div = (timer->freq + (cti->freq / 2)) / cti->freq;
338 freq = cti->freq * div;
340 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
341 i8254_cputimer_div = div;
343 i8254_cputimer_div = 0;
347 * Reload for the next timeout. It is possible for the reload value
348 * to be 0 or negative, indicating that an immediate timer interrupt
349 * is desired. For now make the minimum 2 ticks.
351 * We may have to convert from the system timebase to the 8254 timebase.
354 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
358 if (i8254_cputimer_div)
359 reload /= i8254_cputimer_div;
361 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
367 if (timer0_running) {
368 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
369 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
370 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
371 if (reload < count) {
372 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
373 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
374 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
379 reload = 0; /* full count */
380 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
381 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
382 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
388 * DELAY(usec) - Spin for the specified number of microseconds.
389 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
390 * but do a thread switch in the loop
392 * Relies on timer 1 counting down from (cputimer_freq / hz)
393 * Note: timer had better have been programmed before this is first used!
396 DODELAY(int n, int doswitch)
398 int delta, prev_tick, tick, ticks_left;
403 static int state = 0;
407 for (n1 = 1; n1 <= 10000000; n1 *= 10)
412 kprintf("DELAY(%d)...", n);
415 * Guard against the timer being uninitialized if we are called
416 * early for console i/o.
418 if (timer0_state == RELEASED)
422 * Read the counter first, so that the rest of the setup overhead is
423 * counted. Then calculate the number of hardware timer ticks
424 * required, rounding up to be sure we delay at least the requested
425 * number of microseconds.
427 prev_tick = sys_cputimer->count();
428 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
434 while (ticks_left > 0) {
435 tick = sys_cputimer->count();
439 delta = tick - prev_tick;
444 if (doswitch && ticks_left > 0)
449 kprintf(" %d calls to getit() at %d usec each\n",
450 getit_calls, (n + 5) / getit_calls);
461 DRIVERSLEEP(int usec)
463 globaldata_t gd = mycpu;
465 if (gd->gd_intr_nesting_level ||
466 gd->gd_spinlock_rd ||
467 gd->gd_spinlocks_wr) {
475 sysbeepstop(void *chan)
477 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
483 sysbeep(int pitch, int period)
485 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
488 * Nobody else is using timer2, we do not need the clock lock
490 outb(TIMER_CNTR2, pitch);
491 outb(TIMER_CNTR2, (pitch>>8));
493 /* enable counter2 output to speaker */
494 outb(IO_PPI, inb(IO_PPI) | 3);
496 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
502 * RTC support routines
513 val = inb(IO_RTC + 1);
520 writertc(u_char reg, u_char val)
526 outb(IO_RTC + 1, val);
527 inb(0x84); /* XXX work around wrong order in rtcin() */
534 return(bcd2bin(rtcin(port)));
538 calibrate_clocks(void)
541 u_int count, prev_count, tot_count;
542 int sec, start_sec, timeout;
545 kprintf("Calibrating clock(s) ... ");
546 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
550 /* Read the mc146818A seconds counter. */
552 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
553 sec = rtcin(RTC_SEC);
560 /* Wait for the mC146818A seconds counter to change. */
563 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
564 sec = rtcin(RTC_SEC);
565 if (sec != start_sec)
572 /* Start keeping track of the i8254 counter. */
573 prev_count = sys_cputimer->count();
579 old_tsc = 0; /* shut up gcc */
582 * Wait for the mc146818A seconds counter to change. Read the i8254
583 * counter for each iteration since this is convenient and only
584 * costs a few usec of inaccuracy. The timing of the final reads
585 * of the counters almost matches the timing of the initial reads,
586 * so the main cause of inaccuracy is the varying latency from
587 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
588 * rtcin(RTC_SEC) that returns a changed seconds count. The
589 * maximum inaccuracy from this cause is < 10 usec on 486's.
593 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
594 sec = rtcin(RTC_SEC);
595 count = sys_cputimer->count();
596 tot_count += (int)(count - prev_count);
598 if (sec != start_sec)
605 * Read the cpu cycle counter. The timing considerations are
606 * similar to those for the i8254 clock.
609 tsc_frequency = rdtsc() - old_tsc;
613 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
614 kprintf("i8254 clock: %u Hz\n", tot_count);
618 kprintf("failed, using default i8254 clock of %u Hz\n",
619 i8254_cputimer.freq);
620 return (i8254_cputimer.freq);
626 timer0_state = ACQUIRED;
631 * Timer0 is our fine-grained variable clock interrupt
633 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
634 outb(TIMER_CNTR0, 2); /* lsb */
635 outb(TIMER_CNTR0, 0); /* msb */
639 cputimer_intr_register(&i8254_cputimer_intr);
640 cputimer_intr_select(&i8254_cputimer_intr, 0);
644 * Timer1 or timer2 is our free-running clock, but only if another
645 * has not been selected.
647 cputimer_register(&i8254_cputimer);
648 cputimer_select(&i8254_cputimer, 0);
652 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
657 * Should we use timer 1 or timer 2 ?
660 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
661 if (which != 1 && which != 2)
666 timer->name = "i8254_timer1";
667 timer->type = CPUTIMER_8254_SEL1;
668 i8254_walltimer_sel = TIMER_SEL1;
669 i8254_walltimer_cntr = TIMER_CNTR1;
670 timer1_state = ACQUIRED;
673 timer->name = "i8254_timer2";
674 timer->type = CPUTIMER_8254_SEL2;
675 i8254_walltimer_sel = TIMER_SEL2;
676 i8254_walltimer_cntr = TIMER_CNTR2;
677 timer2_state = ACQUIRED;
681 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
684 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
685 outb(i8254_walltimer_cntr, 0); /* lsb */
686 outb(i8254_walltimer_cntr, 0); /* msb */
687 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
692 i8254_cputimer_destruct(struct cputimer *timer)
694 switch(timer->type) {
695 case CPUTIMER_8254_SEL1:
696 timer1_state = RELEASED;
698 case CPUTIMER_8254_SEL2:
699 timer2_state = RELEASED;
710 /* Restore all of the RTC's "status" (actually, control) registers. */
711 writertc(RTC_STATUSB, RTCSB_24HR);
712 writertc(RTC_STATUSA, rtc_statusa);
713 writertc(RTC_STATUSB, rtc_statusb);
717 * Restore all the timers.
719 * This function is called to resynchronize our core timekeeping after a
720 * long halt, e.g. from apm_default_resume() and friends. It is also
721 * called if after a BIOS call we have detected munging of the 8254.
722 * It is necessary because cputimer_count() counter's delta may have grown
723 * too large for nanouptime() and friends to handle, or (in the case of 8254
724 * munging) might cause the SYSTIMER code to prematurely trigger.
730 i8254_restore(); /* restore timer_freq and hz */
731 rtc_restore(); /* reenable RTC interrupts */
736 * Initialize 8254 timer 0 early so that it can be used in DELAY().
744 * Can we use the TSC?
746 if (cpu_feature & CPUID_TSC)
752 * Initial RTC state, don't do anything unexpected
754 writertc(RTC_STATUSA, rtc_statusa);
755 writertc(RTC_STATUSB, RTCSB_24HR);
758 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
759 * generate an interrupt, which we will ignore for now.
761 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
762 * (so it counts a full 2^16 and repeats). We will use this timer
766 freq = calibrate_clocks();
767 #ifdef CLK_CALIBRATION_LOOP
770 "Press a key on the console to abort clock calibration\n");
771 while (cncheckc() == -1)
777 * Use the calibrated i8254 frequency if it seems reasonable.
778 * Otherwise use the default, and don't use the calibrated i586
781 delta = freq > i8254_cputimer.freq ?
782 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
783 if (delta < i8254_cputimer.freq / 100) {
784 #ifndef CLK_USE_I8254_CALIBRATION
787 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
788 freq = i8254_cputimer.freq;
792 * Interrupt timer's freq must be adjusted
793 * before we change the cuptimer's frequency.
795 i8254_cputimer_intr.freq = freq;
796 cputimer_set_frequency(&i8254_cputimer, freq);
800 "%d Hz differs from default of %d Hz by more than 1%%\n",
801 freq, i8254_cputimer.freq);
805 #ifndef CLK_USE_TSC_CALIBRATION
806 if (tsc_frequency != 0) {
809 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
813 if (tsc_present && tsc_frequency == 0) {
815 * Calibration of the i586 clock relative to the mc146818A
816 * clock failed. Do a less accurate calibration relative
817 * to the i8254 clock.
819 u_int64_t old_tsc = rdtsc();
822 tsc_frequency = rdtsc() - old_tsc;
823 #ifdef CLK_USE_TSC_CALIBRATION
825 kprintf("TSC clock: %llu Hz (Method B)\n",
831 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
835 * We can not use the TSC in SMP mode, until we figure out a
836 * cheap (impossible), reliable and precise (yeah right!) way
837 * to synchronize the TSCs of all the CPUs.
838 * Curse Intel for leaving the counter out of the I/O APIC.
843 * We can not use the TSC if we support APM. Precise timekeeping
844 * on an APM'ed machine is at best a fools pursuit, since
845 * any and all of the time spent in various SMM code can't
846 * be reliably accounted for. Reading the RTC is your only
847 * source of reliable time info. The i8254 looses too of course
848 * but we need to have some kind of time...
849 * We don't know at this point whether APM is going to be used
850 * or not, nor when it might be activated. Play it safe.
853 #endif /* NAPM > 0 */
855 #endif /* !defined(SMP) */
859 * Sync the time of day back to the RTC on shutdown, but only if
860 * we have already loaded it and have not crashed.
863 resettodr_on_shutdown(void *arg __unused)
865 if (rtc_loaded && panicstr == NULL) {
871 * Initialize the time of day register, based on the time base which is, e.g.
875 inittodr(time_t base)
877 unsigned long sec, days;
889 /* Look if we have a RTC present and the time is valid */
890 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
893 /* wait for time update to complete */
894 /* If RTCSA_TUP is zero, we have at least 244us before next update */
896 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
902 #ifdef USE_RTC_CENTURY
903 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
905 year = readrtc(RTC_YEAR) + 1900;
913 month = readrtc(RTC_MONTH);
914 for (m = 1; m < month; m++)
915 days += daysinmonth[m-1];
916 if ((month > 2) && LEAPYEAR(year))
918 days += readrtc(RTC_DAY) - 1;
920 for (y = 1970; y < year; y++)
921 days += DAYSPERYEAR + LEAPYEAR(y);
922 sec = ((( days * 24 +
923 readrtc(RTC_HRS)) * 60 +
924 readrtc(RTC_MIN)) * 60 +
926 /* sec now contains the number of seconds, since Jan 1 1970,
927 in the local time zone */
929 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
931 y = time_second - sec;
932 if (y <= -2 || y >= 2) {
933 /* badly off, adjust it */
943 kprintf("Invalid time in real time clock.\n");
944 kprintf("Check and reset the date immediately!\n");
948 * Write system time back to RTC
965 /* Disable RTC updates and interrupts. */
966 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
968 /* Calculate local time to put in RTC */
970 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
972 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
973 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
974 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
976 /* We have now the days since 01-01-1970 in tm */
977 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
978 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
980 y++, m = DAYSPERYEAR + LEAPYEAR(y))
983 /* Now we have the years in y and the day-of-the-year in tm */
984 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
985 #ifdef USE_RTC_CENTURY
986 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
992 if (m == 1 && LEAPYEAR(y))
999 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
1000 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
1002 /* Reenable RTC updates and interrupts. */
1003 writertc(RTC_STATUSB, rtc_statusb);
1009 * Start both clocks running. DragonFly note: the stat clock is no longer
1010 * used. Instead, 8254 based systimers are used for all major clock
1011 * interrupts. statclock_disable is set by default.
1014 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1018 int apic_8254_trial;
1020 #endif /* APIC_IO */
1022 callout_init(&sysbeepstop_ch);
1024 if (!selected && i8254_intr_disable) {
1025 i8254_nointr = 1; /* don't try to register again */
1026 cputimer_intr_deregister(cti);
1030 if (statclock_disable) {
1032 * The stat interrupt mask is different without the
1033 * statistics clock. Also, don't set the interrupt
1034 * flag which would normally cause the RTC to generate
1037 rtc_statusb = RTCSB_24HR;
1039 /* Setting stathz to nonzero early helps avoid races. */
1040 stathz = RTC_NOPROFRATE;
1041 profhz = RTC_PROFRATE;
1044 /* Finish initializing 8253 timer 0. */
1047 apic_8254_intr = isa_apic_irq(0);
1048 apic_8254_trial = 0;
1049 if (apic_8254_intr >= 0 ) {
1050 if (apic_int_type(0, 0) == 3)
1051 apic_8254_trial = 1;
1053 /* look for ExtInt on pin 0 */
1054 if (apic_int_type(0, 0) == 3) {
1055 apic_8254_intr = apic_irq(0, 0);
1056 setup_8254_mixed_mode();
1058 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1061 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk",
1063 INTR_EXCL | INTR_FAST |
1064 INTR_NOPOLL | INTR_MPSAFE |
1066 machintr_intren(apic_8254_intr);
1070 register_int(0, clkintr, NULL, "clk", NULL,
1071 INTR_EXCL | INTR_FAST |
1072 INTR_NOPOLL | INTR_MPSAFE |
1074 machintr_intren(ICU_IRQ0);
1076 #endif /* APIC_IO */
1078 /* Initialize RTC. */
1079 writertc(RTC_STATUSA, rtc_statusa);
1080 writertc(RTC_STATUSB, RTCSB_24HR);
1082 if (statclock_disable == 0) {
1083 diag = rtcin(RTC_DIAG);
1085 kprintf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1088 if (isa_apic_irq(8) != 8)
1089 panic("APIC RTC != 8");
1090 #endif /* APIC_IO */
1092 register_int(8, (inthand2_t *)rtcintr, NULL, "rtc", NULL,
1093 INTR_EXCL | INTR_FAST | INTR_NOPOLL |
1097 writertc(RTC_STATUSB, rtc_statusb);
1101 if (apic_8254_trial) {
1106 * Following code assumes the 8254 is the cpu timer,
1107 * so make sure it is.
1109 KKASSERT(sys_cputimer == &i8254_cputimer);
1110 KKASSERT(cti == &i8254_cputimer_intr);
1112 lastcnt = get_interrupt_counter(apic_8254_intr);
1115 * Force an 8254 Timer0 interrupt and wait 1/100s for
1116 * it to happen, then see if we got it.
1118 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
1119 i8254_intr_reload(cti, 2);
1120 base = sys_cputimer->count();
1121 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1123 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) {
1125 * The MP table is broken.
1126 * The 8254 was not connected to the specified pin
1128 * Workaround: Limited variant of mixed mode.
1130 machintr_intrdis(apic_8254_intr);
1131 unregister_int(clkdesc);
1132 kprintf("APIC_IO: Broken MP table detected: "
1133 "8254 is not connected to "
1134 "IOAPIC #%d intpin %d\n",
1135 int_to_apicintpin[apic_8254_intr].ioapic,
1136 int_to_apicintpin[apic_8254_intr].int_pin);
1138 * Revoke current ISA IRQ 0 assignment and
1139 * configure a fallback interrupt routing from
1140 * the 8254 Timer via the 8259 PIC to the
1141 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1142 * We reuse the low level interrupt handler number.
1144 if (apic_irq(0, 0) < 0) {
1145 revoke_apic_irq(apic_8254_intr);
1146 assign_apic_irq(0, 0, apic_8254_intr);
1148 apic_8254_intr = apic_irq(0, 0);
1149 setup_8254_mixed_mode();
1150 register_int(apic_8254_intr, clkintr, NULL, "clk",
1152 INTR_EXCL | INTR_FAST |
1153 INTR_NOPOLL | INTR_MPSAFE |
1155 machintr_intren(apic_8254_intr);
1158 if (apic_int_type(0, 0) != 3 ||
1159 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1160 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1161 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1162 int_to_apicintpin[apic_8254_intr].ioapic,
1163 int_to_apicintpin[apic_8254_intr].int_pin);
1166 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1174 setup_8254_mixed_mode(void)
1177 * Allow 8254 timer to INTerrupt 8259:
1178 * re-initialize master 8259:
1179 * reset; prog 4 bytes, single ICU, edge triggered
1181 outb(IO_ICU1, 0x13);
1182 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
1183 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1184 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1185 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1187 /* program IO APIC for type 3 INT on INT0 */
1188 if (ext_int_setup(0, 0) < 0)
1189 panic("8254 redirect via APIC pin0 impossible!");
1194 setstatclockrate(int newhz)
1196 if (newhz == RTC_PROFRATE)
1197 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1199 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1200 writertc(RTC_STATUSA, rtc_statusa);
1205 tsc_get_timecount(struct timecounter *tc)
1211 #ifdef KERN_TIMESTAMP
1212 #define KERN_TIMESTAMP_SIZE 16384
1213 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1214 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1215 sizeof(tsc), "LU", "Kernel timestamps");
1221 tsc[i] = (u_int32_t)rdtsc();
1224 if (i >= KERN_TIMESTAMP_SIZE)
1226 tsc[i] = 0; /* mark last entry */
1228 #endif /* KERN_TIMESTAMP */
1235 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1242 if (sys_cputimer == &i8254_cputimer)
1243 count = sys_cputimer->count();
1251 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1252 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1255 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1256 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1258 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1259 0, 0, hw_i8254_timestamp, "A", "");
1261 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1262 &tsc_present, 0, "TSC Available");
1263 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1264 &tsc_frequency, 0, "TSC Frequency");