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drm - Add valleyview support
[dragonfly.git] / sys / dev / drm / i915 / i915_drv.c
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e555d299 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
7f3c3d6f 2 */
e555d299
FT		 3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7f3c3d6f
HT		 6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
e555d299
FT		 9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
7f3c3d6f 15 *
e555d299
FT		 16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
7f3c3d6f 19 *
e555d299
FT		 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
7f3c3d6f 27 *
7f3c3d6f
HT		 28 */
29
18e26a6d 30#include <drm/drmP.h>
5c6c6f23 31#include <drm/i915_drm.h>
c4a9e910 32#include "i915_drv.h"
18e26a6d 33#include <drm/drm_pciids.h>
e3adcf8f 34#include "intel_drv.h"
7f3c3d6f 35
9edbd4a0
FT		 36#include <linux/module.h>
37#include <drm/drm_crtc_helper.h>
38
39static int i915_modeset __read_mostly = 1;
40TUNABLE_INT("drm.i915.modeset", &i915_modeset);
41module_param_named(modeset, i915_modeset, int, 0400);
42MODULE_PARM_DESC(modeset,
43 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
44 "1=on, -1=force vga console preference [default])");
45
46unsigned int i915_fbpercrtc __always_unused = 0;
47module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
48
49int i915_panel_ignore_lid __read_mostly = 1;
50TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
51module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
55
56unsigned int i915_powersave __read_mostly = 1;
57TUNABLE_INT("drm.i915.powersave", &i915_powersave);
58module_param_named(powersave, i915_powersave, int, 0600);
59MODULE_PARM_DESC(powersave,
60 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61
62int i915_semaphores __read_mostly = -1;
63TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
64module_param_named(semaphores, i915_semaphores, int, 0400);
65MODULE_PARM_DESC(semaphores,
66 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
67
68int i915_enable_rc6 __read_mostly = -1;
69TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
70module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
71MODULE_PARM_DESC(i915_enable_rc6,
72 "Enable power-saving render C-state 6. "
73 "Different stages can be selected via bitmask values "
74 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
75 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
76 "default: -1 (use per-chip default)");
77
78int i915_enable_fbc __read_mostly = -1;
79TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
80module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
81MODULE_PARM_DESC(i915_enable_fbc,
82 "Enable frame buffer compression for power savings "
83 "(default: -1 (use per-chip default))");
84
85unsigned int i915_lvds_downclock __read_mostly = 0;
86TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
87module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
88MODULE_PARM_DESC(lvds_downclock,
89 "Use panel (LVDS/eDP) downclocking for power savings "
90 "(default: false)");
91
19df918d
FT		 92int i915_lvds_channel_mode __read_mostly = 0;
93TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
9edbd4a0
FT		 94module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
95MODULE_PARM_DESC(lvds_channel_mode,
96 "Specify LVDS channel mode "
97 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
19df918d 98
9edbd4a0
FT		 99int i915_panel_use_ssc __read_mostly = -1;
100TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
101module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
102MODULE_PARM_DESC(lvds_use_ssc,
103 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
104 "(default: auto from VBT)");
105
106int i915_vbt_sdvo_panel_type __read_mostly = -1;
107TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
108module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
109MODULE_PARM_DESC(vbt_sdvo_panel_type,
110 "Override/Ignore selection of SDVO panel mode in the VBT "
111 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
112
113static int i915_try_reset = 1;
114TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
115module_param_named(reset, i915_try_reset, bool, 0600);
116MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
a2fdbec6
FT		 117
118bool i915_enable_hangcheck __read_mostly = true;
119module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
120MODULE_PARM_DESC(enable_hangcheck,
121 "Periodically check GPU activity for detecting hangs. "
122 "WARNING: Disabling this can cause system wide hangs. "
123 "(default: true)");
124
9edbd4a0
FT		 125int i915_enable_ppgtt __read_mostly = -1;
126TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
127module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0400);
128MODULE_PARM_DESC(i915_enable_ppgtt,
129 "Enable PPGTT (default: true)");
130
131int i915_enable_psr __read_mostly = 0;
132module_param_named(enable_psr, i915_enable_psr, int, 0600);
133MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
134
135unsigned int i915_preliminary_hw_support __read_mostly = 1;
136module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
137MODULE_PARM_DESC(preliminary_hw_support,
138 "Enable preliminary hardware support.");
139
140int i915_disable_power_well __read_mostly = 1;
141module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
142MODULE_PARM_DESC(disable_power_well,
143 "Disable the power well when possible (default: true)");
144
5d0b1887
FT		 145int i915_enable_ips __read_mostly = 1;
146module_param_named(enable_ips, i915_enable_ips, int, 0600);
147MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
148
9edbd4a0
FT		 149bool i915_fastboot __read_mostly = 0;
150module_param_named(fastboot, i915_fastboot, bool, 0600);
151MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
152 "(default: false)");
f0b54121 153
9edbd4a0
FT		 154int i915_enable_pc8 __read_mostly = 1;
155module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
156MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
8e26cdf6 157
9edbd4a0
FT		 158int i915_pc8_timeout __read_mostly = 5000;
159module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
160MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
161
162bool i915_prefault_disable __read_mostly;
163module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
164MODULE_PARM_DESC(prefault_disable,
165 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
166
167static struct drm_driver driver;
e9243325 168
e3adcf8f 169static const struct intel_device_info intel_i830_info = {
8e26cdf6 170 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
e3adcf8f 171 .has_overlay = 1, .overlay_needs_physical = 1,
9edbd4a0 172 .ring_mask = RENDER_RING,
e3adcf8f
FT		 173};
174
175static const struct intel_device_info intel_845g_info = {
8e26cdf6 176 .gen = 2, .num_pipes = 1,
e3adcf8f 177 .has_overlay = 1, .overlay_needs_physical = 1,
9edbd4a0 178 .ring_mask = RENDER_RING,
e3adcf8f
FT		 179};
180
181static const struct intel_device_info intel_i85x_info = {
8e26cdf6 182 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
e3adcf8f
FT		 183 .cursor_needs_physical = 1,
184 .has_overlay = 1, .overlay_needs_physical = 1,
9edbd4a0
FT		 185 .has_fbc = 1,
186 .ring_mask = RENDER_RING,
e3adcf8f
FT		 187};
188
189static const struct intel_device_info intel_i865g_info = {
8e26cdf6 190 .gen = 2, .num_pipes = 1,
e3adcf8f 191 .has_overlay = 1, .overlay_needs_physical = 1,
9edbd4a0 192 .ring_mask = RENDER_RING,
e3adcf8f
FT		 193};
194
195static const struct intel_device_info intel_i915g_info = {
8e26cdf6 196 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
e3adcf8f 197 .has_overlay = 1, .overlay_needs_physical = 1,
9edbd4a0 198 .ring_mask = RENDER_RING,
e3adcf8f
FT		 199};
200static const struct intel_device_info intel_i915gm_info = {
8e26cdf6 201 .gen = 3, .is_mobile = 1, .num_pipes = 2,
e3adcf8f
FT		 202 .cursor_needs_physical = 1,
203 .has_overlay = 1, .overlay_needs_physical = 1,
204 .supports_tv = 1,
9edbd4a0
FT		 205 .has_fbc = 1,
206 .ring_mask = RENDER_RING,
e3adcf8f
FT		 207};
208static const struct intel_device_info intel_i945g_info = {
8e26cdf6 209 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
e3adcf8f 210 .has_overlay = 1, .overlay_needs_physical = 1,
9edbd4a0 211 .ring_mask = RENDER_RING,
e3adcf8f
FT		 212};
213static const struct intel_device_info intel_i945gm_info = {
8e26cdf6 214 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
e3adcf8f
FT		 215 .has_hotplug = 1, .cursor_needs_physical = 1,
216 .has_overlay = 1, .overlay_needs_physical = 1,
217 .supports_tv = 1,
9edbd4a0
FT		 218 .has_fbc = 1,
219 .ring_mask = RENDER_RING,
e3adcf8f
FT		 220};
221
222static const struct intel_device_info intel_i965g_info = {
8e26cdf6 223 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
e3adcf8f
FT		 224 .has_hotplug = 1,
225 .has_overlay = 1,
9edbd4a0 226 .ring_mask = RENDER_RING,
e3adcf8f
FT		 227};
228
229static const struct intel_device_info intel_i965gm_info = {
8e26cdf6 230 .gen = 4, .is_crestline = 1, .num_pipes = 2,
e3adcf8f
FT		 231 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
232 .has_overlay = 1,
233 .supports_tv = 1,
9edbd4a0 234 .ring_mask = RENDER_RING,
e3adcf8f
FT		 235};
236
237static const struct intel_device_info intel_g33_info = {
8e26cdf6 238 .gen = 3, .is_g33 = 1, .num_pipes = 2,
e3adcf8f
FT		 239 .need_gfx_hws = 1, .has_hotplug = 1,
240 .has_overlay = 1,
9edbd4a0 241 .ring_mask = RENDER_RING,
e3adcf8f
FT		 242};
243
244static const struct intel_device_info intel_g45_info = {
8e26cdf6 245 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
e3adcf8f 246 .has_pipe_cxsr = 1, .has_hotplug = 1,
9edbd4a0 247 .ring_mask = RENDER_RING | BSD_RING,
e3adcf8f
FT		 248};
249
250static const struct intel_device_info intel_gm45_info = {
8e26cdf6 251 .gen = 4, .is_g4x = 1, .num_pipes = 2,
e3adcf8f
FT		 252 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
253 .has_pipe_cxsr = 1, .has_hotplug = 1,
254 .supports_tv = 1,
9edbd4a0 255 .ring_mask = RENDER_RING | BSD_RING,
e3adcf8f
FT		 256};
257
258static const struct intel_device_info intel_pineview_info = {
8e26cdf6 259 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
e3adcf8f
FT		 260 .need_gfx_hws = 1, .has_hotplug = 1,
261 .has_overlay = 1,
262};
263
264static const struct intel_device_info intel_ironlake_d_info = {
8e26cdf6 265 .gen = 5, .num_pipes = 2,
e3adcf8f 266 .need_gfx_hws = 1, .has_hotplug = 1,
9edbd4a0 267 .ring_mask = RENDER_RING | BSD_RING,
e3adcf8f
FT		 268};
269
270static const struct intel_device_info intel_ironlake_m_info = {
8e26cdf6 271 .gen = 5, .is_mobile = 1, .num_pipes = 2,
e3adcf8f 272 .need_gfx_hws = 1, .has_hotplug = 1,
00dca1bb 273 .has_fbc = 1,
9edbd4a0 274 .ring_mask = RENDER_RING | BSD_RING,
e3adcf8f
FT		 275};
276
277static const struct intel_device_info intel_sandybridge_d_info = {
8e26cdf6 278 .gen = 6, .num_pipes = 2,
e3adcf8f 279 .need_gfx_hws = 1, .has_hotplug = 1,
9edbd4a0
FT		 280 .has_fbc = 1,
281 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
e3adcf8f
FT		 282 .has_llc = 1,
283};
284
285static const struct intel_device_info intel_sandybridge_m_info = {
8e26cdf6 286 .gen = 6, .is_mobile = 1, .num_pipes = 2,
e3adcf8f
FT		 287 .need_gfx_hws = 1, .has_hotplug = 1,
288 .has_fbc = 1,
9edbd4a0 289 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
e3adcf8f
FT		 290 .has_llc = 1,
291};
292
8e26cdf6
FT		 293#define GEN7_FEATURES \
294 .gen = 7, .num_pipes = 3, \
295 .need_gfx_hws = 1, .has_hotplug = 1, \
9edbd4a0
FT		 296 .has_fbc = 1, \
297 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
298 .has_llc = 1
8e26cdf6 299
e3adcf8f 300static const struct intel_device_info intel_ivybridge_d_info = {
8e26cdf6
FT		 301 GEN7_FEATURES,
302 .is_ivybridge = 1,
e3adcf8f
FT		 303};
304
305static const struct intel_device_info intel_ivybridge_m_info = {
8e26cdf6
FT		 306 GEN7_FEATURES,
307 .is_ivybridge = 1,
308 .is_mobile = 1,
309};
310
311static const struct intel_device_info intel_ivybridge_q_info = {
312 GEN7_FEATURES,
313 .is_ivybridge = 1,
314 .num_pipes = 0, /* legal, last one wins */
e3adcf8f
FT		 315};
316
e9243325 317static const struct intel_device_info intel_valleyview_m_info = {
8e26cdf6
FT		 318 GEN7_FEATURES,
319 .is_mobile = 1,
320 .num_pipes = 2,
e9243325 321 .is_valleyview = 1,
a2fdbec6 322 .display_mmio_offset = VLV_DISPLAY_BASE,
9edbd4a0 323 .has_fbc = 0, /* legal, last one wins */
8e26cdf6 324 .has_llc = 0, /* legal, last one wins */
e9243325
FT		 325};
326
327static const struct intel_device_info intel_valleyview_d_info = {
8e26cdf6
FT		 328 GEN7_FEATURES,
329 .num_pipes = 2,
e9243325 330 .is_valleyview = 1,
a2fdbec6 331 .display_mmio_offset = VLV_DISPLAY_BASE,
9edbd4a0 332 .has_fbc = 0, /* legal, last one wins */
8e26cdf6 333 .has_llc = 0, /* legal, last one wins */
e9243325
FT		 334};
335
336static const struct intel_device_info intel_haswell_d_info = {
8e26cdf6
FT		 337 GEN7_FEATURES,
338 .is_haswell = 1,
5d0b1887
FT		 339 .has_ddi = 1,
340 .has_fpga_dbg = 1,
9edbd4a0 341 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
e9243325
FT		 342};
343
344static const struct intel_device_info intel_haswell_m_info = {
8e26cdf6
FT		 345 GEN7_FEATURES,
346 .is_haswell = 1,
347 .is_mobile = 1,
5d0b1887
FT		 348 .has_ddi = 1,
349 .has_fpga_dbg = 1,
9edbd4a0
FT		 350 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
351};
352
353static const struct intel_device_info intel_broadwell_d_info = {
354 .gen = 8, .num_pipes = 3,
355 .need_gfx_hws = 1, .has_hotplug = 1,
356 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
357 .has_llc = 1,
358 .has_ddi = 1,
e9243325 359};
e3adcf8f 360
9edbd4a0
FT		 361static const struct intel_device_info intel_broadwell_m_info = {
362 .gen = 8, .is_mobile = 1, .num_pipes = 3,
363 .need_gfx_hws = 1, .has_hotplug = 1,
364 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
365 .has_llc = 1,
366 .has_ddi = 1,
367};
368
369/*
370 * Make sure any device matches here are from most specific to most
371 * general. For example, since the Quanta match is based on the subsystem
372 * and subvendor IDs, we need it to come before the more general IVB
373 * PCI ID matches, otherwise we'll use the wrong info struct above.
374 */
375#define INTEL_PCI_IDS \
376 INTEL_I830_IDS(&intel_i830_info), \
377 INTEL_I845G_IDS(&intel_845g_info), \
378 INTEL_I85X_IDS(&intel_i85x_info), \
379 INTEL_I865G_IDS(&intel_i865g_info), \
380 INTEL_I915G_IDS(&intel_i915g_info), \
381 INTEL_I915GM_IDS(&intel_i915gm_info), \
382 INTEL_I945G_IDS(&intel_i945g_info), \
383 INTEL_I945GM_IDS(&intel_i945gm_info), \
384 INTEL_I965G_IDS(&intel_i965g_info), \
385 INTEL_G33_IDS(&intel_g33_info), \
386 INTEL_I965GM_IDS(&intel_i965gm_info), \
387 INTEL_GM45_IDS(&intel_gm45_info), \
388 INTEL_G45_IDS(&intel_g45_info), \
389 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
390 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
391 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
392 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
393 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
394 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
395 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
396 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
397 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
398 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
399 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
400 INTEL_BDW_M_IDS(&intel_broadwell_m_info), \
401 INTEL_BDW_D_IDS(&intel_broadwell_d_info)
402
8e26cdf6 403static const struct pci_device_id pciidlist[] = { /* aka */
9edbd4a0 404 INTEL_PCI_IDS,
e3adcf8f
FT		 405 {0, 0}
406};
407
e9243325
FT		 408#define PCI_VENDOR_INTEL 0x8086
409
410void intel_detect_pch(struct drm_device *dev)
411{
412 struct drm_i915_private *dev_priv = dev->dev_private;
9edbd4a0 413 struct device *pch = NULL;
27a0f882 414 struct pci_devinfo *di;
e9243325 415
8e26cdf6
FT		 416 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
417 * (which really amounts to a PCH but no South Display).
418 */
419 if (INTEL_INFO(dev)->num_pipes == 0) {
420 dev_priv->pch_type = PCH_NOP;
8e26cdf6
FT		 421 return;
422 }
423
9edbd4a0
FT		 424 /* XXX The ISA bridge probe causes some old Core2 machines to hang */
425 if (INTEL_INFO(dev)->gen < 5)
426 return;
427
e9243325
FT		 428 /*
429 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
430 * make graphics device passthrough work easy for VMM, that only
431 * need to expose ISA bridge to let driver know the real hardware
432 * underneath. This is a requirement from virtualization team.
9edbd4a0
FT		 433 *
434 * In some virtualized environments (e.g. XEN), there is irrelevant
435 * ISA bridge in the system. To work reliably, we should scan trhough
436 * all the ISA bridge devices and check for the first match, instead
437 * of only checking the first one.
e9243325 438 */
27a0f882
MD		 439 di = NULL;
440
441 while ((pch = pci_iterate_class(&di, PCIC_BRIDGE, PCIS_BRIDGE_ISA))) {
e9243325 442 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
9edbd4a0 443 unsigned short id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
e9243325
FT		 444 dev_priv->pch_id = id;
445
446 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
447 dev_priv->pch_type = PCH_IBX;
e9243325
FT		 448 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
449 WARN_ON(!IS_GEN5(dev));
450 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
451 dev_priv->pch_type = PCH_CPT;
e9243325
FT		 452 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
453 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
454 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
455 /* PantherPoint is CPT compatible */
456 dev_priv->pch_type = PCH_CPT;
9edbd4a0 457 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
e9243325
FT		 458 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
459 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
460 dev_priv->pch_type = PCH_LPT;
e9243325
FT		 461 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
462 WARN_ON(!IS_HASWELL(dev));
8e26cdf6 463 WARN_ON(IS_ULT(dev));
9edbd4a0
FT		 464 } else if (IS_BROADWELL(dev)) {
465 dev_priv->pch_type = PCH_LPT;
466 dev_priv->pch_id =
467 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
468 DRM_DEBUG_KMS("This is Broadwell, assuming "
469 "LynxPoint LP PCH\n");
e9243325
FT		 470 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
471 dev_priv->pch_type = PCH_LPT;
e9243325
FT		 472 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
473 WARN_ON(!IS_HASWELL(dev));
8e26cdf6 474 WARN_ON(!IS_ULT(dev));
9edbd4a0
FT		 475 } else
476 continue;
477
478 break;
e9243325 479 }
9edbd4a0
FT		 480 }
481 if (!pch)
482 DRM_DEBUG_KMS("No PCH found.\n");
483
e9243325 484#if 0
9edbd4a0 485 pci_dev_put(pch);
e9243325 486#endif
e9243325
FT		 487}
488
3d4007e0
FT		 489bool i915_semaphore_is_enabled(struct drm_device *dev)
490{
491 if (INTEL_INFO(dev)->gen < 6)
9edbd4a0
FT		 492 return false;
493
494 /* Until we get further testing... */
495 if (IS_GEN8(dev)) {
496 WARN_ON(!i915_preliminary_hw_support);
497 return false;
498 }
3d4007e0
FT		 499
500 if (i915_semaphores >= 0)
501 return i915_semaphores;
502
503#ifdef CONFIG_INTEL_IOMMU
504 /* Enable semaphores on SNB when IO remapping is off */
505 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
506 return false;
507#endif
508
9edbd4a0 509 return true;
3d4007e0
FT		 510}
511
e3adcf8f 512static int i915_drm_freeze(struct drm_device *dev)
7f3c3d6f 513{
e9243325 514 struct drm_i915_private *dev_priv = dev->dev_private;
8e26cdf6 515 struct drm_crtc *crtc;
b3705d71 516
9edbd4a0
FT		 517 intel_runtime_pm_get(dev_priv);
518
a2fdbec6
FT		 519 /* ignore lid events during suspend */
520 mutex_lock(&dev_priv->modeset_restore_lock);
521 dev_priv->modeset_restore = MODESET_SUSPENDED;
522 mutex_unlock(&dev_priv->modeset_restore_lock);
523
9edbd4a0
FT		 524 /* We do a lot of poking in a lot of registers, make sure they work
525 * properly. */
526 hsw_disable_package_c8(dev_priv);
527 intel_display_set_init_power(dev, true);
a2fdbec6 528
e3adcf8f
FT		 529 drm_kms_helper_poll_disable(dev);
530
531#if 0
532 pci_save_state(dev->pdev);
533#endif
b3705d71 534
e3adcf8f
FT		 535 /* If KMS is active, we do the leavevt stuff here */
536 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
9edbd4a0
FT		 537 int error;
538
539 error = i915_gem_suspend(dev);
e3adcf8f 540 if (error) {
a2fdbec6
FT		 541 dev_err(dev->pdev->dev,
542 "GEM idle failed, resume might fail\n");
e9243325 543 return error;
e3adcf8f 544 }
a2fdbec6 545
e9243325
FT		 546 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
547
e3adcf8f 548 drm_irq_uninstall(dev);
a2fdbec6 549 dev_priv->enable_hotplug_processing = false;
8e26cdf6
FT		 550 /*
551 * Disable CRTCs directly since we want to preserve sw state
552 * for _thaw.
553 */
9edbd4a0 554 mutex_lock(&dev->mode_config.mutex);
8e26cdf6
FT		 555 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
556 dev_priv->display.crtc_disable(crtc);
9edbd4a0 557 mutex_unlock(&dev->mode_config.mutex);
5d0b1887
FT		 558
559 intel_modeset_suspend_hw(dev);
e3adcf8f
FT		 560 }
561
9edbd4a0
FT		 562 i915_gem_suspend_gtt_mappings(dev);
563
b3705d71 564 i915_save_state(dev);
e3adcf8f
FT		 565
566 intel_opregion_fini(dev);
567
5d0b1887
FT		 568#if 0
569 console_lock();
570 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
571 console_unlock();
572#endif
573
e3adcf8f 574 return 0;
b3705d71
HT		 575}
576
9edbd4a0 577int i915_suspend(device_t kdev)
b3705d71 578{
9edbd4a0 579 struct drm_device *dev = device_get_softc(kdev);
e3adcf8f
FT		 580 int error;
581
9edbd4a0
FT		 582 if (!dev || !dev->dev_private) {
583 DRM_ERROR("dev: %p\n", dev);
e3adcf8f
FT		 584 DRM_ERROR("DRM not initialized, aborting suspend.\n");
585 return -ENODEV;
586 }
587
9edbd4a0
FT		 588 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
589 return 0;
590
e3adcf8f
FT		 591 error = i915_drm_freeze(dev);
592 if (error)
9edbd4a0
FT		 593 return error;
594
595#if 0
596 if (state.event == PM_EVENT_SUSPEND) {
597 /* Shut down the device */
598 pci_disable_device(dev->pdev);
599 pci_set_power_state(dev->pdev, PCI_D3hot);
600 }
601#endif
e3adcf8f
FT		 602
603 error = bus_generic_suspend(kdev);
e3adcf8f
FT		 604 return (error);
605}
606
5d0b1887
FT		 607#if 0
608void intel_console_resume(struct work_struct *work)
609{
610 struct drm_i915_private *dev_priv =
611 container_of(work, struct drm_i915_private,
612 console_resume_work);
613 struct drm_device *dev = dev_priv->dev;
614
615 console_lock();
616 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
617 console_unlock();
618}
619#endif
620
8e26cdf6
FT		 621static void intel_resume_hotplug(struct drm_device *dev)
622{
623 struct drm_mode_config *mode_config = &dev->mode_config;
624 struct intel_encoder *encoder;
625
626 mutex_lock(&mode_config->mutex);
627 DRM_DEBUG_KMS("running encoder hotplug functions\n");
628
629 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
630 if (encoder->hot_plug)
631 encoder->hot_plug(encoder);
632
633 mutex_unlock(&mode_config->mutex);
634
635 /* Just fire off a uevent and let userspace tell us what to do */
636 drm_helper_hpd_irq_event(dev);
637}
638
9edbd4a0 639static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
e3adcf8f
FT		 640{
641 struct drm_i915_private *dev_priv = dev->dev_private;
642 int error = 0;
b3705d71 643
9edbd4a0
FT		 644 intel_uncore_early_sanitize(dev);
645
646 intel_uncore_sanitize(dev);
647
648 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
649 restore_gtt_mappings) {
650 mutex_lock(&dev->struct_mutex);
651 i915_gem_restore_gtt_mappings(dev);
652 mutex_unlock(&dev->struct_mutex);
653 }
654
655 intel_power_domains_init_hw(dev);
656
b3705d71 657 i915_restore_state(dev);
e3adcf8f
FT		 658 intel_opregion_setup(dev);
659
660 /* KMS EnterVT equivalent */
661 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
19df918d
FT		 662 intel_init_pch_refclk(dev);
663
a2fdbec6 664 mutex_lock(&dev->struct_mutex);
e3adcf8f
FT		 665
666 error = i915_gem_init_hw(dev);
a2fdbec6
FT		 667 mutex_unlock(&dev->struct_mutex);
668
669 /* We need working interrupts for modeset enabling ... */
670 drm_irq_install(dev);
e3adcf8f 671
19df918d 672 intel_modeset_init_hw(dev);
8e26cdf6
FT		 673
674 drm_modeset_lock_all(dev);
9edbd4a0 675 drm_mode_config_reset(dev);
8e26cdf6
FT		 676 intel_modeset_setup_hw_state(dev, true);
677 drm_modeset_unlock_all(dev);
a2fdbec6
FT		 678
679 /*
680 * ... but also need to make sure that hotplug processing
681 * doesn't cause havoc. Like in the driver load code we don't
682 * bother with the tiny race here where we might loose hotplug
683 * notifications.
684 * */
685 intel_hpd_init(dev);
686 dev_priv->enable_hotplug_processing = true;
8e26cdf6
FT		 687 /* Config may have changed between suspend and resume */
688 intel_resume_hotplug(dev);
e3adcf8f
FT		 689 }
690
691 intel_opregion_init(dev);
692
a2fdbec6
FT		 693 /*
694 * The console lock can be pretty contented on resume due
695 * to all the printk activity. Try to keep it out of the hot
696 * path of resume if possible.
697 */
19df918d 698#if 0
a2fdbec6 699 if (console_trylock()) {
5d0b1887 700 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
a2fdbec6
FT		 701 console_unlock();
702 } else {
703 schedule_work(&dev_priv->console_resume_work);
704 }
19df918d 705#endif
a2fdbec6 706
9edbd4a0
FT		 707 /* Undo what we did at i915_drm_freeze so the refcount goes back to the
708 * expected level. */
709 hsw_enable_package_c8(dev_priv);
710
a2fdbec6
FT		 711 mutex_lock(&dev_priv->modeset_restore_lock);
712 dev_priv->modeset_restore = MODESET_DONE;
713 mutex_unlock(&dev_priv->modeset_restore_lock);
9edbd4a0
FT		 714
715 intel_runtime_pm_put(dev_priv);
a2fdbec6
FT		 716 return error;
717}
718
9edbd4a0 719#if 0
a2fdbec6
FT		 720static int i915_drm_thaw(struct drm_device *dev)
721{
9edbd4a0
FT		 722 if (drm_core_check_feature(dev, DRIVER_MODESET))
723 i915_check_and_clear_faults(dev);
a2fdbec6 724
9edbd4a0 725 return __i915_drm_thaw(dev, true);
b3705d71 726}
9edbd4a0 727#endif
b3705d71 728
9edbd4a0 729int i915_resume(struct drm_device *dev)
b3705d71 730{
5d0b1887 731 struct drm_i915_private *dev_priv = dev->dev_private;
e3adcf8f
FT		 732 int ret;
733
e3adcf8f 734#if 0
5d0b1887
FT		 735 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
736 return 0;
737
e3adcf8f
FT		 738 if (pci_enable_device(dev->pdev))
739 return -EIO;
b3705d71 740
e3adcf8f
FT		 741 pci_set_master(dev->pdev);
742#endif
b3705d71 743
5d0b1887
FT		 744 /*
745 * Platforms with opregion should have sane BIOS, older ones (gen3 and
9edbd4a0
FT		 746 * earlier) need to restore the GTT mappings since the BIOS might clear
747 * all our scratch PTEs.
5d0b1887 748 */
9edbd4a0 749 ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
5d0b1887
FT		 750 if (ret)
751 return ret;
752
753 drm_kms_helper_poll_enable(dev);
754 return 0;
7f3c3d6f
HT		 755}
756
62e5f8e8
FT		 757/* XXX Hack for the old *BSD drm code base
758 * The device id field is set at probe time */
759static drm_pci_id_list_t i915_attach_list[] = {
760 {0x8086, 0, 0, "Intel i915 GPU"},
761 {0, 0, 0, NULL}
762};
763
f0b54121 764/* static int __init i915_init(void) */
7f3c3d6f 765static int
b3705d71 766i915_attach(device_t kdev)
7f3c3d6f 767{
e3adcf8f 768 struct drm_device *dev;
b3705d71 769
e3adcf8f 770 dev = device_get_softc(kdev);
f0b54121
FT		 771
772 driver.num_ioctls = i915_max_ioctl;
773
e3adcf8f 774 if (i915_modeset == 1)
f0b54121
FT		 775 driver.driver_features |= DRIVER_MODESET;
776
777 dev->driver = &driver;
62e5f8e8 778 return (drm_attach(kdev, i915_attach_list));
b3705d71
HT		 779}
780
e3adcf8f
FT		 781const struct intel_device_info *
782i915_get_device_id(int device)
b3705d71 783{
8e26cdf6 784 const struct pci_device_id *did;
b3705d71 785
e3adcf8f
FT		 786 for (did = &pciidlist[0]; did->device != 0; did++) {
787 if (did->device != device)
788 continue;
8e26cdf6 789 return (struct intel_device_info *)did->driver_data;
e3adcf8f
FT		 790 }
791 return (NULL);
7f3c3d6f
HT		 792}
793
7f3c3d6f 794extern devclass_t drm_devclass;
e3adcf8f 795
e9243325
FT		 796/**
797 * i915_reset - reset chip after a hang
798 * @dev: drm device to reset
799 *
800 * Reset the chip. Useful if a hang is detected. Returns zero on successful
801 * reset or otherwise an error code.
802 *
803 * Procedure is fairly simple:
804 * - reset the chip using the reset reg
805 * - re-init context state
806 * - re-init hardware status page
807 * - re-init ring buffer
808 * - re-init interrupt state
809 * - re-init display
810 */
00640ec9 811int i915_reset(struct drm_device *dev)
e3adcf8f
FT		 812{
813 drm_i915_private_t *dev_priv = dev->dev_private;
5d0b1887 814 bool simulated;
e9243325
FT		 815 int ret;
816
817 if (!i915_try_reset)
818 return 0;
819
a2fdbec6 820 mutex_lock(&dev->struct_mutex);
e3adcf8f
FT		 821
822 i915_gem_reset(dev);
823
5d0b1887
FT		 824 simulated = dev_priv->gpu_error.stop_rings != 0;
825
9edbd4a0
FT		 826 ret = intel_gpu_reset(dev);
827
828 /* Also reset the gpu hangman. */
829 if (simulated) {
830 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
831 dev_priv->gpu_error.stop_rings = 0;
832 if (ret == -ENODEV) {
833 DRM_INFO("Reset not implemented, but ignoring "
834 "error for simulated gpu hangs\n");
835 ret = 0;
836 }
5d0b1887 837 }
9edbd4a0 838
e3adcf8f 839 if (ret) {
9edbd4a0 840 DRM_ERROR("Failed to reset chip: %i\n", ret);
a2fdbec6 841 mutex_unlock(&dev->struct_mutex);
00640ec9 842 return ret;
e3adcf8f
FT		 843 }
844
e9243325
FT		 845 /* Ok, now get things going again... */
846
847 /*
848 * Everything depends on having the GTT running, so we need to start
849 * there. Fortunately we don't need to do this unless we reset the
850 * chip at a PCI level.
851 *
852 * Next we need to restore the context, but we don't use those
853 * yet either...
854 *
855 * Ring buffer needs to be re-initialized in the KMS case, or if X
856 * was running at the time of the reset (i.e. we weren't VT
857 * switched away).
858 */
e3adcf8f 859 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
9edbd4a0
FT		 860 !dev_priv->ums.mm_suspended) {
861 dev_priv->ums.mm_suspended = 0;
00640ec9 862
9edbd4a0 863 ret = i915_gem_init_hw(dev);
a2fdbec6 864 mutex_unlock(&dev->struct_mutex);
9edbd4a0
FT		 865 if (ret) {
866 DRM_ERROR("Failed hw init on reset %d\n", ret);
867 return ret;
868 }
e3adcf8f 869
00640ec9
FT		 870 drm_irq_uninstall(dev);
871 drm_irq_install(dev);
a2fdbec6 872 intel_hpd_init(dev);
00640ec9 873 } else {
a2fdbec6 874 mutex_unlock(&dev->struct_mutex);
e3adcf8f
FT		 875 }
876
e9243325
FT		 877 return 0;
878}
879
a2fdbec6
FT		 880static int
881i915_pci_probe(device_t kdev)
882{
883 int device, i = 0;
884
885 if (pci_get_class(kdev) != PCIC_DISPLAY)
886 return ENXIO;
887
888 if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL)
889 return ENXIO;
890
891 device = pci_get_device(kdev);
892
893 for (i = 0; pciidlist[i].device != 0; i++) {
894 if (pciidlist[i].device == device) {
895 i915_attach_list[0].device = device;
896 return 0;
897 }
898 }
899
900 return ENXIO;
901}
902
9edbd4a0
FT		 903#if 0
904static void
905i915_pci_remove(struct pci_dev *pdev)
906{
907 struct drm_device *dev = pci_get_drvdata(pdev);
908
909 drm_put_dev(dev);
910}
911
912static int i915_pm_suspend(struct device *dev)
913{
914 struct pci_dev *pdev = to_pci_dev(dev);
915 struct drm_device *drm_dev = pci_get_drvdata(pdev);
916 int error;
917
918 if (!drm_dev || !drm_dev->dev_private) {
919 dev_err(dev, "DRM not initialized, aborting suspend.\n");
920 return -ENODEV;
921 }
922
923 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
924 return 0;
925
926 error = i915_drm_freeze(drm_dev);
927 if (error)
928 return error;
929
930 pci_disable_device(pdev);
931 pci_set_power_state(pdev, PCI_D3hot);
932
933 return 0;
934}
935
936static int i915_pm_resume(struct device *dev)
937{
938 struct pci_dev *pdev = to_pci_dev(dev);
939 struct drm_device *drm_dev = pci_get_drvdata(pdev);
940
941 return i915_resume(drm_dev);
942}
943
944static int i915_pm_freeze(struct device *dev)
945{
946 struct pci_dev *pdev = to_pci_dev(dev);
947 struct drm_device *drm_dev = pci_get_drvdata(pdev);
948
949 if (!drm_dev || !drm_dev->dev_private) {
950 dev_err(dev, "DRM not initialized, aborting suspend.\n");
951 return -ENODEV;
952 }
953
954 return i915_drm_freeze(drm_dev);
955}
956
957static int i915_pm_thaw(struct device *dev)
958{
959 struct pci_dev *pdev = to_pci_dev(dev);
960 struct drm_device *drm_dev = pci_get_drvdata(pdev);
961
962 return i915_drm_thaw(drm_dev);
963}
964
965static int i915_pm_poweroff(struct device *dev)
966{
967 struct pci_dev *pdev = to_pci_dev(dev);
968 struct drm_device *drm_dev = pci_get_drvdata(pdev);
969
970 return i915_drm_freeze(drm_dev);
971}
972
973static int i915_runtime_suspend(struct device *device)
974{
975 struct pci_dev *pdev = to_pci_dev(device);
976 struct drm_device *dev = pci_get_drvdata(pdev);
977 struct drm_i915_private *dev_priv = dev->dev_private;
978
979 WARN_ON(!HAS_RUNTIME_PM(dev));
980
981 DRM_DEBUG_KMS("Suspending device\n");
982
983 i915_gem_release_all_mmaps(dev_priv);
984
985 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
986 dev_priv->pm.suspended = true;
987
988 /*
989 * current versions of firmware which depend on this opregion
990 * notification have repurposed the D1 definition to mean
991 * "runtime suspended" vs. what you would normally expect (D3)
992 * to distinguish it from notifications that might be sent
993 * via the suspend path.
994 */
995 intel_opregion_notify_adapter(dev, PCI_D1);
996
997 return 0;
998}
999
1000static int i915_runtime_resume(struct device *device)
1001{
1002 struct pci_dev *pdev = to_pci_dev(device);
1003 struct drm_device *dev = pci_get_drvdata(pdev);
1004 struct drm_i915_private *dev_priv = dev->dev_private;
1005
1006 WARN_ON(!HAS_RUNTIME_PM(dev));
1007
1008 DRM_DEBUG_KMS("Resuming device\n");
1009
1010 intel_opregion_notify_adapter(dev, PCI_D0);
1011 dev_priv->pm.suspended = false;
1012
1013 return 0;
1014}
1015
1016static const struct dev_pm_ops i915_pm_ops = {
1017 .suspend = i915_pm_suspend,
1018 .resume = i915_pm_resume,
1019 .freeze = i915_pm_freeze,
1020 .thaw = i915_pm_thaw,
1021 .poweroff = i915_pm_poweroff,
1022 .restore = i915_pm_resume,
1023 .runtime_suspend = i915_runtime_suspend,
1024 .runtime_resume = i915_runtime_resume,
1025};
1026
1027static const struct vm_operations_struct i915_gem_vm_ops = {
1028 .fault = i915_gem_fault,
1029 .open = drm_gem_vm_open,
1030 .close = drm_gem_vm_close,
1031};
1032
1033static const struct file_operations i915_driver_fops = {
1034 .owner = THIS_MODULE,
1035 .open = drm_open,
1036 .release = drm_release,
1037 .unlocked_ioctl = drm_ioctl,
1038 .mmap = drm_gem_mmap,
1039 .poll = drm_poll,
1040 .read = drm_read,
1041#ifdef CONFIG_COMPAT
1042 .compat_ioctl = i915_compat_ioctl,
1043#endif
1044 .llseek = noop_llseek,
1045};
1046#endif
1047
e9587a4e
FT		 1048static struct cdev_pager_ops i915_gem_vm_ops = {
1049 .cdev_pg_fault = i915_gem_fault,
1050 .cdev_pg_ctor = i915_gem_pager_ctor,
1051 .cdev_pg_dtor = i915_gem_pager_dtor
1052};
1053
f0b54121 1054static struct drm_driver driver = {
9edbd4a0
FT		 1055 /* Don't use MTRRs here; the Xserver or userspace app should
1056 * deal with them for Intel hardware.
1057 */
1058 .driver_features =
1059 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1060 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
79f713b0
FT		 1061
1062 .buf_priv_size = sizeof(drm_i915_private_t),
f0b54121 1063 .load = i915_driver_load,
2aa08105 1064 .open = i915_driver_open,
79f713b0 1065 .unload = i915_driver_unload,
2aa08105 1066 .preclose = i915_driver_preclose,
79f713b0 1067 .lastclose = i915_driver_lastclose,
f0b54121
FT		 1068 .postclose = i915_driver_postclose,
1069 .device_is_agp = i915_driver_device_is_agp,
f0b54121 1070 .gem_free_object = i915_gem_free_object,
e9587a4e 1071 .gem_pager_ops = &i915_gem_vm_ops,
f0b54121
FT		 1072 .dumb_create = i915_gem_dumb_create,
1073 .dumb_map_offset = i915_gem_mmap_gtt,
9edbd4a0 1074 .dumb_destroy = drm_gem_dumb_destroy,
f0b54121
FT		 1075 .ioctls = i915_ioctls,
1076
1077 .name = DRIVER_NAME,
1078 .desc = DRIVER_DESC,
1079 .date = DRIVER_DATE,
1080 .major = DRIVER_MAJOR,
1081 .minor = DRIVER_MINOR,
1082 .patchlevel = DRIVER_PATCHLEVEL,
1083};
1084
a2fdbec6
FT		 1085static device_method_t i915_methods[] = {
1086 /* Device interface */
1087 DEVMETHOD(device_probe, i915_pci_probe),
1088 DEVMETHOD(device_attach, i915_attach),
1089 DEVMETHOD(device_suspend, i915_suspend),
1090 DEVMETHOD(device_resume, i915_resume),
d0cc45b6 1091 DEVMETHOD(device_detach, drm_release),
a2fdbec6
FT		 1092 DEVMETHOD_END
1093};
1094
1095static driver_t i915_driver = {
1096 "drm",
1097 i915_methods,
1098 sizeof(struct drm_device)
1099};
1100
1101DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
1102 SI_ORDER_ANY);
1103MODULE_DEPEND(i915kms, drm, 1, 1, 1);
1104MODULE_DEPEND(i915kms, agp, 1, 1, 1);
1105MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
1106MODULE_DEPEND(i915kms, iic, 1, 1, 1);
1107MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
Nuno's DragonFly repo.