vkernel - Fix systat -vm 1
[dragonfly.git] / sys / dev / drm / i915 / i915_drv.c
CommitLineData
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1/* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
3 */
4/*-
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
e3adcf8f 30 * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.c,v 1.1 2012/05/22 11:07:44 kib Exp $
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31 */
32
18e26a6d 33#include <drm/drmP.h>
5c6c6f23 34#include <drm/i915_drm.h>
c4a9e910 35#include "i915_drv.h"
18e26a6d 36#include <drm/drm_pciids.h>
e3adcf8f 37#include "intel_drv.h"
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38
39/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
40static drm_pci_id_list_t i915_pciidlist[] = {
41 i915_PCI_IDS
42};
43
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44#define INTEL_VGA_DEVICE(id, info_) { \
45 .device = id, \
46 .info = info_, \
47}
48
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49static const struct intel_device_info intel_i830_info = {
50 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
51 .has_overlay = 1, .overlay_needs_physical = 1,
52};
53
54static const struct intel_device_info intel_845g_info = {
55 .gen = 2,
56 .has_overlay = 1, .overlay_needs_physical = 1,
57};
58
59static const struct intel_device_info intel_i85x_info = {
60 .gen = 2, .is_i85x = 1, .is_mobile = 1,
61 .cursor_needs_physical = 1,
62 .has_overlay = 1, .overlay_needs_physical = 1,
63};
64
65static const struct intel_device_info intel_i865g_info = {
66 .gen = 2,
67 .has_overlay = 1, .overlay_needs_physical = 1,
68};
69
70static const struct intel_device_info intel_i915g_info = {
71 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
72 .has_overlay = 1, .overlay_needs_physical = 1,
73};
74static const struct intel_device_info intel_i915gm_info = {
75 .gen = 3, .is_mobile = 1,
76 .cursor_needs_physical = 1,
77 .has_overlay = 1, .overlay_needs_physical = 1,
78 .supports_tv = 1,
79};
80static const struct intel_device_info intel_i945g_info = {
81 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
82 .has_overlay = 1, .overlay_needs_physical = 1,
83};
84static const struct intel_device_info intel_i945gm_info = {
85 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
86 .has_hotplug = 1, .cursor_needs_physical = 1,
87 .has_overlay = 1, .overlay_needs_physical = 1,
88 .supports_tv = 1,
89};
90
91static const struct intel_device_info intel_i965g_info = {
92 .gen = 4, .is_broadwater = 1,
93 .has_hotplug = 1,
94 .has_overlay = 1,
95};
96
97static const struct intel_device_info intel_i965gm_info = {
98 .gen = 4, .is_crestline = 1,
99 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
100 .has_overlay = 1,
101 .supports_tv = 1,
102};
103
104static const struct intel_device_info intel_g33_info = {
105 .gen = 3, .is_g33 = 1,
106 .need_gfx_hws = 1, .has_hotplug = 1,
107 .has_overlay = 1,
108};
109
110static const struct intel_device_info intel_g45_info = {
111 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
112 .has_pipe_cxsr = 1, .has_hotplug = 1,
113 .has_bsd_ring = 1,
114};
115
116static const struct intel_device_info intel_gm45_info = {
117 .gen = 4, .is_g4x = 1,
118 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
119 .has_pipe_cxsr = 1, .has_hotplug = 1,
120 .supports_tv = 1,
121 .has_bsd_ring = 1,
122};
123
124static const struct intel_device_info intel_pineview_info = {
125 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
126 .need_gfx_hws = 1, .has_hotplug = 1,
127 .has_overlay = 1,
128};
129
130static const struct intel_device_info intel_ironlake_d_info = {
131 .gen = 5,
132 .need_gfx_hws = 1, .has_hotplug = 1,
133 .has_bsd_ring = 1,
134};
135
136static const struct intel_device_info intel_ironlake_m_info = {
137 .gen = 5, .is_mobile = 1,
138 .need_gfx_hws = 1, .has_hotplug = 1,
139 .has_fbc = 0, /* disabled due to buggy hardware */
140 .has_bsd_ring = 1,
141};
142
143static const struct intel_device_info intel_sandybridge_d_info = {
144 .gen = 6,
145 .need_gfx_hws = 1, .has_hotplug = 1,
146 .has_bsd_ring = 1,
147 .has_blt_ring = 1,
148 .has_llc = 1,
e9243325 149 .has_force_wake = 1,
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150};
151
152static const struct intel_device_info intel_sandybridge_m_info = {
153 .gen = 6, .is_mobile = 1,
154 .need_gfx_hws = 1, .has_hotplug = 1,
155 .has_fbc = 1,
156 .has_bsd_ring = 1,
157 .has_blt_ring = 1,
158 .has_llc = 1,
e9243325 159 .has_force_wake = 1,
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160};
161
162static const struct intel_device_info intel_ivybridge_d_info = {
163 .is_ivybridge = 1, .gen = 7,
164 .need_gfx_hws = 1, .has_hotplug = 1,
165 .has_bsd_ring = 1,
166 .has_blt_ring = 1,
167 .has_llc = 1,
e9243325 168 .has_force_wake = 1,
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169};
170
171static const struct intel_device_info intel_ivybridge_m_info = {
172 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
173 .need_gfx_hws = 1, .has_hotplug = 1,
174 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
175 .has_bsd_ring = 1,
176 .has_blt_ring = 1,
177 .has_llc = 1,
e9243325 178 .has_force_wake = 1,
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179};
180
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181static const struct intel_device_info intel_valleyview_m_info = {
182 .gen = 7, .is_mobile = 1,
183 .need_gfx_hws = 1, .has_hotplug = 1,
184 .has_fbc = 0,
185 .has_bsd_ring = 1,
186 .has_blt_ring = 1,
187 .is_valleyview = 1,
188};
189
190static const struct intel_device_info intel_valleyview_d_info = {
191 .gen = 7,
192 .need_gfx_hws = 1, .has_hotplug = 1,
193 .has_fbc = 0,
194 .has_bsd_ring = 1,
195 .has_blt_ring = 1,
196 .is_valleyview = 1,
197};
198
199static const struct intel_device_info intel_haswell_d_info = {
200 .is_haswell = 1, .gen = 7,
201 .need_gfx_hws = 1, .has_hotplug = 1,
202 .has_bsd_ring = 1,
203 .has_blt_ring = 1,
204 .has_llc = 1,
205 .has_force_wake = 1,
206};
207
208static const struct intel_device_info intel_haswell_m_info = {
209 .is_haswell = 1, .gen = 7, .is_mobile = 1,
210 .need_gfx_hws = 1, .has_hotplug = 1,
211 .has_bsd_ring = 1,
212 .has_blt_ring = 1,
213 .has_llc = 1,
214 .has_force_wake = 1,
215};
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216
217static const struct intel_gfx_device_id {
218 int device;
219 const struct intel_device_info *info;
220} pciidlist[] = { /* aka */
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221 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
222 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
223 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
e3adcf8f 224 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
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225 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
226 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
227 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
228 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
229 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
230 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
231 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
232 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
233 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
234 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
235 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
236 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
237 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
238 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
239 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
240 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
241 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
242 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
243 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
244 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
245 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
246 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
247 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
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248 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
249 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
250 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
251 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
252 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
253 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
254 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
255 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
256 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
257 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
258 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
259 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
260 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
261 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
262 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
263 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
264 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
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265 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
266 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
267 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
268 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
269 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
270 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
271 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
272 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
273 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
274 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
275 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
276 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
277 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
278 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
279 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
280 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
281 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
282 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
283 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
284 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
285 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
286 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
287 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
288 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
289 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
290 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
291 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
292 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
293 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
294 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
295 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
296 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
297 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
298 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
299 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
300 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
301 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
302 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
303 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
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304 {0, 0}
305};
306
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307#define PCI_VENDOR_INTEL 0x8086
308
309void intel_detect_pch(struct drm_device *dev)
310{
311 struct drm_i915_private *dev_priv = dev->dev_private;
312 device_t pch;
313
314 /*
315 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
316 * make graphics device passthrough work easy for VMM, that only
317 * need to expose ISA bridge to let driver know the real hardware
318 * underneath. This is a requirement from virtualization team.
319 */
320 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
321 if (pch) {
322 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
323 unsigned short id;
324 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
325 dev_priv->pch_id = id;
326
327 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
328 dev_priv->pch_type = PCH_IBX;
329 dev_priv->num_pch_pll = 2;
330 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
331 WARN_ON(!IS_GEN5(dev));
332 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
333 dev_priv->pch_type = PCH_CPT;
334 dev_priv->num_pch_pll = 2;
335 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
336 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
337 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
338 /* PantherPoint is CPT compatible */
339 dev_priv->pch_type = PCH_CPT;
340 dev_priv->num_pch_pll = 2;
341 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
342 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
343 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
344 dev_priv->pch_type = PCH_LPT;
345 dev_priv->num_pch_pll = 0;
346 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
347 WARN_ON(!IS_HASWELL(dev));
348 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
349 dev_priv->pch_type = PCH_LPT;
350 dev_priv->num_pch_pll = 0;
351 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
352 WARN_ON(!IS_HASWELL(dev));
353 }
354 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
355 }
356#if 0
357 pci_dev_put(pch);
358#endif
359 }
360}
361
e3adcf8f 362static int i915_drm_freeze(struct drm_device *dev)
7f3c3d6f 363{
e9243325 364 struct drm_i915_private *dev_priv = dev->dev_private;
b3705d71 365
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366 drm_kms_helper_poll_disable(dev);
367
368#if 0
369 pci_save_state(dev->pdev);
370#endif
b3705d71 371
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372 /* If KMS is active, we do the leavevt stuff here */
373 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
e9243325 374 int error = i915_gem_idle(dev);
e3adcf8f 375 if (error) {
6df74fa7 376 device_printf(dev->dev,
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377 "GEM idle failed, resume might fail");
378 return error;
e3adcf8f 379 }
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380 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
381
382#if 0
383 intel_modeset_disable(dev);
384#endif
385
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386 drm_irq_uninstall(dev);
387 }
388
b3705d71 389 i915_save_state(dev);
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390
391 intel_opregion_fini(dev);
392
393 /* Modeset on resume, not lid events */
394 dev_priv->modeset_on_lid = 0;
b3705d71 395
e3adcf8f 396 return 0;
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397}
398
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399static int
400i915_suspend(device_t kdev)
b3705d71 401{
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402 struct drm_device *dev;
403 int error;
404
405 dev = device_get_softc(kdev);
406 if (dev == NULL || dev->dev_private == NULL) {
407 DRM_ERROR("DRM not initialized, aborting suspend.\n");
408 return -ENODEV;
409 }
410
411 DRM_DEBUG_KMS("starting suspend\n");
412 error = i915_drm_freeze(dev);
413 if (error)
414 return (error);
415
416 error = bus_generic_suspend(kdev);
417 DRM_DEBUG_KMS("finished suspend %d\n", error);
418 return (error);
419}
420
421static int i915_drm_thaw(struct drm_device *dev)
422{
423 struct drm_i915_private *dev_priv = dev->dev_private;
424 int error = 0;
b3705d71 425
5718399f 426 DRM_LOCK(dev);
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427 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
428 i915_gem_restore_gtt_mappings(dev);
429 }
430
b3705d71 431 i915_restore_state(dev);
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432 intel_opregion_setup(dev);
433
434 /* KMS EnterVT equivalent */
435 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
436 dev_priv->mm.suspended = 0;
437
438 error = i915_gem_init_hw(dev);
439
440 if (HAS_PCH_SPLIT(dev))
441 ironlake_init_pch_refclk(dev);
442
443 DRM_UNLOCK(dev);
af4b81b9 444 lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE);
e3adcf8f 445 drm_mode_config_reset(dev);
af4b81b9 446 lockmgr(&dev->mode_config.mutex, LK_RELEASE);
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447 drm_irq_install(dev);
448
af4b81b9 449 lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE);
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450 /* Resume the modeset for every activated CRTC */
451 drm_helper_resume_force_mode(dev);
af4b81b9 452 lockmgr(&dev->mode_config.mutex, LK_RELEASE);
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453
454 if (IS_IRONLAKE_M(dev))
455 ironlake_enable_rc6(dev);
456 DRM_LOCK(dev);
457 }
458
459 intel_opregion_init(dev);
460
461 dev_priv->modeset_on_lid = 0;
462
5718399f 463 DRM_UNLOCK(dev);
b3705d71 464
e3adcf8f 465 return error;
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466}
467
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468static int
469i915_resume(device_t kdev)
b3705d71 470{
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471 struct drm_device *dev;
472 int ret;
473
474 dev = device_get_softc(kdev);
475 DRM_DEBUG_KMS("starting resume\n");
476#if 0
477 if (pci_enable_device(dev->pdev))
478 return -EIO;
b3705d71 479
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480 pci_set_master(dev->pdev);
481#endif
b3705d71 482
e3adcf8f
FT
483 ret = -i915_drm_thaw(dev);
484 if (ret != 0)
485 return (ret);
b3705d71 486
e3adcf8f
FT
487 drm_kms_helper_poll_enable(dev);
488 ret = bus_generic_resume(kdev);
489 DRM_DEBUG_KMS("finished resume %d\n", ret);
490 return (ret);
7f3c3d6f
HT
491}
492
7f3c3d6f 493static int
b3705d71 494i915_probe(device_t kdev)
7f3c3d6f 495{
e3adcf8f 496
b3705d71 497 return drm_probe(kdev, i915_pciidlist);
7f3c3d6f
HT
498}
499
e3adcf8f
FT
500int i915_modeset;
501
7f3c3d6f 502static int
b3705d71 503i915_attach(device_t kdev)
7f3c3d6f 504{
e3adcf8f 505 struct drm_device *dev;
b3705d71 506
e3adcf8f
FT
507 dev = device_get_softc(kdev);
508 if (i915_modeset == 1)
509 i915_driver_info.driver_features |= DRIVER_MODESET;
510 dev->driver = &i915_driver_info;
511 return (drm_attach(kdev, i915_pciidlist));
b3705d71
HT
512}
513
e3adcf8f
FT
514const struct intel_device_info *
515i915_get_device_id(int device)
b3705d71 516{
e3adcf8f 517 const struct intel_gfx_device_id *did;
b3705d71 518
e3adcf8f
FT
519 for (did = &pciidlist[0]; did->device != 0; did++) {
520 if (did->device != device)
521 continue;
522 return (did->info);
523 }
524 return (NULL);
7f3c3d6f
HT
525}
526
527static device_method_t i915_methods[] = {
528 /* Device interface */
529 DEVMETHOD(device_probe, i915_probe),
530 DEVMETHOD(device_attach, i915_attach),
b3705d71
HT
531 DEVMETHOD(device_suspend, i915_suspend),
532 DEVMETHOD(device_resume, i915_resume),
e3adcf8f 533 DEVMETHOD(device_detach, drm_detach),
d3c9c58e 534 DEVMETHOD_END
7f3c3d6f
HT
535};
536
537static driver_t i915_driver = {
7f3c3d6f 538 "drm",
7f3c3d6f 539 i915_methods,
b3705d71 540 sizeof(struct drm_device)
7f3c3d6f
HT
541};
542
543extern devclass_t drm_devclass;
e3adcf8f
FT
544DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
545 SI_ORDER_ANY);
546MODULE_DEPEND(i915kms, drm, 1, 1, 1);
547MODULE_DEPEND(i915kms, agp, 1, 1, 1);
548MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
549MODULE_DEPEND(i915kms, iic, 1, 1, 1);
550MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
551
552int intel_iommu_enabled = 0;
553TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
554
555int i915_semaphores = -1;
556TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
557static int i915_try_reset = 1;
558TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
559unsigned int i915_lvds_downclock = 0;
560TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
561int i915_vbt_sdvo_panel_type = -1;
562TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
563unsigned int i915_powersave = 1;
564TUNABLE_INT("drm.i915.powersave", &i915_powersave);
565int i915_enable_fbc = 0;
566TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
567int i915_enable_rc6 = 0;
568TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
569int i915_panel_use_ssc = -1;
570TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
571int i915_panel_ignore_lid = 0;
572TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
573int i915_modeset = 1;
574TUNABLE_INT("drm.i915.modeset", &i915_modeset);
575int i915_enable_ppgtt = -1;
576TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
577int i915_enable_hangcheck = 1;
578TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
579
00640ec9 580static int i8xx_do_reset(struct drm_device *dev)
e3adcf8f
FT
581{
582 struct drm_i915_private *dev_priv = dev->dev_private;
583
584 if (IS_I85X(dev))
585 return -ENODEV;
586
587 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
588 POSTING_READ(D_STATE);
589
590 if (IS_I830(dev) || IS_845G(dev)) {
591 I915_WRITE(DEBUG_RESET_I830,
592 DEBUG_RESET_DISPLAY |
593 DEBUG_RESET_RENDER |
594 DEBUG_RESET_FULL);
595 POSTING_READ(DEBUG_RESET_I830);
00640ec9 596 msleep(1);
e3adcf8f
FT
597
598 I915_WRITE(DEBUG_RESET_I830, 0);
599 POSTING_READ(DEBUG_RESET_I830);
600 }
601
00640ec9 602 msleep(1);
e3adcf8f
FT
603
604 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
605 POSTING_READ(D_STATE);
606
607 return 0;
608}
609
00640ec9 610static int i965_reset_complete(struct drm_device *dev)
e3adcf8f
FT
611{
612 u8 gdrst;
6df74fa7 613 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
e3adcf8f
FT
614 return (gdrst & 0x1);
615}
616
00640ec9 617static int i965_do_reset(struct drm_device *dev)
e3adcf8f 618{
00640ec9 619 int ret;
e3adcf8f
FT
620 u8 gdrst;
621
622 /*
623 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
624 * well as the reset bit (GR/bit 0). Setting the GR bit
625 * triggers the reset; when done, the hardware will clear it.
626 */
6df74fa7 627 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
00640ec9
FT
628 pci_write_config(dev->dev, I965_GDRST,
629 gdrst | GRDOM_RENDER |
630 GRDOM_RESET_ENABLE, 1);
631 ret = wait_for(i965_reset_complete(dev), 500);
632 if (ret)
633 return ret;
634
635 /* We can't reset render&media without also resetting display ... */
636 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
637 pci_write_config(dev->dev, I965_GDRST,
638 gdrst | GRDOM_MEDIA |
639 GRDOM_RESET_ENABLE, 1);
e3adcf8f 640
00640ec9 641 return wait_for(i965_reset_complete(dev), 500);
e3adcf8f
FT
642}
643
00640ec9 644static int ironlake_do_reset(struct drm_device *dev)
e3adcf8f 645{
00640ec9 646 struct drm_i915_private *dev_priv = dev->dev_private;
e3adcf8f 647 u32 gdrst;
00640ec9 648 int ret;
e3adcf8f 649
e3adcf8f 650 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
00640ec9
FT
651 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
652 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
653 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
654 if (ret)
655 return ret;
656
657 /* We can't reset render&media without also resetting display ... */
658 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
659 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
660 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
661 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
e3adcf8f
FT
662}
663
e9243325 664static int gen6_do_reset(struct drm_device *dev)
e3adcf8f 665{
e9243325 666 struct drm_i915_private *dev_priv = dev->dev_private;
e3adcf8f
FT
667 int ret;
668
669 dev_priv = dev->dev_private;
670
671 /* Hold gt_lock across reset to prevent any register access
672 * with forcewake not set correctly
673 */
674 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
675
676 /* Reset the chip */
677
678 /* GEN6_GDRST is not in the gt power well, no need to check
679 * for fifo space for the write or forcewake the chip for
680 * the read
681 */
682 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
683
684 /* Spin waiting for the device to ack the reset request */
685 ret = _intel_wait_for(dev,
686 (I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
687 500, 1, "915rst");
688
689 /* If reset with a user forcewake, try to restore, otherwise turn it off */
e9243325
FT
690 if (dev_priv->forcewake_count)
691 dev_priv->gt.force_wake_get(dev_priv);
e3adcf8f 692 else
e9243325 693 dev_priv->gt.force_wake_put(dev_priv);
e3adcf8f
FT
694
695 /* Restore fifo count */
696 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
697
698 lockmgr(&dev_priv->gt_lock, LK_RELEASE);
e9243325 699 return ret;
e3adcf8f
FT
700}
701
00640ec9
FT
702int intel_gpu_reset(struct drm_device *dev)
703{
704 struct drm_i915_private *dev_priv = dev->dev_private;
705 int ret = -ENODEV;
706
707 switch (INTEL_INFO(dev)->gen) {
708 case 7:
709 case 6:
710 ret = gen6_do_reset(dev);
711 break;
712 case 5:
713 ret = ironlake_do_reset(dev);
714 break;
715 case 4:
716 ret = i965_do_reset(dev);
717 break;
718 case 2:
719 ret = i8xx_do_reset(dev);
720 break;
721 }
722
723 /* Also reset the gpu hangman. */
724 if (dev_priv->stop_rings) {
725 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
726 dev_priv->stop_rings = 0;
727 if (ret == -ENODEV) {
728 DRM_ERROR("Reset not implemented, but ignoring "
729 "error for simulated gpu hangs\n");
730 ret = 0;
731 }
732 }
733
734 return ret;
735}
736
e9243325
FT
737/**
738 * i915_reset - reset chip after a hang
739 * @dev: drm device to reset
740 *
741 * Reset the chip. Useful if a hang is detected. Returns zero on successful
742 * reset or otherwise an error code.
743 *
744 * Procedure is fairly simple:
745 * - reset the chip using the reset reg
746 * - re-init context state
747 * - re-init hardware status page
748 * - re-init ring buffer
749 * - re-init interrupt state
750 * - re-init display
751 */
00640ec9 752int i915_reset(struct drm_device *dev)
e3adcf8f
FT
753{
754 drm_i915_private_t *dev_priv = dev->dev_private;
e9243325
FT
755 int ret;
756
757 if (!i915_try_reset)
758 return 0;
759
00640ec9 760 DRM_LOCK(dev);
e3adcf8f
FT
761
762 i915_gem_reset(dev);
763
764 ret = -ENODEV;
00640ec9 765 if (time_uptime - dev_priv->last_gpu_reset < 5)
e3adcf8f 766 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
00640ec9
FT
767 else
768 ret = intel_gpu_reset(dev);
769
e3adcf8f
FT
770 dev_priv->last_gpu_reset = time_uptime;
771 if (ret) {
772 DRM_ERROR("Failed to reset chip.\n");
773 DRM_UNLOCK(dev);
00640ec9 774 return ret;
e3adcf8f
FT
775 }
776
e9243325
FT
777 /* Ok, now get things going again... */
778
779 /*
780 * Everything depends on having the GTT running, so we need to start
781 * there. Fortunately we don't need to do this unless we reset the
782 * chip at a PCI level.
783 *
784 * Next we need to restore the context, but we don't use those
785 * yet either...
786 *
787 * Ring buffer needs to be re-initialized in the KMS case, or if X
788 * was running at the time of the reset (i.e. we weren't VT
789 * switched away).
790 */
e3adcf8f 791 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
00640ec9
FT
792 !dev_priv->mm.suspended) {
793 struct intel_ring_buffer *ring;
794 int i;
795
e3adcf8f
FT
796 dev_priv->mm.suspended = 0;
797
798 i915_gem_init_swizzling(dev);
799
00640ec9
FT
800 for_each_ring(ring, dev_priv, i)
801 ring->init(ring);
e3adcf8f 802
00640ec9
FT
803#if 0 /* XXX: HW context support */
804 i915_gem_context_init(dev);
805#endif
e3adcf8f
FT
806 i915_gem_init_ppgtt(dev);
807
00640ec9
FT
808 /*
809 * It would make sense to re-init all the other hw state, at
810 * least the rps/rc6/emon init done within modeset_init_hw. For
811 * some unknown reason, this blows up my ilk, so don't.
812 */
813
e3adcf8f 814 DRM_UNLOCK(dev);
e3adcf8f 815
00640ec9
FT
816 drm_irq_uninstall(dev);
817 drm_irq_install(dev);
818 } else {
819 DRM_UNLOCK(dev);
e3adcf8f
FT
820 }
821
e9243325
FT
822 return 0;
823}
824
c0bdd5d9
FT
825/* We give fast paths for the really cool registers */
826#define NEEDS_FORCE_WAKE(dev_priv, reg) \
827 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
828 ((reg) < 0x40000) && \
829 ((reg) != FORCEWAKE))
830
e9243325
FT
831static bool IS_DISPLAYREG(u32 reg)
832{
833 /*
834 * This should make it easier to transition modules over to the
835 * new register block scheme, since we can do it incrementally.
836 */
837 if (reg >= VLV_DISPLAY_BASE)
838 return false;
839
840 if (reg >= RENDER_RING_BASE &&
841 reg < RENDER_RING_BASE + 0xff)
842 return false;
843 if (reg >= GEN6_BSD_RING_BASE &&
844 reg < GEN6_BSD_RING_BASE + 0xff)
845 return false;
846 if (reg >= BLT_RING_BASE &&
847 reg < BLT_RING_BASE + 0xff)
848 return false;
849
850 if (reg == PGTBL_ER)
851 return false;
852
853 if (reg >= IPEIR_I965 &&
854 reg < HWSTAM)
855 return false;
856
857 if (reg == MI_MODE)
858 return false;
859
860 if (reg == GFX_MODE_GEN7)
861 return false;
862
863 if (reg == RENDER_HWS_PGA_GEN7 ||
864 reg == BSD_HWS_PGA_GEN7 ||
865 reg == BLT_HWS_PGA_GEN7)
866 return false;
867
868 if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
869 reg == GEN6_BSD_RNCID)
870 return false;
871
872 if (reg == GEN6_BLITTER_ECOSKPD)
873 return false;
874
875 if (reg >= 0x4000c &&
876 reg <= 0x4002c)
877 return false;
878
879 if (reg >= 0x4f000 &&
880 reg <= 0x4f08f)
881 return false;
882
883 if (reg >= 0x4f100 &&
884 reg <= 0x4f11f)
885 return false;
886
887 if (reg >= VLV_MASTER_IER &&
888 reg <= GEN6_PMIER)
889 return false;
890
891 if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
892 reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
893 return false;
894
895 if (reg >= VLV_IIR_RW &&
896 reg <= VLV_ISR)
897 return false;
898
899 if (reg == FORCEWAKE_VLV ||
900 reg == FORCEWAKE_ACK_VLV)
901 return false;
902
903 if (reg == GEN6_GDRST)
904 return false;
905
906 switch (reg) {
907 case _3D_CHICKEN3:
908 case IVB_CHICKEN3:
909 case GEN7_COMMON_SLICE_CHICKEN1:
910 case GEN7_L3CNTLREG1:
911 case GEN7_L3_CHICKEN_MODE_REGISTER:
912 case GEN7_ROW_CHICKEN2:
913 case GEN7_L3SQCREG4:
914 case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
915 case GEN7_HALF_SLICE_CHICKEN1:
916 case GEN6_MBCTL:
917 case GEN6_UCGCTL2:
918 return false;
919 default:
920 break;
921 }
922
923 return true;
924}
925
926static void
927ilk_dummy_write(struct drm_i915_private *dev_priv)
928{
929 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
930 * chip from rc6 before touching it for real. MI_MODE is masked, hence
931 * harmless to write 0 into. */
932 I915_WRITE_NOTRACE(MI_MODE, 0);
e3adcf8f
FT
933}
934
935#define __i915_read(x, y) \
936u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
937 u##x val = 0; \
e9243325
FT
938 if (IS_GEN5(dev_priv->dev)) \
939 ilk_dummy_write(dev_priv); \
e3adcf8f
FT
940 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
941 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); \
942 if (dev_priv->forcewake_count == 0) \
e9243325 943 dev_priv->gt.force_wake_get(dev_priv); \
e3adcf8f
FT
944 val = DRM_READ##y(dev_priv->mmio_map, reg); \
945 if (dev_priv->forcewake_count == 0) \
e9243325 946 dev_priv->gt.force_wake_put(dev_priv); \
e3adcf8f 947 lockmgr(&dev_priv->gt_lock, LK_RELEASE); \
e9243325
FT
948 } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
949 val = DRM_READ##y(dev_priv->mmio_map, reg + 0x180000); \
e3adcf8f
FT
950 } else { \
951 val = DRM_READ##y(dev_priv->mmio_map, reg); \
952 } \
953 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
954 return val; \
955}
956
957__i915_read(8, 8)
958__i915_read(16, 16)
959__i915_read(32, 32)
960__i915_read(64, 64)
961#undef __i915_read
962
963#define __i915_write(x, y) \
964void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
965 u32 __fifo_ret = 0; \
966 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
967 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
968 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
969 } \
e9243325
FT
970 if (IS_GEN5(dev_priv->dev)) \
971 ilk_dummy_write(dev_priv); \
972 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
973 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
974 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
975 } \
976 if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
977 DRM_WRITE##y(dev_priv->mmio_map, reg + 0x180000, val); \
978 } else { \
979 DRM_WRITE##y(dev_priv->mmio_map, reg, val); \
980 } \
981 if (unlikely(__fifo_ret)) { \
e3adcf8f
FT
982 gen6_gt_check_fifodbg(dev_priv); \
983 } \
e9243325
FT
984 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
985 DRM_ERROR("Unclaimed write to %x\n", reg); \
986 DRM_WRITE32(dev_priv->mmio_map, GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
987 } \
e3adcf8f 988}
e9243325 989
e3adcf8f
FT
990__i915_write(8, 8)
991__i915_write(16, 16)
992__i915_write(32, 32)
993__i915_write(64, 64)
994#undef __i915_write