drm/radeon: Sync to Linux 3.11
[dragonfly.git] / sys / dev / drm / radeon / evergreen_hdmi.c
CommitLineData
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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 * Rafał Miłecki
926deccb 26 */
b403bed8 27#include <linux/hdmi.h>
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28#include <drm/drmP.h>
29#include <uapi_drm/radeon_drm.h>
30#include "radeon.h"
31#include "radeon_asic.h"
32#include "evergreend.h"
33#include "atom.h"
34
35/*
36 * update the N and CTS parameters for a given pixel clock rate
37 */
38static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
39{
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
43 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
44 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
45 uint32_t offset = dig->afmt->offset;
46
47 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
48 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
49
50 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
51 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
52
53 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
54 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
55}
56
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57static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
58{
59 struct radeon_device *rdev = encoder->dev->dev_private;
60 struct drm_connector *connector;
61 struct radeon_connector *radeon_connector = NULL;
62 struct cea_sad *sads;
63 int i, sad_count;
64
65 static const u16 eld_reg_to_type[][2] = {
66 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
67 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
68 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
69 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
70 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
71 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
72 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
73 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
74 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
75 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
76 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
77 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
78 };
79
80 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
81 if (connector->encoder == encoder)
82 radeon_connector = to_radeon_connector(connector);
83 }
84
85 if (!radeon_connector) {
86 DRM_ERROR("Couldn't find encoder's connector\n");
87 return;
88 }
89
90 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
91 if (sad_count < 0) {
92 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
93 return;
94 }
95 BUG_ON(!sads);
96
97 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
98 u32 value = 0;
99 int j;
100
101 for (j = 0; j < sad_count; j++) {
102 struct cea_sad *sad = &sads[j];
103
104 if (sad->format == eld_reg_to_type[i][1]) {
105 value = MAX_CHANNELS(sad->channels) |
106 DESCRIPTOR_BYTE_2(sad->byte2) |
107 SUPPORTED_FREQUENCIES(sad->freq);
108 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
109 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
110 break;
111 }
112 }
113 WREG32(eld_reg_to_type[i][0], value);
114 }
115
116 kfree(sads);
117}
118
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119/*
120 * build a HDMI Video Info Frame
121 */
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122static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
123 void *buffer, size_t size)
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124{
125 struct drm_device *dev = encoder->dev;
126 struct radeon_device *rdev = dev->dev_private;
127 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
128 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
129 uint32_t offset = dig->afmt->offset;
b403bed8 130 uint8_t *frame = (uint8_t*)buffer + 3;
926deccb 131
57e252bf 132 uint8_t *header = buffer;
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133
134 WREG32(AFMT_AVI_INFO0 + offset,
135 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
136 WREG32(AFMT_AVI_INFO1 + offset,
137 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
138 WREG32(AFMT_AVI_INFO2 + offset,
139 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
140 WREG32(AFMT_AVI_INFO3 + offset,
57e252bf 141 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
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142}
143
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144static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
145{
146 struct drm_device *dev = encoder->dev;
147 struct radeon_device *rdev = dev->dev_private;
148 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
149 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
150 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
151 u32 base_rate = 24000;
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152 u32 max_ratio = clock / base_rate;
153 u32 dto_phase;
154 u32 dto_modulo = clock;
155 u32 wallclock_ratio;
156 u32 dto_cntl;
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157
158 if (!dig || !dig->afmt)
159 return;
160
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161 if (max_ratio >= 8) {
162 dto_phase = 192 * 1000;
163 wallclock_ratio = 3;
164 } else if (max_ratio >= 4) {
165 dto_phase = 96 * 1000;
166 wallclock_ratio = 2;
167 } else if (max_ratio >= 2) {
168 dto_phase = 48 * 1000;
169 wallclock_ratio = 1;
170 } else {
171 dto_phase = 24 * 1000;
172 wallclock_ratio = 0;
173 }
174 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
175 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
176 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
177
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178 /* XXX two dtos; generally use dto0 for hdmi */
179 /* Express [24MHz / target pixel clock] as an exact rational
180 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
181 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
182 */
f43cf1b1 183 WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
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184 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
185 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
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186}
187
188
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189/*
190 * update the info frames with the data from the current display mode
191 */
192void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
193{
194 struct drm_device *dev = encoder->dev;
195 struct radeon_device *rdev = dev->dev_private;
196 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
197 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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198 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
199 struct hdmi_avi_infoframe frame;
926deccb 200 uint32_t offset;
b403bed8 201 ssize_t err;
926deccb 202
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203 if (!dig || !dig->afmt)
204 return;
205
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206 /* Silent, r600_hdmi_enable will raise WARN for us */
207 if (!dig->afmt->enabled)
208 return;
209 offset = dig->afmt->offset;
210
f43cf1b1 211 evergreen_audio_set_dto(encoder, mode->clock);
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212
213 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
214 HDMI_NULL_SEND); /* send null packets when required */
215
216 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
217
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218 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
219 HDMI_NULL_SEND | /* send null packets when required */
220 HDMI_GC_SEND | /* send general control packets */
221 HDMI_GC_CONT); /* send general control packets every frame */
222
223 WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
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224 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
225 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
226
227 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
228 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
229
230 WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
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231 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
232
233 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
234
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235 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
236 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
237 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
238
239 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
240 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
241
242 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
243
244 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
245 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
246 HDMI_ACR_SOURCE); /* select SW CTS value */
247
248 evergreen_hdmi_update_ACR(encoder, mode->clock);
249
250 WREG32(AFMT_60958_0 + offset,
251 AFMT_60958_CS_CHANNEL_NUMBER_L(1));
252
253 WREG32(AFMT_60958_1 + offset,
254 AFMT_60958_CS_CHANNEL_NUMBER_R(2));
255
256 WREG32(AFMT_60958_2 + offset,
257 AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
258 AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
259 AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
260 AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
261 AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
262 AFMT_60958_CS_CHANNEL_NUMBER_7(8));
263
264 /* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */
265
266 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
267 AFMT_AUDIO_CHANNEL_ENABLE(0xff));
268
269 /* fglrx sets 0x40 in 0x5f80 here */
270 evergreen_hdmi_write_sad_regs(encoder);
271
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272 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
273 if (err < 0) {
274 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
275 return;
276 }
277
278 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
279 if (err < 0) {
280 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
281 return;
282 }
926deccb 283
b403bed8 284 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
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285
286 WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
287 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
288 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
289
290 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
291 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
292 ~HDMI_AVI_INFO_LINE_MASK);
293
294 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
295 AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
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296
297 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
298 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
299 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
300 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
301 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
302}
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303
304void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
305{
306 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
307 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
308
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309 if (!dig || !dig->afmt)
310 return;
311
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312 /* Silent, r600_hdmi_enable will raise WARN for us */
313 if (enable && dig->afmt->enabled)
314 return;
315 if (!enable && !dig->afmt->enabled)
316 return;
317
318 dig->afmt->enabled = enable;
319
320 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
321 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
322}