drm/radeon: Sync to Linux 3.11
[dragonfly.git] / sys / dev / drm / radeon / r600.c
CommitLineData
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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 *
28 * $FreeBSD: head/sys/dev/drm2/radeon/r600.c 254885 2013-08-25 19:37:15Z dumbbell $
29 */
30
31#include <drm/drmP.h>
32#include <uapi_drm/radeon_drm.h>
33#include "radeon.h"
34#include "radeon_asic.h"
35#include "radeon_mode.h"
36#include "r600d.h"
37#include "atom.h"
38#include "avivod.h"
57e252bf 39#include "radeon_ucode.h"
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40
41#ifdef DUMBBELL_WIP
42/* Firmware Names */
43MODULE_FIRMWARE("radeon/R600_pfp.bin");
44MODULE_FIRMWARE("radeon/R600_me.bin");
45MODULE_FIRMWARE("radeon/RV610_pfp.bin");
46MODULE_FIRMWARE("radeon/RV610_me.bin");
47MODULE_FIRMWARE("radeon/RV630_pfp.bin");
48MODULE_FIRMWARE("radeon/RV630_me.bin");
49MODULE_FIRMWARE("radeon/RV620_pfp.bin");
50MODULE_FIRMWARE("radeon/RV620_me.bin");
51MODULE_FIRMWARE("radeon/RV635_pfp.bin");
52MODULE_FIRMWARE("radeon/RV635_me.bin");
53MODULE_FIRMWARE("radeon/RV670_pfp.bin");
54MODULE_FIRMWARE("radeon/RV670_me.bin");
55MODULE_FIRMWARE("radeon/RS780_pfp.bin");
56MODULE_FIRMWARE("radeon/RS780_me.bin");
57MODULE_FIRMWARE("radeon/RV770_pfp.bin");
58MODULE_FIRMWARE("radeon/RV770_me.bin");
57e252bf 59MODULE_FIRMWARE("radeon/RV770_smc.bin");
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60MODULE_FIRMWARE("radeon/RV730_pfp.bin");
61MODULE_FIRMWARE("radeon/RV730_me.bin");
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62MODULE_FIRMWARE("radeon/RV730_smc.bin");
63MODULE_FIRMWARE("radeon/RV740_smc.bin");
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64MODULE_FIRMWARE("radeon/RV710_pfp.bin");
65MODULE_FIRMWARE("radeon/RV710_me.bin");
57e252bf 66MODULE_FIRMWARE("radeon/RV710_smc.bin");
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67MODULE_FIRMWARE("radeon/R600_rlc.bin");
68MODULE_FIRMWARE("radeon/R700_rlc.bin");
69MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
70MODULE_FIRMWARE("radeon/CEDAR_me.bin");
71MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
57e252bf 72MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
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73MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
74MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
75MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
57e252bf 76MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
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77MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
78MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
79MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
57e252bf 80MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
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81MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
82MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
83MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
57e252bf 84MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
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85MODULE_FIRMWARE("radeon/PALM_pfp.bin");
86MODULE_FIRMWARE("radeon/PALM_me.bin");
87MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
88MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
89MODULE_FIRMWARE("radeon/SUMO_me.bin");
90MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
91MODULE_FIRMWARE("radeon/SUMO2_me.bin");
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92MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
93MODULE_FIRMWARE("radeon/OLAND_me.bin");
94MODULE_FIRMWARE("radeon/OLAND_ce.bin");
95MODULE_FIRMWARE("radeon/OLAND_mc.bin");
96MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
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97#endif /* DUMBBELL_WIP */
98
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99static const u32 crtc_offsets[2] =
100{
101 0,
102 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
103};
104
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105int r600_debugfs_mc_info_init(struct radeon_device *rdev);
106
107/* r600,rv610,rv630,rv620,rv635,rv670 */
108static void r600_gpu_init(struct radeon_device *rdev);
109void r600_irq_disable(struct radeon_device *rdev);
110static void r600_pcie_gen2_enable(struct radeon_device *rdev);
111
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112/**
113 * r600_get_xclk - get the xclk
114 *
115 * @rdev: radeon_device pointer
116 *
117 * Returns the reference clock used by the gfx engine
118 * (r6xx, IGPs, APUs).
119 */
120u32 r600_get_xclk(struct radeon_device *rdev)
121{
122 return rdev->clock.spll.reference_freq;
123}
124
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125/* get temperature in millidegrees */
126int rv6xx_get_temp(struct radeon_device *rdev)
127{
128 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
129 ASIC_T_SHIFT;
130 int actual_temp = temp & 0xff;
131
132 if (temp & 0x100)
133 actual_temp -= 256;
134
135 return actual_temp * 1000;
136}
137
138void r600_pm_get_dynpm_state(struct radeon_device *rdev)
139{
140 int i;
141
142 rdev->pm.dynpm_can_upclock = true;
143 rdev->pm.dynpm_can_downclock = true;
144
145 /* power state array is low to high, default is first */
146 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
147 int min_power_state_index = 0;
148
149 if (rdev->pm.num_power_states > 2)
150 min_power_state_index = 1;
151
152 switch (rdev->pm.dynpm_planned_action) {
153 case DYNPM_ACTION_MINIMUM:
154 rdev->pm.requested_power_state_index = min_power_state_index;
155 rdev->pm.requested_clock_mode_index = 0;
156 rdev->pm.dynpm_can_downclock = false;
157 break;
158 case DYNPM_ACTION_DOWNCLOCK:
159 if (rdev->pm.current_power_state_index == min_power_state_index) {
160 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
161 rdev->pm.dynpm_can_downclock = false;
162 } else {
163 if (rdev->pm.active_crtc_count > 1) {
164 for (i = 0; i < rdev->pm.num_power_states; i++) {
165 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
166 continue;
167 else if (i >= rdev->pm.current_power_state_index) {
168 rdev->pm.requested_power_state_index =
169 rdev->pm.current_power_state_index;
170 break;
171 } else {
172 rdev->pm.requested_power_state_index = i;
173 break;
174 }
175 }
176 } else {
177 if (rdev->pm.current_power_state_index == 0)
178 rdev->pm.requested_power_state_index =
179 rdev->pm.num_power_states - 1;
180 else
181 rdev->pm.requested_power_state_index =
182 rdev->pm.current_power_state_index - 1;
183 }
184 }
185 rdev->pm.requested_clock_mode_index = 0;
186 /* don't use the power state if crtcs are active and no display flag is set */
187 if ((rdev->pm.active_crtc_count > 0) &&
188 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
189 clock_info[rdev->pm.requested_clock_mode_index].flags &
190 RADEON_PM_MODE_NO_DISPLAY)) {
191 rdev->pm.requested_power_state_index++;
192 }
193 break;
194 case DYNPM_ACTION_UPCLOCK:
195 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
196 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
197 rdev->pm.dynpm_can_upclock = false;
198 } else {
199 if (rdev->pm.active_crtc_count > 1) {
200 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
201 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
202 continue;
203 else if (i <= rdev->pm.current_power_state_index) {
204 rdev->pm.requested_power_state_index =
205 rdev->pm.current_power_state_index;
206 break;
207 } else {
208 rdev->pm.requested_power_state_index = i;
209 break;
210 }
211 }
212 } else
213 rdev->pm.requested_power_state_index =
214 rdev->pm.current_power_state_index + 1;
215 }
216 rdev->pm.requested_clock_mode_index = 0;
217 break;
218 case DYNPM_ACTION_DEFAULT:
219 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
220 rdev->pm.requested_clock_mode_index = 0;
221 rdev->pm.dynpm_can_upclock = false;
222 break;
223 case DYNPM_ACTION_NONE:
224 default:
225 DRM_ERROR("Requested mode for not defined action\n");
226 return;
227 }
228 } else {
229 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
230 /* for now just select the first power state and switch between clock modes */
231 /* power state array is low to high, default is first (0) */
232 if (rdev->pm.active_crtc_count > 1) {
233 rdev->pm.requested_power_state_index = -1;
234 /* start at 1 as we don't want the default mode */
235 for (i = 1; i < rdev->pm.num_power_states; i++) {
236 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
237 continue;
238 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
239 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
240 rdev->pm.requested_power_state_index = i;
241 break;
242 }
243 }
244 /* if nothing selected, grab the default state. */
245 if (rdev->pm.requested_power_state_index == -1)
246 rdev->pm.requested_power_state_index = 0;
247 } else
248 rdev->pm.requested_power_state_index = 1;
249
250 switch (rdev->pm.dynpm_planned_action) {
251 case DYNPM_ACTION_MINIMUM:
252 rdev->pm.requested_clock_mode_index = 0;
253 rdev->pm.dynpm_can_downclock = false;
254 break;
255 case DYNPM_ACTION_DOWNCLOCK:
256 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
257 if (rdev->pm.current_clock_mode_index == 0) {
258 rdev->pm.requested_clock_mode_index = 0;
259 rdev->pm.dynpm_can_downclock = false;
260 } else
261 rdev->pm.requested_clock_mode_index =
262 rdev->pm.current_clock_mode_index - 1;
263 } else {
264 rdev->pm.requested_clock_mode_index = 0;
265 rdev->pm.dynpm_can_downclock = false;
266 }
267 /* don't use the power state if crtcs are active and no display flag is set */
268 if ((rdev->pm.active_crtc_count > 0) &&
269 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
270 clock_info[rdev->pm.requested_clock_mode_index].flags &
271 RADEON_PM_MODE_NO_DISPLAY)) {
272 rdev->pm.requested_clock_mode_index++;
273 }
274 break;
275 case DYNPM_ACTION_UPCLOCK:
276 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
277 if (rdev->pm.current_clock_mode_index ==
278 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
279 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
280 rdev->pm.dynpm_can_upclock = false;
281 } else
282 rdev->pm.requested_clock_mode_index =
283 rdev->pm.current_clock_mode_index + 1;
284 } else {
285 rdev->pm.requested_clock_mode_index =
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
287 rdev->pm.dynpm_can_upclock = false;
288 }
289 break;
290 case DYNPM_ACTION_DEFAULT:
291 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
292 rdev->pm.requested_clock_mode_index = 0;
293 rdev->pm.dynpm_can_upclock = false;
294 break;
295 case DYNPM_ACTION_NONE:
296 default:
297 DRM_ERROR("Requested mode for not defined action\n");
298 return;
299 }
300 }
301
302 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
303 rdev->pm.power_state[rdev->pm.requested_power_state_index].
304 clock_info[rdev->pm.requested_clock_mode_index].sclk,
305 rdev->pm.power_state[rdev->pm.requested_power_state_index].
306 clock_info[rdev->pm.requested_clock_mode_index].mclk,
307 rdev->pm.power_state[rdev->pm.requested_power_state_index].
308 pcie_lanes);
309}
310
311void rs780_pm_init_profile(struct radeon_device *rdev)
312{
313 if (rdev->pm.num_power_states == 2) {
314 /* default */
315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
319 /* low sh */
320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
324 /* mid sh */
325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
329 /* high sh */
330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
334 /* low mh */
335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
339 /* mid mh */
340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
344 /* high mh */
345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
349 } else if (rdev->pm.num_power_states == 3) {
350 /* default */
351 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
352 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
353 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
355 /* low sh */
356 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
357 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
358 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
359 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
360 /* mid sh */
361 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
362 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
363 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
364 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
365 /* high sh */
366 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
367 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
368 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
369 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
370 /* low mh */
371 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
372 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
373 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
374 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
375 /* mid mh */
376 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
377 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
378 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
379 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
380 /* high mh */
381 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
382 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
384 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
385 } else {
386 /* default */
387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
388 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
389 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
391 /* low sh */
392 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
393 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
394 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
396 /* mid sh */
397 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
398 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
399 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
400 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
401 /* high sh */
402 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
403 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
404 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
405 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
406 /* low mh */
407 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
408 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
409 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
410 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
411 /* mid mh */
412 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
413 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
414 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
415 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
416 /* high mh */
417 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
418 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
419 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
420 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
421 }
422}
423
424void r600_pm_init_profile(struct radeon_device *rdev)
425{
426 int idx;
427
428 if (rdev->family == CHIP_R600) {
429 /* XXX */
430 /* default */
431 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
432 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
434 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
435 /* low sh */
436 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
437 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
439 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
440 /* mid sh */
441 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
442 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
444 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
445 /* high sh */
446 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
447 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
448 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
449 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
450 /* low mh */
451 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
452 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
453 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
454 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
455 /* mid mh */
456 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
457 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
458 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
459 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
460 /* high mh */
461 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
462 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
463 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
464 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
465 } else {
466 if (rdev->pm.num_power_states < 4) {
467 /* default */
468 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
469 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
470 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
471 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
472 /* low sh */
473 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
474 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
475 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
476 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
477 /* mid sh */
478 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
479 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
480 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
481 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
482 /* high sh */
483 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
484 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
485 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
486 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
487 /* low mh */
488 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
489 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
490 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
491 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
492 /* low mh */
493 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
494 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
495 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
496 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
497 /* high mh */
498 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
499 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
500 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
501 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
502 } else {
503 /* default */
504 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
505 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
506 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
507 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
508 /* low sh */
509 if (rdev->flags & RADEON_IS_MOBILITY)
510 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
511 else
512 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
513 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
514 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
515 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
516 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
517 /* mid sh */
518 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
519 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
520 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
522 /* high sh */
523 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
524 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
525 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
526 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
527 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
528 /* low mh */
529 if (rdev->flags & RADEON_IS_MOBILITY)
530 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
531 else
532 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
533 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
534 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
535 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
536 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
537 /* mid mh */
538 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
539 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
540 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
541 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
542 /* high mh */
543 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
544 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
545 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
546 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
547 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
548 }
549 }
550}
551
552void r600_pm_misc(struct radeon_device *rdev)
553{
554 int req_ps_idx = rdev->pm.requested_power_state_index;
555 int req_cm_idx = rdev->pm.requested_clock_mode_index;
556 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
557 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
558
559 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
560 /* 0xff01 is a flag rather then an actual voltage */
561 if (voltage->voltage == 0xff01)
562 return;
563 if (voltage->voltage != rdev->pm.current_vddc) {
564 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
565 rdev->pm.current_vddc = voltage->voltage;
566 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
567 }
568 }
569}
570
571bool r600_gui_idle(struct radeon_device *rdev)
572{
573 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
574 return false;
575 else
576 return true;
577}
578
579/* hpd for digital panel detect/disconnect */
580bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
581{
582 bool connected = false;
583
584 if (ASIC_IS_DCE3(rdev)) {
585 switch (hpd) {
586 case RADEON_HPD_1:
587 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
588 connected = true;
589 break;
590 case RADEON_HPD_2:
591 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
592 connected = true;
593 break;
594 case RADEON_HPD_3:
595 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
596 connected = true;
597 break;
598 case RADEON_HPD_4:
599 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
600 connected = true;
601 break;
602 /* DCE 3.2 */
603 case RADEON_HPD_5:
604 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
605 connected = true;
606 break;
607 case RADEON_HPD_6:
608 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
609 connected = true;
610 break;
611 default:
612 break;
613 }
614 } else {
615 switch (hpd) {
616 case RADEON_HPD_1:
617 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
618 connected = true;
619 break;
620 case RADEON_HPD_2:
621 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
622 connected = true;
623 break;
624 case RADEON_HPD_3:
625 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
626 connected = true;
627 break;
628 default:
629 break;
630 }
631 }
632 return connected;
633}
634
635void r600_hpd_set_polarity(struct radeon_device *rdev,
636 enum radeon_hpd_id hpd)
637{
638 u32 tmp;
639 bool connected = r600_hpd_sense(rdev, hpd);
640
641 if (ASIC_IS_DCE3(rdev)) {
642 switch (hpd) {
643 case RADEON_HPD_1:
644 tmp = RREG32(DC_HPD1_INT_CONTROL);
645 if (connected)
646 tmp &= ~DC_HPDx_INT_POLARITY;
647 else
648 tmp |= DC_HPDx_INT_POLARITY;
649 WREG32(DC_HPD1_INT_CONTROL, tmp);
650 break;
651 case RADEON_HPD_2:
652 tmp = RREG32(DC_HPD2_INT_CONTROL);
653 if (connected)
654 tmp &= ~DC_HPDx_INT_POLARITY;
655 else
656 tmp |= DC_HPDx_INT_POLARITY;
657 WREG32(DC_HPD2_INT_CONTROL, tmp);
658 break;
659 case RADEON_HPD_3:
660 tmp = RREG32(DC_HPD3_INT_CONTROL);
661 if (connected)
662 tmp &= ~DC_HPDx_INT_POLARITY;
663 else
664 tmp |= DC_HPDx_INT_POLARITY;
665 WREG32(DC_HPD3_INT_CONTROL, tmp);
666 break;
667 case RADEON_HPD_4:
668 tmp = RREG32(DC_HPD4_INT_CONTROL);
669 if (connected)
670 tmp &= ~DC_HPDx_INT_POLARITY;
671 else
672 tmp |= DC_HPDx_INT_POLARITY;
673 WREG32(DC_HPD4_INT_CONTROL, tmp);
674 break;
675 case RADEON_HPD_5:
676 tmp = RREG32(DC_HPD5_INT_CONTROL);
677 if (connected)
678 tmp &= ~DC_HPDx_INT_POLARITY;
679 else
680 tmp |= DC_HPDx_INT_POLARITY;
681 WREG32(DC_HPD5_INT_CONTROL, tmp);
682 break;
683 /* DCE 3.2 */
684 case RADEON_HPD_6:
685 tmp = RREG32(DC_HPD6_INT_CONTROL);
686 if (connected)
687 tmp &= ~DC_HPDx_INT_POLARITY;
688 else
689 tmp |= DC_HPDx_INT_POLARITY;
690 WREG32(DC_HPD6_INT_CONTROL, tmp);
691 break;
692 default:
693 break;
694 }
695 } else {
696 switch (hpd) {
697 case RADEON_HPD_1:
698 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
699 if (connected)
700 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
701 else
702 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
703 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
704 break;
705 case RADEON_HPD_2:
706 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
707 if (connected)
708 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
709 else
710 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
711 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
712 break;
713 case RADEON_HPD_3:
714 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
715 if (connected)
716 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
717 else
718 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
719 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
720 break;
721 default:
722 break;
723 }
724 }
725}
726
727void r600_hpd_init(struct radeon_device *rdev)
728{
729 struct drm_device *dev = rdev->ddev;
730 struct drm_connector *connector;
731 unsigned enable = 0;
732
733 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
734 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
735
736 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
737 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
738 /* don't try to enable hpd on eDP or LVDS avoid breaking the
739 * aux dp channel on imac and help (but not completely fix)
740 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
741 */
742 continue;
743 }
744 if (ASIC_IS_DCE3(rdev)) {
745 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
746 if (ASIC_IS_DCE32(rdev))
747 tmp |= DC_HPDx_EN;
748
749 switch (radeon_connector->hpd.hpd) {
750 case RADEON_HPD_1:
751 WREG32(DC_HPD1_CONTROL, tmp);
752 break;
753 case RADEON_HPD_2:
754 WREG32(DC_HPD2_CONTROL, tmp);
755 break;
756 case RADEON_HPD_3:
757 WREG32(DC_HPD3_CONTROL, tmp);
758 break;
759 case RADEON_HPD_4:
760 WREG32(DC_HPD4_CONTROL, tmp);
761 break;
762 /* DCE 3.2 */
763 case RADEON_HPD_5:
764 WREG32(DC_HPD5_CONTROL, tmp);
765 break;
766 case RADEON_HPD_6:
767 WREG32(DC_HPD6_CONTROL, tmp);
768 break;
769 default:
770 break;
771 }
772 } else {
773 switch (radeon_connector->hpd.hpd) {
774 case RADEON_HPD_1:
775 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
776 break;
777 case RADEON_HPD_2:
778 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
779 break;
780 case RADEON_HPD_3:
781 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
782 break;
783 default:
784 break;
785 }
786 }
787 enable |= 1 << radeon_connector->hpd.hpd;
788 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
789 }
790 radeon_irq_kms_enable_hpd(rdev, enable);
791}
792
793void r600_hpd_fini(struct radeon_device *rdev)
794{
795 struct drm_device *dev = rdev->ddev;
796 struct drm_connector *connector;
797 unsigned disable = 0;
798
799 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
800 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
801 if (ASIC_IS_DCE3(rdev)) {
802 switch (radeon_connector->hpd.hpd) {
803 case RADEON_HPD_1:
804 WREG32(DC_HPD1_CONTROL, 0);
805 break;
806 case RADEON_HPD_2:
807 WREG32(DC_HPD2_CONTROL, 0);
808 break;
809 case RADEON_HPD_3:
810 WREG32(DC_HPD3_CONTROL, 0);
811 break;
812 case RADEON_HPD_4:
813 WREG32(DC_HPD4_CONTROL, 0);
814 break;
815 /* DCE 3.2 */
816 case RADEON_HPD_5:
817 WREG32(DC_HPD5_CONTROL, 0);
818 break;
819 case RADEON_HPD_6:
820 WREG32(DC_HPD6_CONTROL, 0);
821 break;
822 default:
823 break;
824 }
825 } else {
826 switch (radeon_connector->hpd.hpd) {
827 case RADEON_HPD_1:
828 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
829 break;
830 case RADEON_HPD_2:
831 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
832 break;
833 case RADEON_HPD_3:
834 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
835 break;
836 default:
837 break;
838 }
839 }
840 disable |= 1 << radeon_connector->hpd.hpd;
841 }
842 radeon_irq_kms_disable_hpd(rdev, disable);
843}
844
845/*
846 * R600 PCIE GART
847 */
848void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
849{
850 unsigned i;
851 u32 tmp;
852
853 /* flush hdp cache so updates hit vram */
854 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
855 !(rdev->flags & RADEON_IS_AGP)) {
856 volatile uint32_t *ptr = rdev->gart.ptr;
857 u32 tmp;
858
859 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
860 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
861 * This seems to cause problems on some AGP cards. Just use the old
862 * method for them.
863 */
864 WREG32(HDP_DEBUG1, 0);
865 tmp = *ptr;
866 } else
867 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
868
869 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
870 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
871 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
872 for (i = 0; i < rdev->usec_timeout; i++) {
873 /* read MC_STATUS */
874 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
875 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
876 if (tmp == 2) {
877 DRM_ERROR("[drm] r600 flush TLB failed\n");
878 return;
879 }
880 if (tmp) {
881 return;
882 }
883 DRM_UDELAY(1);
884 }
885}
886
887int r600_pcie_gart_init(struct radeon_device *rdev)
888{
889 int r;
890
891 if (rdev->gart.robj) {
892 DRM_ERROR("R600 PCIE GART already initialized\n");
893 return 0;
894 }
895 /* Initialize common gart structure */
896 r = radeon_gart_init(rdev);
897 if (r)
898 return r;
899 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
900 return radeon_gart_table_vram_alloc(rdev);
901}
902
903static int r600_pcie_gart_enable(struct radeon_device *rdev)
904{
905 u32 tmp;
906 int r, i;
907
908 if (rdev->gart.robj == NULL) {
909 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
910 return -EINVAL;
911 }
912 r = radeon_gart_table_vram_pin(rdev);
913 if (r)
914 return r;
915 radeon_gart_restore(rdev);
916
917 /* Setup L2 cache */
918 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
919 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
920 EFFECTIVE_L2_QUEUE_SIZE(7));
921 WREG32(VM_L2_CNTL2, 0);
922 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
923 /* Setup TLB control */
924 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
925 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
926 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
927 ENABLE_WAIT_L2_QUERY;
928 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
929 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
930 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
931 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
932 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
933 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
934 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
935 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
936 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
937 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
938 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
939 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
940 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
941 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
942 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
943 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
944 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
945 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
946 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
947 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
948 (u32)(rdev->dummy_page.addr >> 12));
949 for (i = 1; i < 7; i++)
950 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
951
952 r600_pcie_gart_tlb_flush(rdev);
953 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
954 (unsigned)(rdev->mc.gtt_size >> 20),
955 (unsigned long long)rdev->gart.table_addr);
956 rdev->gart.ready = true;
957 return 0;
958}
959
960static void r600_pcie_gart_disable(struct radeon_device *rdev)
961{
962 u32 tmp;
963 int i;
964
965 /* Disable all tables */
966 for (i = 0; i < 7; i++)
967 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
968
969 /* Disable L2 cache */
970 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
971 EFFECTIVE_L2_QUEUE_SIZE(7));
972 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
973 /* Setup L1 TLB control */
974 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
975 ENABLE_WAIT_L2_QUERY;
976 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
980 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
981 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
982 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
983 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
984 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
985 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
986 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
987 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
988 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
989 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
990 radeon_gart_table_vram_unpin(rdev);
991}
992
993static void r600_pcie_gart_fini(struct radeon_device *rdev)
994{
995 radeon_gart_fini(rdev);
996 r600_pcie_gart_disable(rdev);
997 radeon_gart_table_vram_free(rdev);
998}
999
1000static void r600_agp_enable(struct radeon_device *rdev)
1001{
1002 u32 tmp;
1003 int i;
1004
1005 /* Setup L2 cache */
1006 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1007 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1008 EFFECTIVE_L2_QUEUE_SIZE(7));
1009 WREG32(VM_L2_CNTL2, 0);
1010 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1011 /* Setup TLB control */
1012 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1013 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1014 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1015 ENABLE_WAIT_L2_QUERY;
1016 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1017 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1018 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1019 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1020 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1021 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1022 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1023 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1024 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1025 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1026 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1027 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1028 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1029 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1030 for (i = 0; i < 7; i++)
1031 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1032}
1033
1034int r600_mc_wait_for_idle(struct radeon_device *rdev)
1035{
1036 unsigned i;
1037 u32 tmp;
1038
1039 for (i = 0; i < rdev->usec_timeout; i++) {
1040 /* read MC_STATUS */
1041 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1042 if (!tmp)
1043 return 0;
1044 DRM_UDELAY(1);
1045 }
1046 return -1;
1047}
1048
f43cf1b1
MN
1049uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1050{
1051 uint32_t r;
1052
1053 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1054 r = RREG32(R_0028FC_MC_DATA);
1055 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1056 return r;
1057}
1058
1059void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1060{
1061 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1062 S_0028F8_MC_IND_WR_EN(1));
1063 WREG32(R_0028FC_MC_DATA, v);
1064 WREG32(R_0028F8_MC_INDEX, 0x7F);
1065}
1066
926deccb
FT
1067static void r600_mc_program(struct radeon_device *rdev)
1068{
1069 struct rv515_mc_save save;
1070 u32 tmp;
1071 int i, j;
1072
1073 /* Initialize HDP */
1074 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1075 WREG32((0x2c14 + j), 0x00000000);
1076 WREG32((0x2c18 + j), 0x00000000);
1077 WREG32((0x2c1c + j), 0x00000000);
1078 WREG32((0x2c20 + j), 0x00000000);
1079 WREG32((0x2c24 + j), 0x00000000);
1080 }
1081 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1082
1083 rv515_mc_stop(rdev, &save);
1084 if (r600_mc_wait_for_idle(rdev)) {
1085 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1086 }
1087 /* Lockout access through VGA aperture (doesn't exist before R600) */
1088 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1089 /* Update configuration */
1090 if (rdev->flags & RADEON_IS_AGP) {
1091 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1092 /* VRAM before AGP */
1093 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1094 rdev->mc.vram_start >> 12);
1095 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1096 rdev->mc.gtt_end >> 12);
1097 } else {
1098 /* VRAM after AGP */
1099 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1100 rdev->mc.gtt_start >> 12);
1101 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1102 rdev->mc.vram_end >> 12);
1103 }
1104 } else {
1105 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1106 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1107 }
1108 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1109 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1110 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1111 WREG32(MC_VM_FB_LOCATION, tmp);
1112 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1113 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1114 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1115 if (rdev->flags & RADEON_IS_AGP) {
1116 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1117 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1118 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1119 } else {
1120 WREG32(MC_VM_AGP_BASE, 0);
1121 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1122 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1123 }
1124 if (r600_mc_wait_for_idle(rdev)) {
1125 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1126 }
1127 rv515_mc_resume(rdev, &save);
1128 /* we need to own VRAM, so turn off the VGA renderer here
1129 * to stop it overwriting our objects */
1130 rv515_vga_render_disable(rdev);
1131}
1132
1133/**
1134 * r600_vram_gtt_location - try to find VRAM & GTT location
1135 * @rdev: radeon device structure holding all necessary informations
1136 * @mc: memory controller structure holding memory informations
1137 *
1138 * Function will place try to place VRAM at same place as in CPU (PCI)
1139 * address space as some GPU seems to have issue when we reprogram at
1140 * different address space.
1141 *
1142 * If there is not enough space to fit the unvisible VRAM after the
1143 * aperture then we limit the VRAM size to the aperture.
1144 *
1145 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1146 * them to be in one from GPU point of view so that we can program GPU to
1147 * catch access outside them (weird GPU policy see ??).
1148 *
1149 * This function will never fails, worst case are limiting VRAM or GTT.
1150 *
1151 * Note: GTT start, end, size should be initialized before calling this
1152 * function on AGP platform.
1153 */
1154static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1155{
1156 u64 size_bf, size_af;
1157
1158 if (mc->mc_vram_size > 0xE0000000) {
1159 /* leave room for at least 512M GTT */
1160 dev_warn(rdev->dev, "limiting VRAM\n");
1161 mc->real_vram_size = 0xE0000000;
1162 mc->mc_vram_size = 0xE0000000;
1163 }
1164 if (rdev->flags & RADEON_IS_AGP) {
1165 size_bf = mc->gtt_start;
f43cf1b1 1166 size_af = mc->mc_mask - mc->gtt_end;
926deccb
FT
1167 if (size_bf > size_af) {
1168 if (mc->mc_vram_size > size_bf) {
1169 dev_warn(rdev->dev, "limiting VRAM\n");
1170 mc->real_vram_size = size_bf;
1171 mc->mc_vram_size = size_bf;
1172 }
1173 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1174 } else {
1175 if (mc->mc_vram_size > size_af) {
1176 dev_warn(rdev->dev, "limiting VRAM\n");
1177 mc->real_vram_size = size_af;
1178 mc->mc_vram_size = size_af;
1179 }
1180 mc->vram_start = mc->gtt_end + 1;
1181 }
1182 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1183 dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n",
1184 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
1185 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20);
1186 } else {
1187 u64 base = 0;
1188 if (rdev->flags & RADEON_IS_IGP) {
1189 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1190 base <<= 24;
1191 }
1192 radeon_vram_location(rdev, &rdev->mc, base);
1193 rdev->mc.gtt_base_align = 0;
1194 radeon_gtt_location(rdev, mc);
1195 }
1196}
1197
1198static int r600_mc_init(struct radeon_device *rdev)
1199{
1200 u32 tmp;
1201 int chansize, numchan;
f43cf1b1
MN
1202 uint32_t h_addr, l_addr;
1203 unsigned long long k8_addr;
926deccb
FT
1204
1205 /* Get VRAM informations */
1206 rdev->mc.vram_is_ddr = true;
1207 tmp = RREG32(RAMCFG);
1208 if (tmp & CHANSIZE_OVERRIDE) {
1209 chansize = 16;
1210 } else if (tmp & CHANSIZE_MASK) {
1211 chansize = 64;
1212 } else {
1213 chansize = 32;
1214 }
1215 tmp = RREG32(CHMAP);
1216 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1217 case 0:
1218 default:
1219 numchan = 1;
1220 break;
1221 case 1:
1222 numchan = 2;
1223 break;
1224 case 2:
1225 numchan = 4;
1226 break;
1227 case 3:
1228 numchan = 8;
1229 break;
1230 }
1231 rdev->mc.vram_width = numchan * chansize;
1232 /* Could aper size report 0 ? */
1233 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1234 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1235 /* Setup GPU memory space */
1236 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1237 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1238 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1239 r600_vram_gtt_location(rdev, &rdev->mc);
1240
1241 if (rdev->flags & RADEON_IS_IGP) {
1242 rs690_pm_info(rdev);
1243 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f43cf1b1
MN
1244
1245 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1246 /* Use K8 direct mapping for fast fb access. */
1247 rdev->fastfb_working = false;
1248 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1249 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1250 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1251#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1252 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1253#endif
1254 {
1255 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1256 * memory is present.
1257 */
1258 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1259 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1260 (unsigned long long)rdev->mc.aper_base, k8_addr);
1261 rdev->mc.aper_base = (resource_size_t)k8_addr;
1262 rdev->fastfb_working = true;
1263 }
1264 }
1265 }
926deccb 1266 }
f43cf1b1 1267
926deccb
FT
1268 radeon_update_bandwidth_info(rdev);
1269 return 0;
1270}
1271
1272int r600_vram_scratch_init(struct radeon_device *rdev)
1273{
1274 int r;
1275 void *vram_scratch_ptr_ptr;
1276
1277 if (rdev->vram_scratch.robj == NULL) {
1278 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1279 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1280 NULL, &rdev->vram_scratch.robj);
1281 if (r) {
1282 return r;
1283 }
1284 }
1285
1286 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1287 if (unlikely(r != 0)) {
1288 radeon_bo_unref(&rdev->vram_scratch.robj);
1289 return r;
1290 }
1291 r = radeon_bo_pin(rdev->vram_scratch.robj,
1292 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1293 if (r) {
1294 radeon_bo_unreserve(rdev->vram_scratch.robj);
1295 radeon_bo_unref(&rdev->vram_scratch.robj);
1296 return r;
1297 }
1298 vram_scratch_ptr_ptr = &rdev->vram_scratch.ptr;
1299 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1300 vram_scratch_ptr_ptr);
1301 if (r)
1302 radeon_bo_unpin(rdev->vram_scratch.robj);
1303 radeon_bo_unreserve(rdev->vram_scratch.robj);
1304 if (r)
1305 radeon_bo_unref(&rdev->vram_scratch.robj);
1306
1307 return r;
1308}
1309
1310void r600_vram_scratch_fini(struct radeon_device *rdev)
1311{
1312 int r;
1313
1314 if (rdev->vram_scratch.robj == NULL) {
1315 return;
1316 }
1317 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1318 if (likely(r == 0)) {
1319 radeon_bo_kunmap(rdev->vram_scratch.robj);
1320 radeon_bo_unpin(rdev->vram_scratch.robj);
1321 radeon_bo_unreserve(rdev->vram_scratch.robj);
1322 }
1323 radeon_bo_unref(&rdev->vram_scratch.robj);
1324}
1325
b403bed8 1326void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
926deccb 1327{
b403bed8 1328 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
926deccb 1329
b403bed8
MN
1330 if (hung)
1331 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1332 else
1333 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1334
1335 WREG32(R600_BIOS_3_SCRATCH, tmp);
1336}
926deccb 1337
b403bed8
MN
1338static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1339{
926deccb 1340 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
b403bed8 1341 RREG32(R_008010_GRBM_STATUS));
926deccb 1342 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
b403bed8 1343 RREG32(R_008014_GRBM_STATUS2));
926deccb 1344 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
b403bed8 1345 RREG32(R_000E50_SRBM_STATUS));
926deccb 1346 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
b403bed8 1347 RREG32(CP_STALLED_STAT1));
926deccb 1348 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
b403bed8 1349 RREG32(CP_STALLED_STAT2));
926deccb 1350 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
b403bed8 1351 RREG32(CP_BUSY_STAT));
926deccb 1352 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
b403bed8
MN
1353 RREG32(CP_STAT));
1354 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1355 RREG32(DMA_STATUS_REG));
1356}
926deccb 1357
b403bed8
MN
1358static bool r600_is_display_hung(struct radeon_device *rdev)
1359{
1360 u32 crtc_hung = 0;
1361 u32 crtc_status[2];
1362 u32 i, j, tmp;
1363
1364 for (i = 0; i < rdev->num_crtc; i++) {
1365 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1366 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1367 crtc_hung |= (1 << i);
1368 }
926deccb 1369 }
926deccb 1370
b403bed8
MN
1371 for (j = 0; j < 10; j++) {
1372 for (i = 0; i < rdev->num_crtc; i++) {
1373 if (crtc_hung & (1 << i)) {
1374 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1375 if (tmp != crtc_status[i])
1376 crtc_hung &= ~(1 << i);
1377 }
1378 }
1379 if (crtc_hung == 0)
1380 return false;
1381 DRM_UDELAY(100);
1382 }
926deccb 1383
b403bed8 1384 return true;
926deccb
FT
1385}
1386
b403bed8 1387static u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
926deccb 1388{
b403bed8 1389 u32 reset_mask = 0;
926deccb
FT
1390 u32 tmp;
1391
b403bed8
MN
1392 /* GRBM_STATUS */
1393 tmp = RREG32(R_008010_GRBM_STATUS);
1394 if (rdev->family >= CHIP_RV770) {
1395 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1396 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1397 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1398 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1399 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1400 reset_mask |= RADEON_RESET_GFX;
1401 } else {
1402 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1403 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1404 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1405 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1406 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1407 reset_mask |= RADEON_RESET_GFX;
1408 }
926deccb 1409
b403bed8
MN
1410 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1411 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1412 reset_mask |= RADEON_RESET_CP;
926deccb 1413
b403bed8
MN
1414 if (G_008010_GRBM_EE_BUSY(tmp))
1415 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
926deccb 1416
b403bed8
MN
1417 /* DMA_STATUS_REG */
1418 tmp = RREG32(DMA_STATUS_REG);
1419 if (!(tmp & DMA_IDLE))
1420 reset_mask |= RADEON_RESET_DMA;
926deccb 1421
b403bed8
MN
1422 /* SRBM_STATUS */
1423 tmp = RREG32(R_000E50_SRBM_STATUS);
1424 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1425 reset_mask |= RADEON_RESET_RLC;
1426
1427 if (G_000E50_IH_BUSY(tmp))
1428 reset_mask |= RADEON_RESET_IH;
1429
1430 if (G_000E50_SEM_BUSY(tmp))
1431 reset_mask |= RADEON_RESET_SEM;
1432
1433 if (G_000E50_GRBM_RQ_PENDING(tmp))
1434 reset_mask |= RADEON_RESET_GRBM;
1435
1436 if (G_000E50_VMC_BUSY(tmp))
1437 reset_mask |= RADEON_RESET_VMC;
1438
1439 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1440 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1441 G_000E50_MCDW_BUSY(tmp))
1442 reset_mask |= RADEON_RESET_MC;
1443
1444 if (r600_is_display_hung(rdev))
1445 reset_mask |= RADEON_RESET_DISPLAY;
1446
1447 /* Skip MC reset as it's mostly likely not hung, just busy */
1448 if (reset_mask & RADEON_RESET_MC) {
1449 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1450 reset_mask &= ~RADEON_RESET_MC;
1451 }
1452
1453 return reset_mask;
926deccb
FT
1454}
1455
b403bed8 1456static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
926deccb
FT
1457{
1458 struct rv515_mc_save save;
b403bed8
MN
1459 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1460 u32 tmp;
926deccb
FT
1461
1462 if (reset_mask == 0)
b403bed8 1463 return;
926deccb
FT
1464
1465 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1466
b403bed8
MN
1467 r600_print_gpu_status_regs(rdev);
1468
1469 /* Disable CP parsing/prefetching */
1470 if (rdev->family >= CHIP_RV770)
1471 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1472 else
1473 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1474
1475 /* disable the RLC */
1476 WREG32(RLC_CNTL, 0);
1477
1478 if (reset_mask & RADEON_RESET_DMA) {
1479 /* Disable DMA */
1480 tmp = RREG32(DMA_RB_CNTL);
1481 tmp &= ~DMA_RB_ENABLE;
1482 WREG32(DMA_RB_CNTL, tmp);
1483 }
1484
1485 DRM_MDELAY(50);
1486
926deccb
FT
1487 rv515_mc_stop(rdev, &save);
1488 if (r600_mc_wait_for_idle(rdev)) {
1489 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1490 }
1491
b403bed8
MN
1492 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1493 if (rdev->family >= CHIP_RV770)
1494 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1495 S_008020_SOFT_RESET_CB(1) |
1496 S_008020_SOFT_RESET_PA(1) |
1497 S_008020_SOFT_RESET_SC(1) |
1498 S_008020_SOFT_RESET_SPI(1) |
1499 S_008020_SOFT_RESET_SX(1) |
1500 S_008020_SOFT_RESET_SH(1) |
1501 S_008020_SOFT_RESET_TC(1) |
1502 S_008020_SOFT_RESET_TA(1) |
1503 S_008020_SOFT_RESET_VC(1) |
1504 S_008020_SOFT_RESET_VGT(1);
1505 else
1506 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1507 S_008020_SOFT_RESET_DB(1) |
1508 S_008020_SOFT_RESET_CB(1) |
1509 S_008020_SOFT_RESET_PA(1) |
1510 S_008020_SOFT_RESET_SC(1) |
1511 S_008020_SOFT_RESET_SMX(1) |
1512 S_008020_SOFT_RESET_SPI(1) |
1513 S_008020_SOFT_RESET_SX(1) |
1514 S_008020_SOFT_RESET_SH(1) |
1515 S_008020_SOFT_RESET_TC(1) |
1516 S_008020_SOFT_RESET_TA(1) |
1517 S_008020_SOFT_RESET_VC(1) |
1518 S_008020_SOFT_RESET_VGT(1);
1519 }
1520
1521 if (reset_mask & RADEON_RESET_CP) {
1522 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1523 S_008020_SOFT_RESET_VGT(1);
1524
1525 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1526 }
1527
1528 if (reset_mask & RADEON_RESET_DMA) {
1529 if (rdev->family >= CHIP_RV770)
1530 srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1531 else
1532 srbm_soft_reset |= SOFT_RESET_DMA;
1533 }
1534
1535 if (reset_mask & RADEON_RESET_RLC)
1536 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1537
1538 if (reset_mask & RADEON_RESET_SEM)
1539 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1540
1541 if (reset_mask & RADEON_RESET_IH)
1542 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1543
1544 if (reset_mask & RADEON_RESET_GRBM)
1545 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1546
1547 if (!(rdev->flags & RADEON_IS_IGP)) {
1548 if (reset_mask & RADEON_RESET_MC)
1549 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1550 }
1551
1552 if (reset_mask & RADEON_RESET_VMC)
1553 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1554
1555 if (grbm_soft_reset) {
1556 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1557 tmp |= grbm_soft_reset;
1558 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1559 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1560 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
926deccb 1561
b403bed8
MN
1562 DRM_UDELAY(50);
1563
1564 tmp &= ~grbm_soft_reset;
1565 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1566 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1567 }
1568
1569 if (srbm_soft_reset) {
1570 tmp = RREG32(SRBM_SOFT_RESET);
1571 tmp |= srbm_soft_reset;
1572 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1573 WREG32(SRBM_SOFT_RESET, tmp);
1574 tmp = RREG32(SRBM_SOFT_RESET);
1575
1576 DRM_UDELAY(50);
1577
1578 tmp &= ~srbm_soft_reset;
1579 WREG32(SRBM_SOFT_RESET, tmp);
1580 tmp = RREG32(SRBM_SOFT_RESET);
1581 }
926deccb
FT
1582
1583 /* Wait a little for things to settle down */
1584 DRM_MDELAY(1);
1585
1586 rv515_mc_resume(rdev, &save);
b403bed8
MN
1587 DRM_UDELAY(50);
1588
1589 r600_print_gpu_status_regs(rdev);
1590}
1591
1592int r600_asic_reset(struct radeon_device *rdev)
1593{
1594 u32 reset_mask;
1595
1596 reset_mask = r600_gpu_check_soft_reset(rdev);
1597
1598 if (reset_mask)
1599 r600_set_bios_scratch_engine_hung(rdev, true);
1600
1601 r600_gpu_soft_reset(rdev, reset_mask);
1602
1603 reset_mask = r600_gpu_check_soft_reset(rdev);
1604
1605 if (!reset_mask)
1606 r600_set_bios_scratch_engine_hung(rdev, false);
1607
926deccb
FT
1608 return 0;
1609}
1610
b403bed8
MN
1611/**
1612 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1613 *
1614 * @rdev: radeon_device pointer
1615 * @ring: radeon_ring structure holding ring information
1616 *
1617 * Check if the GFX engine is locked up.
1618 * Returns true if the engine appears to be locked up, false if not.
1619 */
1620bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
926deccb 1621{
b403bed8
MN
1622 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1623
1624 if (!(reset_mask & (RADEON_RESET_GFX |
1625 RADEON_RESET_COMPUTE |
1626 RADEON_RESET_CP))) {
926deccb
FT
1627 radeon_ring_lockup_update(ring);
1628 return false;
1629 }
1630 /* force CP activities */
1631 radeon_ring_force_activity(rdev, ring);
1632 return radeon_ring_test_lockup(rdev, ring);
1633}
1634
1635/**
1636 * r600_dma_is_lockup - Check if the DMA engine is locked up
1637 *
1638 * @rdev: radeon_device pointer
1639 * @ring: radeon_ring structure holding ring information
1640 *
b403bed8 1641 * Check if the async DMA engine is locked up.
926deccb
FT
1642 * Returns true if the engine appears to be locked up, false if not.
1643 */
1644bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1645{
b403bed8 1646 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
926deccb 1647
b403bed8 1648 if (!(reset_mask & RADEON_RESET_DMA)) {
926deccb
FT
1649 radeon_ring_lockup_update(ring);
1650 return false;
1651 }
1652 /* force ring activities */
1653 radeon_ring_force_activity(rdev, ring);
1654 return radeon_ring_test_lockup(rdev, ring);
1655}
1656
926deccb
FT
1657u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1658 u32 tiling_pipe_num,
1659 u32 max_rb_num,
1660 u32 total_max_rb_num,
1661 u32 disabled_rb_mask)
1662{
1663 u32 rendering_pipe_num, rb_num_width, req_rb_num;
1664 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1665 u32 data = 0, mask = 1 << (max_rb_num - 1);
1666 unsigned i, j;
1667
1668 /* mask out the RBs that don't exist on that asic */
1669 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1670 /* make sure at least one RB is available */
1671 if ((tmp & 0xff) != 0xff)
1672 disabled_rb_mask = tmp;
1673
1674 rendering_pipe_num = 1 << tiling_pipe_num;
1675 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1676 KASSERT(rendering_pipe_num >= req_rb_num, ("rendering_pipe_num < req_rb_num"));
1677
1678 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1679 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1680
1681 if (rdev->family <= CHIP_RV740) {
1682 /* r6xx/r7xx */
1683 rb_num_width = 2;
1684 } else {
1685 /* eg+ */
1686 rb_num_width = 4;
1687 }
1688
1689 for (i = 0; i < max_rb_num; i++) {
1690 if (!(mask & disabled_rb_mask)) {
1691 for (j = 0; j < pipe_rb_ratio; j++) {
1692 data <<= rb_num_width;
1693 data |= max_rb_num - i - 1;
1694 }
1695 if (pipe_rb_remain) {
1696 data <<= rb_num_width;
1697 data |= max_rb_num - i - 1;
1698 pipe_rb_remain--;
1699 }
1700 }
1701 mask >>= 1;
1702 }
1703
1704 return data;
1705}
1706
1707int r600_count_pipe_bits(uint32_t val)
1708{
1709 return hweight32(val);
1710}
1711
1712static void r600_gpu_init(struct radeon_device *rdev)
1713{
1714 u32 tiling_config;
1715 u32 ramcfg;
1716 u32 cc_rb_backend_disable;
1717 u32 cc_gc_shader_pipe_config;
1718 u32 tmp;
1719 int i, j;
1720 u32 sq_config;
1721 u32 sq_gpr_resource_mgmt_1 = 0;
1722 u32 sq_gpr_resource_mgmt_2 = 0;
1723 u32 sq_thread_resource_mgmt = 0;
1724 u32 sq_stack_resource_mgmt_1 = 0;
1725 u32 sq_stack_resource_mgmt_2 = 0;
1726 u32 disabled_rb_mask;
1727
1728 rdev->config.r600.tiling_group_size = 256;
1729 switch (rdev->family) {
1730 case CHIP_R600:
1731 rdev->config.r600.max_pipes = 4;
1732 rdev->config.r600.max_tile_pipes = 8;
1733 rdev->config.r600.max_simds = 4;
1734 rdev->config.r600.max_backends = 4;
1735 rdev->config.r600.max_gprs = 256;
1736 rdev->config.r600.max_threads = 192;
1737 rdev->config.r600.max_stack_entries = 256;
1738 rdev->config.r600.max_hw_contexts = 8;
1739 rdev->config.r600.max_gs_threads = 16;
1740 rdev->config.r600.sx_max_export_size = 128;
1741 rdev->config.r600.sx_max_export_pos_size = 16;
1742 rdev->config.r600.sx_max_export_smx_size = 128;
1743 rdev->config.r600.sq_num_cf_insts = 2;
1744 break;
1745 case CHIP_RV630:
1746 case CHIP_RV635:
1747 rdev->config.r600.max_pipes = 2;
1748 rdev->config.r600.max_tile_pipes = 2;
1749 rdev->config.r600.max_simds = 3;
1750 rdev->config.r600.max_backends = 1;
1751 rdev->config.r600.max_gprs = 128;
1752 rdev->config.r600.max_threads = 192;
1753 rdev->config.r600.max_stack_entries = 128;
1754 rdev->config.r600.max_hw_contexts = 8;
1755 rdev->config.r600.max_gs_threads = 4;
1756 rdev->config.r600.sx_max_export_size = 128;
1757 rdev->config.r600.sx_max_export_pos_size = 16;
1758 rdev->config.r600.sx_max_export_smx_size = 128;
1759 rdev->config.r600.sq_num_cf_insts = 2;
1760 break;
1761 case CHIP_RV610:
1762 case CHIP_RV620:
1763 case CHIP_RS780:
1764 case CHIP_RS880:
1765 rdev->config.r600.max_pipes = 1;
1766 rdev->config.r600.max_tile_pipes = 1;
1767 rdev->config.r600.max_simds = 2;
1768 rdev->config.r600.max_backends = 1;
1769 rdev->config.r600.max_gprs = 128;
1770 rdev->config.r600.max_threads = 192;
1771 rdev->config.r600.max_stack_entries = 128;
1772 rdev->config.r600.max_hw_contexts = 4;
1773 rdev->config.r600.max_gs_threads = 4;
1774 rdev->config.r600.sx_max_export_size = 128;
1775 rdev->config.r600.sx_max_export_pos_size = 16;
1776 rdev->config.r600.sx_max_export_smx_size = 128;
1777 rdev->config.r600.sq_num_cf_insts = 1;
1778 break;
1779 case CHIP_RV670:
1780 rdev->config.r600.max_pipes = 4;
1781 rdev->config.r600.max_tile_pipes = 4;
1782 rdev->config.r600.max_simds = 4;
1783 rdev->config.r600.max_backends = 4;
1784 rdev->config.r600.max_gprs = 192;
1785 rdev->config.r600.max_threads = 192;
1786 rdev->config.r600.max_stack_entries = 256;
1787 rdev->config.r600.max_hw_contexts = 8;
1788 rdev->config.r600.max_gs_threads = 16;
1789 rdev->config.r600.sx_max_export_size = 128;
1790 rdev->config.r600.sx_max_export_pos_size = 16;
1791 rdev->config.r600.sx_max_export_smx_size = 128;
1792 rdev->config.r600.sq_num_cf_insts = 2;
1793 break;
1794 default:
1795 break;
1796 }
1797
1798 /* Initialize HDP */
1799 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1800 WREG32((0x2c14 + j), 0x00000000);
1801 WREG32((0x2c18 + j), 0x00000000);
1802 WREG32((0x2c1c + j), 0x00000000);
1803 WREG32((0x2c20 + j), 0x00000000);
1804 WREG32((0x2c24 + j), 0x00000000);
1805 }
1806
1807 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1808
1809 /* Setup tiling */
1810 tiling_config = 0;
1811 ramcfg = RREG32(RAMCFG);
1812 switch (rdev->config.r600.max_tile_pipes) {
1813 case 1:
1814 tiling_config |= PIPE_TILING(0);
1815 break;
1816 case 2:
1817 tiling_config |= PIPE_TILING(1);
1818 break;
1819 case 4:
1820 tiling_config |= PIPE_TILING(2);
1821 break;
1822 case 8:
1823 tiling_config |= PIPE_TILING(3);
1824 break;
1825 default:
1826 break;
1827 }
1828 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1829 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1830 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1831 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1832
1833 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1834 if (tmp > 3) {
1835 tiling_config |= ROW_TILING(3);
1836 tiling_config |= SAMPLE_SPLIT(3);
1837 } else {
1838 tiling_config |= ROW_TILING(tmp);
1839 tiling_config |= SAMPLE_SPLIT(tmp);
1840 }
1841 tiling_config |= BANK_SWAPS(1);
1842
1843 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1844 tmp = R6XX_MAX_BACKENDS -
1845 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1846 if (tmp < rdev->config.r600.max_backends) {
1847 rdev->config.r600.max_backends = tmp;
1848 }
1849
1850 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1851 tmp = R6XX_MAX_PIPES -
1852 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1853 if (tmp < rdev->config.r600.max_pipes) {
1854 rdev->config.r600.max_pipes = tmp;
1855 }
1856 tmp = R6XX_MAX_SIMDS -
1857 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1858 if (tmp < rdev->config.r600.max_simds) {
1859 rdev->config.r600.max_simds = tmp;
1860 }
1861
1862 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1863 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1864 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1865 R6XX_MAX_BACKENDS, disabled_rb_mask);
1866 tiling_config |= tmp << 16;
1867 rdev->config.r600.backend_map = tmp;
1868
1869 rdev->config.r600.tile_config = tiling_config;
1870 WREG32(GB_TILING_CONFIG, tiling_config);
1871 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1872 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1873 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
1874
1875 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1876 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1877 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1878
1879 /* Setup some CP states */
1880 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1881 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1882
1883 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1884 SYNC_WALKER | SYNC_ALIGNER));
1885 /* Setup various GPU states */
1886 if (rdev->family == CHIP_RV670)
1887 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1888
1889 tmp = RREG32(SX_DEBUG_1);
1890 tmp |= SMX_EVENT_RELEASE;
1891 if ((rdev->family > CHIP_R600))
1892 tmp |= ENABLE_NEW_SMX_ADDRESS;
1893 WREG32(SX_DEBUG_1, tmp);
1894
1895 if (((rdev->family) == CHIP_R600) ||
1896 ((rdev->family) == CHIP_RV630) ||
1897 ((rdev->family) == CHIP_RV610) ||
1898 ((rdev->family) == CHIP_RV620) ||
1899 ((rdev->family) == CHIP_RS780) ||
1900 ((rdev->family) == CHIP_RS880)) {
1901 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1902 } else {
1903 WREG32(DB_DEBUG, 0);
1904 }
1905 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1906 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1907
1908 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1909 WREG32(VGT_NUM_INSTANCES, 0);
1910
1911 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1912 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1913
1914 tmp = RREG32(SQ_MS_FIFO_SIZES);
1915 if (((rdev->family) == CHIP_RV610) ||
1916 ((rdev->family) == CHIP_RV620) ||
1917 ((rdev->family) == CHIP_RS780) ||
1918 ((rdev->family) == CHIP_RS880)) {
1919 tmp = (CACHE_FIFO_SIZE(0xa) |
1920 FETCH_FIFO_HIWATER(0xa) |
1921 DONE_FIFO_HIWATER(0xe0) |
1922 ALU_UPDATE_FIFO_HIWATER(0x8));
1923 } else if (((rdev->family) == CHIP_R600) ||
1924 ((rdev->family) == CHIP_RV630)) {
1925 tmp &= ~DONE_FIFO_HIWATER(0xff);
1926 tmp |= DONE_FIFO_HIWATER(0x4);
1927 }
1928 WREG32(SQ_MS_FIFO_SIZES, tmp);
1929
1930 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1931 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1932 */
1933 sq_config = RREG32(SQ_CONFIG);
1934 sq_config &= ~(PS_PRIO(3) |
1935 VS_PRIO(3) |
1936 GS_PRIO(3) |
1937 ES_PRIO(3));
1938 sq_config |= (DX9_CONSTS |
1939 VC_ENABLE |
1940 PS_PRIO(0) |
1941 VS_PRIO(1) |
1942 GS_PRIO(2) |
1943 ES_PRIO(3));
1944
1945 if ((rdev->family) == CHIP_R600) {
1946 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1947 NUM_VS_GPRS(124) |
1948 NUM_CLAUSE_TEMP_GPRS(4));
1949 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1950 NUM_ES_GPRS(0));
1951 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1952 NUM_VS_THREADS(48) |
1953 NUM_GS_THREADS(4) |
1954 NUM_ES_THREADS(4));
1955 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1956 NUM_VS_STACK_ENTRIES(128));
1957 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1958 NUM_ES_STACK_ENTRIES(0));
1959 } else if (((rdev->family) == CHIP_RV610) ||
1960 ((rdev->family) == CHIP_RV620) ||
1961 ((rdev->family) == CHIP_RS780) ||
1962 ((rdev->family) == CHIP_RS880)) {
1963 /* no vertex cache */
1964 sq_config &= ~VC_ENABLE;
1965
1966 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1967 NUM_VS_GPRS(44) |
1968 NUM_CLAUSE_TEMP_GPRS(2));
1969 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1970 NUM_ES_GPRS(17));
1971 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1972 NUM_VS_THREADS(78) |
1973 NUM_GS_THREADS(4) |
1974 NUM_ES_THREADS(31));
1975 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1976 NUM_VS_STACK_ENTRIES(40));
1977 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1978 NUM_ES_STACK_ENTRIES(16));
1979 } else if (((rdev->family) == CHIP_RV630) ||
1980 ((rdev->family) == CHIP_RV635)) {
1981 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1982 NUM_VS_GPRS(44) |
1983 NUM_CLAUSE_TEMP_GPRS(2));
1984 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1985 NUM_ES_GPRS(18));
1986 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1987 NUM_VS_THREADS(78) |
1988 NUM_GS_THREADS(4) |
1989 NUM_ES_THREADS(31));
1990 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1991 NUM_VS_STACK_ENTRIES(40));
1992 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1993 NUM_ES_STACK_ENTRIES(16));
1994 } else if ((rdev->family) == CHIP_RV670) {
1995 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1996 NUM_VS_GPRS(44) |
1997 NUM_CLAUSE_TEMP_GPRS(2));
1998 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1999 NUM_ES_GPRS(17));
2000 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2001 NUM_VS_THREADS(78) |
2002 NUM_GS_THREADS(4) |
2003 NUM_ES_THREADS(31));
2004 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2005 NUM_VS_STACK_ENTRIES(64));
2006 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2007 NUM_ES_STACK_ENTRIES(64));
2008 }
2009
2010 WREG32(SQ_CONFIG, sq_config);
2011 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2012 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2013 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2014 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2015 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2016
2017 if (((rdev->family) == CHIP_RV610) ||
2018 ((rdev->family) == CHIP_RV620) ||
2019 ((rdev->family) == CHIP_RS780) ||
2020 ((rdev->family) == CHIP_RS880)) {
2021 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2022 } else {
2023 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2024 }
2025
2026 /* More default values. 2D/3D driver should adjust as needed */
2027 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2028 S1_X(0x4) | S1_Y(0xc)));
2029 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2030 S1_X(0x2) | S1_Y(0x2) |
2031 S2_X(0xa) | S2_Y(0x6) |
2032 S3_X(0x6) | S3_Y(0xa)));
2033 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2034 S1_X(0x4) | S1_Y(0xc) |
2035 S2_X(0x1) | S2_Y(0x6) |
2036 S3_X(0xa) | S3_Y(0xe)));
2037 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2038 S5_X(0x0) | S5_Y(0x0) |
2039 S6_X(0xb) | S6_Y(0x4) |
2040 S7_X(0x7) | S7_Y(0x8)));
2041
2042 WREG32(VGT_STRMOUT_EN, 0);
2043 tmp = rdev->config.r600.max_pipes * 16;
2044 switch (rdev->family) {
2045 case CHIP_RV610:
2046 case CHIP_RV620:
2047 case CHIP_RS780:
2048 case CHIP_RS880:
2049 tmp += 32;
2050 break;
2051 case CHIP_RV670:
2052 tmp += 128;
2053 break;
2054 default:
2055 break;
2056 }
2057 if (tmp > 256) {
2058 tmp = 256;
2059 }
2060 WREG32(VGT_ES_PER_GS, 128);
2061 WREG32(VGT_GS_PER_ES, tmp);
2062 WREG32(VGT_GS_PER_VS, 2);
2063 WREG32(VGT_GS_VERTEX_REUSE, 16);
2064
2065 /* more default values. 2D/3D driver should adjust as needed */
2066 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2067 WREG32(VGT_STRMOUT_EN, 0);
2068 WREG32(SX_MISC, 0);
2069 WREG32(PA_SC_MODE_CNTL, 0);
2070 WREG32(PA_SC_AA_CONFIG, 0);
2071 WREG32(PA_SC_LINE_STIPPLE, 0);
2072 WREG32(SPI_INPUT_Z, 0);
2073 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2074 WREG32(CB_COLOR7_FRAG, 0);
2075
2076 /* Clear render buffer base addresses */
2077 WREG32(CB_COLOR0_BASE, 0);
2078 WREG32(CB_COLOR1_BASE, 0);
2079 WREG32(CB_COLOR2_BASE, 0);
2080 WREG32(CB_COLOR3_BASE, 0);
2081 WREG32(CB_COLOR4_BASE, 0);
2082 WREG32(CB_COLOR5_BASE, 0);
2083 WREG32(CB_COLOR6_BASE, 0);
2084 WREG32(CB_COLOR7_BASE, 0);
2085 WREG32(CB_COLOR7_FRAG, 0);
2086
2087 switch (rdev->family) {
2088 case CHIP_RV610:
2089 case CHIP_RV620:
2090 case CHIP_RS780:
2091 case CHIP_RS880:
2092 tmp = TC_L2_SIZE(8);
2093 break;
2094 case CHIP_RV630:
2095 case CHIP_RV635:
2096 tmp = TC_L2_SIZE(4);
2097 break;
2098 case CHIP_R600:
2099 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2100 break;
2101 default:
2102 tmp = TC_L2_SIZE(0);
2103 break;
2104 }
2105 WREG32(TC_CNTL, tmp);
2106
2107 tmp = RREG32(HDP_HOST_PATH_CNTL);
2108 WREG32(HDP_HOST_PATH_CNTL, tmp);
2109
2110 tmp = RREG32(ARB_POP);
2111 tmp |= ENABLE_TC128;
2112 WREG32(ARB_POP, tmp);
2113
2114 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2115 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2116 NUM_CLIP_SEQ(3)));
2117 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2118 WREG32(VC_ENHANCE, 0);
2119}
2120
2121
2122/*
2123 * Indirect registers accessor
2124 */
2125u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2126{
2127 u32 r;
2128
2129 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2130 (void)RREG32(PCIE_PORT_INDEX);
2131 r = RREG32(PCIE_PORT_DATA);
2132 return r;
2133}
2134
2135void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2136{
2137 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2138 (void)RREG32(PCIE_PORT_INDEX);
2139 WREG32(PCIE_PORT_DATA, (v));
2140 (void)RREG32(PCIE_PORT_DATA);
2141}
2142
2143/*
2144 * CP & Ring
2145 */
2146void r600_cp_stop(struct radeon_device *rdev)
2147{
2148 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2149 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2150 WREG32(SCRATCH_UMSK, 0);
2151 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2152}
2153
2154int r600_init_microcode(struct radeon_device *rdev)
2155{
2156 const char *chip_name;
2157 const char *rlc_chip_name;
57e252bf
MN
2158 const char *smc_chip_name = "RV770";
2159 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
926deccb
FT
2160 char fw_name[30];
2161 int err;
2162
2163 DRM_DEBUG("\n");
2164
2165 switch (rdev->family) {
2166 case CHIP_R600:
2167 chip_name = "R600";
2168 rlc_chip_name = "R600";
2169 break;
2170 case CHIP_RV610:
2171 chip_name = "RV610";
2172 rlc_chip_name = "R600";
2173 break;
2174 case CHIP_RV630:
2175 chip_name = "RV630";
2176 rlc_chip_name = "R600";
2177 break;
2178 case CHIP_RV620:
2179 chip_name = "RV620";
2180 rlc_chip_name = "R600";
2181 break;
2182 case CHIP_RV635:
2183 chip_name = "RV635";
2184 rlc_chip_name = "R600";
2185 break;
2186 case CHIP_RV670:
2187 chip_name = "RV670";
2188 rlc_chip_name = "R600";
2189 break;
2190 case CHIP_RS780:
2191 case CHIP_RS880:
2192 chip_name = "RS780";
2193 rlc_chip_name = "R600";
2194 break;
2195 case CHIP_RV770:
2196 chip_name = "RV770";
2197 rlc_chip_name = "R700";
57e252bf
MN
2198 smc_chip_name = "RV770";
2199 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
926deccb
FT
2200 break;
2201 case CHIP_RV730:
926deccb
FT
2202 chip_name = "RV730";
2203 rlc_chip_name = "R700";
57e252bf
MN
2204 smc_chip_name = "RV730";
2205 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
926deccb
FT
2206 break;
2207 case CHIP_RV710:
2208 chip_name = "RV710";
2209 rlc_chip_name = "R700";
57e252bf
MN
2210 smc_chip_name = "RV710";
2211 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2212 break;
2213 case CHIP_RV740:
2214 chip_name = "RV730";
2215 rlc_chip_name = "R700";
2216 smc_chip_name = "RV740";
2217 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
926deccb
FT
2218 break;
2219 case CHIP_CEDAR:
2220 chip_name = "CEDAR";
2221 rlc_chip_name = "CEDAR";
57e252bf
MN
2222 smc_chip_name = "CEDAR";
2223 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
926deccb
FT
2224 break;
2225 case CHIP_REDWOOD:
2226 chip_name = "REDWOOD";
2227 rlc_chip_name = "REDWOOD";
57e252bf
MN
2228 smc_chip_name = "REDWOOD";
2229 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
926deccb
FT
2230 break;
2231 case CHIP_JUNIPER:
2232 chip_name = "JUNIPER";
2233 rlc_chip_name = "JUNIPER";
57e252bf
MN
2234 smc_chip_name = "JUNIPER";
2235 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
926deccb
FT
2236 break;
2237 case CHIP_CYPRESS:
2238 case CHIP_HEMLOCK:
2239 chip_name = "CYPRESS";
2240 rlc_chip_name = "CYPRESS";
57e252bf
MN
2241 smc_chip_name = "CYPRESS";
2242 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
926deccb
FT
2243 break;
2244 case CHIP_PALM:
2245 chip_name = "PALM";
2246 rlc_chip_name = "SUMO";
2247 break;
2248 case CHIP_SUMO:
2249 chip_name = "SUMO";
2250 rlc_chip_name = "SUMO";
2251 break;
2252 case CHIP_SUMO2:
2253 chip_name = "SUMO2";
2254 rlc_chip_name = "SUMO";
2255 break;
2256 default: panic("%s: Unsupported family %d", __func__, rdev->family);
2257 }
2258
2259 if (rdev->family >= CHIP_CEDAR) {
2260 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2261 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2262 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2263 } else if (rdev->family >= CHIP_RV770) {
2264 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2265 me_req_size = R700_PM4_UCODE_SIZE * 4;
2266 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2267 } else {
57e252bf
MN
2268 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2269 me_req_size = R600_PM4_UCODE_SIZE * 12;
2270 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
926deccb
FT
2271 }
2272
2273 DRM_INFO("Loading %s Microcode\n", chip_name);
2274 err = 0;
2275
2276 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
2277 rdev->pfp_fw = firmware_get(fw_name);
2278 if (rdev->pfp_fw == NULL) {
2279 err = -ENOENT;
2280 goto out;
2281 }
2282 if (rdev->pfp_fw->datasize != pfp_req_size) {
2283 DRM_ERROR(
2284 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2285 rdev->pfp_fw->datasize, fw_name);
2286 err = -EINVAL;
2287 goto out;
2288 }
2289
2290 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
2291 rdev->me_fw = firmware_get(fw_name);
2292 if (rdev->me_fw == NULL) {
2293 err = -ENOENT;
2294 goto out;
2295 }
2296 if (rdev->me_fw->datasize != me_req_size) {
2297 DRM_ERROR(
2298 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2299 rdev->me_fw->datasize, fw_name);
2300 err = -EINVAL;
2301 }
2302
2303 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc",
2304 rlc_chip_name);
2305 rdev->rlc_fw = firmware_get(fw_name);
2306 if (rdev->rlc_fw == NULL) {
2307 err = -ENOENT;
2308 goto out;
2309 }
2310 if (rdev->rlc_fw->datasize != rlc_req_size) {
2311 DRM_ERROR(
2312 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2313 rdev->rlc_fw->datasize, fw_name);
2314 err = -EINVAL;
2315 }
2316
57e252bf
MN
2317 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2318 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", smc_chip_name);
2319 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2320 if (err) {
2321 printk(KERN_ERR
2322 "smc: error loading firmware \"%s\"\n",
2323 fw_name);
2324 release_firmware(rdev->smc_fw);
2325 rdev->smc_fw = NULL;
2326 } else if (rdev->smc_fw->datasize != smc_req_size) {
2327 printk(KERN_ERR
2328 "smc: Bogus length %zu in firmware \"%s\"\n",
2329 rdev->smc_fw->datasize, fw_name);
2330 err = -EINVAL;
2331 }
2332 }
2333
926deccb
FT
2334out:
2335 if (err) {
2336 if (err != -EINVAL)
2337 DRM_ERROR(
2338 "r600_cp: Failed to load firmware \"%s\"\n",
2339 fw_name);
2340 if (rdev->pfp_fw != NULL) {
2341 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD);
2342 rdev->pfp_fw = NULL;
2343 }
2344 if (rdev->me_fw != NULL) {
2345 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
2346 rdev->me_fw = NULL;
2347 }
2348 if (rdev->rlc_fw != NULL) {
2349 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD);
2350 rdev->rlc_fw = NULL;
2351 }
2352 }
2353 return err;
2354}
2355
2356/**
2357 * r600_fini_microcode - drop the firmwares image references
2358 *
2359 * @rdev: radeon_device pointer
2360 *
2361 * Drop the pfp, me and rlc firmwares image references.
2362 * Called at driver shutdown.
2363 */
2364void r600_fini_microcode(struct radeon_device *rdev)
2365{
2366
2367 if (rdev->pfp_fw != NULL) {
2368 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD);
2369 rdev->pfp_fw = NULL;
2370 }
2371
2372 if (rdev->me_fw != NULL) {
2373 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
2374 rdev->me_fw = NULL;
2375 }
2376
2377 if (rdev->rlc_fw != NULL) {
2378 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD);
2379 rdev->rlc_fw = NULL;
57e252bf
MN
2380 firmware_put(rdev->smc_fw, FIRMWARE_UNLOAD);
2381 rdev->smc_fw = NULL;
926deccb
FT
2382 }
2383}
2384
2385static int r600_cp_load_microcode(struct radeon_device *rdev)
2386{
2387 const __be32 *fw_data;
2388 int i;
2389
2390 if (!rdev->me_fw || !rdev->pfp_fw)
2391 return -EINVAL;
2392
2393 r600_cp_stop(rdev);
2394
2395 WREG32(CP_RB_CNTL,
2396#ifdef __BIG_ENDIAN
2397 BUF_SWAP_32BIT |
2398#endif
2399 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2400
2401 /* Reset cp */
2402 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2403 RREG32(GRBM_SOFT_RESET);
2404 DRM_MDELAY(15);
2405 WREG32(GRBM_SOFT_RESET, 0);
2406
2407 WREG32(CP_ME_RAM_WADDR, 0);
2408
2409 fw_data = (const __be32 *)rdev->me_fw->data;
2410 WREG32(CP_ME_RAM_WADDR, 0);
57e252bf 2411 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
926deccb
FT
2412 WREG32(CP_ME_RAM_DATA,
2413 be32_to_cpup(fw_data++));
2414
2415 fw_data = (const __be32 *)rdev->pfp_fw->data;
2416 WREG32(CP_PFP_UCODE_ADDR, 0);
57e252bf 2417 for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
926deccb
FT
2418 WREG32(CP_PFP_UCODE_DATA,
2419 be32_to_cpup(fw_data++));
2420
2421 WREG32(CP_PFP_UCODE_ADDR, 0);
2422 WREG32(CP_ME_RAM_WADDR, 0);
2423 WREG32(CP_ME_RAM_RADDR, 0);
2424 return 0;
2425}
2426
2427int r600_cp_start(struct radeon_device *rdev)
2428{
2429 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2430 int r;
2431 uint32_t cp_me;
2432
2433 r = radeon_ring_lock(rdev, ring, 7);
2434 if (r) {
2435 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2436 return r;
2437 }
2438 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2439 radeon_ring_write(ring, 0x1);
2440 if (rdev->family >= CHIP_RV770) {
2441 radeon_ring_write(ring, 0x0);
2442 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2443 } else {
2444 radeon_ring_write(ring, 0x3);
2445 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2446 }
2447 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2448 radeon_ring_write(ring, 0);
2449 radeon_ring_write(ring, 0);
2450 radeon_ring_unlock_commit(rdev, ring);
2451
2452 cp_me = 0xff;
2453 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2454 return 0;
2455}
2456
2457int r600_cp_resume(struct radeon_device *rdev)
2458{
2459 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2460 u32 tmp;
2461 u32 rb_bufsz;
2462 int r;
2463
2464 /* Reset cp */
2465 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2466 RREG32(GRBM_SOFT_RESET);
2467 DRM_MDELAY(15);
2468 WREG32(GRBM_SOFT_RESET, 0);
2469
2470 /* Set ring buffer size */
2471 rb_bufsz = drm_order(ring->ring_size / 8);
2472 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2473#ifdef __BIG_ENDIAN
2474 tmp |= BUF_SWAP_32BIT;
2475#endif
2476 WREG32(CP_RB_CNTL, tmp);
2477 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2478
2479 /* Set the write pointer delay */
2480 WREG32(CP_RB_WPTR_DELAY, 0);
2481
2482 /* Initialize the ring buffer's read and write pointers */
2483 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2484 WREG32(CP_RB_RPTR_WR, 0);
2485 ring->wptr = 0;
2486 WREG32(CP_RB_WPTR, ring->wptr);
2487
2488 /* set the wb address whether it's enabled or not */
2489 WREG32(CP_RB_RPTR_ADDR,
2490 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2491 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2492 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2493
2494 if (rdev->wb.enabled)
2495 WREG32(SCRATCH_UMSK, 0xff);
2496 else {
2497 tmp |= RB_NO_UPDATE;
2498 WREG32(SCRATCH_UMSK, 0);
2499 }
2500
2501 DRM_MDELAY(1);
2502 WREG32(CP_RB_CNTL, tmp);
2503
2504 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2505 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2506
2507 ring->rptr = RREG32(CP_RB_RPTR);
2508
2509 r600_cp_start(rdev);
2510 ring->ready = true;
2511 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2512 if (r) {
2513 ring->ready = false;
2514 return r;
2515 }
2516 return 0;
2517}
2518
2519void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2520{
2521 u32 rb_bufsz;
2522 int r;
2523
2524 /* Align ring size */
2525 rb_bufsz = drm_order(ring_size / 8);
2526 ring_size = (1 << (rb_bufsz + 1)) * 4;
2527 ring->ring_size = ring_size;
2528 ring->align_mask = 16 - 1;
2529
2530 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2531 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2532 if (r) {
2533 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2534 ring->rptr_save_reg = 0;
2535 }
2536 }
2537}
2538
2539void r600_cp_fini(struct radeon_device *rdev)
2540{
2541 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2542 r600_cp_stop(rdev);
2543 radeon_ring_fini(rdev, ring);
2544 radeon_scratch_free(rdev, ring->rptr_save_reg);
2545}
2546
2547/*
2548 * DMA
2549 * Starting with R600, the GPU has an asynchronous
2550 * DMA engine. The programming model is very similar
2551 * to the 3D engine (ring buffer, IBs, etc.), but the
2552 * DMA controller has it's own packet format that is
2553 * different form the PM4 format used by the 3D engine.
2554 * It supports copying data, writing embedded data,
2555 * solid fills, and a number of other things. It also
2556 * has support for tiling/detiling of buffers.
2557 */
2558/**
2559 * r600_dma_stop - stop the async dma engine
2560 *
2561 * @rdev: radeon_device pointer
2562 *
2563 * Stop the async dma engine (r6xx-evergreen).
2564 */
2565void r600_dma_stop(struct radeon_device *rdev)
2566{
2567 u32 rb_cntl = RREG32(DMA_RB_CNTL);
2568
2569 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2570
2571 rb_cntl &= ~DMA_RB_ENABLE;
2572 WREG32(DMA_RB_CNTL, rb_cntl);
2573
2574 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2575}
2576
2577/**
2578 * r600_dma_resume - setup and start the async dma engine
2579 *
2580 * @rdev: radeon_device pointer
2581 *
2582 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2583 * Returns 0 for success, error for failure.
2584 */
2585int r600_dma_resume(struct radeon_device *rdev)
2586{
2587 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2588 u32 rb_cntl, dma_cntl, ib_cntl;
2589 u32 rb_bufsz;
2590 int r;
2591
2592 /* Reset dma */
2593 if (rdev->family >= CHIP_RV770)
2594 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2595 else
2596 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2597 RREG32(SRBM_SOFT_RESET);
2598 DRM_UDELAY(50);
2599 WREG32(SRBM_SOFT_RESET, 0);
2600
2601 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2602 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2603
2604 /* Set ring buffer size in dwords */
2605 rb_bufsz = drm_order(ring->ring_size / 4);
2606 rb_cntl = rb_bufsz << 1;
2607#ifdef __BIG_ENDIAN
2608 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2609#endif
2610 WREG32(DMA_RB_CNTL, rb_cntl);
2611
2612 /* Initialize the ring buffer's read and write pointers */
2613 WREG32(DMA_RB_RPTR, 0);
2614 WREG32(DMA_RB_WPTR, 0);
2615
2616 /* set the wb address whether it's enabled or not */
2617 WREG32(DMA_RB_RPTR_ADDR_HI,
2618 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2619 WREG32(DMA_RB_RPTR_ADDR_LO,
2620 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2621
2622 if (rdev->wb.enabled)
2623 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2624
2625 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2626
2627 /* enable DMA IBs */
2628 ib_cntl = DMA_IB_ENABLE;
2629#ifdef __BIG_ENDIAN
2630 ib_cntl |= DMA_IB_SWAP_ENABLE;
2631#endif
2632 WREG32(DMA_IB_CNTL, ib_cntl);
2633
2634 dma_cntl = RREG32(DMA_CNTL);
2635 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2636 WREG32(DMA_CNTL, dma_cntl);
2637
2638 if (rdev->family >= CHIP_RV770)
2639 WREG32(DMA_MODE, 1);
2640
2641 ring->wptr = 0;
2642 WREG32(DMA_RB_WPTR, ring->wptr << 2);
2643
2644 ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2645
2646 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2647
2648 ring->ready = true;
2649
2650 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2651 if (r) {
2652 ring->ready = false;
2653 return r;
2654 }
2655
2656 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2657
2658 return 0;
2659}
2660
2661/**
2662 * r600_dma_fini - tear down the async dma engine
2663 *
2664 * @rdev: radeon_device pointer
2665 *
2666 * Stop the async dma engine and free the ring (r6xx-evergreen).
2667 */
2668void r600_dma_fini(struct radeon_device *rdev)
2669{
2670 r600_dma_stop(rdev);
2671 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2672}
2673
f43cf1b1
MN
2674/*
2675 * UVD
2676 */
2677int r600_uvd_rbc_start(struct radeon_device *rdev)
2678{
2679 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2680 uint64_t rptr_addr;
2681 uint32_t rb_bufsz, tmp;
2682 int r;
2683
2684 rptr_addr = rdev->wb.gpu_addr + R600_WB_UVD_RPTR_OFFSET;
2685
2686 if (upper_32_bits(rptr_addr) != upper_32_bits(ring->gpu_addr)) {
2687 DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n");
2688 return -EINVAL;
2689 }
2690
2691 /* force RBC into idle state */
2692 WREG32(UVD_RBC_RB_CNTL, 0x11010101);
2693
2694 /* Set the write pointer delay */
2695 WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
2696
2697 /* set the wb address */
2698 WREG32(UVD_RBC_RB_RPTR_ADDR, rptr_addr >> 2);
2699
2700 /* programm the 4GB memory segment for rptr and ring buffer */
2701 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(rptr_addr) |
2702 (0x7 << 16) | (0x1 << 31));
2703
2704 /* Initialize the ring buffer's read and write pointers */
2705 WREG32(UVD_RBC_RB_RPTR, 0x0);
2706
2707 ring->wptr = ring->rptr = RREG32(UVD_RBC_RB_RPTR);
2708 WREG32(UVD_RBC_RB_WPTR, ring->wptr);
2709
2710 /* set the ring address */
2711 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
2712
2713 /* Set ring buffer size */
2714 rb_bufsz = drm_order(ring->ring_size);
2715 rb_bufsz = (0x1 << 8) | rb_bufsz;
2716 WREG32(UVD_RBC_RB_CNTL, rb_bufsz);
2717
2718 ring->ready = true;
2719 r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);
2720 if (r) {
2721 ring->ready = false;
2722 return r;
2723 }
2724
2725 r = radeon_ring_lock(rdev, ring, 10);
2726 if (r) {
2727 DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);
2728 return r;
2729 }
2730
2731 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
2732 radeon_ring_write(ring, tmp);
2733 radeon_ring_write(ring, 0xFFFFF);
2734
2735 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
2736 radeon_ring_write(ring, tmp);
2737 radeon_ring_write(ring, 0xFFFFF);
2738
2739 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
2740 radeon_ring_write(ring, tmp);
2741 radeon_ring_write(ring, 0xFFFFF);
2742
2743 /* Clear timeout status bits */
2744 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));
2745 radeon_ring_write(ring, 0x8);
2746
2747 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
2748 radeon_ring_write(ring, 3);
2749
2750 radeon_ring_unlock_commit(rdev, ring);
2751
2752 return 0;
2753}
2754
57e252bf 2755void r600_uvd_stop(struct radeon_device *rdev)
f43cf1b1
MN
2756{
2757 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2758
2759 /* force RBC into idle state */
2760 WREG32(UVD_RBC_RB_CNTL, 0x11010101);
57e252bf
MN
2761
2762 /* Stall UMC and register bus before resetting VCPU */
2763 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
2764 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
2765 DRM_MDELAY(1);
2766
2767 /* put VCPU into reset */
2768 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
2769 DRM_MDELAY(5);
2770
2771 /* disable VCPU clock */
2772 WREG32(UVD_VCPU_CNTL, 0x0);
2773
2774 /* Unstall UMC and register bus */
2775 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
2776 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
2777
f43cf1b1
MN
2778 ring->ready = false;
2779}
2780
2781int r600_uvd_init(struct radeon_device *rdev)
2782{
2783 int i, j, r;
2784 /* disable byte swapping */
2785 u32 lmi_swap_cntl = 0;
2786 u32 mp_swap_cntl = 0;
2787
2788 /* raise clocks while booting up the VCPU */
2789 radeon_set_uvd_clocks(rdev, 53300, 40000);
2790
2791 /* disable clock gating */
2792 WREG32(UVD_CGC_GATE, 0);
2793
2794 /* disable interupt */
2795 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
2796
57e252bf
MN
2797 /* Stall UMC and register bus before resetting VCPU */
2798 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
2799 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
2800 DRM_MDELAY(1);
2801
f43cf1b1
MN
2802 /* put LMI, VCPU, RBC etc... into reset */
2803 WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
2804 LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET |
2805 CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET);
2806 DRM_MDELAY(5);
2807
2808 /* take UVD block out of reset */
2809 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);
2810 DRM_MDELAY(5);
2811
2812 /* initialize UVD memory controller */
2813 WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
2814 (1 << 21) | (1 << 9) | (1 << 20));
2815
2816#ifdef __BIG_ENDIAN
2817 /* swap (8 in 32) RB and IB */
2818 lmi_swap_cntl = 0xa;
2819 mp_swap_cntl = 0;
2820#endif
2821 WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);
2822 WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);
2823
2824 WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
2825 WREG32(UVD_MPC_SET_MUXA1, 0x0);
2826 WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);
2827 WREG32(UVD_MPC_SET_MUXB1, 0x0);
2828 WREG32(UVD_MPC_SET_ALU, 0);
2829 WREG32(UVD_MPC_SET_MUX, 0x88);
2830
f43cf1b1
MN
2831 /* take all subblocks out of reset, except VCPU */
2832 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
2833 DRM_MDELAY(5);
2834
2835 /* enable VCPU clock */
2836 WREG32(UVD_VCPU_CNTL, 1 << 9);
2837
2838 /* enable UMC */
2839 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
2840
2841 /* boot up the VCPU */
2842 WREG32(UVD_SOFT_RESET, 0);
2843 DRM_MDELAY(10);
2844
2845 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
2846
2847 for (i = 0; i < 10; ++i) {
2848 uint32_t status;
2849 for (j = 0; j < 100; ++j) {
2850 status = RREG32(UVD_STATUS);
2851 if (status & 2)
2852 break;
2853 DRM_MDELAY(10);
2854 }
2855 r = 0;
2856 if (status & 2)
2857 break;
2858
2859 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
2860 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);
2861 DRM_MDELAY(10);
2862 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);
2863 DRM_MDELAY(10);
2864 r = -1;
2865 }
2866
2867 if (r) {
2868 DRM_ERROR("UVD not responding, giving up!!!\n");
2869 radeon_set_uvd_clocks(rdev, 0, 0);
2870 return r;
2871 }
2872
2873 /* enable interupt */
2874 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
2875
2876 r = r600_uvd_rbc_start(rdev);
2877 if (!r)
2878 DRM_INFO("UVD initialized successfully.\n");
2879
2880 /* lower clocks again */
2881 radeon_set_uvd_clocks(rdev, 0, 0);
2882
2883 return r;
2884}
2885
926deccb
FT
2886/*
2887 * GPU scratch registers helpers function.
2888 */
2889void r600_scratch_init(struct radeon_device *rdev)
2890{
2891 int i;
2892
2893 rdev->scratch.num_reg = 7;
2894 rdev->scratch.reg_base = SCRATCH_REG0;
2895 for (i = 0; i < rdev->scratch.num_reg; i++) {
2896 rdev->scratch.free[i] = true;
2897 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2898 }
2899}
2900
2901int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2902{
2903 uint32_t scratch;
2904 uint32_t tmp = 0;
2905 unsigned i;
2906 int r;
2907
2908 r = radeon_scratch_get(rdev, &scratch);
2909 if (r) {
2910 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2911 return r;
2912 }
2913 WREG32(scratch, 0xCAFEDEAD);
2914 r = radeon_ring_lock(rdev, ring, 3);
2915 if (r) {
2916 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2917 radeon_scratch_free(rdev, scratch);
2918 return r;
2919 }
2920 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2921 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2922 radeon_ring_write(ring, 0xDEADBEEF);
2923 radeon_ring_unlock_commit(rdev, ring);
2924 for (i = 0; i < rdev->usec_timeout; i++) {
2925 tmp = RREG32(scratch);
2926 if (tmp == 0xDEADBEEF)
2927 break;
2928 DRM_UDELAY(1);
2929 }
2930 if (i < rdev->usec_timeout) {
2931 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2932 } else {
2933 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2934 ring->idx, scratch, tmp);
2935 r = -EINVAL;
2936 }
2937 radeon_scratch_free(rdev, scratch);
2938 return r;
2939}
2940
2941/**
2942 * r600_dma_ring_test - simple async dma engine test
2943 *
2944 * @rdev: radeon_device pointer
2945 * @ring: radeon_ring structure holding ring information
2946 *
2947 * Test the DMA engine by writing using it to write an
2948 * value to memory. (r6xx-SI).
2949 * Returns 0 for success, error for failure.
2950 */
2951int r600_dma_ring_test(struct radeon_device *rdev,
2952 struct radeon_ring *ring)
2953{
2954 unsigned i;
2955 int r;
2956 volatile uint32_t *ptr = rdev->vram_scratch.ptr;
2957 u32 tmp;
2958
2959 if (!ptr) {
2960 DRM_ERROR("invalid vram scratch pointer\n");
2961 return -EINVAL;
2962 }
2963
2964 tmp = 0xCAFEDEAD;
2965 *ptr = tmp;
2966
2967 r = radeon_ring_lock(rdev, ring, 4);
2968 if (r) {
2969 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2970 return r;
2971 }
2972 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2973 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2974 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2975 radeon_ring_write(ring, 0xDEADBEEF);
2976 radeon_ring_unlock_commit(rdev, ring);
2977
2978 for (i = 0; i < rdev->usec_timeout; i++) {
2979 tmp = *ptr;
2980 if (tmp == 0xDEADBEEF)
2981 break;
2982 DRM_UDELAY(1);
2983 }
2984
2985 if (i < rdev->usec_timeout) {
2986 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2987 } else {
2988 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2989 ring->idx, tmp);
2990 r = -EINVAL;
2991 }
2992 return r;
2993}
2994
f43cf1b1
MN
2995int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2996{
2997 uint32_t tmp = 0;
2998 unsigned i;
2999 int r;
3000
3001 WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);
3002 r = radeon_ring_lock(rdev, ring, 3);
3003 if (r) {
3004 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",
3005 ring->idx, r);
3006 return r;
3007 }
3008 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
3009 radeon_ring_write(ring, 0xDEADBEEF);
3010 radeon_ring_unlock_commit(rdev, ring);
3011 for (i = 0; i < rdev->usec_timeout; i++) {
3012 tmp = RREG32(UVD_CONTEXT_ID);
3013 if (tmp == 0xDEADBEEF)
3014 break;
3015 DRM_UDELAY(1);
3016 }
3017
3018 if (i < rdev->usec_timeout) {
3019 DRM_INFO("ring test on %d succeeded in %d usecs\n",
3020 ring->idx, i);
3021 } else {
3022 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
3023 ring->idx, tmp);
3024 r = -EINVAL;
3025 }
3026 return r;
3027}
3028
926deccb
FT
3029/*
3030 * CP fences/semaphores
3031 */
3032
3033void r600_fence_ring_emit(struct radeon_device *rdev,
3034 struct radeon_fence *fence)
3035{
3036 struct radeon_ring *ring = &rdev->ring[fence->ring];
3037
3038 if (rdev->wb.use_event) {
3039 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3040 /* flush read cache over gart */
3041 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3042 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
3043 PACKET3_VC_ACTION_ENA |
3044 PACKET3_SH_ACTION_ENA);
3045 radeon_ring_write(ring, 0xFFFFFFFF);
3046 radeon_ring_write(ring, 0);
3047 radeon_ring_write(ring, 10); /* poll interval */
3048 /* EVENT_WRITE_EOP - flush caches, send int */
3049 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3050 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
3051 radeon_ring_write(ring, addr & 0xffffffff);
3052 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
3053 radeon_ring_write(ring, fence->seq);
3054 radeon_ring_write(ring, 0);
3055 } else {
3056 /* flush read cache over gart */
3057 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3058 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
3059 PACKET3_VC_ACTION_ENA |
3060 PACKET3_SH_ACTION_ENA);
3061 radeon_ring_write(ring, 0xFFFFFFFF);
3062 radeon_ring_write(ring, 0);
3063 radeon_ring_write(ring, 10); /* poll interval */
3064 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
3065 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
3066 /* wait for 3D idle clean */
3067 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3068 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3069 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
3070 /* Emit fence sequence & fire IRQ */
3071 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3072 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3073 radeon_ring_write(ring, fence->seq);
3074 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
3075 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
3076 radeon_ring_write(ring, RB_INT_STAT);
3077 }
3078}
3079
f43cf1b1
MN
3080void r600_uvd_fence_emit(struct radeon_device *rdev,
3081 struct radeon_fence *fence)
3082{
3083 struct radeon_ring *ring = &rdev->ring[fence->ring];
57e252bf 3084 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
f43cf1b1
MN
3085
3086 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
3087 radeon_ring_write(ring, fence->seq);
3088 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
3089 radeon_ring_write(ring, addr & 0xffffffff);
3090 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
3091 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
3092 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
3093 radeon_ring_write(ring, 0);
3094
3095 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
3096 radeon_ring_write(ring, 0);
3097 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
3098 radeon_ring_write(ring, 0);
3099 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
3100 radeon_ring_write(ring, 2);
3101 return;
3102}
3103
926deccb
FT
3104void r600_semaphore_ring_emit(struct radeon_device *rdev,
3105 struct radeon_ring *ring,
3106 struct radeon_semaphore *semaphore,
3107 bool emit_wait)
3108{
3109 uint64_t addr = semaphore->gpu_addr;
3110 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3111
3112 if (rdev->family < CHIP_CAYMAN)
3113 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
3114
3115 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3116 radeon_ring_write(ring, addr & 0xffffffff);
3117 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
3118}
3119
3120/*
3121 * DMA fences/semaphores
3122 */
3123
3124/**
3125 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
3126 *
3127 * @rdev: radeon_device pointer
3128 * @fence: radeon fence object
3129 *
3130 * Add a DMA fence packet to the ring to write
3131 * the fence seq number and DMA trap packet to generate
3132 * an interrupt if needed (r6xx-r7xx).
3133 */
3134void r600_dma_fence_ring_emit(struct radeon_device *rdev,
3135 struct radeon_fence *fence)
3136{
3137 struct radeon_ring *ring = &rdev->ring[fence->ring];
3138 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3139
3140 /* write the fence */
3141 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
3142 radeon_ring_write(ring, addr & 0xfffffffc);
3143 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3144 radeon_ring_write(ring, lower_32_bits(fence->seq));
3145 /* generate an interrupt */
3146 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
3147}
3148
3149/**
3150 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
3151 *
3152 * @rdev: radeon_device pointer
3153 * @ring: radeon_ring structure holding ring information
3154 * @semaphore: radeon semaphore object
3155 * @emit_wait: wait or signal semaphore
3156 *
3157 * Add a DMA semaphore packet to the ring wait on or signal
3158 * other rings (r6xx-SI).
3159 */
3160void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
3161 struct radeon_ring *ring,
3162 struct radeon_semaphore *semaphore,
3163 bool emit_wait)
3164{
3165 u64 addr = semaphore->gpu_addr;
3166 u32 s = emit_wait ? 0 : 1;
3167
3168 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
3169 radeon_ring_write(ring, addr & 0xfffffffc);
3170 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
3171}
3172
f43cf1b1
MN
3173void r600_uvd_semaphore_emit(struct radeon_device *rdev,
3174 struct radeon_ring *ring,
3175 struct radeon_semaphore *semaphore,
3176 bool emit_wait)
3177{
3178 uint64_t addr = semaphore->gpu_addr;
3179
3180 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
3181 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
3182
3183 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
3184 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
3185
3186 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
3187 radeon_ring_write(ring, emit_wait ? 1 : 0);
3188}
3189
926deccb
FT
3190int r600_copy_blit(struct radeon_device *rdev,
3191 uint64_t src_offset,
3192 uint64_t dst_offset,
3193 unsigned num_gpu_pages,
3194 struct radeon_fence **fence)
3195{
3196 struct radeon_semaphore *sem = NULL;
3197 struct radeon_sa_bo *vb = NULL;
3198 int r;
3199
3200 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
3201 if (r) {
3202 return r;
3203 }
3204 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
3205 r600_blit_done_copy(rdev, fence, vb, sem);
3206 return 0;
3207}
3208
57e252bf
MN
3209/**
3210 * r600_copy_cpdma - copy pages using the CP DMA engine
3211 *
3212 * @rdev: radeon_device pointer
3213 * @src_offset: src GPU address
3214 * @dst_offset: dst GPU address
3215 * @num_gpu_pages: number of GPU pages to xfer
3216 * @fence: radeon fence object
3217 *
3218 * Copy GPU paging using the CP DMA engine (r6xx+).
3219 * Used by the radeon ttm implementation to move pages if
3220 * registered as the asic copy callback.
3221 */
3222int r600_copy_cpdma(struct radeon_device *rdev,
3223 uint64_t src_offset, uint64_t dst_offset,
3224 unsigned num_gpu_pages,
3225 struct radeon_fence **fence)
3226{
3227 struct radeon_semaphore *sem = NULL;
3228 int ring_index = rdev->asic->copy.blit_ring_index;
3229 struct radeon_ring *ring = &rdev->ring[ring_index];
3230 u32 size_in_bytes, cur_size_in_bytes, tmp;
3231 int i, num_loops;
3232 int r = 0;
3233
3234 r = radeon_semaphore_create(rdev, &sem);
3235 if (r) {
3236 DRM_ERROR("radeon: moving bo (%d).\n", r);
3237 return r;
3238 }
3239
3240 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
3241 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
3242 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
3243 if (r) {
3244 DRM_ERROR("radeon: moving bo (%d).\n", r);
3245 radeon_semaphore_free(rdev, &sem, NULL);
3246 return r;
3247 }
3248
3249 if (radeon_fence_need_sync(*fence, ring->idx)) {
3250 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3251 ring->idx);
3252 radeon_fence_note_sync(*fence, ring->idx);
3253 } else {
3254 radeon_semaphore_free(rdev, &sem, NULL);
3255 }
3256
3257 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3258 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3259 radeon_ring_write(ring, WAIT_3D_IDLE_bit);
3260 for (i = 0; i < num_loops; i++) {
3261 cur_size_in_bytes = size_in_bytes;
3262 if (cur_size_in_bytes > 0x1fffff)
3263 cur_size_in_bytes = 0x1fffff;
3264 size_in_bytes -= cur_size_in_bytes;
3265 tmp = upper_32_bits(src_offset) & 0xff;
3266 if (size_in_bytes == 0)
3267 tmp |= PACKET3_CP_DMA_CP_SYNC;
3268 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
3269 radeon_ring_write(ring, src_offset & 0xffffffff);
3270 radeon_ring_write(ring, tmp);
3271 radeon_ring_write(ring, dst_offset & 0xffffffff);
3272 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3273 radeon_ring_write(ring, cur_size_in_bytes);
3274 src_offset += cur_size_in_bytes;
3275 dst_offset += cur_size_in_bytes;
3276 }
3277 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3278 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3279 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
3280
3281 r = radeon_fence_emit(rdev, fence, ring->idx);
3282 if (r) {
3283 radeon_ring_unlock_undo(rdev, ring);
3284 return r;
3285 }
3286
3287 radeon_ring_unlock_commit(rdev, ring);
3288 radeon_semaphore_free(rdev, &sem, *fence);
3289
3290 return r;
3291}
3292
926deccb
FT
3293/**
3294 * r600_copy_dma - copy pages using the DMA engine
3295 *
3296 * @rdev: radeon_device pointer
3297 * @src_offset: src GPU address
3298 * @dst_offset: dst GPU address
3299 * @num_gpu_pages: number of GPU pages to xfer
3300 * @fence: radeon fence object
3301 *
3302 * Copy GPU paging using the DMA engine (r6xx).
3303 * Used by the radeon ttm implementation to move pages if
3304 * registered as the asic copy callback.
3305 */
3306int r600_copy_dma(struct radeon_device *rdev,
3307 uint64_t src_offset, uint64_t dst_offset,
3308 unsigned num_gpu_pages,
3309 struct radeon_fence **fence)
3310{
3311 struct radeon_semaphore *sem = NULL;
3312 int ring_index = rdev->asic->copy.dma_ring_index;
3313 struct radeon_ring *ring = &rdev->ring[ring_index];
3314 u32 size_in_dw, cur_size_in_dw;
3315 int i, num_loops;
3316 int r = 0;
3317
3318 r = radeon_semaphore_create(rdev, &sem);
3319 if (r) {
3320 DRM_ERROR("radeon: moving bo (%d).\n", r);
3321 return r;
3322 }
3323
3324 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
3325 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
3326 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
3327 if (r) {
3328 DRM_ERROR("radeon: moving bo (%d).\n", r);
3329 radeon_semaphore_free(rdev, &sem, NULL);
3330 return r;
3331 }
3332
3333 if (radeon_fence_need_sync(*fence, ring->idx)) {
3334 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3335 ring->idx);
3336 radeon_fence_note_sync(*fence, ring->idx);
3337 } else {
3338 radeon_semaphore_free(rdev, &sem, NULL);
3339 }
3340
3341 for (i = 0; i < num_loops; i++) {
3342 cur_size_in_dw = size_in_dw;
3343 if (cur_size_in_dw > 0xFFFE)
3344 cur_size_in_dw = 0xFFFE;
3345 size_in_dw -= cur_size_in_dw;
3346 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
3347 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3348 radeon_ring_write(ring, src_offset & 0xfffffffc);
3349 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
3350 (upper_32_bits(src_offset) & 0xff)));
3351 src_offset += cur_size_in_dw * 4;
3352 dst_offset += cur_size_in_dw * 4;
3353 }
3354
3355 r = radeon_fence_emit(rdev, fence, ring->idx);
3356 if (r) {
3357 radeon_ring_unlock_undo(rdev, ring);
3358 return r;
3359 }
3360
3361 radeon_ring_unlock_commit(rdev, ring);
3362 radeon_semaphore_free(rdev, &sem, *fence);
3363
3364 return r;
3365}
3366
3367int r600_set_surface_reg(struct radeon_device *rdev, int reg,
3368 uint32_t tiling_flags, uint32_t pitch,
3369 uint32_t offset, uint32_t obj_size)
3370{
3371 /* FIXME: implement */
3372 return 0;
3373}
3374
3375void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
3376{
3377 /* FIXME: implement */
3378}
3379
3380static int r600_startup(struct radeon_device *rdev)
3381{
3382 struct radeon_ring *ring;
3383 int r;
3384
3385 /* enable pcie gen2 link */
3386 r600_pcie_gen2_enable(rdev);
3387
57e252bf
MN
3388 r600_mc_program(rdev);
3389
926deccb
FT
3390 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3391 r = r600_init_microcode(rdev);
3392 if (r) {
3393 DRM_ERROR("Failed to load firmware!\n");
3394 return r;
3395 }
3396 }
3397
3398 r = r600_vram_scratch_init(rdev);
3399 if (r)
3400 return r;
3401
926deccb
FT
3402 if (rdev->flags & RADEON_IS_AGP) {
3403 r600_agp_enable(rdev);
3404 } else {
3405 r = r600_pcie_gart_enable(rdev);
3406 if (r)
3407 return r;
3408 }
3409 r600_gpu_init(rdev);
3410 r = r600_blit_init(rdev);
3411 if (r) {
3412 r600_blit_fini(rdev);
3413 rdev->asic->copy.copy = NULL;
3414 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3415 }
3416
3417 /* allocate wb buffer */
3418 r = radeon_wb_init(rdev);
3419 if (r)
3420 return r;
3421
3422 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3423 if (r) {
3424 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3425 return r;
3426 }
3427
3428 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
3429 if (r) {
3430 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3431 return r;
3432 }
3433
3434 /* Enable IRQ */
f43cf1b1
MN
3435 if (!rdev->irq.installed) {
3436 r = radeon_irq_kms_init(rdev);
3437 if (r)
3438 return r;
3439 }
3440
926deccb
FT
3441 r = r600_irq_init(rdev);
3442 if (r) {
3443 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3444 radeon_irq_kms_fini(rdev);
3445 return r;
3446 }
3447 r600_irq_set(rdev);
3448
3449 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3450 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3451 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3452 0, 0xfffff, RADEON_CP_PACKET2);
3453 if (r)
3454 return r;
3455
3456 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3457 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3458 DMA_RB_RPTR, DMA_RB_WPTR,
3459 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3460 if (r)
3461 return r;
3462
3463 r = r600_cp_load_microcode(rdev);
3464 if (r)
3465 return r;
3466 r = r600_cp_resume(rdev);
3467 if (r)
3468 return r;
3469
3470 r = r600_dma_resume(rdev);
3471 if (r)
3472 return r;
3473
3474 r = radeon_ib_pool_init(rdev);
3475 if (r) {
3476 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3477 return r;
3478 }
3479
3480 r = r600_audio_init(rdev);
3481 if (r) {
3482 DRM_ERROR("radeon: audio init failed\n");
3483 return r;
3484 }
3485
3486 return 0;
3487}
3488
3489void r600_vga_set_state(struct radeon_device *rdev, bool state)
3490{
3491 uint32_t temp;
3492
3493 temp = RREG32(CONFIG_CNTL);
3494 if (state == false) {
3495 temp &= ~(1<<0);
3496 temp |= (1<<1);
3497 } else {
3498 temp &= ~(1<<1);
3499 }
3500 WREG32(CONFIG_CNTL, temp);
3501}
3502
3503int r600_resume(struct radeon_device *rdev)
3504{
3505 int r;
3506
3507 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3508 * posting will perform necessary task to bring back GPU into good
3509 * shape.
3510 */
3511 /* post card */
3512 atom_asic_init(rdev->mode_info.atom_context);
3513
3514 rdev->accel_working = true;
3515 r = r600_startup(rdev);
3516 if (r) {
3517 DRM_ERROR("r600 startup failed on resume\n");
3518 rdev->accel_working = false;
3519 return r;
3520 }
3521
3522 return r;
3523}
3524
3525int r600_suspend(struct radeon_device *rdev)
3526{
3527 r600_audio_fini(rdev);
3528 r600_cp_stop(rdev);
3529 r600_dma_stop(rdev);
3530 r600_irq_suspend(rdev);
3531 radeon_wb_disable(rdev);
3532 r600_pcie_gart_disable(rdev);
3533
3534 return 0;
3535}
3536
3537/* Plan is to move initialization in that function and use
3538 * helper function so that radeon_device_init pretty much
3539 * do nothing more than calling asic specific function. This
3540 * should also allow to remove a bunch of callback function
3541 * like vram_info.
3542 */
3543int r600_init(struct radeon_device *rdev)
3544{
3545 int r;
3546
3547 if (r600_debugfs_mc_info_init(rdev)) {
3548 DRM_ERROR("Failed to register debugfs file for mc !\n");
3549 }
3550 /* Read BIOS */
3551 if (!radeon_get_bios(rdev)) {
3552 if (ASIC_IS_AVIVO(rdev))
3553 return -EINVAL;
3554 }
3555 /* Must be an ATOMBIOS */
3556 if (!rdev->is_atom_bios) {
3557 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3558 return -EINVAL;
3559 }
3560 r = radeon_atombios_init(rdev);
3561 if (r)
3562 return r;
3563 /* Post card if necessary */
3564 if (!radeon_card_posted(rdev)) {
3565 if (!rdev->bios) {
3566 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3567 return -EINVAL;
3568 }
3569 DRM_INFO("GPU not posted. posting now...\n");
3570 atom_asic_init(rdev->mode_info.atom_context);
3571 }
3572 /* Initialize scratch registers */
3573 r600_scratch_init(rdev);
3574 /* Initialize surface registers */
3575 radeon_surface_init(rdev);
3576 /* Initialize clocks */
3577 radeon_get_clock_info(rdev->ddev);
3578 /* Fence driver */
3579 r = radeon_fence_driver_init(rdev);
3580 if (r)
3581 return r;
3582 if (rdev->flags & RADEON_IS_AGP) {
3583 r = radeon_agp_init(rdev);
3584 if (r)
3585 radeon_agp_disable(rdev);
3586 }
3587 r = r600_mc_init(rdev);
3588 if (r)
3589 return r;
3590 /* Memory manager */
3591 r = radeon_bo_init(rdev);
3592 if (r)
3593 return r;
3594
926deccb
FT
3595 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3596 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3597
3598 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3599 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3600
3601 rdev->ih.ring_obj = NULL;
3602 r600_ih_ring_init(rdev, 64 * 1024);
3603
3604 r = r600_pcie_gart_init(rdev);
3605 if (r)
3606 return r;
3607
3608 rdev->accel_working = true;
3609 r = r600_startup(rdev);
3610 if (r) {
3611 dev_err(rdev->dev, "disabling GPU acceleration\n");
3612 r600_cp_fini(rdev);
3613 r600_dma_fini(rdev);
3614 r600_irq_fini(rdev);
3615 radeon_wb_fini(rdev);
3616 radeon_ib_pool_fini(rdev);
3617 radeon_irq_kms_fini(rdev);
3618 r600_pcie_gart_fini(rdev);
3619 rdev->accel_working = false;
3620 }
3621
3622 return 0;
3623}
3624
3625void r600_fini(struct radeon_device *rdev)
3626{
3627 r600_audio_fini(rdev);
3628 r600_blit_fini(rdev);
3629 r600_cp_fini(rdev);
3630 r600_dma_fini(rdev);
3631 r600_irq_fini(rdev);
3632 radeon_wb_fini(rdev);
3633 radeon_ib_pool_fini(rdev);
3634 radeon_irq_kms_fini(rdev);
3635 r600_pcie_gart_fini(rdev);
3636 r600_vram_scratch_fini(rdev);
3637 radeon_agp_fini(rdev);
3638 radeon_gem_fini(rdev);
3639 radeon_fence_driver_fini(rdev);
3640 radeon_bo_fini(rdev);
3641 radeon_atombios_fini(rdev);
3642 r600_fini_microcode(rdev);
5a3b77d5 3643 drm_free(rdev->bios, M_DRM);
926deccb
FT
3644 rdev->bios = NULL;
3645}
3646
3647
3648/*
3649 * CS stuff
3650 */
3651void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3652{
3653 struct radeon_ring *ring = &rdev->ring[ib->ring];
3654 u32 next_rptr;
3655
3656 if (ring->rptr_save_reg) {
3657 next_rptr = ring->wptr + 3 + 4;
3658 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3659 radeon_ring_write(ring, ((ring->rptr_save_reg -
3660 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3661 radeon_ring_write(ring, next_rptr);
3662 } else if (rdev->wb.enabled) {
3663 next_rptr = ring->wptr + 5 + 4;
3664 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3665 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3666 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3667 radeon_ring_write(ring, next_rptr);
3668 radeon_ring_write(ring, 0);
3669 }
3670
3671 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3672 radeon_ring_write(ring,
3673#ifdef __BIG_ENDIAN
3674 (2 << 0) |
3675#endif
3676 (ib->gpu_addr & 0xFFFFFFFC));
3677 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3678 radeon_ring_write(ring, ib->length_dw);
3679}
3680
f43cf1b1
MN
3681void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3682{
3683 struct radeon_ring *ring = &rdev->ring[ib->ring];
3684
3685 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));
3686 radeon_ring_write(ring, ib->gpu_addr);
3687 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));
3688 radeon_ring_write(ring, ib->length_dw);
3689}
3690
926deccb
FT
3691int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3692{
3693 struct radeon_ib ib;
3694 uint32_t scratch;
3695 uint32_t tmp = 0;
3696 unsigned i;
3697 int r;
3698
3699 r = radeon_scratch_get(rdev, &scratch);
3700 if (r) {
3701 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3702 return r;
3703 }
3704 WREG32(scratch, 0xCAFEDEAD);
3705 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3706 if (r) {
3707 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3708 goto free_scratch;
3709 }
3710 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3711 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3712 ib.ptr[2] = 0xDEADBEEF;
3713 ib.length_dw = 3;
3714 r = radeon_ib_schedule(rdev, &ib, NULL);
3715 if (r) {
3716 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3717 goto free_ib;
3718 }
3719 r = radeon_fence_wait(ib.fence, false);
3720 if (r) {
3721 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3722 goto free_ib;
3723 }
3724 for (i = 0; i < rdev->usec_timeout; i++) {
3725 tmp = RREG32(scratch);
3726 if (tmp == 0xDEADBEEF)
3727 break;
3728 DRM_UDELAY(1);
3729 }
3730 if (i < rdev->usec_timeout) {
3731 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3732 } else {
3733 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3734 scratch, tmp);
3735 r = -EINVAL;
3736 }
3737free_ib:
3738 radeon_ib_free(rdev, &ib);
3739free_scratch:
3740 radeon_scratch_free(rdev, scratch);
3741 return r;
3742}
3743
3744/**
3745 * r600_dma_ib_test - test an IB on the DMA engine
3746 *
3747 * @rdev: radeon_device pointer
3748 * @ring: radeon_ring structure holding ring information
3749 *
3750 * Test a simple IB in the DMA ring (r6xx-SI).
3751 * Returns 0 on success, error on failure.
3752 */
3753int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3754{
3755 struct radeon_ib ib;
3756 unsigned i;
3757 int r;
3758 volatile uint32_t *ptr = rdev->vram_scratch.ptr;
3759 u32 tmp = 0;
3760
3761 if (!ptr) {
3762 DRM_ERROR("invalid vram scratch pointer\n");
3763 return -EINVAL;
3764 }
3765
3766 tmp = 0xCAFEDEAD;
3767 *ptr = tmp;
3768
3769 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3770 if (r) {
3771 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3772 return r;
3773 }
3774
3775 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3776 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3777 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3778 ib.ptr[3] = 0xDEADBEEF;
3779 ib.length_dw = 4;
3780
3781 r = radeon_ib_schedule(rdev, &ib, NULL);
3782 if (r) {
3783 radeon_ib_free(rdev, &ib);
3784 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3785 return r;
3786 }
3787 r = radeon_fence_wait(ib.fence, false);
3788 if (r) {
3789 radeon_ib_free(rdev, &ib);
3790 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3791 return r;
3792 }
3793 for (i = 0; i < rdev->usec_timeout; i++) {
3794 tmp = *ptr;
3795 if (tmp == 0xDEADBEEF)
3796 break;
3797 DRM_UDELAY(1);
3798 }
3799 if (i < rdev->usec_timeout) {
3800 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3801 } else {
3802 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3803 r = -EINVAL;
3804 }
3805 radeon_ib_free(rdev, &ib);
3806 return r;
3807}
3808
f43cf1b1
MN
3809int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3810{
3811 struct radeon_fence *fence = NULL;
3812 int r;
3813
3814 r = radeon_set_uvd_clocks(rdev, 53300, 40000);
3815 if (r) {
3816 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r);
3817 return r;
3818 }
3819
3820 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
3821 if (r) {
3822 DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
3823 goto error;
3824 }
3825
3826 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);
3827 if (r) {
3828 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
3829 goto error;
3830 }
3831
3832 r = radeon_fence_wait(fence, false);
3833 if (r) {
3834 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3835 goto error;
3836 }
3837 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
3838error:
3839 radeon_fence_unref(&fence);
3840 radeon_set_uvd_clocks(rdev, 0, 0);
3841 return r;
3842}
3843
926deccb
FT
3844/**
3845 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3846 *
3847 * @rdev: radeon_device pointer
3848 * @ib: IB object to schedule
3849 *
3850 * Schedule an IB in the DMA ring (r6xx-r7xx).
3851 */
3852void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3853{
3854 struct radeon_ring *ring = &rdev->ring[ib->ring];
3855
3856 if (rdev->wb.enabled) {
3857 u32 next_rptr = ring->wptr + 4;
3858 while ((next_rptr & 7) != 5)
3859 next_rptr++;
3860 next_rptr += 3;
3861 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3862 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3863 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3864 radeon_ring_write(ring, next_rptr);
3865 }
3866
3867 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3868 * Pad as necessary with NOPs.
3869 */
3870 while ((ring->wptr & 7) != 5)
3871 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3872 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3873 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3874 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3875
3876}
3877
3878/*
3879 * Interrupts
3880 *
3881 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3882 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3883 * writing to the ring and the GPU consuming, the GPU writes to the ring
3884 * and host consumes. As the host irq handler processes interrupts, it
3885 * increments the rptr. When the rptr catches up with the wptr, all the
3886 * current interrupts have been processed.
3887 */
3888
3889void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3890{
3891 u32 rb_bufsz;
3892
3893 /* Align ring size */
3894 rb_bufsz = drm_order(ring_size / 4);
3895 ring_size = (1 << rb_bufsz) * 4;
3896 rdev->ih.ring_size = ring_size;
3897 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3898 rdev->ih.rptr = 0;
3899}
3900
3901int r600_ih_ring_alloc(struct radeon_device *rdev)
3902{
3903 int r;
3904 void *ring_ptr;
3905
3906 /* Allocate ring buffer */
3907 if (rdev->ih.ring_obj == NULL) {
3908 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3909 PAGE_SIZE, true,
3910 RADEON_GEM_DOMAIN_GTT,
3911 NULL, &rdev->ih.ring_obj);
3912 if (r) {
3913 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3914 return r;
3915 }
3916 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3917 if (unlikely(r != 0)) {
3918 radeon_bo_unref(&rdev->ih.ring_obj);
3919 return r;
3920 }
3921 r = radeon_bo_pin(rdev->ih.ring_obj,
3922 RADEON_GEM_DOMAIN_GTT,
3923 &rdev->ih.gpu_addr);
3924 if (r) {
3925 radeon_bo_unreserve(rdev->ih.ring_obj);
3926 radeon_bo_unref(&rdev->ih.ring_obj);
3927 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3928 return r;
3929 }
3930 ring_ptr = &rdev->ih.ring;
3931 r = radeon_bo_kmap(rdev->ih.ring_obj,
3932 ring_ptr);
3933 if (r)
3934 radeon_bo_unpin(rdev->ih.ring_obj);
3935 radeon_bo_unreserve(rdev->ih.ring_obj);
3936 if (r) {
3937 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3938 radeon_bo_unref(&rdev->ih.ring_obj);
3939 return r;
3940 }
3941 }
3942 return 0;
3943}
3944
3945void r600_ih_ring_fini(struct radeon_device *rdev)
3946{
3947 int r;
3948 if (rdev->ih.ring_obj) {
3949 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3950 if (likely(r == 0)) {
3951 radeon_bo_kunmap(rdev->ih.ring_obj);
3952 radeon_bo_unpin(rdev->ih.ring_obj);
3953 radeon_bo_unreserve(rdev->ih.ring_obj);
3954 }
3955 radeon_bo_unref(&rdev->ih.ring_obj);
3956 rdev->ih.ring = NULL;
3957 rdev->ih.ring_obj = NULL;
3958 }
3959}
3960
3961void r600_rlc_stop(struct radeon_device *rdev)
3962{
3963
3964 if ((rdev->family >= CHIP_RV770) &&
3965 (rdev->family <= CHIP_RV740)) {
3966 /* r7xx asics need to soft reset RLC before halting */
3967 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3968 RREG32(SRBM_SOFT_RESET);
3969 DRM_MDELAY(15);
3970 WREG32(SRBM_SOFT_RESET, 0);
3971 RREG32(SRBM_SOFT_RESET);
3972 }
3973
3974 WREG32(RLC_CNTL, 0);
3975}
3976
3977static void r600_rlc_start(struct radeon_device *rdev)