drm/radeon: Sync to Linux 3.11
[dragonfly.git] / sys / dev / drm / radeon / radeon_atombios.c
CommitLineData
926deccb
FT
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 *
26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_atombios.c 254885 2013-08-25 19:37:15Z dumbbell $
27 */
28
29#include <drm/drmP.h>
30#include <uapi_drm/radeon_drm.h>
31#include "radeon.h"
32#include "radeon_asic.h" /* Declares several prototypes; clang is pleased. */
33
34#include "atom.h"
35#include "atom-bits.h"
36
926deccb
FT
37union atom_supported_devices {
38 struct _ATOM_SUPPORTED_DEVICES_INFO info;
39 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
40 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
41};
42
43static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
44 ATOM_GPIO_I2C_ASSIGMENT *gpio,
45 u8 index)
46{
47 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
48 if ((rdev->family == CHIP_R420) ||
49 (rdev->family == CHIP_R423) ||
50 (rdev->family == CHIP_RV410)) {
51 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
52 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
53 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
54 gpio->ucClkMaskShift = 0x19;
55 gpio->ucDataMaskShift = 0x18;
56 }
57 }
58
59 /* some evergreen boards have bad data for this entry */
60 if (ASIC_IS_DCE4(rdev)) {
61 if ((index == 7) &&
62 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
63 (gpio->sucI2cId.ucAccess == 0)) {
64 gpio->sucI2cId.ucAccess = 0x97;
65 gpio->ucDataMaskShift = 8;
66 gpio->ucDataEnShift = 8;
67 gpio->ucDataY_Shift = 8;
68 gpio->ucDataA_Shift = 8;
69 }
70 }
71
72 /* some DCE3 boards have bad data for this entry */
73 if (ASIC_IS_DCE3(rdev)) {
74 if ((index == 4) &&
75 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
76 (gpio->sucI2cId.ucAccess == 0x94))
77 gpio->sucI2cId.ucAccess = 0x14;
78 }
79}
80
81static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
82{
83 struct radeon_i2c_bus_rec i2c;
84
85 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
86
87 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
88 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
89 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
90 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
91 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
92 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
93 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
94 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
95 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
96 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
97 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
98 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
99 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
100 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
101 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
102 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
103
104 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
105 i2c.hw_capable = true;
106 else
107 i2c.hw_capable = false;
108
109 if (gpio->sucI2cId.ucAccess == 0xa0)
110 i2c.mm_i2c = true;
111 else
112 i2c.mm_i2c = false;
113
114 i2c.i2c_id = gpio->sucI2cId.ucAccess;
115
116 if (i2c.mask_clk_reg)
117 i2c.valid = true;
118 else
119 i2c.valid = false;
120
121 return i2c;
122}
123
124static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
125 uint8_t id)
126{
127 struct atom_context *ctx = rdev->mode_info.atom_context;
128 ATOM_GPIO_I2C_ASSIGMENT *gpio;
129 struct radeon_i2c_bus_rec i2c;
130 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
131 struct _ATOM_GPIO_I2C_INFO *i2c_info;
132 uint16_t data_offset, size;
133 int i, num_indices;
134
135 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
136 i2c.valid = false;
137
138 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
139 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset);
140
141 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
142 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
143
144 for (i = 0; i < num_indices; i++) {
145 gpio = &i2c_info->asGPIO_Info[i];
146
147 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
148
149 if (gpio->sucI2cId.ucAccess == id) {
150 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
151 break;
152 }
153 }
154 }
155
156 return i2c;
157}
158
159void radeon_atombios_i2c_init(struct radeon_device *rdev)
160{
161 struct atom_context *ctx = rdev->mode_info.atom_context;
162 ATOM_GPIO_I2C_ASSIGMENT *gpio;
163 struct radeon_i2c_bus_rec i2c;
164 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
165 struct _ATOM_GPIO_I2C_INFO *i2c_info;
166 uint16_t data_offset, size;
167 int i, num_indices;
168 char stmp[32];
169
170 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
171 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset);
172
173 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
174 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
175
176 for (i = 0; i < num_indices; i++) {
177 gpio = &i2c_info->asGPIO_Info[i];
178
179 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
180
181 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
182
183 if (i2c.valid) {
184 ksprintf(stmp, "0x%x", i2c.i2c_id);
185 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
186 }
187 }
188 }
189}
190
191static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
192 u8 id)
193{
194 struct atom_context *ctx = rdev->mode_info.atom_context;
195 struct radeon_gpio_rec gpio;
196 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
197 struct _ATOM_GPIO_PIN_LUT *gpio_info;
198 ATOM_GPIO_PIN_ASSIGNMENT *pin;
199 u16 data_offset, size;
200 int i, num_indices;
201
202 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
203 gpio.valid = false;
204
205 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
206 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)((char *)ctx->bios + data_offset);
207
208 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
209 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
210
211 for (i = 0; i < num_indices; i++) {
212 pin = &gpio_info->asGPIO_Pin[i];
213 if (id == pin->ucGPIO_ID) {
214 gpio.id = pin->ucGPIO_ID;
215 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
216 gpio.mask = (1 << pin->ucGpioPinBitShift);
217 gpio.valid = true;
218 break;
219 }
220 }
221 }
222
223 return gpio;
224}
225
226static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
227 struct radeon_gpio_rec *gpio)
228{
229 struct radeon_hpd hpd;
230 u32 reg;
231
232 memset(&hpd, 0, sizeof(struct radeon_hpd));
233
234 if (ASIC_IS_DCE6(rdev))
235 reg = SI_DC_GPIO_HPD_A;
236 else if (ASIC_IS_DCE4(rdev))
237 reg = EVERGREEN_DC_GPIO_HPD_A;
238 else
239 reg = AVIVO_DC_GPIO_HPD_A;
240
241 hpd.gpio = *gpio;
242 if (gpio->reg == reg) {
243 switch(gpio->mask) {
244 case (1 << 0):
245 hpd.hpd = RADEON_HPD_1;
246 break;
247 case (1 << 8):
248 hpd.hpd = RADEON_HPD_2;
249 break;
250 case (1 << 16):
251 hpd.hpd = RADEON_HPD_3;
252 break;
253 case (1 << 24):
254 hpd.hpd = RADEON_HPD_4;
255 break;
256 case (1 << 26):
257 hpd.hpd = RADEON_HPD_5;
258 break;
259 case (1 << 28):
260 hpd.hpd = RADEON_HPD_6;
261 break;
262 default:
263 hpd.hpd = RADEON_HPD_NONE;
264 break;
265 }
266 } else
267 hpd.hpd = RADEON_HPD_NONE;
268 return hpd;
269}
270
271static bool radeon_atom_apply_quirks(struct drm_device *dev,
272 uint32_t supported_device,
273 int *connector_type,
274 struct radeon_i2c_bus_rec *i2c_bus,
275 uint16_t *line_mux,
276 struct radeon_hpd *hpd)
277{
278
279 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
280 if ((dev->pci_device == 0x791e) &&
281 (dev->pci_subvendor == 0x1043) &&
282 (dev->pci_subdevice == 0x826d)) {
283 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
284 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
285 *connector_type = DRM_MODE_CONNECTOR_DVID;
286 }
287
288 /* Asrock RS600 board lists the DVI port as HDMI */
289 if ((dev->pci_device == 0x7941) &&
290 (dev->pci_subvendor == 0x1849) &&
291 (dev->pci_subdevice == 0x7941)) {
292 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
293 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
294 *connector_type = DRM_MODE_CONNECTOR_DVID;
295 }
296
297 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
298 if ((dev->pci_device == 0x796e) &&
299 (dev->pci_subvendor == 0x1462) &&
300 (dev->pci_subdevice == 0x7302)) {
301 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
302 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
303 return false;
304 }
305
306 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
307 if ((dev->pci_device == 0x7941) &&
308 (dev->pci_subvendor == 0x147b) &&
309 (dev->pci_subdevice == 0x2412)) {
310 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
311 return false;
312 }
313
314 /* Falcon NW laptop lists vga ddc line for LVDS */
315 if ((dev->pci_device == 0x5653) &&
316 (dev->pci_subvendor == 0x1462) &&
317 (dev->pci_subdevice == 0x0291)) {
318 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
319 i2c_bus->valid = false;
320 *line_mux = 53;
321 }
322 }
323
324 /* HIS X1300 is DVI+VGA, not DVI+DVI */
325 if ((dev->pci_device == 0x7146) &&
326 (dev->pci_subvendor == 0x17af) &&
327 (dev->pci_subdevice == 0x2058)) {
328 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
329 return false;
330 }
331
332 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
333 if ((dev->pci_device == 0x7142) &&
334 (dev->pci_subvendor == 0x1458) &&
335 (dev->pci_subdevice == 0x2134)) {
336 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
337 return false;
338 }
339
340
341 /* Funky macbooks */
342 if ((dev->pci_device == 0x71C5) &&
343 (dev->pci_subvendor == 0x106b) &&
344 (dev->pci_subdevice == 0x0080)) {
345 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
346 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
347 return false;
348 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
349 *line_mux = 0x90;
350 }
351
352 /* mac rv630, rv730, others */
353 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
354 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
355 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
356 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
357 }
358
359 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
360 if ((dev->pci_device == 0x9598) &&
361 (dev->pci_subvendor == 0x1043) &&
362 (dev->pci_subdevice == 0x01da)) {
363 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
364 *connector_type = DRM_MODE_CONNECTOR_DVII;
365 }
366 }
367
368 /* ASUS HD 3600 board lists the DVI port as HDMI */
369 if ((dev->pci_device == 0x9598) &&
370 (dev->pci_subvendor == 0x1043) &&
371 (dev->pci_subdevice == 0x01e4)) {
372 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
373 *connector_type = DRM_MODE_CONNECTOR_DVII;
374 }
375 }
376
377 /* ASUS HD 3450 board lists the DVI port as HDMI */
378 if ((dev->pci_device == 0x95C5) &&
379 (dev->pci_subvendor == 0x1043) &&
380 (dev->pci_subdevice == 0x01e2)) {
381 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
382 *connector_type = DRM_MODE_CONNECTOR_DVII;
383 }
384 }
385
386 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
387 * HDMI + VGA reporting as HDMI
388 */
389 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
390 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
391 *connector_type = DRM_MODE_CONNECTOR_VGA;
392 *line_mux = 0;
393 }
394 }
395
396 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
397 * on the laptop and a DVI port on the docking station and
398 * both share the same encoder, hpd pin, and ddc line.
399 * So while the bios table is technically correct,
400 * we drop the DVI port here since xrandr has no concept of
401 * encoders and will try and drive both connectors
402 * with different crtcs which isn't possible on the hardware
403 * side and leaves no crtcs for LVDS or VGA.
404 */
405 if (((dev->pci_device == 0x95c4) || (dev->pci_device == 0x9591)) &&
406 (dev->pci_subvendor == 0x1025) &&
407 (dev->pci_subdevice == 0x013c)) {
408 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
409 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
410 /* actually it's a DVI-D port not DVI-I */
411 *connector_type = DRM_MODE_CONNECTOR_DVID;
412 return false;
413 }
414 }
415
416 /* XFX Pine Group device rv730 reports no VGA DDC lines
417 * even though they are wired up to record 0x93
418 */
419 if ((dev->pci_device == 0x9498) &&
420 (dev->pci_subvendor == 0x1682) &&
421 (dev->pci_subdevice == 0x2452) &&
422 (i2c_bus->valid == false) &&
423 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
424 struct radeon_device *rdev = dev->dev_private;
425 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
426 }
427
428 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
429 if (((dev->pci_device == 0x9802) || (dev->pci_device == 0x9806)) &&
430 (dev->pci_subvendor == 0x1734) &&
431 (dev->pci_subdevice == 0x11bd)) {
432 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
433 *connector_type = DRM_MODE_CONNECTOR_DVII;
434 *line_mux = 0x3103;
435 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
436 *connector_type = DRM_MODE_CONNECTOR_DVII;
437 }
438 }
439
440
441 return true;
442}
443
444const int supported_devices_connector_convert[] = {
445 DRM_MODE_CONNECTOR_Unknown,
446 DRM_MODE_CONNECTOR_VGA,
447 DRM_MODE_CONNECTOR_DVII,
448 DRM_MODE_CONNECTOR_DVID,
449 DRM_MODE_CONNECTOR_DVIA,
450 DRM_MODE_CONNECTOR_SVIDEO,
451 DRM_MODE_CONNECTOR_Composite,
452 DRM_MODE_CONNECTOR_LVDS,
453 DRM_MODE_CONNECTOR_Unknown,
454 DRM_MODE_CONNECTOR_Unknown,
455 DRM_MODE_CONNECTOR_HDMIA,
456 DRM_MODE_CONNECTOR_HDMIB,
457 DRM_MODE_CONNECTOR_Unknown,
458 DRM_MODE_CONNECTOR_Unknown,
459 DRM_MODE_CONNECTOR_9PinDIN,
460 DRM_MODE_CONNECTOR_DisplayPort
461};
462
463const uint16_t supported_devices_connector_object_id_convert[] = {
464 CONNECTOR_OBJECT_ID_NONE,
465 CONNECTOR_OBJECT_ID_VGA,
466 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
467 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
468 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
469 CONNECTOR_OBJECT_ID_COMPOSITE,
470 CONNECTOR_OBJECT_ID_SVIDEO,
471 CONNECTOR_OBJECT_ID_LVDS,
472 CONNECTOR_OBJECT_ID_9PIN_DIN,
473 CONNECTOR_OBJECT_ID_9PIN_DIN,
474 CONNECTOR_OBJECT_ID_DISPLAYPORT,
475 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
476 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
477 CONNECTOR_OBJECT_ID_SVIDEO
478};
479
480const int object_connector_convert[] = {
481 DRM_MODE_CONNECTOR_Unknown,
482 DRM_MODE_CONNECTOR_DVII,
483 DRM_MODE_CONNECTOR_DVII,
484 DRM_MODE_CONNECTOR_DVID,
485 DRM_MODE_CONNECTOR_DVID,
486 DRM_MODE_CONNECTOR_VGA,
487 DRM_MODE_CONNECTOR_Composite,
488 DRM_MODE_CONNECTOR_SVIDEO,
489 DRM_MODE_CONNECTOR_Unknown,
490 DRM_MODE_CONNECTOR_Unknown,
491 DRM_MODE_CONNECTOR_9PinDIN,
492 DRM_MODE_CONNECTOR_Unknown,
493 DRM_MODE_CONNECTOR_HDMIA,
494 DRM_MODE_CONNECTOR_HDMIB,
495 DRM_MODE_CONNECTOR_LVDS,
496 DRM_MODE_CONNECTOR_9PinDIN,
497 DRM_MODE_CONNECTOR_Unknown,
498 DRM_MODE_CONNECTOR_Unknown,
499 DRM_MODE_CONNECTOR_Unknown,
500 DRM_MODE_CONNECTOR_DisplayPort,
501 DRM_MODE_CONNECTOR_eDP,
502 DRM_MODE_CONNECTOR_Unknown
503};
504
505bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
506{
507 struct radeon_device *rdev = dev->dev_private;
508 struct radeon_mode_info *mode_info = &rdev->mode_info;
509 struct atom_context *ctx = mode_info->atom_context;
510 int index = GetIndexIntoMasterTable(DATA, Object_Header);
511 u16 size, data_offset;
512 u8 frev, crev;
513 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
514 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
515 ATOM_OBJECT_TABLE *router_obj;
516 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
517 ATOM_OBJECT_HEADER *obj_header;
518 int i, j, k, path_size, device_support;
519 int connector_type;
520 u16 igp_lane_info, conn_id, connector_object_id;
521 struct radeon_i2c_bus_rec ddc_bus;
522 struct radeon_router router;
523 struct radeon_gpio_rec gpio;
524 struct radeon_hpd hpd;
525
526 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
527 return false;
528
529 if (crev < 2)
530 return false;
531
532 obj_header = (ATOM_OBJECT_HEADER *) ((char *)ctx->bios + data_offset);
533 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
534 ((char *)ctx->bios + data_offset +
535 le16_to_cpu(obj_header->usDisplayPathTableOffset));
536 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
537 ((char *)ctx->bios + data_offset +
538 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
539 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
540 ((char *)ctx->bios + data_offset +
541 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
542 router_obj = (ATOM_OBJECT_TABLE *)
543 ((char *)ctx->bios + data_offset +
544 le16_to_cpu(obj_header->usRouterObjectTableOffset));
545 device_support = le16_to_cpu(obj_header->usDeviceSupport);
546
547 path_size = 0;
548 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
549 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
550 ATOM_DISPLAY_OBJECT_PATH *path;
551 addr += path_size;
552 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
553 path_size += le16_to_cpu(path->usSize);
554
555 if (device_support & le16_to_cpu(path->usDeviceTag)) {
556 uint8_t con_obj_id, con_obj_num, con_obj_type;
557
558 con_obj_id =
559 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
560 >> OBJECT_ID_SHIFT;
561 con_obj_num =
562 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
563 >> ENUM_ID_SHIFT;
564 con_obj_type =
565 (le16_to_cpu(path->usConnObjectId) &
566 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
567
568 /* TODO CV support */
569 if (le16_to_cpu(path->usDeviceTag) ==
570 ATOM_DEVICE_CV_SUPPORT)
571 continue;
572
573 /* IGP chips */
574 if ((rdev->flags & RADEON_IS_IGP) &&
575 (con_obj_id ==
576 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
577 uint16_t igp_offset = 0;
578 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
579
580 index =
581 GetIndexIntoMasterTable(DATA,
582 IntegratedSystemInfo);
583
584 if (atom_parse_data_header(ctx, index, &size, &frev,
585 &crev, &igp_offset)) {
586
587 if (crev >= 2) {
588 igp_obj =
589 (ATOM_INTEGRATED_SYSTEM_INFO_V2
590 *) ((char *)ctx->bios + igp_offset);
591
592 if (igp_obj) {
593 uint32_t slot_config, ct;
594
595 if (con_obj_num == 1)
596 slot_config =
597 igp_obj->
598 ulDDISlot1Config;
599 else
600 slot_config =
601 igp_obj->
602 ulDDISlot2Config;
603
604 ct = (slot_config >> 16) & 0xff;
605 connector_type =
606 object_connector_convert
607 [ct];
608 connector_object_id = ct;
609 igp_lane_info =
610 slot_config & 0xffff;
611 } else
612 continue;
613 } else
614 continue;
615 } else {
616 igp_lane_info = 0;
617 connector_type =
618 object_connector_convert[con_obj_id];
619 connector_object_id = con_obj_id;
620 }
621 } else {
622 igp_lane_info = 0;
623 connector_type =
624 object_connector_convert[con_obj_id];
625 connector_object_id = con_obj_id;
626 }
627
628 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
629 continue;
630
631 router.ddc_valid = false;
632 router.cd_valid = false;
633 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
634 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
635
636 grph_obj_id =
637 (le16_to_cpu(path->usGraphicObjIds[j]) &
638 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
639 grph_obj_num =
640 (le16_to_cpu(path->usGraphicObjIds[j]) &
641 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
642 grph_obj_type =
643 (le16_to_cpu(path->usGraphicObjIds[j]) &
644 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
645
646 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
647 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
648 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
649 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
650 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
651 ((char *)ctx->bios + data_offset +
652 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
653 ATOM_ENCODER_CAP_RECORD *cap_record;
654 u16 caps = 0;
655
656 while (record->ucRecordSize > 0 &&
657 record->ucRecordType > 0 &&
658 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
659 switch (record->ucRecordType) {
660 case ATOM_ENCODER_CAP_RECORD_TYPE:
661 cap_record =(ATOM_ENCODER_CAP_RECORD *)
662 record;
663 caps = le16_to_cpu(cap_record->usEncoderCap);
664 break;
665 }
666 record = (ATOM_COMMON_RECORD_HEADER *)
667 ((char *)record + record->ucRecordSize);
668 }
669 radeon_add_atom_encoder(dev,
670 encoder_obj,
671 le16_to_cpu
672 (path->
673 usDeviceTag),
674 caps);
675 }
676 }
677 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
678 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
679 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
680 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
681 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
682 ((char *)ctx->bios + data_offset +
683 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
684 ATOM_I2C_RECORD *i2c_record;
685 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
686 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
687 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
688 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
689 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
690 ((char *)ctx->bios + data_offset +
691 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
692 int enum_id;
693
694 router.router_id = router_obj_id;
695 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
696 enum_id++) {
697 if (le16_to_cpu(path->usConnObjectId) ==
698 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
699 break;
700 }
701
702 while (record->ucRecordSize > 0 &&
703 record->ucRecordType > 0 &&
704 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
705 switch (record->ucRecordType) {
706 case ATOM_I2C_RECORD_TYPE:
707 i2c_record =
708 (ATOM_I2C_RECORD *)
709 record;
710 i2c_config =
711 (ATOM_I2C_ID_CONFIG_ACCESS *)
712 &i2c_record->sucI2cId;
713 router.i2c_info =
714 radeon_lookup_i2c_gpio(rdev,
715 i2c_config->
716 ucAccess);
717 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
718 break;
719 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
720 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
721 record;
722 router.ddc_valid = true;
723 router.ddc_mux_type = ddc_path->ucMuxType;
724 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
725 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
726 break;
727 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
728 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
729 record;
730 router.cd_valid = true;
731 router.cd_mux_type = cd_path->ucMuxType;
732 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
733 router.cd_mux_state = cd_path->ucMuxState[enum_id];
734 break;
735 }
736 record = (ATOM_COMMON_RECORD_HEADER *)
737 ((char *)record + record->ucRecordSize);
738 }
739 }
740 }
741 }
742 }
743
744 /* look up gpio for ddc, hpd */
745 ddc_bus.valid = false;
746 hpd.hpd = RADEON_HPD_NONE;
747 if ((le16_to_cpu(path->usDeviceTag) &
748 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
749 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
750 if (le16_to_cpu(path->usConnObjectId) ==
751 le16_to_cpu(con_obj->asObjects[j].
752 usObjectID)) {
753 ATOM_COMMON_RECORD_HEADER
754 *record =
755 (ATOM_COMMON_RECORD_HEADER
756 *)
757 ((char *)ctx->bios + data_offset +
758 le16_to_cpu(con_obj->
759 asObjects[j].
760 usRecordOffset));
761 ATOM_I2C_RECORD *i2c_record;
762 ATOM_HPD_INT_RECORD *hpd_record;
763 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
764
765 while (record->ucRecordSize > 0 &&
766 record->ucRecordType > 0 &&
767 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
768 switch (record->ucRecordType) {
769 case ATOM_I2C_RECORD_TYPE:
770 i2c_record =
771 (ATOM_I2C_RECORD *)
772 record;
773 i2c_config =
774 (ATOM_I2C_ID_CONFIG_ACCESS *)
775 &i2c_record->sucI2cId;
776 ddc_bus = radeon_lookup_i2c_gpio(rdev,
777 i2c_config->
778 ucAccess);
779 break;
780 case ATOM_HPD_INT_RECORD_TYPE:
781 hpd_record =
782 (ATOM_HPD_INT_RECORD *)
783 record;
784 gpio = radeon_lookup_gpio(rdev,
785 hpd_record->ucHPDIntGPIOID);
786 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
787 hpd.plugged_state = hpd_record->ucPlugged_PinState;
788 break;
789 }
790 record =
791 (ATOM_COMMON_RECORD_HEADER
792 *) ((char *)record
793 +
794 record->
795 ucRecordSize);
796 }
797 break;
798 }
799 }
800 }
801
802 /* needed for aux chan transactions */
803 ddc_bus.hpd = hpd.hpd;
804
805 conn_id = le16_to_cpu(path->usConnObjectId);
806
807 if (!radeon_atom_apply_quirks
808 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
809 &ddc_bus, &conn_id, &hpd))
810 continue;
811
812 radeon_add_atom_connector(dev,
813 conn_id,
814 le16_to_cpu(path->
815 usDeviceTag),
816 connector_type, &ddc_bus,
817 igp_lane_info,
818 connector_object_id,
819 &hpd,
820 &router);
821
822 }
823 }
824
825 radeon_link_encoder_connector(dev);
826
827 return true;
828}
829
830static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
831 int connector_type,
832 uint16_t devices)
833{
834 struct radeon_device *rdev = dev->dev_private;
835
836 if (rdev->flags & RADEON_IS_IGP) {
837 return supported_devices_connector_object_id_convert
838 [connector_type];
839 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
840 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
841 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
842 struct radeon_mode_info *mode_info = &rdev->mode_info;
843 struct atom_context *ctx = mode_info->atom_context;
844 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
845 uint16_t size, data_offset;
846 uint8_t frev, crev;
847 ATOM_XTMDS_INFO *xtmds;
848
849 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
850 xtmds = (ATOM_XTMDS_INFO *)((char *)ctx->bios + data_offset);
851
852 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
853 if (connector_type == DRM_MODE_CONNECTOR_DVII)
854 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
855 else
856 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
857 } else {
858 if (connector_type == DRM_MODE_CONNECTOR_DVII)
859 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
860 else
861 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
862 }
863 } else
864 return supported_devices_connector_object_id_convert
865 [connector_type];
866 } else {
867 return supported_devices_connector_object_id_convert
868 [connector_type];
869 }
870}
871
872struct bios_connector {
873 bool valid;
874 uint16_t line_mux;
875 uint16_t devices;
876 int connector_type;
877 struct radeon_i2c_bus_rec ddc_bus;
878 struct radeon_hpd hpd;
879};
880
881bool radeon_get_atom_connector_info_from_supported_devices_table(struct
882 drm_device
883 *dev)
884{
885 struct radeon_device *rdev = dev->dev_private;
886 struct radeon_mode_info *mode_info = &rdev->mode_info;
887 struct atom_context *ctx = mode_info->atom_context;
888 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
889 uint16_t size, data_offset;
890 uint8_t frev, crev;
891 uint16_t device_support;
892 uint8_t dac;
893 union atom_supported_devices *supported_devices;
894 int i, j, max_device;
895 struct bios_connector *bios_connectors;
896 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
897 struct radeon_router router;
898
899 router.ddc_valid = false;
900 router.cd_valid = false;
901
5a3b77d5 902 bios_connectors = kmalloc(bc_size, M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
903 if (!bios_connectors)
904 return false;
905
906 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
907 &data_offset)) {
5a3b77d5 908 drm_free(bios_connectors, M_DRM);
926deccb
FT
909 return false;
910 }
911
912 supported_devices =
913 (union atom_supported_devices *)((char *)ctx->bios + data_offset);
914
915 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
916
917 if (frev > 1)
918 max_device = ATOM_MAX_SUPPORTED_DEVICE;
919 else
920 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
921
922 for (i = 0; i < max_device; i++) {
923 ATOM_CONNECTOR_INFO_I2C ci =
924 supported_devices->info.asConnInfo[i];
925
926 bios_connectors[i].valid = false;
927
928 if (!(device_support & (1 << i))) {
929 continue;
930 }
931
932 if (i == ATOM_DEVICE_CV_INDEX) {
933 DRM_DEBUG_KMS("Skipping Component Video\n");
934 continue;
935 }
936
937 bios_connectors[i].connector_type =
938 supported_devices_connector_convert[ci.sucConnectorInfo.
939 sbfAccess.
940 bfConnectorType];
941
942 if (bios_connectors[i].connector_type ==
943 DRM_MODE_CONNECTOR_Unknown)
944 continue;
945
946 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
947
948 bios_connectors[i].line_mux =
949 ci.sucI2cId.ucAccess;
950
951 /* give tv unique connector ids */
952 if (i == ATOM_DEVICE_TV1_INDEX) {
953 bios_connectors[i].ddc_bus.valid = false;
954 bios_connectors[i].line_mux = 50;
955 } else if (i == ATOM_DEVICE_TV2_INDEX) {
956 bios_connectors[i].ddc_bus.valid = false;
957 bios_connectors[i].line_mux = 51;
958 } else if (i == ATOM_DEVICE_CV_INDEX) {
959 bios_connectors[i].ddc_bus.valid = false;
960 bios_connectors[i].line_mux = 52;
961 } else
962 bios_connectors[i].ddc_bus =
963 radeon_lookup_i2c_gpio(rdev,
964 bios_connectors[i].line_mux);
965
966 if ((crev > 1) && (frev > 1)) {
967 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
968 switch (isb) {
969 case 0x4:
970 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
971 break;
972 case 0xa:
973 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
974 break;
975 default:
976 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
977 break;
978 }
979 } else {
980 if (i == ATOM_DEVICE_DFP1_INDEX)
981 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
982 else if (i == ATOM_DEVICE_DFP2_INDEX)
983 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
984 else
985 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
986 }
987
988 /* Always set the connector type to VGA for CRT1/CRT2. if they are
989 * shared with a DVI port, we'll pick up the DVI connector when we
990 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
991 */
992 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
993 bios_connectors[i].connector_type =
994 DRM_MODE_CONNECTOR_VGA;
995
996 if (!radeon_atom_apply_quirks
997 (dev, (1 << i), &bios_connectors[i].connector_type,
998 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
999 &bios_connectors[i].hpd))
1000 continue;
1001
1002 bios_connectors[i].valid = true;
1003 bios_connectors[i].devices = (1 << i);
1004
1005 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1006 radeon_add_atom_encoder(dev,
1007 radeon_get_encoder_enum(dev,
1008 (1 << i),
1009 dac),
1010 (1 << i),
1011 0);
1012 else
1013 radeon_add_legacy_encoder(dev,
1014 radeon_get_encoder_enum(dev,
1015 (1 << i),
1016 dac),
1017 (1 << i));
1018 }
1019
1020 /* combine shared connectors */
1021 for (i = 0; i < max_device; i++) {
1022 if (bios_connectors[i].valid) {
1023 for (j = 0; j < max_device; j++) {
1024 if (bios_connectors[j].valid && (i != j)) {
1025 if (bios_connectors[i].line_mux ==
1026 bios_connectors[j].line_mux) {
1027 /* make sure not to combine LVDS */
1028 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1029 bios_connectors[i].line_mux = 53;
1030 bios_connectors[i].ddc_bus.valid = false;
1031 continue;
1032 }
1033 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1034 bios_connectors[j].line_mux = 53;
1035 bios_connectors[j].ddc_bus.valid = false;
1036 continue;
1037 }
1038 /* combine analog and digital for DVI-I */
1039 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1040 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1041 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1042 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1043 bios_connectors[i].devices |=
1044 bios_connectors[j].devices;
1045 bios_connectors[i].connector_type =
1046 DRM_MODE_CONNECTOR_DVII;
1047 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1048 bios_connectors[i].hpd =
1049 bios_connectors[j].hpd;
1050 bios_connectors[j].valid = false;
1051 }
1052 }
1053 }
1054 }
1055 }
1056 }
1057
1058 /* add the connectors */
1059 for (i = 0; i < max_device; i++) {
1060 if (bios_connectors[i].valid) {
1061 uint16_t connector_object_id =
1062 atombios_get_connector_object_id(dev,
1063 bios_connectors[i].connector_type,
1064 bios_connectors[i].devices);
1065 radeon_add_atom_connector(dev,
1066 bios_connectors[i].line_mux,
1067 bios_connectors[i].devices,
1068 bios_connectors[i].
1069 connector_type,
1070 &bios_connectors[i].ddc_bus,
1071 0,
1072 connector_object_id,
1073 &bios_connectors[i].hpd,
1074 &router);
1075 }
1076 }
1077
1078 radeon_link_encoder_connector(dev);
1079
5a3b77d5 1080 drm_free(bios_connectors, M_DRM);
926deccb
FT
1081 return true;
1082}
1083
1084union firmware_info {
1085 ATOM_FIRMWARE_INFO info;
1086 ATOM_FIRMWARE_INFO_V1_2 info_12;
1087 ATOM_FIRMWARE_INFO_V1_3 info_13;
1088 ATOM_FIRMWARE_INFO_V1_4 info_14;
1089 ATOM_FIRMWARE_INFO_V2_1 info_21;
1090 ATOM_FIRMWARE_INFO_V2_2 info_22;
1091};
1092
1093bool radeon_atom_get_clock_info(struct drm_device *dev)
1094{
1095 struct radeon_device *rdev = dev->dev_private;
1096 struct radeon_mode_info *mode_info = &rdev->mode_info;
1097 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1098 union firmware_info *firmware_info;
1099 uint8_t frev, crev;
1100 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1101 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1102 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1103 struct radeon_pll *spll = &rdev->clock.spll;
1104 struct radeon_pll *mpll = &rdev->clock.mpll;
1105 uint16_t data_offset;
1106
1107 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1108 &frev, &crev, &data_offset)) {
1109 firmware_info =
1110 (union firmware_info *)((char *)mode_info->atom_context->bios +
1111 data_offset);
1112 /* pixel clocks */
1113 p1pll->reference_freq =
1114 le16_to_cpu(firmware_info->info.usReferenceClock);
1115 p1pll->reference_div = 0;
1116
1117 if (crev < 2)
1118 p1pll->pll_out_min =
1119 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1120 else
1121 p1pll->pll_out_min =
1122 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1123 p1pll->pll_out_max =
1124 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1125
1126 if (crev >= 4) {
1127 p1pll->lcd_pll_out_min =
1128 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1129 if (p1pll->lcd_pll_out_min == 0)
1130 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1131 p1pll->lcd_pll_out_max =
1132 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1133 if (p1pll->lcd_pll_out_max == 0)
1134 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1135 } else {
1136 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1137 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1138 }
1139
1140 if (p1pll->pll_out_min == 0) {
1141 if (ASIC_IS_AVIVO(rdev))
1142 p1pll->pll_out_min = 64800;
1143 else
1144 p1pll->pll_out_min = 20000;
1145 }
1146
1147 p1pll->pll_in_min =
1148 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1149 p1pll->pll_in_max =
1150 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1151
1152 *p2pll = *p1pll;
1153
1154 /* system clock */
1155 if (ASIC_IS_DCE4(rdev))
1156 spll->reference_freq =
1157 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1158 else
1159 spll->reference_freq =
1160 le16_to_cpu(firmware_info->info.usReferenceClock);
1161 spll->reference_div = 0;
1162
1163 spll->pll_out_min =
1164 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1165 spll->pll_out_max =
1166 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1167
1168 /* ??? */
1169 if (spll->pll_out_min == 0) {
1170 if (ASIC_IS_AVIVO(rdev))
1171 spll->pll_out_min = 64800;
1172 else
1173 spll->pll_out_min = 20000;
1174 }
1175
1176 spll->pll_in_min =
1177 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1178 spll->pll_in_max =
1179 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1180
1181 /* memory clock */
1182 if (ASIC_IS_DCE4(rdev))
1183 mpll->reference_freq =
1184 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1185 else
1186 mpll->reference_freq =
1187 le16_to_cpu(firmware_info->info.usReferenceClock);
1188 mpll->reference_div = 0;
1189
1190 mpll->pll_out_min =
1191 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1192 mpll->pll_out_max =
1193 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1194
1195 /* ??? */
1196 if (mpll->pll_out_min == 0) {
1197 if (ASIC_IS_AVIVO(rdev))
1198 mpll->pll_out_min = 64800;
1199 else
1200 mpll->pll_out_min = 20000;
1201 }
1202
1203 mpll->pll_in_min =
1204 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1205 mpll->pll_in_max =
1206 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1207
1208 rdev->clock.default_sclk =
1209 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1210 rdev->clock.default_mclk =
1211 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1212
1213 if (ASIC_IS_DCE4(rdev)) {
1214 rdev->clock.default_dispclk =
1215 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1216 if (rdev->clock.default_dispclk == 0) {
1217 if (ASIC_IS_DCE5(rdev))
1218 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1219 else
1220 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1221 }
1222 rdev->clock.dp_extclk =
1223 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
57e252bf 1224 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
926deccb
FT
1225 }
1226 *dcpll = *p1pll;
1227
1228 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1229 if (rdev->clock.max_pixel_clock == 0)
1230 rdev->clock.max_pixel_clock = 40000;
1231
1232 /* not technically a clock, but... */
1233 rdev->mode_info.firmware_flags =
1234 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1235
1236 return true;
1237 }
1238
1239 return false;
1240}
1241
1242union igp_info {
1243 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1244 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1245 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1246 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
57e252bf 1247 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
926deccb
FT
1248};
1249
1250bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1251{
1252 struct radeon_mode_info *mode_info = &rdev->mode_info;
1253 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1254 union igp_info *igp_info;
1255 u8 frev, crev;
1256 u16 data_offset;
1257
1258 /* sideport is AMD only */
1259 if (rdev->family == CHIP_RS600)
1260 return false;
1261
1262 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1263 &frev, &crev, &data_offset)) {
1264 igp_info = (union igp_info *)((char *)mode_info->atom_context->bios +
1265 data_offset);
1266 switch (crev) {
1267 case 1:
1268 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1269 return true;
1270 break;
1271 case 2:
1272 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1273 return true;
1274 break;
1275 default:
1276 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1277 break;
1278 }
1279 }
1280 return false;
1281}
1282
1283bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1284 struct radeon_encoder_int_tmds *tmds)
1285{
1286 struct drm_device *dev = encoder->base.dev;
1287 struct radeon_device *rdev = dev->dev_private;
1288 struct radeon_mode_info *mode_info = &rdev->mode_info;
1289 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1290 uint16_t data_offset;
1291 struct _ATOM_TMDS_INFO *tmds_info;
1292 uint8_t frev, crev;
1293 uint16_t maxfreq;
1294 int i;
1295
1296 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1297 &frev, &crev, &data_offset)) {
1298 tmds_info =
1299 (struct _ATOM_TMDS_INFO *)((char *)mode_info->atom_context->bios +
1300 data_offset);
1301
1302 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1303 for (i = 0; i < 4; i++) {
1304 tmds->tmds_pll[i].freq =
1305 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1306 tmds->tmds_pll[i].value =
1307 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1308 tmds->tmds_pll[i].value |=
1309 (tmds_info->asMiscInfo[i].
1310 ucPLL_VCO_Gain & 0x3f) << 6;
1311 tmds->tmds_pll[i].value |=
1312 (tmds_info->asMiscInfo[i].
1313 ucPLL_DutyCycle & 0xf) << 12;
1314 tmds->tmds_pll[i].value |=
1315 (tmds_info->asMiscInfo[i].
1316 ucPLL_VoltageSwing & 0xf) << 16;
1317
1318 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1319 tmds->tmds_pll[i].freq,
1320 tmds->tmds_pll[i].value);
1321
1322 if (maxfreq == tmds->tmds_pll[i].freq) {
1323 tmds->tmds_pll[i].freq = 0xffffffff;
1324 break;
1325 }
1326 }
1327 return true;
1328 }
1329 return false;
1330}
1331
1332bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1333 struct radeon_atom_ss *ss,
1334 int id)
1335{
1336 struct radeon_mode_info *mode_info = &rdev->mode_info;
1337 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1338 uint16_t data_offset, size;
1339 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1340 uint8_t frev, crev;
1341 int i, num_indices;
1342
1343 memset(ss, 0, sizeof(struct radeon_atom_ss));
1344 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1345 &frev, &crev, &data_offset)) {
1346 ss_info =
1347 (struct _ATOM_SPREAD_SPECTRUM_INFO *)((char *)mode_info->atom_context->bios + data_offset);
1348
1349 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1350 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1351
1352 for (i = 0; i < num_indices; i++) {
1353 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1354 ss->percentage =
1355 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1356 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1357 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1358 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1359 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1360 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1361 return true;
1362 }
1363 }
1364 }
1365 return false;
1366}
1367
1368static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1369 struct radeon_atom_ss *ss,
1370 int id)
1371{
1372 struct radeon_mode_info *mode_info = &rdev->mode_info;
1373 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1374 u16 data_offset, size;
1375 union igp_info *igp_info;
1376 u8 frev, crev;
1377 u16 percentage = 0, rate = 0;
1378
1379 /* get any igp specific overrides */
1380 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1381 &frev, &crev, &data_offset)) {
1382 igp_info = (union igp_info *)
1383 ((char *)mode_info->atom_context->bios + data_offset);
1384 switch (crev) {
1385 case 6:
1386 switch (id) {
1387 case ASIC_INTERNAL_SS_ON_TMDS:
1388 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1389 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1390 break;
1391 case ASIC_INTERNAL_SS_ON_HDMI:
1392 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1393 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1394 break;
1395 case ASIC_INTERNAL_SS_ON_LVDS:
1396 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1397 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1398 break;
1399 }
1400 break;
1401 case 7:
1402 switch (id) {
1403 case ASIC_INTERNAL_SS_ON_TMDS:
1404 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1405 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1406 break;
1407 case ASIC_INTERNAL_SS_ON_HDMI:
1408 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1409 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1410 break;
1411 case ASIC_INTERNAL_SS_ON_LVDS:
1412 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1413 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1414 break;
1415 }
1416 break;
57e252bf
MN
1417 case 8:
1418 switch (id) {
1419 case ASIC_INTERNAL_SS_ON_TMDS:
1420 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1421 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1422 break;
1423 case ASIC_INTERNAL_SS_ON_HDMI:
1424 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1425 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1426 break;
1427 case ASIC_INTERNAL_SS_ON_LVDS:
1428 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1429 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1430 break;
1431 }
1432 break;
926deccb
FT
1433 default:
1434 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1435 break;
1436 }
1437 if (percentage)
1438 ss->percentage = percentage;
1439 if (rate)
1440 ss->rate = rate;
1441 }
1442}
1443
1444union asic_ss_info {
1445 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1446 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1447 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1448};
1449
1450bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1451 struct radeon_atom_ss *ss,
1452 int id, u32 clock)
1453{
1454 struct radeon_mode_info *mode_info = &rdev->mode_info;
1455 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1456 uint16_t data_offset, size;
1457 union asic_ss_info *ss_info;
1458 uint8_t frev, crev;
1459 int i, num_indices;
1460
1461 memset(ss, 0, sizeof(struct radeon_atom_ss));
1462 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1463 &frev, &crev, &data_offset)) {
1464
1465 ss_info =
1466 (union asic_ss_info *)((char *)mode_info->atom_context->bios + data_offset);
1467
1468 switch (frev) {
1469 case 1:
1470 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1471 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1472
1473 for (i = 0; i < num_indices; i++) {
1474 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1475 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1476 ss->percentage =
1477 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1478 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1479 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1480 return true;
1481 }
1482 }
1483 break;
1484 case 2:
1485 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1486 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1487 for (i = 0; i < num_indices; i++) {
1488 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1489 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1490 ss->percentage =
1491 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1492 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1493 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
57e252bf
MN
1494 if ((crev == 2) &&
1495 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1496 (id == ASIC_INTERNAL_MEMORY_SS)))
1497 ss->rate /= 100;
926deccb
FT
1498 return true;
1499 }
1500 }
1501 break;
1502 case 3:
1503 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1504 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1505 for (i = 0; i < num_indices; i++) {
1506 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1507 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1508 ss->percentage =
1509 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1510 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1511 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
57e252bf
MN
1512 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1513 (id == ASIC_INTERNAL_MEMORY_SS))
1514 ss->rate /= 100;
926deccb
FT
1515 if (rdev->flags & RADEON_IS_IGP)
1516 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1517 return true;
1518 }
1519 }
1520 break;
1521 default:
1522 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1523 break;
1524 }
1525
1526 }
1527 return false;
1528}
1529
1530union lvds_info {
1531 struct _ATOM_LVDS_INFO info;
1532 struct _ATOM_LVDS_INFO_V12 info_12;
1533};
1534
1535struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1536 radeon_encoder
1537 *encoder)
1538{
1539 struct drm_device *dev = encoder->base.dev;
1540 struct radeon_device *rdev = dev->dev_private;
1541 struct radeon_mode_info *mode_info = &rdev->mode_info;
1542 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1543 uint16_t data_offset, misc;
1544 union lvds_info *lvds_info;
1545 uint8_t frev, crev;
1546 struct radeon_encoder_atom_dig *lvds = NULL;
1547 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1548
1549 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1550 &frev, &crev, &data_offset)) {
1551 lvds_info =
1552 (union lvds_info *)((char *)mode_info->atom_context->bios + data_offset);
1553 lvds =
1554 kmalloc(sizeof(struct radeon_encoder_atom_dig),
5a3b77d5 1555 M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
1556
1557 if (!lvds)
1558 return NULL;
1559
1560 lvds->native_mode.clock =
1561 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1562 lvds->native_mode.hdisplay =
1563 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1564 lvds->native_mode.vdisplay =
1565 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1566 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1567 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1568 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1569 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1570 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1571 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1572 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1573 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1574 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1575 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1576 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1577 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1578 lvds->panel_pwr_delay =
1579 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1580 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1581
1582 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1583 if (misc & ATOM_VSYNC_POLARITY)
1584 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1585 if (misc & ATOM_HSYNC_POLARITY)
1586 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1587 if (misc & ATOM_COMPOSITESYNC)
1588 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1589 if (misc & ATOM_INTERLACE)
1590 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1591 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1592 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1593
1594 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1595 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1596
1597 /* set crtc values */
1598 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1599
1600 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1601
1602 encoder->native_mode = lvds->native_mode;
1603
1604 if (encoder_enum == 2)
1605 lvds->linkb = true;
1606 else
1607 lvds->linkb = false;
1608
1609 /* parse the lcd record table */
1610 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1611 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1612 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1613 bool bad_record = false;
1614 u8 *record;
1615
1616 if ((frev == 1) && (crev < 2))
1617 /* absolute */
1618 record = (u8 *)((char *)mode_info->atom_context->bios +
1619 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1620 else
1621 /* relative */
1622 record = (u8 *)((char *)mode_info->atom_context->bios +
1623 data_offset +
1624 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1625 while (*record != ATOM_RECORD_END_TYPE) {
1626 switch (*record) {
1627 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1628 record += sizeof(ATOM_PATCH_RECORD_MODE);
1629 break;
1630 case LCD_RTS_RECORD_TYPE:
1631 record += sizeof(ATOM_LCD_RTS_RECORD);
1632 break;
1633 case LCD_CAP_RECORD_TYPE:
1634 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1635 break;
1636 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1637 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1638 if (fake_edid_record->ucFakeEDIDLength) {
1639 struct edid *edid;
1640 int edid_size =
1641 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
5a3b77d5 1642 edid = kmalloc(edid_size, M_DRM, M_WAITOK);
926deccb
FT
1643 if (edid) {
1644 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1645 fake_edid_record->ucFakeEDIDLength);
1646
1647 if (drm_edid_is_valid(edid)) {
1648 rdev->mode_info.bios_hardcoded_edid = edid;
1649 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1650 } else
1651 drm_free(edid,
5a3b77d5 1652 M_DRM);
926deccb
FT
1653 }
1654 }
1655 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1656 break;
1657 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1658 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1659 lvds->native_mode.width_mm = panel_res_record->usHSize;
1660 lvds->native_mode.height_mm = panel_res_record->usVSize;
1661 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1662 break;
1663 default:
1664 DRM_ERROR("Bad LCD record %d\n", *record);
1665 bad_record = true;
1666 break;
1667 }
1668 if (bad_record)
1669 break;
1670 }
1671 }
1672 }
1673 return lvds;
1674}
1675
1676struct radeon_encoder_primary_dac *
1677radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1678{
1679 struct drm_device *dev = encoder->base.dev;
1680 struct radeon_device *rdev = dev->dev_private;
1681 struct radeon_mode_info *mode_info = &rdev->mode_info;
1682 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1683 uint16_t data_offset;
1684 struct _COMPASSIONATE_DATA *dac_info;
1685 uint8_t frev, crev;
1686 uint8_t bg, dac;
1687 struct radeon_encoder_primary_dac *p_dac = NULL;
1688
1689 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1690 &frev, &crev, &data_offset)) {
1691 dac_info = (struct _COMPASSIONATE_DATA *)
1692 ((char *)mode_info->atom_context->bios + data_offset);
1693
1694 p_dac = kmalloc(sizeof(struct radeon_encoder_primary_dac),
5a3b77d5 1695 M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
1696
1697 if (!p_dac)
1698 return NULL;
1699
1700 bg = dac_info->ucDAC1_BG_Adjustment;
1701 dac = dac_info->ucDAC1_DAC_Adjustment;
1702 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1703
1704 }
1705 return p_dac;
1706}
1707
1708bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1709 struct drm_display_mode *mode)
1710{
1711 struct radeon_mode_info *mode_info = &rdev->mode_info;
1712 ATOM_ANALOG_TV_INFO *tv_info;
1713 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1714 ATOM_DTD_FORMAT *dtd_timings;
1715 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1716 u8 frev, crev;
1717 u16 data_offset, misc;
1718
1719 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1720 &frev, &crev, &data_offset))
1721 return false;
1722
1723 switch (crev) {
1724 case 1:
1725 tv_info = (ATOM_ANALOG_TV_INFO *)((char *)mode_info->atom_context->bios + data_offset);
1726 if (index >= MAX_SUPPORTED_TV_TIMING)
1727 return false;
1728
1729 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1730 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1731 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1732 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1733 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1734
1735 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1736 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1737 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1738 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1739 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1740
1741 mode->flags = 0;
1742 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1743 if (misc & ATOM_VSYNC_POLARITY)
1744 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1745 if (misc & ATOM_HSYNC_POLARITY)
1746 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1747 if (misc & ATOM_COMPOSITESYNC)
1748 mode->flags |= DRM_MODE_FLAG_CSYNC;
1749 if (misc & ATOM_INTERLACE)
1750 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1751 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1752 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1753
1754 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1755
1756 if (index == 1) {
1757 /* PAL timings appear to have wrong values for totals */
1758 mode->crtc_htotal -= 1;
1759 mode->crtc_vtotal -= 1;
1760 }
1761 break;
1762 case 2:
1763 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)((char *)mode_info->atom_context->bios + data_offset);
1764 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1765 return false;
1766
1767 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1768 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1769 le16_to_cpu(dtd_timings->usHBlanking_Time);
1770 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1771 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1772 le16_to_cpu(dtd_timings->usHSyncOffset);
1773 mode->crtc_hsync_end = mode->crtc_hsync_start +
1774 le16_to_cpu(dtd_timings->usHSyncWidth);
1775
1776 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1777 le16_to_cpu(dtd_timings->usVBlanking_Time);
1778 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1779 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1780 le16_to_cpu(dtd_timings->usVSyncOffset);
1781 mode->crtc_vsync_end = mode->crtc_vsync_start +
1782 le16_to_cpu(dtd_timings->usVSyncWidth);
1783
1784 mode->flags = 0;
1785 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1786 if (misc & ATOM_VSYNC_POLARITY)
1787 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1788 if (misc & ATOM_HSYNC_POLARITY)
1789 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1790 if (misc & ATOM_COMPOSITESYNC)
1791 mode->flags |= DRM_MODE_FLAG_CSYNC;
1792 if (misc & ATOM_INTERLACE)
1793 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1794 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1795 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1796
1797 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1798 break;
1799 }
1800 return true;
1801}
1802
1803enum radeon_tv_std
1804radeon_atombios_get_tv_info(struct radeon_device *rdev)
1805{
1806 struct radeon_mode_info *mode_info = &rdev->mode_info;
1807 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1808 uint16_t data_offset;
1809 uint8_t frev, crev;
1810 struct _ATOM_ANALOG_TV_INFO *tv_info;
1811 enum radeon_tv_std tv_std = TV_STD_NTSC;
1812
1813 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1814 &frev, &crev, &data_offset)) {
1815
1816 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1817 ((char *)mode_info->atom_context->bios + data_offset);
1818
1819 switch (tv_info->ucTV_BootUpDefaultStandard) {
1820 case ATOM_TV_NTSC:
1821 tv_std = TV_STD_NTSC;
1822 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1823 break;
1824 case ATOM_TV_NTSCJ:
1825 tv_std = TV_STD_NTSC_J;
1826 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1827 break;
1828 case ATOM_TV_PAL:
1829 tv_std = TV_STD_PAL;
1830 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1831 break;
1832 case ATOM_TV_PALM:
1833 tv_std = TV_STD_PAL_M;
1834 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1835 break;
1836 case ATOM_TV_PALN:
1837 tv_std = TV_STD_PAL_N;
1838 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1839 break;
1840 case ATOM_TV_PALCN:
1841 tv_std = TV_STD_PAL_CN;
1842 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1843 break;
1844 case ATOM_TV_PAL60:
1845 tv_std = TV_STD_PAL_60;
1846 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1847 break;
1848 case ATOM_TV_SECAM:
1849 tv_std = TV_STD_SECAM;
1850 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1851 break;
1852 default:
1853 tv_std = TV_STD_NTSC;
1854 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1855 break;
1856 }
1857 }
1858 return tv_std;
1859}
1860
1861struct radeon_encoder_tv_dac *
1862radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1863{
1864 struct drm_device *dev = encoder->base.dev;
1865 struct radeon_device *rdev = dev->dev_private;
1866 struct radeon_mode_info *mode_info = &rdev->mode_info;
1867 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1868 uint16_t data_offset;
1869 struct _COMPASSIONATE_DATA *dac_info;
1870 uint8_t frev, crev;
1871 uint8_t bg, dac;
1872 struct radeon_encoder_tv_dac *tv_dac = NULL;
1873
1874 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1875 &frev, &crev, &data_offset)) {
1876
1877 dac_info = (struct _COMPASSIONATE_DATA *)
1878 ((char *)mode_info->atom_context->bios + data_offset);
1879
1880 tv_dac = kmalloc(sizeof(struct radeon_encoder_tv_dac),
5a3b77d5 1881 M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
1882
1883 if (!tv_dac)
1884 return NULL;
1885
1886 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1887 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1888 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1889
1890 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1891 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1892 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1893
1894 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1895 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1896 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1897
1898 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1899 }
1900 return tv_dac;
1901}
1902
1903static const char *thermal_controller_names[] = {
1904 "NONE",
1905 "lm63",
1906 "adm1032",
1907 "adm1030",
1908 "max6649",
1909 "lm64",
1910 "f75375",
1911 "asc7xxx",
1912};
1913
1914static const char *pp_lib_thermal_controller_names[] = {
1915 "NONE",
1916 "lm63",
1917 "adm1032",
1918 "adm1030",
1919 "max6649",
1920 "lm64",
1921 "f75375",
1922 "RV6xx",
1923 "RV770",
1924 "adt7473",
1925 "NONE",
1926 "External GPIO",
1927 "Evergreen",
1928 "emc2103",
1929 "Sumo",
1930 "Northern Islands",
1931 "Southern Islands",
1932 "lm96163",
57e252bf 1933 "Sea Islands",
926deccb
FT
1934};
1935
1936union power_info {
1937 struct _ATOM_POWERPLAY_INFO info;
1938 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1939 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1940 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1941 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1942 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1943};
1944
1945union pplib_clock_info {
1946 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1947 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1948 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1949 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1950 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
57e252bf 1951 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
926deccb
FT
1952};
1953
1954union pplib_power_state {
1955 struct _ATOM_PPLIB_STATE v1;
1956 struct _ATOM_PPLIB_STATE_V2 v2;
1957};
1958
1959static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1960 int state_index,
1961 u32 misc, u32 misc2)
1962{
1963 rdev->pm.power_state[state_index].misc = misc;
1964 rdev->pm.power_state[state_index].misc2 = misc2;
1965 /* order matters! */
1966 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1967 rdev->pm.power_state[state_index].type =
1968 POWER_STATE_TYPE_POWERSAVE;
1969 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1970 rdev->pm.power_state[state_index].type =
1971 POWER_STATE_TYPE_BATTERY;
1972 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1973 rdev->pm.power_state[state_index].type =
1974 POWER_STATE_TYPE_BATTERY;
1975 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1976 rdev->pm.power_state[state_index].type =
1977 POWER_STATE_TYPE_BALANCED;
1978 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1979 rdev->pm.power_state[state_index].type =
1980 POWER_STATE_TYPE_PERFORMANCE;
1981 rdev->pm.power_state[state_index].flags &=
1982 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1983 }
1984 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1985 rdev->pm.power_state[state_index].type =
1986 POWER_STATE_TYPE_BALANCED;
1987 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1988 rdev->pm.power_state[state_index].type =
1989 POWER_STATE_TYPE_DEFAULT;
1990 rdev->pm.default_power_state_index = state_index;
1991 rdev->pm.power_state[state_index].default_clock_mode =
1992 &rdev->pm.power_state[state_index].clock_info[0];
1993 } else if (state_index == 0) {
1994 rdev->pm.power_state[state_index].clock_info[0].flags |=
1995 RADEON_PM_MODE_NO_DISPLAY;
1996 }
1997}
1998
1999static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2000{
2001 struct radeon_mode_info *mode_info = &rdev->mode_info;
2002 u32 misc, misc2 = 0;
2003 int num_modes = 0, i;
2004 int state_index = 0;
2005 struct radeon_i2c_bus_rec i2c_bus;
2006 union power_info *power_info;
2007 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2008 u16 data_offset;
2009 u8 frev, crev;
2010
2011 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2012 &frev, &crev, &data_offset))
2013 return state_index;
2014 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2015
2016 /* add the i2c bus for thermal/fan chip */
2017 if ((power_info->info.ucOverdriveThermalController > 0) &&
2018 (power_info->info.ucOverdriveThermalController < DRM_ARRAY_SIZE(thermal_controller_names))) {
2019 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2020 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2021 power_info->info.ucOverdriveControllerAddress >> 1);
2022 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2023 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2024#ifdef DUMBBELL_WIP
2025 if (rdev->pm.i2c_bus) {
2026 struct i2c_board_info info = { };
2027 const char *name = thermal_controller_names[power_info->info.
2028 ucOverdriveThermalController];
2029 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2030 strlcpy(info.type, name, sizeof(info.type));
2031 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2032 }
2033#endif /* DUMBBELL_WIP */
2034 }
2035 num_modes = power_info->info.ucNumOfPowerModeEntries;
2036 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2037 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
f43cf1b1
MN
2038 if (num_modes == 0)
2039 return state_index;
926deccb 2040 rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) * num_modes,
5a3b77d5 2041 M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
2042 if (!rdev->pm.power_state)
2043 return state_index;
2044 /* last mode is usually default, array is low to high */
2045 for (i = 0; i < num_modes; i++) {
2046 rdev->pm.power_state[state_index].clock_info =
2047 kmalloc(sizeof(struct radeon_pm_clock_info) * 1,
5a3b77d5 2048 M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
2049 if (!rdev->pm.power_state[state_index].clock_info)
2050 return state_index;
2051 rdev->pm.power_state[state_index].num_clock_modes = 1;
2052 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2053 switch (frev) {
2054 case 1:
2055 rdev->pm.power_state[state_index].clock_info[0].mclk =
2056 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2057 rdev->pm.power_state[state_index].clock_info[0].sclk =
2058 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2059 /* skip invalid modes */
2060 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2061 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2062 continue;
2063 rdev->pm.power_state[state_index].pcie_lanes =
2064 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2065 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2066 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2067 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2068 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2069 VOLTAGE_GPIO;
2070 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2071 radeon_lookup_gpio(rdev,
2072 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2073 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2074 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2075 true;
2076 else
2077 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2078 false;
2079 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2080 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2081 VOLTAGE_VDDC;
2082 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2083 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2084 }
2085 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2086 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2087 state_index++;
2088 break;
2089 case 2:
2090 rdev->pm.power_state[state_index].clock_info[0].mclk =
2091 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2092 rdev->pm.power_state[state_index].clock_info[0].sclk =
2093 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2094 /* skip invalid modes */
2095 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2096 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2097 continue;
2098 rdev->pm.power_state[state_index].pcie_lanes =
2099 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2100 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2101 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2102 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2103 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2104 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2105 VOLTAGE_GPIO;
2106 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2107 radeon_lookup_gpio(rdev,
2108 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2109 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2110 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2111 true;
2112 else
2113 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2114 false;
2115 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2116 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2117 VOLTAGE_VDDC;
2118 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2119 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2120 }
2121 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2122 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2123 state_index++;
2124 break;
2125 case 3:
2126 rdev->pm.power_state[state_index].clock_info[0].mclk =
2127 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2128 rdev->pm.power_state[state_index].clock_info[0].sclk =
2129 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2130 /* skip invalid modes */
2131 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2132 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2133 continue;
2134 rdev->pm.power_state[state_index].pcie_lanes =
2135 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2136 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2137 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2138 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2139 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2140 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2141 VOLTAGE_GPIO;
2142 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2143 radeon_lookup_gpio(rdev,
2144 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2145 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2146 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2147 true;
2148 else
2149 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2150 false;
2151 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2152 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2153 VOLTAGE_VDDC;
2154 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2155 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2156 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2157 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2158 true;
2159 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2160 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2161 }
2162 }
2163 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2164 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2165 state_index++;
2166 break;
2167 }
2168 }
2169 /* last mode is usually default */
2170 if (rdev->pm.default_power_state_index == -1) {
2171 rdev->pm.power_state[state_index - 1].type =
2172 POWER_STATE_TYPE_DEFAULT;
2173 rdev->pm.default_power_state_index = state_index - 1;
2174 rdev->pm.power_state[state_index - 1].default_clock_mode =
2175 &rdev->pm.power_state[state_index - 1].clock_info[0];
2176 rdev->pm.power_state[state_index].flags &=
2177 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2178 rdev->pm.power_state[state_index].misc = 0;
2179 rdev->pm.power_state[state_index].misc2 = 0;
2180 }
2181 return state_index;
2182}
2183
2184static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2185 ATOM_PPLIB_THERMALCONTROLLER *controller)
2186{
2187 struct radeon_i2c_bus_rec i2c_bus;
2188
2189 /* add the i2c bus for thermal/fan chip */
2190 if (controller->ucType > 0) {
2191 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2192 DRM_INFO("Internal thermal controller %s fan control\n",
2193 (controller->ucFanParameters &
2194 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2195 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2196 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2197 DRM_INFO("Internal thermal controller %s fan control\n",
2198 (controller->ucFanParameters &
2199 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2200 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2201 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2202 DRM_INFO("Internal thermal controller %s fan control\n",
2203 (controller->ucFanParameters &
2204 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2205 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2206 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2207 DRM_INFO("Internal thermal controller %s fan control\n",
2208 (controller->ucFanParameters &
2209 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2210 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2211 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2212 DRM_INFO("Internal thermal controller %s fan control\n",
2213 (controller->ucFanParameters &
2214 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2215 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2216 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2217 DRM_INFO("Internal thermal controller %s fan control\n",
2218 (controller->ucFanParameters &
2219 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2220 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
57e252bf
MN
2221 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2222 DRM_INFO("Internal thermal controller %s fan control\n",
2223 (controller->ucFanParameters &
2224 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2225 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
926deccb
FT
2226 } else if ((controller->ucType ==
2227 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2228 (controller->ucType ==
2229 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2230 (controller->ucType ==
2231 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2232 DRM_INFO("Special thermal controller config\n");
2233 } else if (controller->ucType < DRM_ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2234 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2235 pp_lib_thermal_controller_names[controller->ucType],
2236 controller->ucI2cAddress >> 1,
2237 (controller->ucFanParameters &
2238 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2239 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2240 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2241#ifdef DUMBBELL_WIP
2242 if (rdev->pm.i2c_bus) {
2243 struct i2c_board_info info = { };
2244 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2245 info.addr = controller->ucI2cAddress >> 1;
2246 strlcpy(info.type, name, sizeof(info.type));
2247 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2248 }
2249#endif /* DUMBBELL_WIP */
2250 } else {
2251 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2252 controller->ucType,
2253 controller->ucI2cAddress >> 1,
2254 (controller->ucFanParameters &
2255 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2256 }
2257 }
2258}
2259
57e252bf
MN
2260void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2261 u16 *vddc, u16 *vddci, u16 *mvdd)
926deccb
FT
2262{
2263 struct radeon_mode_info *mode_info = &rdev->mode_info;
2264 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2265 u8 frev, crev;
2266 u16 data_offset;
2267 union firmware_info *firmware_info;
2268
2269 *vddc = 0;
2270 *vddci = 0;
57e252bf 2271 *mvdd = 0;
926deccb
FT
2272
2273 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2274 &frev, &crev, &data_offset)) {
2275 firmware_info =
2276 (union firmware_info *)((char *)mode_info->atom_context->bios +
2277 data_offset);
2278 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
57e252bf 2279 if ((frev == 2) && (crev >= 2)) {
926deccb 2280 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
57e252bf
MN
2281 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2282 }
926deccb
FT
2283 }
2284}
2285
2286static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2287 int state_index, int mode_index,
2288 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2289{
2290 int j;
2291 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2292 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
57e252bf 2293 u16 vddc, vddci, mvdd;
926deccb 2294
57e252bf 2295 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
926deccb
FT
2296
2297 rdev->pm.power_state[state_index].misc = misc;
2298 rdev->pm.power_state[state_index].misc2 = misc2;
2299 rdev->pm.power_state[state_index].pcie_lanes =
2300 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2301 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2302 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2303 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2304 rdev->pm.power_state[state_index].type =
2305 POWER_STATE_TYPE_BATTERY;
2306 break;
2307 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2308 rdev->pm.power_state[state_index].type =
2309 POWER_STATE_TYPE_BALANCED;
2310 break;
2311 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2312 rdev->pm.power_state[state_index].type =
2313 POWER_STATE_TYPE_PERFORMANCE;
2314 break;
2315 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2316 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2317 rdev->pm.power_state[state_index].type =
2318 POWER_STATE_TYPE_PERFORMANCE;
2319 break;
2320 }
2321 rdev->pm.power_state[state_index].flags = 0;
2322 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2323 rdev->pm.power_state[state_index].flags |=
2324 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2325 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2326 rdev->pm.power_state[state_index].type =
2327 POWER_STATE_TYPE_DEFAULT;
2328 rdev->pm.default_power_state_index = state_index;
2329 rdev->pm.power_state[state_index].default_clock_mode =
2330 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
f43cf1b1 2331 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
926deccb
FT
2332 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2333 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2334 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2335 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2336 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2337 } else {
57e252bf
MN
2338 u16 max_vddci = 0;
2339
2340 if (ASIC_IS_DCE4(rdev))
2341 radeon_atom_get_max_voltage(rdev,
2342 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2343 &max_vddci);
2344 /* patch the table values with the default sclk/mclk from firmware info */
926deccb
FT
2345 for (j = 0; j < mode_index; j++) {
2346 rdev->pm.power_state[state_index].clock_info[j].mclk =
2347 rdev->clock.default_mclk;
2348 rdev->pm.power_state[state_index].clock_info[j].sclk =
2349 rdev->clock.default_sclk;
2350 if (vddc)
2351 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2352 vddc;
57e252bf
MN
2353 if (max_vddci)
2354 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2355 max_vddci;
926deccb
FT
2356 }
2357 }
2358 }
2359}
2360
2361static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2362 int state_index, int mode_index,
2363 union pplib_clock_info *clock_info)
2364{
2365 u32 sclk, mclk;
2366 u16 vddc;
2367
2368 if (rdev->flags & RADEON_IS_IGP) {
2369 if (rdev->family >= CHIP_PALM) {
2370 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2371 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2372 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2373 } else {
2374 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2375 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2376 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2377 }
57e252bf
MN
2378 } else if (rdev->family >= CHIP_BONAIRE) {
2379 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2380 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2381 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2382 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2383 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2384 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2385 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2386 VOLTAGE_NONE;
f43cf1b1 2387 } else if (rdev->family >= CHIP_TAHITI) {
926deccb
FT
2388 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2389 sclk |= clock_info->si.ucEngineClockHigh << 16;
2390 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2391 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2392 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2393 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2394 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2395 VOLTAGE_SW;
2396 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2397 le16_to_cpu(clock_info->si.usVDDC);
2398 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2399 le16_to_cpu(clock_info->si.usVDDCI);
f43cf1b1 2400 } else if (rdev->family >= CHIP_CEDAR) {
926deccb
FT
2401 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2402 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2403 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2404 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2405 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2406 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2407 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2408 VOLTAGE_SW;
2409 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2410 le16_to_cpu(clock_info->evergreen.usVDDC);
2411 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2412 le16_to_cpu(clock_info->evergreen.usVDDCI);
2413 } else {
2414 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2415 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2416 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2417 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2418 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2419 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2420 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2421 VOLTAGE_SW;
2422 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2423 le16_to_cpu(clock_info->r600.usVDDC);
2424 }
2425
2426 /* patch up vddc if necessary */
2427 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2428 case ATOM_VIRTUAL_VOLTAGE_ID0:
2429 case ATOM_VIRTUAL_VOLTAGE_ID1:
2430 case ATOM_VIRTUAL_VOLTAGE_ID2:
2431 case ATOM_VIRTUAL_VOLTAGE_ID3:
57e252bf
MN
2432 case ATOM_VIRTUAL_VOLTAGE_ID4:
2433 case ATOM_VIRTUAL_VOLTAGE_ID5:
2434 case ATOM_VIRTUAL_VOLTAGE_ID6:
2435 case ATOM_VIRTUAL_VOLTAGE_ID7:
926deccb
FT
2436 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2437 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2438 &vddc) == 0)
2439 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2440 break;
2441 default:
2442 break;
2443 }
2444
2445 if (rdev->flags & RADEON_IS_IGP) {
2446 /* skip invalid modes */
2447 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2448 return false;
2449 } else {
2450 /* skip invalid modes */
2451 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2452 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2453 return false;
2454 }
2455 return true;
2456}
2457
2458static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2459{
2460 struct radeon_mode_info *mode_info = &rdev->mode_info;
2461 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2462 union pplib_power_state *power_state;
2463 int i, j;
2464 int state_index = 0, mode_index = 0;
2465 union pplib_clock_info *clock_info;
2466 bool valid;
2467 union power_info *power_info;
2468 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2469 u16 data_offset;
2470 u8 frev, crev;
2471
2472 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2473 &frev, &crev, &data_offset))
2474 return state_index;
2475 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2476
2477 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
f43cf1b1
MN
2478 if (power_info->pplib.ucNumStates == 0)
2479 return state_index;
926deccb
FT
2480 rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) *
2481 power_info->pplib.ucNumStates,
5a3b77d5 2482 M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
2483 if (!rdev->pm.power_state)
2484 return state_index;
2485 /* first mode is usually default, followed by low to high */
2486 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2487 mode_index = 0;
2488 power_state = (union pplib_power_state *)
2489 ((char *)mode_info->atom_context->bios + data_offset +
2490 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2491 i * power_info->pplib.ucStateEntrySize);
2492 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2493 ((char *)mode_info->atom_context->bios + data_offset +
2494 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2495 (power_state->v1.ucNonClockStateIndex *
2496 power_info->pplib.ucNonClockSize));
2497 rdev->pm.power_state[i].clock_info = kmalloc(sizeof(struct radeon_pm_clock_info) *
2498 ((power_info->pplib.ucStateEntrySize - 1) ?
2499 (power_info->pplib.ucStateEntrySize - 1) : 1),
5a3b77d5 2500 M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
2501 if (!rdev->pm.power_state[i].clock_info)
2502 return state_index;
2503 if (power_info->pplib.ucStateEntrySize - 1) {
2504 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2505 clock_info = (union pplib_clock_info *)
2506 ((char *)mode_info->atom_context->bios + data_offset +
2507 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2508 (power_state->v1.ucClockStateIndices[j] *
2509 power_info->pplib.ucClockInfoSize));
2510 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2511 state_index, mode_index,
2512 clock_info);
2513 if (valid)
2514 mode_index++;
2515 }
2516 } else {
2517 rdev->pm.power_state[state_index].clock_info[0].mclk =
2518 rdev->clock.default_mclk;
2519 rdev->pm.power_state[state_index].clock_info[0].sclk =
2520 rdev->clock.default_sclk;
2521 mode_index++;
2522 }
2523 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2524 if (mode_index) {
2525 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2526 non_clock_info);
2527 state_index++;
2528 }
2529 }
2530 /* if multiple clock modes, mark the lowest as no display */
2531 for (i = 0; i < state_index; i++) {
2532 if (rdev->pm.power_state[i].num_clock_modes > 1)
2533 rdev->pm.power_state[i].clock_info[0].flags |=
2534 RADEON_PM_MODE_NO_DISPLAY;
2535 }
2536 /* first mode is usually default */
2537 if (rdev->pm.default_power_state_index == -1) {
2538 rdev->pm.power_state[0].type =
2539 POWER_STATE_TYPE_DEFAULT;
2540 rdev->pm.default_power_state_index = 0;
2541 rdev->pm.power_state[0].default_clock_mode =
2542 &rdev->pm.power_state[0].clock_info[0];
2543 }
2544 return state_index;
2545}
2546
2547static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2548{
2549 struct radeon_mode_info *mode_info = &rdev->mode_info;
2550 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2551 union pplib_power_state *power_state;
2552 int i, j, non_clock_array_index, clock_array_index;
2553 int state_index = 0, mode_index = 0;
2554 union pplib_clock_info *clock_info;
2555 struct _StateArray *state_array;
2556 struct _ClockInfoArray *clock_info_array;
2557 struct _NonClockInfoArray *non_clock_info_array;
2558 bool valid;
2559 union power_info *power_info;
2560 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2561 u16 data_offset;
2562 u8 frev, crev;
f43cf1b1 2563 u8 *power_state_offset;
926deccb
FT
2564
2565 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2566 &frev, &crev, &data_offset))
2567 return state_index;
2568 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2569
2570 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2571 state_array = (struct _StateArray *)
2572 ((char *)mode_info->atom_context->bios + data_offset +
2573 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2574 clock_info_array = (struct _ClockInfoArray *)
2575 ((char *)mode_info->atom_context->bios + data_offset +
2576 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2577 non_clock_info_array = (struct _NonClockInfoArray *)
2578 ((char *)mode_info->atom_context->bios + data_offset +
2579 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
f43cf1b1
MN
2580 if (state_array->ucNumEntries == 0)
2581 return state_index;
926deccb
FT
2582 rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) *
2583 state_array->ucNumEntries,
5a3b77d5 2584 M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
2585 if (!rdev->pm.power_state)
2586 return state_index;
f43cf1b1 2587 power_state_offset = (u8 *)state_array->states;
926deccb
FT
2588 for (i = 0; i < state_array->ucNumEntries; i++) {
2589 mode_index = 0;
f43cf1b1
MN
2590 power_state = (union pplib_power_state *)power_state_offset;
2591 non_clock_array_index = power_state->v2.nonClockInfoIndex;
926deccb
FT
2592 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2593 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2594 rdev->pm.power_state[i].clock_info = kmalloc(sizeof(struct radeon_pm_clock_info) *
2595 (power_state->v2.ucNumDPMLevels ?
2596 power_state->v2.ucNumDPMLevels : 1),
5a3b77d5 2597 M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
2598 if (!rdev->pm.power_state[i].clock_info)
2599 return state_index;
2600 if (power_state->v2.ucNumDPMLevels) {
2601 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2602 clock_array_index = power_state->v2.clockInfoIndex[j];
926deccb
FT
2603 clock_info = (union pplib_clock_info *)
2604 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2605 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2606 state_index, mode_index,
2607 clock_info);
2608 if (valid)
2609 mode_index++;
2610 }
2611 } else {
2612 rdev->pm.power_state[state_index].clock_info[0].mclk =
2613 rdev->clock.default_mclk;
2614 rdev->pm.power_state[state_index].clock_info[0].sclk =
2615 rdev->clock.default_sclk;
2616 mode_index++;
2617 }
2618 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2619 if (mode_index) {
2620 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2621 non_clock_info);
2622 state_index++;
2623 }
f43cf1b1 2624 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
926deccb
FT
2625 }
2626 /* if multiple clock modes, mark the lowest as no display */
2627 for (i = 0; i < state_index; i++) {
2628 if (rdev->pm.power_state[i].num_clock_modes > 1)
2629 rdev->pm.power_state[i].clock_info[0].flags |=
2630 RADEON_PM_MODE_NO_DISPLAY;
2631 }
2632 /* first mode is usually default */
2633 if (rdev->pm.default_power_state_index == -1) {
2634 rdev->pm.power_state[0].type =
2635 POWER_STATE_TYPE_DEFAULT;
2636 rdev->pm.default_power_state_index = 0;
2637 rdev->pm.power_state[0].default_clock_mode =
2638 &rdev->pm.power_state[0].clock_info[0];
2639 }
2640 return state_index;
2641}
2642
2643void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2644{
2645 struct radeon_mode_info *mode_info = &rdev->mode_info;
2646 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2647 u16 data_offset;
2648 u8 frev, crev;
2649 int state_index = 0;
2650
2651 rdev->pm.default_power_state_index = -1;
2652
2653 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2654 &frev, &crev, &data_offset)) {
2655 switch (frev) {
2656 case 1:
2657 case 2:
2658 case 3:
2659 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2660 break;
2661 case 4:
2662 case 5:
2663 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2664 break;
2665 case 6:
2666 state_index = radeon_atombios_parse_power_table_6(rdev);
2667 break;
2668 default:
2669 break;
2670 }
f43cf1b1
MN
2671 }
2672
2673 if (state_index == 0) {
926deccb 2674 rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state),
5a3b77d5 2675 M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
2676 if (rdev->pm.power_state) {
2677 rdev->pm.power_state[0].clock_info =
2678 kmalloc(sizeof(struct radeon_pm_clock_info) * 1,
5a3b77d5 2679 M_DRM, M_WAITOK | M_ZERO);
926deccb
FT
2680 if (rdev->pm.power_state[0].clock_info) {
2681 /* add the default mode */
2682 rdev->pm.power_state[state_index].type =
2683 POWER_STATE_TYPE_DEFAULT;
2684 rdev->pm.power_state[state_index].num_clock_modes = 1;
2685 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2686 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2687 rdev->pm.power_state[state_index].default_clock_mode =
2688 &rdev->pm.power_state[state_index].clock_info[0];
2689 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2690 rdev->pm.power_state[state_index].pcie_lanes = 16;
2691 rdev->pm.default_power_state_index = state_index;
2692 rdev->pm.power_state[state_index].flags = 0;
2693 state_index++;
2694 }
2695 }
2696 }
2697
2698 rdev->pm.num_power_states = state_index;
2699
2700 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2701 rdev->pm.current_clock_mode_index = 0;
2702 if (rdev->pm.default_power_state_index >= 0)
2703 rdev->pm.current_vddc =
2704 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2705 else
2706 rdev->pm.current_vddc = 0;
2707}
2708
f43cf1b1
MN
2709union get_clock_dividers {
2710 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2711 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2712 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2713 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2714 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
57e252bf
MN
2715 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2716 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
f43cf1b1
MN
2717};
2718
2719int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2720 u8 clock_type,
2721 u32 clock,
2722 bool strobe_mode,
2723 struct atom_clock_dividers *dividers)
2724{
2725 union get_clock_dividers args;
2726 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2727 u8 frev, crev;
2728
2729 memset(&args, 0, sizeof(args));
2730 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2731
2732 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2733 return -EINVAL;
2734
2735 switch (crev) {
2736 case 1:
2737 /* r4xx, r5xx */
2738 args.v1.ucAction = clock_type;
2739 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2740
2741 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2742
2743 dividers->post_div = args.v1.ucPostDiv;
2744 dividers->fb_div = args.v1.ucFbDiv;
2745 dividers->enable_post_div = true;
2746 break;
2747 case 2:
2748 case 3:
57e252bf
MN
2749 case 5:
2750 /* r6xx, r7xx, evergreen, ni, si */
f43cf1b1
MN
2751 if (rdev->family <= CHIP_RV770) {
2752 args.v2.ucAction = clock_type;
2753 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2754
2755 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2756
2757 dividers->post_div = args.v2.ucPostDiv;
2758 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2759 dividers->ref_div = args.v2.ucAction;
2760 if (rdev->family == CHIP_RV770) {
2761 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2762 true : false;
2763 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2764 } else
2765 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2766 } else {
2767 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2768 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2769
2770 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2771
2772 dividers->post_div = args.v3.ucPostDiv;
2773 dividers->enable_post_div = (args.v3.ucCntlFlag &
2774 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2775 dividers->enable_dithen = (args.v3.ucCntlFlag &
2776 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
57e252bf 2777 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
f43cf1b1
MN
2778 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2779 dividers->ref_div = args.v3.ucRefDiv;
2780 dividers->vco_mode = (args.v3.ucCntlFlag &
2781 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2782 } else {
57e252bf
MN
2783 /* for SI we use ComputeMemoryClockParam for memory plls */
2784 if (rdev->family >= CHIP_TAHITI)
2785 return -EINVAL;
f43cf1b1
MN
2786 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2787 if (strobe_mode)
2788 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2789
2790 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2791
2792 dividers->post_div = args.v5.ucPostDiv;
2793 dividers->enable_post_div = (args.v5.ucCntlFlag &
2794 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2795 dividers->enable_dithen = (args.v5.ucCntlFlag &
2796 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2797 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2798 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2799 dividers->ref_div = args.v5.ucRefDiv;
2800 dividers->vco_mode = (args.v5.ucCntlFlag &
2801 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2802 }
2803 }
2804 break;
2805 case 4:
2806 /* fusion */
2807 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2808
2809 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2810
57e252bf 2811 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
f43cf1b1
MN
2812 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2813 break;
57e252bf
MN
2814 case 6:
2815 /* CI */
2816 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2817 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2818 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2819
2820 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2821
2822 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2823 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2824 dividers->ref_div = args.v6_out.ucPllRefDiv;
2825 dividers->post_div = args.v6_out.ucPllPostDiv;
2826 dividers->flags = args.v6_out.ucPllCntlFlag;
2827 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2828 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2829 break;
2830 default:
2831 return -EINVAL;
2832 }
2833 return 0;
2834}
2835
2836int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2837 u32 clock,
2838 bool strobe_mode,
2839 struct atom_mpll_param *mpll_param)
2840{
2841 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2842 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2843 u8 frev, crev;
2844
2845 memset(&args, 0, sizeof(args));
2846 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2847
2848 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2849 return -EINVAL;
2850
2851 switch (frev) {
2852 case 2:
2853 switch (crev) {
2854 case 1:
2855 /* SI */
2856 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2857 args.ucInputFlag = 0;
2858 if (strobe_mode)
2859 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2860
2861 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2862
2863 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2864 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2865 mpll_param->post_div = args.ucPostDiv;
2866 mpll_param->dll_speed = args.ucDllSpeed;
2867 mpll_param->bwcntl = args.ucBWCntl;
2868 mpll_param->vco_mode =
2869 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK) ? 1 : 0;
2870 mpll_param->yclk_sel =
2871 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2872 mpll_param->qdr =
2873 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2874 mpll_param->half_rate =
2875 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2876 break;
2877 default:
2878 return -EINVAL;
2879 }
2880 break;
f43cf1b1
MN
2881 default:
2882 return -EINVAL;
2883 }
2884 return 0;
2885}
2886
926deccb
FT
2887void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2888{
2889 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2890 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2891
2892 args.ucEnable = enable;
2893
2894 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2895}
2896
2897uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2898{
2899 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2900 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2901
2902 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2903 return le32_to_cpu(args.ulReturnEngineClock);
2904}
2905
2906uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2907{
2908 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2909 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2910
2911 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2912 return le32_to_cpu(args.ulReturnMemoryClock);
2913}
2914
2915void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2916 uint32_t eng_clock)
2917{
2918 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2919 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2920
2921 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2922
2923 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2924}
2925
2926void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2927 uint32_t mem_clock)
2928{
2929 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2930 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2931
2932 if (rdev->flags & RADEON_IS_IGP)
2933 return;
2934
2935 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2936
2937 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2938}
2939
57e252bf
MN
2940void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
2941 u32 eng_clock, u32 mem_clock)
2942{
2943 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2944 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2945 u32 tmp;
2946
2947 memset(&args, 0, sizeof(args));
2948
2949 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
2950 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
2951
2952 args.ulTargetEngineClock = cpu_to_le32(tmp);
2953 if (mem_clock)
2954 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
2955
2956 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2957}
2958
2959void radeon_atom_update_memory_dll(struct radeon_device *rdev,
2960 u32 mem_clock)
2961{
2962 u32 args;
2963 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2964
2965 args = cpu_to_le32(mem_clock); /* 10 khz */
2966
2967 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2968}
2969
2970void radeon_atom_set_ac_timing(struct radeon_device *rdev,
2971 u32 mem_clock)
2972{
2973 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2974 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2975 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
2976
2977 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
2978
2979 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2980}
2981
926deccb
FT
2982union set_voltage {
2983 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2984 struct _SET_VOLTAGE_PARAMETERS v1;
2985 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2986 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
2987};
2988
2989void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2990{
2991 union set_voltage args;
2992 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2993 u8 frev, crev, volt_index = voltage_level;
2994
2995 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2996 return;
2997
2998 /* 0xff01 is a flag rather then an actual voltage */
2999 if (voltage_level == 0xff01)
3000 return;
3001
3002 switch (crev) {
3003 case 1:
3004 args.v1.ucVoltageType = voltage_type;
3005 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3006 args.v1.ucVoltageIndex = volt_index;
3007 break;
3008 case 2:
3009 args.v2.ucVoltageType = voltage_type;
3010 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3011 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3012 break;
3013 case 3:
3014 args.v3.ucVoltageType = voltage_type;
3015 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3016 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3017 break;
3018 default:
3019 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3020 return;
3021 }
3022
3023 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3024}
3025
57e252bf
MN
3026int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3027 u16 voltage_id, u16 *voltage)
926deccb
FT
3028{
3029 union set_voltage args;
3030 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3031 u8 frev, crev;
3032
3033 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3034 return -EINVAL;
3035
3036 switch (crev) {
3037 case 1:
3038 return -EINVAL;
3039 case 2:
3040 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3041 args.v2.ucVoltageMode = 0;
3042 args.v2.usVoltageLevel = 0;
3043
3044 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3045
3046 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3047 break;
3048 case 3:
3049 args.v3.ucVoltageType = voltage_type;
3050 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3051 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3052
3053 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3054
3055 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3056 break;
3057 default:
3058 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3059 return -EINVAL;
3060 }
3061
3062 return 0;
3063}
3064
57e252bf
MN
3065int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3066 u16 *voltage,
3067 u16 leakage_idx)
3068{
3069 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3070}
3071
3072int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3073 u16 voltage_level, u8 voltage_type,
3074 u32 *gpio_value, u32 *gpio_mask)
3075{
3076 union set_voltage args;
3077 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3078 u8 frev, crev;
3079
3080 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3081 return -EINVAL;
3082
3083 switch (crev) {
3084 case 1:
3085 return -EINVAL;
3086 case 2:
3087 args.v2.ucVoltageType = voltage_type;
3088 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3089 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3090
3091 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3092
3093 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3094
3095 args.v2.ucVoltageType = voltage_type;
3096 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3097 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3098
3099 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3100
3101 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3102 break;
3103 default:
3104 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3105 return -EINVAL;
3106 }
3107
3108 return 0;
3109}
3110
3111union voltage_object_info {
3112 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3113 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3114 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3115};
3116
3117union voltage_object {
3118 struct _ATOM_VOLTAGE_OBJECT v1;
3119 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3120 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3121};
3122
3123static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3124 u8 voltage_type)
3125{
3126 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3127 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3128 u8 *start = (u8 *)v1;
3129
3130 while (offset < size) {
3131 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3132 if (vo->ucVoltageType == voltage_type)
3133 return vo;
3134 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3135 vo->asFormula.ucNumOfVoltageEntries;
3136 }
3137 return NULL;
3138}
3139
3140static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3141 u8 voltage_type)
3142{
3143 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3144 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3145 u8 *start = (u8*)v2;
3146
3147 while (offset < size) {
3148 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3149 if (vo->ucVoltageType == voltage_type)
3150 return vo;
3151 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3152 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3153 }
3154 return NULL;
3155}
3156
3157static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3158 u8 voltage_type, u8 voltage_mode)
3159{
3160 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3161 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3162 u8 *start = (u8*)v3;
3163
3164 while (offset < size) {
3165 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3166 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3167 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3168 return vo;
3169 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3170 }
3171 return NULL;
3172}
3173
3174bool
3175radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3176 u8 voltage_type, u8 voltage_mode)
3177{
3178 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3179 u8 frev, crev;
3180 u16 data_offset, size;
3181 union voltage_object_info *voltage_info;
3182 union voltage_object *voltage_object = NULL;
3183
3184 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3185 &frev, &crev, &data_offset)) {
3186 voltage_info = (union voltage_object_info *)
3187 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset);
3188
3189 switch (frev) {
3190 case 1:
3191 case 2:
3192 switch (crev) {
3193 case 1:
3194 voltage_object = (union voltage_object *)
3195 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3196 if (voltage_object &&
3197 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3198 return true;
3199 break;
3200 case 2:
3201 voltage_object = (union voltage_object *)
3202 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3203 if (voltage_object &&
3204 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3205 return true;
3206 break;
3207 default:
3208 DRM_ERROR("unknown voltage object table\n");
3209 return false;
3210 }
3211 break;
3212 case 3:
3213 switch (crev) {
3214 case 1:
3215 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3216 voltage_type, voltage_mode))
3217 return true;
3218 break;
3219 default:
3220 DRM_ERROR("unknown voltage object table\n");
3221 return false;
3222 }
3223 break;
3224 default:
3225 DRM_ERROR("unknown voltage object table\n");
3226 return false;
3227 }
3228
3229 }
3230 return false;
3231}
3232
3233int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3234 u8 voltage_type, u16 *max_voltage)
3235{
3236 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3237 u8 frev, crev;
3238 u16 data_offset, size;
3239 union voltage_object_info *voltage_info;
3240 union voltage_object *voltage_object = NULL;
3241
3242 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3243 &frev, &crev, &data_offset)) {
3244 voltage_info = (union voltage_object_info *)
3245 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset);
3246
3247 switch (crev) {
3248 case 1:
3249 voltage_object = (union voltage_object *)
3250 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3251 if (voltage_object) {
3252 ATOM_VOLTAGE_FORMULA *formula =
3253 &voltage_object->v1.asFormula;
3254 if (formula->ucFlag & 1)
3255 *max_voltage =
3256 le16_to_cpu(formula->usVoltageBaseLevel) +
3257 formula->ucNumOfVoltageEntries / 2 *
3258 le16_to_cpu(formula->usVoltageStep);
3259 else
3260 *max_voltage =
3261 le16_to_cpu(formula->usVoltageBaseLevel) +
3262 (formula->ucNumOfVoltageEntries - 1) *
3263 le16_to_cpu(formula->usVoltageStep);
3264 return 0;
3265 }
3266 break;
3267 case 2:
3268 voltage_object = (union voltage_object *)
3269 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3270 if (voltage_object) {
3271 ATOM_VOLTAGE_FORMULA_V2 *formula =
3272 &voltage_object->v2.asFormula;
3273 if (formula->ucNumOfVoltageEntries) {
3274 *max_voltage =
3275 le16_to_cpu(formula->asVIDAdjustEntries[
3276 formula->ucNumOfVoltageEntries - 1
3277 ].usVoltageValue);
3278 return 0;
3279 }
3280 }
3281 break;
3282 default:
3283 DRM_ERROR("unknown voltage object table\n");
3284 return -EINVAL;
3285 }
3286
3287 }
3288 return -EINVAL;
3289}
3290
3291int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3292 u8 voltage_type, u16 *min_voltage)
3293{
3294 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3295 u8 frev, crev;
3296 u16 data_offset, size;
3297 union voltage_object_info *voltage_info;
3298 union voltage_object *voltage_object = NULL;
3299
3300 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3301 &frev, &crev, &data_offset)) {
3302 voltage_info = (union voltage_object_info *)
3303 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset);
3304
3305 switch (crev) {
3306 case 1:
3307 voltage_object = (union voltage_object *)
3308 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3309 if (voltage_object) {
3310 ATOM_VOLTAGE_FORMULA *formula =
3311 &voltage_object->v1.asFormula;
3312 *min_voltage =
3313 le16_to_cpu(formula->usVoltageBaseLevel);
3314 return 0;
3315 }
3316 break;
3317 case 2:
3318 voltage_object = (union voltage_object *)
3319 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3320 if (voltage_object) {
3321 ATOM_VOLTAGE_FORMULA_V2 *formula =
3322 &voltage_object->v2.asFormula;
3323 if (formula->ucNumOfVoltageEntries) {
3324 *min_voltage =
3325 le16_to_cpu(formula->asVIDAdjustEntries[
3326 0
3327 ].usVoltageValue);
3328 return 0;
3329 }
3330 }
3331 break;
3332 default:
3333 DRM_ERROR("unknown voltage object table\n");
3334 return -EINVAL;
3335 }
3336
3337 }
3338 return -EINVAL;
3339}
3340
3341int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3342 u8 voltage_type, u16 *voltage_step)
3343{
3344 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3345 u8 frev, crev;
3346 u16 data_offset, size;
3347 union voltage_object_info *voltage_info;
3348 union voltage_object *voltage_object = NULL;
3349
3350 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3351 &frev, &crev, &data_offset)) {
3352 voltage_info = (union voltage_object_info *)
3353 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset);
3354
3355 switch (crev) {
3356 case 1:
3357 voltage_object = (union voltage_object *)
3358 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3359 if (voltage_object) {
3360 ATOM_VOLTAGE_FORMULA *formula =
3361 &voltage_object->v1.asFormula;
3362 if (formula->ucFlag & 1)
3363 *voltage_step =
3364 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3365 else
3366 *voltage_step =
3367 le16_to_cpu(formula->usVoltageStep);
3368 return 0;
3369 }
3370 break;
3371 case 2:
3372 return -EINVAL;
3373 default:
3374 DRM_ERROR("unknown voltage object table\n");
3375 return -EINVAL;
3376 }
3377
3378 }
3379 return -EINVAL;
3380}
3381
3382int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3383 u8 voltage_type,
3384 u16 nominal_voltage,
3385 u16 *true_voltage)
3386{
3387 u16 min_voltage, max_voltage, voltage_step;
3388
3389 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3390 return -EINVAL;
3391 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3392 return -EINVAL;
3393 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3394 return -EINVAL;
3395
3396 if (nominal_voltage <= min_voltage)
3397 *true_voltage = min_voltage;
3398 else if (nominal_voltage >= max_voltage)
3399 *true_voltage = max_voltage;
3400 else
3401 *true_voltage = min_voltage +
3402 ((nominal_voltage - min_voltage) / voltage_step) *
3403 voltage_step;
3404
3405 return 0;
3406}
3407
3408int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3409 u8 voltage_type, u8 voltage_mode,
3410 struct atom_voltage_table *voltage_table)
3411{
3412 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3413 u8 frev, crev;
3414 u16 data_offset, size;
3415 int i, ret;
3416 union voltage_object_info *voltage_info;
3417 union voltage_object *voltage_object = NULL;
3418
3419 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3420 &frev, &crev, &data_offset)) {
3421 voltage_info = (union voltage_object_info *)
3422 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset);
3423
3424 switch (frev) {
3425 case 1:
3426 case 2:
3427 switch (crev) {
3428 case 1:
3429 DRM_ERROR("old table version %d, %d\n", frev, crev);
3430 return -EINVAL;
3431 case 2:
3432 voltage_object = (union voltage_object *)
3433 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3434 if (voltage_object) {
3435 ATOM_VOLTAGE_FORMULA_V2 *formula =
3436 &voltage_object->v2.asFormula;
3437 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3438 return -EINVAL;
3439 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3440 voltage_table->entries[i].value =
3441 le16_to_cpu(formula->asVIDAdjustEntries[i].usVoltageValue);
3442 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3443 voltage_table->entries[i].value,
3444 voltage_type,
3445 &voltage_table->entries[i].smio_low,
3446 &voltage_table->mask_low);
3447 if (ret)
3448 return ret;
3449 }
3450 voltage_table->count = formula->ucNumOfVoltageEntries;
3451 return 0;
3452 }
3453 break;
3454 default:
3455 DRM_ERROR("unknown voltage object table\n");
3456 return -EINVAL;
3457 }
3458 break;
3459 case 3:
3460 switch (crev) {
3461 case 1:
3462 voltage_object = (union voltage_object *)
3463 atom_lookup_voltage_object_v3(&voltage_info->v3,
3464 voltage_type, voltage_mode);
3465 if (voltage_object) {
3466 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3467 &voltage_object->v3.asGpioVoltageObj;
3468 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3469 return -EINVAL;
3470 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3471 voltage_table->entries[i].value =
3472 le16_to_cpu(gpio->asVolGpioLut[i].usVoltageValue);
3473 voltage_table->entries[i].smio_low =
3474 le32_to_cpu(gpio->asVolGpioLut[i].ulVoltageId);
3475 }
3476 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3477 voltage_table->count = gpio->ucGpioEntryNum;
3478 voltage_table->phase_delay = gpio->ucPhaseDelay;
3479 return 0;
3480 }
3481 break;
3482 default:
3483 DRM_ERROR("unknown voltage object table\n");
3484 return -EINVAL;
3485 }
3486 break;
3487 default:
3488 DRM_ERROR("unknown voltage object table\n");
3489 return -EINVAL;
3490 }
3491 }
3492 return -EINVAL;
3493}
3494
3495union vram_info {
3496 struct _ATOM_VRAM_INFO_V3 v1_3;
3497 struct _ATOM_VRAM_INFO_V4 v1_4;
3498 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3499};
3500
3501int radeon_atom_get_memory_info(struct radeon_device *rdev,
3502 u8 module_index, struct atom_memory_info *mem_info)
3503{
3504 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3505 u8 frev, crev, i;
3506 u16 data_offset, size;
3507 union vram_info *vram_info;
3508
3509 memset(mem_info, 0, sizeof(struct atom_memory_info));
3510
3511 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3512 &frev, &crev, &data_offset)) {
3513 vram_info = (union vram_info *)
3514 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset);
3515 switch (frev) {
3516 case 1:
3517 switch (crev) {
3518 case 3:
3519 /* r6xx */
3520 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3521 ATOM_VRAM_MODULE_V3 *vram_module =
3522 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3523
3524 for (i = 0; i < module_index; i++) {
3525 if (le16_to_cpu(vram_module->usSize) == 0)
3526 return -EINVAL;
3527 vram_module = (ATOM_VRAM_MODULE_V3 *)
3528 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3529 }
3530 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3531 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3532 } else
3533 return -EINVAL;
3534 break;
3535 case 4:
3536 /* r7xx, evergreen */
3537 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3538 ATOM_VRAM_MODULE_V4 *vram_module =
3539 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3540
3541 for (i = 0; i < module_index; i++) {
3542 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3543 return -EINVAL;
3544 vram_module = (ATOM_VRAM_MODULE_V4 *)
3545 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3546 }
3547 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3548 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3549 } else
3550 return -EINVAL;
3551 break;
3552 default:
3553 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3554 return -EINVAL;
3555 }
3556 break;
3557 case 2:
3558 switch (crev) {
3559 case 1:
3560 /* ni */
3561 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3562 ATOM_VRAM_MODULE_V7 *vram_module =
3563 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3564
3565 for (i = 0; i < module_index; i++) {
3566 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3567 return -EINVAL;
3568 vram_module = (ATOM_VRAM_MODULE_V7 *)
3569 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3570 }
3571 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3572 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3573 } else
3574 return -EINVAL;
3575 break;
3576 default:
3577 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3578 return -EINVAL;
3579 }
3580 break;
3581 default:
3582 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3583 return -EINVAL;
3584 }
3585 return 0;
3586 }
3587 return -EINVAL;
3588}
3589
3590int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3591 bool gddr5, u8 module_index,
3592 struct atom_memory_clock_range_table *mclk_range_table)
3593{
3594 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3595 u8 frev, crev, i;
3596 u16 data_offset, size;
3597 union vram_info *vram_info;
3598 u32 mem_timing_size = gddr5 ?
3599 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3600 u8 *p;
3601
3602 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3603
3604 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3605 &frev, &crev, &data_offset)) {
3606 vram_info = (union vram_info *)
3607 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset);
3608 switch (frev) {
3609 case 1:
3610 switch (crev) {
3611 case 3:
3612 DRM_ERROR("old table version %d, %d\n", frev, crev);
3613 return -EINVAL;
3614 case 4:
3615 /* r7xx, evergreen */
3616 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3617 ATOM_VRAM_MODULE_V4 *vram_module =
3618 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3619
3620 for (i = 0; i < module_index; i++) {
3621 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3622 return -EINVAL;
3623 vram_module = (ATOM_VRAM_MODULE_V4 *)
3624 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3625 }
3626 mclk_range_table->num_entries = (u8)
3627 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3628 mem_timing_size);
3629 p = (u8 *)&vram_module->asMemTiming[0];
3630 for (i = 0; i < mclk_range_table->num_entries; i++) {
3631 ATOM_MEMORY_TIMING_FORMAT *format = (ATOM_MEMORY_TIMING_FORMAT *)p;
3632 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3633 p += mem_timing_size;
3634 }
3635 } else
3636 return -EINVAL;
3637 break;
3638 default:
3639 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3640 return -EINVAL;
3641 }
3642 break;
3643 case 2:
3644 DRM_ERROR("new table version %d, %d\n", frev, crev);
3645 return -EINVAL;
3646 default:
3647 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3648 return -EINVAL;
3649 }
3650 return 0;
3651 }
3652 return -EINVAL;
3653}
3654
3655#define MEM_ID_MASK 0xff000000
3656#define MEM_ID_SHIFT 24
3657#define CLOCK_RANGE_MASK 0x00ffffff
3658#define CLOCK_RANGE_SHIFT 0
3659#define LOW_NIBBLE_MASK 0xf
3660#define DATA_EQU_PREV 0
3661#define DATA_FROM_TABLE 4
3662
3663int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3664 u8 module_index,
3665 struct atom_mc_reg_table *reg_table)
3666{
3667 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3668 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3669 u32 i = 0, j;
3670 u16 data_offset, size;
3671 union vram_info *vram_info;
3672
3673 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3674
3675 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3676 &frev, &crev, &data_offset)) {
3677 vram_info = (union vram_info *)
3678 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset);
3679 switch (frev) {
3680 case 1:
3681 DRM_ERROR("old table version %d, %d\n", frev, crev);
3682 return -EINVAL;
3683 case 2:
3684 switch (crev) {
3685 case 1:
3686 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3687 ATOM_INIT_REG_BLOCK *reg_block =
3688 (ATOM_INIT_REG_BLOCK *)
3689 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
3690 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
3691 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3692 ((u8 *)reg_block + (2 * sizeof(u16)) +
3693 le16_to_cpu(reg_block->usRegIndexTblSize));
3694 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
3695 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
3696 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
3697 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
3698 return -EINVAL;
3699 while (i < num_entries) {
3700 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
3701 break;
3702 reg_table->mc_reg_address[i].s1 =
3703 (u16)(le16_to_cpu(format->usRegIndex));
3704 reg_table->mc_reg_address[i].pre_reg_data =
3705 (u8)(format->ucPreRegDataLength);
3706 i++;
3707 format = (ATOM_INIT_REG_INDEX_FORMAT *)
3708 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
3709 }
3710 reg_table->last = i;
3711 while ((*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) &&
3712 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
3713 t_mem_id = (u8)((*(u32 *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT);
3714 if (module_index == t_mem_id) {
3715 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
3716 (u32)((*(u32 *)reg_data & CLOCK_RANGE_MASK) >> CLOCK_RANGE_SHIFT);
3717 for (i = 0, j = 1; i < reg_table->last; i++) {
3718 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
3719 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3720 (u32)*((u32 *)reg_data + j);
3721 j++;
3722 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
3723 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3724 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
3725 }
3726 }
3727 num_ranges++;
3728 }
3729 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3730 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
3731 }
3732 if (*(u32 *)reg_data != END_OF_REG_DATA_BLOCK)
3733 return -EINVAL;
3734 reg_table->num_entries = num_ranges;
3735 } else
3736 return -EINVAL;
3737 break;
3738 default:
3739 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3740 return -EINVAL;
3741 }
3742 break;
3743 default:
3744 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3745 return -EINVAL;
3746 }
3747 return 0;
3748 }
3749 return -EINVAL;
3750}
3751
926deccb
FT
3752void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
3753{
3754 struct radeon_device *rdev = dev->dev_private;
3755 uint32_t bios_2_scratch, bios_6_scratch;
3756
3757 if (rdev->family >= CHIP_R600) {
3758 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3759 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
3760 } else {
3761 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3762 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3763 }
3764
3765 /* let the bios control the backlight */
3766 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
3767
3768 /* tell the bios not to handle mode switching */
3769 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
3770
3771 if (rdev->family >= CHIP_R600) {
3772 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3773 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3774 } else {
3775 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3776 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3777 }
3778
3779}
3780
3781void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
3782{
3783 uint32_t scratch_reg;
3784 int i;
3785
3786 if (rdev->family >= CHIP_R600)
3787 scratch_reg = R600_BIOS_0_SCRATCH;
3788 else
3789 scratch_reg = RADEON_BIOS_0_SCRATCH;
3790
3791 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
3792 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
3793}
3794
3795void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
3796{