drm/radeon: Sync to Linux 3.11
[dragonfly.git] / sys / dev / drm / radeon / radeon_cursor.c
CommitLineData
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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 *
26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_cursor.c 254885 2013-08-25 19:37:15Z dumbbell $
27 */
28
29#include <drm/drmP.h>
30#include <uapi_drm/radeon_drm.h>
31#include "radeon.h"
32
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33static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
34{
35 struct radeon_device *rdev = crtc->dev->dev_private;
36 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
37 uint32_t cur_lock;
38
39 if (ASIC_IS_DCE4(rdev)) {
40 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
41 if (lock)
42 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
43 else
44 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
45 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
46 } else if (ASIC_IS_AVIVO(rdev)) {
47 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
48 if (lock)
49 cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
50 else
51 cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
52 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
53 } else {
54 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
55 if (lock)
56 cur_lock |= RADEON_CUR_LOCK;
57 else
58 cur_lock &= ~RADEON_CUR_LOCK;
59 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
60 }
61}
62
63static void radeon_hide_cursor(struct drm_crtc *crtc)
64{
65 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
66 struct radeon_device *rdev = crtc->dev->dev_private;
67
68 if (ASIC_IS_DCE4(rdev)) {
69 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
70 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
71 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
72 } else if (ASIC_IS_AVIVO(rdev)) {
73 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
74 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
75 } else {
76 u32 reg;
77 switch (radeon_crtc->crtc_id) {
78 case 0:
79 reg = RADEON_CRTC_GEN_CNTL;
80 break;
81 case 1:
82 reg = RADEON_CRTC2_GEN_CNTL;
83 break;
84 default:
85 return;
86 }
87 WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);
88 }
89}
90
91static void radeon_show_cursor(struct drm_crtc *crtc)
92{
93 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
94 struct radeon_device *rdev = crtc->dev->dev_private;
95
96 if (ASIC_IS_DCE4(rdev)) {
97 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
98 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
99 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
100 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
101 } else if (ASIC_IS_AVIVO(rdev)) {
102 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
103 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
104 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
105 } else {
106 switch (radeon_crtc->crtc_id) {
107 case 0:
108 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
109 break;
110 case 1:
111 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
112 break;
113 default:
114 return;
115 }
116
117 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
118 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
119 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
120 }
121}
122
123static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
124 uint64_t gpu_addr)
125{
126 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
127 struct radeon_device *rdev = crtc->dev->dev_private;
128
129 if (ASIC_IS_DCE4(rdev)) {
130 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
131 upper_32_bits(gpu_addr));
132 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
133 gpu_addr & 0xffffffff);
134 } else if (ASIC_IS_AVIVO(rdev)) {
135 if (rdev->family >= CHIP_RV770) {
136 if (radeon_crtc->crtc_id)
137 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
138 else
139 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
140 }
141 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
142 gpu_addr & 0xffffffff);
143 } else {
144 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
145 /* offset is from DISP(2)_BASE_ADDRESS */
146 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
147 }
148}
149
150int radeon_crtc_cursor_set(struct drm_crtc *crtc,
151 struct drm_file *file_priv,
152 uint32_t handle,
153 uint32_t width,
154 uint32_t height)
155{
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
157 struct radeon_device *rdev = crtc->dev->dev_private;
158 struct drm_gem_object *obj;
159 struct radeon_bo *robj;
160 uint64_t gpu_addr;
161 int ret;
162
163 if (!handle) {
164 /* turn off cursor */
165 radeon_hide_cursor(crtc);
166 obj = NULL;
167 goto unpin;
168 }
169
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170 if ((width > radeon_crtc->max_cursor_width) ||
171 (height > radeon_crtc->max_cursor_height)) {
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172 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
173 return -EINVAL;
174 }
175
176 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
177 if (!obj) {
178 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
179 return -ENOENT;
180 }
181
182 robj = gem_to_radeon_bo(obj);
183 ret = radeon_bo_reserve(robj, false);
184 if (unlikely(ret != 0))
185 goto fail;
186 /* Only 27 bit offset for legacy cursor */
187 ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
188 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
189 &gpu_addr);
190 radeon_bo_unreserve(robj);
191 if (ret)
192 goto fail;
193
194 radeon_crtc->cursor_width = width;
195 radeon_crtc->cursor_height = height;
196
197 radeon_lock_cursor(crtc, true);
198 radeon_set_cursor(crtc, obj, gpu_addr);
199 radeon_show_cursor(crtc);
200 radeon_lock_cursor(crtc, false);
201
202unpin:
203 if (radeon_crtc->cursor_bo) {
204 robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
205 ret = radeon_bo_reserve(robj, false);
206 if (likely(ret == 0)) {
207 radeon_bo_unpin(robj);
208 radeon_bo_unreserve(robj);
209 }
210 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
211 }
212
213 radeon_crtc->cursor_bo = obj;
214 return 0;
215fail:
216 drm_gem_object_unreference_unlocked(obj);
217
218 return ret;
219}
220
221int radeon_crtc_cursor_move(struct drm_crtc *crtc,
222 int x, int y)
223{
224 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
225 struct radeon_device *rdev = crtc->dev->dev_private;
226 int xorigin = 0, yorigin = 0;
227 int w = radeon_crtc->cursor_width;
228
229 if (ASIC_IS_AVIVO(rdev)) {
230 /* avivo cursor are offset into the total surface */
231 x += crtc->x;
232 y += crtc->y;
233 }
234 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
235
236 if (x < 0) {
57e252bf 237 xorigin = min(-x, radeon_crtc->max_cursor_width - 1);
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238 x = 0;
239 }
240 if (y < 0) {
57e252bf 241 yorigin = min(-y, radeon_crtc->max_cursor_height - 1);
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242 y = 0;
243 }
244
245 /* fixed on DCE6 and newer */
246 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
247 int i = 0;
248 struct drm_crtc *crtc_p;
249
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250 /*
251 * avivo cursor image can't end on 128 pixel boundary or
926deccb 252 * go past the end of the frame if both crtcs are enabled
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253 *
254 * NOTE: It is safe to access crtc->enabled of other crtcs
255 * without holding either the mode_config lock or the other
256 * crtc's lock as long as write access to this flag _always_
257 * grabs all locks.
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258 */
259 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
260 if (crtc_p->enabled)
261 i++;
262 }
263 if (i > 1) {
264 int cursor_end, frame_end;
265
266 cursor_end = x - xorigin + w;
267 frame_end = crtc->x + crtc->mode.crtc_hdisplay;
268 if (cursor_end >= frame_end) {
269 w = w - (cursor_end - frame_end);
270 if (!(frame_end & 0x7f))
271 w--;
272 } else {
273 if (!(cursor_end & 0x7f))
274 w--;
275 }
276 if (w <= 0) {
277 w = 1;
278 cursor_end = x - xorigin + w;
279 if (!(cursor_end & 0x7f)) {
280 x--;
281 if (x < 0) {
282 DRM_ERROR("%s: x(%d) < 0", __func__, x);
283 }
284 }
285 }
286 }
287 }
288
289 radeon_lock_cursor(crtc, true);
290 if (ASIC_IS_DCE4(rdev)) {
291 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
292 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
293 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
294 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
295 } else if (ASIC_IS_AVIVO(rdev)) {
296 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
297 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
298 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
299 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
300 } else {
301 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
302 y *= 2;
303
304 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
305 (RADEON_CUR_LOCK
306 | (xorigin << 16)
307 | yorigin));
308 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
309 (RADEON_CUR_LOCK
310 | (x << 16)
311 | y));
312 /* offset is from DISP(2)_BASE_ADDRESS */
313 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
314 (yorigin * 256)));
315 }
316 radeon_lock_cursor(crtc, false);
317
318 return 0;
319}