drm/radeon: Sync to Linux 3.11
[dragonfly.git] / sys / dev / drm / radeon / radeon_fb.c
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1/*
2 * Copyright © 2007 David Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * David Airlie
25 *
26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_fb.c 254885 2013-08-25 19:37:15Z dumbbell $
27 */
28
29#include <drm/drmP.h>
30#include <drm/drm_crtc.h>
31#include <drm/drm_crtc_helper.h>
32#include <uapi_drm/radeon_drm.h>
33#include "radeon.h"
34
35#include <drm/drm_fb_helper.h>
36
37/* object hierarchy -
38 this contains a helper + a radeon fb
39 the helper contains a pointer to radeon framebuffer baseclass.
40*/
41struct radeon_fbdev {
42 struct drm_fb_helper helper;
43 struct radeon_framebuffer rfb;
44 struct list_head fbdev_list;
45 struct radeon_device *rdev;
46};
47
48#ifdef DUMBBELL_WIP
49static struct fb_ops radeonfb_ops = {
50 .owner = THIS_MODULE,
51 .fb_check_var = drm_fb_helper_check_var,
52 .fb_set_par = drm_fb_helper_set_par,
53 .fb_fillrect = cfb_fillrect,
54 .fb_copyarea = cfb_copyarea,
55 .fb_imageblit = cfb_imageblit,
56 .fb_pan_display = drm_fb_helper_pan_display,
57 .fb_blank = drm_fb_helper_blank,
58 .fb_setcmap = drm_fb_helper_setcmap,
59 .fb_debug_enter = drm_fb_helper_debug_enter,
60 .fb_debug_leave = drm_fb_helper_debug_leave,
61};
62#endif /* DUMBBELL_WIP */
63
64
65int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
66{
67 int aligned = width;
68 int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
69 int pitch_mask = 0;
70
71 switch (bpp / 8) {
72 case 1:
73 pitch_mask = align_large ? 255 : 127;
74 break;
75 case 2:
76 pitch_mask = align_large ? 127 : 31;
77 break;
78 case 3:
79 case 4:
80 pitch_mask = align_large ? 63 : 15;
81 break;
82 }
83
84 aligned += pitch_mask;
85 aligned &= ~pitch_mask;
86 return aligned;
87}
88
89static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
90{
91 struct radeon_bo *rbo = gem_to_radeon_bo(gobj);
92 int ret;
93
94 ret = radeon_bo_reserve(rbo, false);
95 if (likely(ret == 0)) {
96 radeon_bo_kunmap(rbo);
97 radeon_bo_unpin(rbo);
98 radeon_bo_unreserve(rbo);
99 }
100 drm_gem_object_unreference_unlocked(gobj);
101}
102
103static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
104 struct drm_mode_fb_cmd2 *mode_cmd,
105 struct drm_gem_object **gobj_p)
106{
107 struct radeon_device *rdev = rfbdev->rdev;
108 struct drm_gem_object *gobj = NULL;
109 struct radeon_bo *rbo = NULL;
110 bool fb_tiled = false; /* useful for testing */
111 u32 tiling_flags = 0;
112 int ret;
113 int aligned_size, size;
114 int height = mode_cmd->height;
115 u32 bpp, depth;
116
117 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
118
119 /* need to align pitch with crtc limits */
120 mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp,
121 fb_tiled) * ((bpp + 1) / 8);
122
123 if (rdev->family >= CHIP_R600)
124 height = roundup2(mode_cmd->height, 8);
125 size = mode_cmd->pitches[0] * height;
126 aligned_size = roundup2(size, PAGE_SIZE);
127 ret = radeon_gem_object_create(rdev, aligned_size, 0,
128 RADEON_GEM_DOMAIN_VRAM,
129 false, true,
130 &gobj);
131 if (ret) {
132 DRM_ERROR("failed to allocate framebuffer (%d)\n",
133 aligned_size);
134 return -ENOMEM;
135 }
136 rbo = gem_to_radeon_bo(gobj);
137
138 if (fb_tiled)
139 tiling_flags = RADEON_TILING_MACRO;
140
141#ifdef __BIG_ENDIAN
142 switch (bpp) {
143 case 32:
144 tiling_flags |= RADEON_TILING_SWAP_32BIT;
145 break;
146 case 16:
147 tiling_flags |= RADEON_TILING_SWAP_16BIT;
148 default:
149 break;
150 }
151#endif
152
153 if (tiling_flags) {
154 ret = radeon_bo_set_tiling_flags(rbo,
155 tiling_flags | RADEON_TILING_SURFACE,
156 mode_cmd->pitches[0]);
157 if (ret)
158 dev_err(rdev->dev, "FB failed to set tiling flags\n");
159 }
160
161
162 ret = radeon_bo_reserve(rbo, false);
163 if (unlikely(ret != 0))
164 goto out_unref;
165 /* Only 27 bit offset for legacy CRTC */
166 ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
167 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
168 NULL);
169 if (ret) {
170 radeon_bo_unreserve(rbo);
171 goto out_unref;
172 }
173 if (fb_tiled)
174 radeon_bo_check_tiling(rbo, 0, 0);
175 ret = radeon_bo_kmap(rbo, NULL);
176 radeon_bo_unreserve(rbo);
177 if (ret) {
178 goto out_unref;
179 }
180
181 *gobj_p = gobj;
182 return 0;
183out_unref:
184 radeonfb_destroy_pinned_object(gobj);
185 *gobj_p = NULL;
186 return ret;
187}
188
b403bed8 189static int radeonfb_create(struct drm_fb_helper *helper,
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190 struct drm_fb_helper_surface_size *sizes)
191{
b403bed8 192 struct radeon_fbdev *rfbdev = (struct radeon_fbdev *)helper;
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193 struct radeon_device *rdev = rfbdev->rdev;
194#ifdef DUMBBELL_WIP
195 struct fb_info *info;
196#endif /* DUMBBELL_WIP */
197 struct drm_framebuffer *fb = NULL;
198 struct drm_mode_fb_cmd2 mode_cmd;
199 struct drm_gem_object *gobj = NULL;
200 struct radeon_bo *rbo = NULL;
201#ifdef DUMBBELL_WIP
202 device_t device = rdev->dev;
203#endif /* DUMBBELL_WIP */
204 int ret;
205#ifdef DUMBBELL_WIP
206 unsigned long tmp;
207#endif /* DUMBBELL_WIP */
208
209 mode_cmd.width = sizes->surface_width;
210 mode_cmd.height = sizes->surface_height;
211
212 /* avivo can't scanout real 24bpp */
213 if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
214 sizes->surface_bpp = 32;
215
216 mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
217 sizes->surface_depth);
218
219 ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
220 if (ret) {
221 DRM_ERROR("failed to create fbcon object %d\n", ret);
222 return ret;
223 }
224
225 rbo = gem_to_radeon_bo(gobj);
226
227#ifdef DUMBBELL_WIP
228 /* okay we have an object now allocate the framebuffer */
229 info = framebuffer_alloc(0, device);
230 if (info == NULL) {
231 ret = -ENOMEM;
232 goto out_unref;
233 }
234
235 info->par = rfbdev;
236#endif /* DUMBBELL_WIP */
237
238 ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
239 if (ret) {
57e252bf 240 DRM_ERROR("failed to initialize framebuffer %d\n", ret);
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241 goto out_unref;
242 }
243
244 fb = &rfbdev->rfb.base;
245
246 /* setup helper */
247 rfbdev->helper.fb = fb;
248#ifdef DUMBBELL_WIP
249 rfbdev->helper.fbdev = info;
250
251 memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
252
253 strcpy(info->fix.id, "radeondrmfb");
254
255 drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
256
257 info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
258 info->fbops = &radeonfb_ops;
259
260 tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
261 info->fix.smem_start = rdev->mc.aper_base + tmp;
262 info->fix.smem_len = radeon_bo_size(rbo);
263 info->screen_base = rbo->kptr;
264 info->screen_size = radeon_bo_size(rbo);
265
266 drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
267
268 /* setup aperture base/size for vesafb takeover */
269 info->apertures = alloc_apertures(1);
270 if (!info->apertures) {
271 ret = -ENOMEM;
272 goto out_unref;
273 }
274 info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
275 info->apertures->ranges[0].size = rdev->mc.aper_size;
276
277 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
278
279 if (info->screen_base == NULL) {
280 ret = -ENOSPC;
281 goto out_unref;
282 }
283
284 ret = fb_alloc_cmap(&info->cmap, 256, 0);
285 if (ret) {
286 ret = -ENOMEM;
287 goto out_unref;
288 }
289
290 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
291 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
292 DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
293 DRM_INFO("fb depth is %d\n", fb->depth);
294 DRM_INFO(" pitch is %d\n", fb->pitches[0]);
295
296 vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
297#endif /* DUMBBELL_WIP */
298 return 0;
299
300out_unref:
301 if (rbo) {
302
303 }
304 if (fb && ret) {
305 drm_gem_object_unreference(gobj);
b403bed8 306 drm_framebuffer_unregister_private(fb);
926deccb 307 drm_framebuffer_cleanup(fb);
5a3b77d5 308 drm_free(fb, M_DRM); /* XXX malloc'd in radeon_user_framebuffer_create? */
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309 }
310 return ret;
311}
312
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313void radeon_fb_output_poll_changed(struct radeon_device *rdev)
314{
315 drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
316}
317
318static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev)
319{
320#ifdef DUMBBELL_WIP
321 struct fb_info *info;
322#endif /* DUMBBELL_WIP */
323 struct radeon_framebuffer *rfb = &rfbdev->rfb;
324
325#ifdef DUMBBELL_WIP
326 if (rfbdev->helper.fbdev) {
327 info = rfbdev->helper.fbdev;
328
329 unregister_framebuffer(info);
330 if (info->cmap.len)
331 fb_dealloc_cmap(&info->cmap);
332 framebuffer_release(info);
333 }
334#endif /* DUMBBELL_WIP */
335
336 if (rfb->obj) {
337 DRM_UNLOCK(dev); /* Work around lock recursion. dumbbell@ */
338 radeonfb_destroy_pinned_object(rfb->obj);
339 DRM_LOCK(dev);
340 rfb->obj = NULL;
341 }
342 drm_fb_helper_fini(&rfbdev->helper);
b403bed8 343 drm_framebuffer_unregister_private(&rfb->base);
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344 drm_framebuffer_cleanup(&rfb->base);
345
346 return 0;
347}
348
349static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
350 .gamma_set = radeon_crtc_fb_gamma_set,
351 .gamma_get = radeon_crtc_fb_gamma_get,
b403bed8 352 .fb_probe = radeonfb_create,
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353};
354
355int radeon_fbdev_init(struct radeon_device *rdev)
356{
357 struct radeon_fbdev *rfbdev;
358 int bpp_sel = 32;
359 int ret;
360
361 /* select 8 bpp console on RN50 or 16MB cards */
362 if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
363 bpp_sel = 8;
364
5a3b77d5 365 rfbdev = kmalloc(sizeof(struct radeon_fbdev), M_DRM,
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366 M_WAITOK | M_ZERO);
367 if (!rfbdev)
368 return -ENOMEM;
369
370 rfbdev->rdev = rdev;
371 rdev->mode_info.rfbdev = rfbdev;
372 rfbdev->helper.funcs = &radeon_fb_helper_funcs;
373
374 ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
375 rdev->num_crtc,
376 RADEONFB_CONN_LIMIT);
377 if (ret) {
5a3b77d5 378 drm_free(rfbdev, M_DRM);
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379 return ret;
380 }
381
382 drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
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383
384 /* disable all the possible outputs/crtcs before entering KMS mode */
385 drm_helper_disable_unused_functions(rdev->ddev);
386
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387 drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
388 return 0;
389}
390
391void radeon_fbdev_fini(struct radeon_device *rdev)
392{
393 if (!rdev->mode_info.rfbdev)
394 return;
395
396 radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
5a3b77d5 397 drm_free(rdev->mode_info.rfbdev, M_DRM);
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398 rdev->mode_info.rfbdev = NULL;
399}
400
401void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
402{
403#ifdef DUMBBELL_WIP
404 fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
405#endif /* DUMBBELL_WIP */
406}
407
408int radeon_fbdev_total_size(struct radeon_device *rdev)
409{
410 struct radeon_bo *robj;
411 int size = 0;
412
413 robj = gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj);
414 size += radeon_bo_size(robj);
415 return size;
416}
417
418bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
419{
420 if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj))
421 return true;
422 return false;
423}