drm/radeon: Sync to Linux 3.11
[dragonfly.git] / sys / dev / drm / radeon / si.c
CommitLineData
926deccb
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1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 *
24 * $FreeBSD: head/sys/dev/drm2/radeon/si.c 254885 2013-08-25 19:37:15Z dumbbell $
25 */
26
27#include <drm/drmP.h>
57e252bf 28#include <linux/firmware.h>
926deccb
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29#include "radeon.h"
30#include "radeon_asic.h"
31#include <uapi_drm/radeon_drm.h>
32#include "sid.h"
33#include "atom.h"
34#include "si_blit_shaders.h"
57e252bf
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35#include "clearstate_si.h"
36#include "radeon_ucode.h"
37
38
39#define PCI_EXP_LNKCTL PCIER_LINKCTRL /* 16 */
40#define PCI_EXP_LNKCTL2 48
41#define PCI_EXP_LNKCTL_HAWD PCIEM_LNKCTL_HAWD /* 0x0200 */
42#define PCI_EXP_DEVSTA PCIER_DEVSTS /* 10 */
43#define PCI_EXP_DEVSTA_TRPND 0x0020
44#define PCI_EXP_LNKCAP_CLKPM 0x00040000
45
46MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
47MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
48MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
49MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
50MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
51MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
52MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
53MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
54MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
55MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
56MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
57MODULE_FIRMWARE("radeon/VERDE_me.bin");
58MODULE_FIRMWARE("radeon/VERDE_ce.bin");
59MODULE_FIRMWARE("radeon/VERDE_mc.bin");
60MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
61MODULE_FIRMWARE("radeon/VERDE_smc.bin");
62MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
63MODULE_FIRMWARE("radeon/OLAND_me.bin");
64MODULE_FIRMWARE("radeon/OLAND_ce.bin");
65MODULE_FIRMWARE("radeon/OLAND_mc.bin");
66MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
67MODULE_FIRMWARE("radeon/OLAND_smc.bin");
68MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
69MODULE_FIRMWARE("radeon/HAINAN_me.bin");
70MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
71MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
72MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
73MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
74
75static void si_pcie_gen3_enable(struct radeon_device *rdev);
76static void si_program_aspm(struct radeon_device *rdev);
b403bed8 77extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
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78
79static const u32 verde_rlc_save_restore_register_list[] =
80{
81 (0x8000 << 16) | (0x98f4 >> 2),
82 0x00000000,
83 (0x8040 << 16) | (0x98f4 >> 2),
84 0x00000000,
85 (0x8000 << 16) | (0xe80 >> 2),
86 0x00000000,
87 (0x8040 << 16) | (0xe80 >> 2),
88 0x00000000,
89 (0x8000 << 16) | (0x89bc >> 2),
90 0x00000000,
91 (0x8040 << 16) | (0x89bc >> 2),
92 0x00000000,
93 (0x8000 << 16) | (0x8c1c >> 2),
94 0x00000000,
95 (0x8040 << 16) | (0x8c1c >> 2),
96 0x00000000,
97 (0x9c00 << 16) | (0x98f0 >> 2),
98 0x00000000,
99 (0x9c00 << 16) | (0xe7c >> 2),
100 0x00000000,
101 (0x8000 << 16) | (0x9148 >> 2),
102 0x00000000,
103 (0x8040 << 16) | (0x9148 >> 2),
104 0x00000000,
105 (0x9c00 << 16) | (0x9150 >> 2),
106 0x00000000,
107 (0x9c00 << 16) | (0x897c >> 2),
108 0x00000000,
109 (0x9c00 << 16) | (0x8d8c >> 2),
110 0x00000000,
111 (0x9c00 << 16) | (0xac54 >> 2),
112 0X00000000,
113 0x3,
114 (0x9c00 << 16) | (0x98f8 >> 2),
115 0x00000000,
116 (0x9c00 << 16) | (0x9910 >> 2),
117 0x00000000,
118 (0x9c00 << 16) | (0x9914 >> 2),
119 0x00000000,
120 (0x9c00 << 16) | (0x9918 >> 2),
121 0x00000000,
122 (0x9c00 << 16) | (0x991c >> 2),
123 0x00000000,
124 (0x9c00 << 16) | (0x9920 >> 2),
125 0x00000000,
126 (0x9c00 << 16) | (0x9924 >> 2),
127 0x00000000,
128 (0x9c00 << 16) | (0x9928 >> 2),
129 0x00000000,
130 (0x9c00 << 16) | (0x992c >> 2),
131 0x00000000,
132 (0x9c00 << 16) | (0x9930 >> 2),
133 0x00000000,
134 (0x9c00 << 16) | (0x9934 >> 2),
135 0x00000000,
136 (0x9c00 << 16) | (0x9938 >> 2),
137 0x00000000,
138 (0x9c00 << 16) | (0x993c >> 2),
139 0x00000000,
140 (0x9c00 << 16) | (0x9940 >> 2),
141 0x00000000,
142 (0x9c00 << 16) | (0x9944 >> 2),
143 0x00000000,
144 (0x9c00 << 16) | (0x9948 >> 2),
145 0x00000000,
146 (0x9c00 << 16) | (0x994c >> 2),
147 0x00000000,
148 (0x9c00 << 16) | (0x9950 >> 2),
149 0x00000000,
150 (0x9c00 << 16) | (0x9954 >> 2),
151 0x00000000,
152 (0x9c00 << 16) | (0x9958 >> 2),
153 0x00000000,
154 (0x9c00 << 16) | (0x995c >> 2),
155 0x00000000,
156 (0x9c00 << 16) | (0x9960 >> 2),
157 0x00000000,
158 (0x9c00 << 16) | (0x9964 >> 2),
159 0x00000000,
160 (0x9c00 << 16) | (0x9968 >> 2),
161 0x00000000,
162 (0x9c00 << 16) | (0x996c >> 2),
163 0x00000000,
164 (0x9c00 << 16) | (0x9970 >> 2),
165 0x00000000,
166 (0x9c00 << 16) | (0x9974 >> 2),
167 0x00000000,
168 (0x9c00 << 16) | (0x9978 >> 2),
169 0x00000000,
170 (0x9c00 << 16) | (0x997c >> 2),
171 0x00000000,
172 (0x9c00 << 16) | (0x9980 >> 2),
173 0x00000000,
174 (0x9c00 << 16) | (0x9984 >> 2),
175 0x00000000,
176 (0x9c00 << 16) | (0x9988 >> 2),
177 0x00000000,
178 (0x9c00 << 16) | (0x998c >> 2),
179 0x00000000,
180 (0x9c00 << 16) | (0x8c00 >> 2),
181 0x00000000,
182 (0x9c00 << 16) | (0x8c14 >> 2),
183 0x00000000,
184 (0x9c00 << 16) | (0x8c04 >> 2),
185 0x00000000,
186 (0x9c00 << 16) | (0x8c08 >> 2),
187 0x00000000,
188 (0x8000 << 16) | (0x9b7c >> 2),
189 0x00000000,
190 (0x8040 << 16) | (0x9b7c >> 2),
191 0x00000000,
192 (0x8000 << 16) | (0xe84 >> 2),
193 0x00000000,
194 (0x8040 << 16) | (0xe84 >> 2),
195 0x00000000,
196 (0x8000 << 16) | (0x89c0 >> 2),
197 0x00000000,
198 (0x8040 << 16) | (0x89c0 >> 2),
199 0x00000000,
200 (0x8000 << 16) | (0x914c >> 2),
201 0x00000000,
202 (0x8040 << 16) | (0x914c >> 2),
203 0x00000000,
204 (0x8000 << 16) | (0x8c20 >> 2),
205 0x00000000,
206 (0x8040 << 16) | (0x8c20 >> 2),
207 0x00000000,
208 (0x8000 << 16) | (0x9354 >> 2),
209 0x00000000,
210 (0x8040 << 16) | (0x9354 >> 2),
211 0x00000000,
212 (0x9c00 << 16) | (0x9060 >> 2),
213 0x00000000,
214 (0x9c00 << 16) | (0x9364 >> 2),
215 0x00000000,
216 (0x9c00 << 16) | (0x9100 >> 2),
217 0x00000000,
218 (0x9c00 << 16) | (0x913c >> 2),
219 0x00000000,
220 (0x8000 << 16) | (0x90e0 >> 2),
221 0x00000000,
222 (0x8000 << 16) | (0x90e4 >> 2),
223 0x00000000,
224 (0x8000 << 16) | (0x90e8 >> 2),
225 0x00000000,
226 (0x8040 << 16) | (0x90e0 >> 2),
227 0x00000000,
228 (0x8040 << 16) | (0x90e4 >> 2),
229 0x00000000,
230 (0x8040 << 16) | (0x90e8 >> 2),
231 0x00000000,
232 (0x9c00 << 16) | (0x8bcc >> 2),
233 0x00000000,
234 (0x9c00 << 16) | (0x8b24 >> 2),
235 0x00000000,
236 (0x9c00 << 16) | (0x88c4 >> 2),
237 0x00000000,
238 (0x9c00 << 16) | (0x8e50 >> 2),
239 0x00000000,
240 (0x9c00 << 16) | (0x8c0c >> 2),
241 0x00000000,
242 (0x9c00 << 16) | (0x8e58 >> 2),
243 0x00000000,
244 (0x9c00 << 16) | (0x8e5c >> 2),
245 0x00000000,
246 (0x9c00 << 16) | (0x9508 >> 2),
247 0x00000000,
248 (0x9c00 << 16) | (0x950c >> 2),
249 0x00000000,
250 (0x9c00 << 16) | (0x9494 >> 2),
251 0x00000000,
252 (0x9c00 << 16) | (0xac0c >> 2),
253 0x00000000,
254 (0x9c00 << 16) | (0xac10 >> 2),
255 0x00000000,
256 (0x9c00 << 16) | (0xac14 >> 2),
257 0x00000000,
258 (0x9c00 << 16) | (0xae00 >> 2),
259 0x00000000,
260 (0x9c00 << 16) | (0xac08 >> 2),
261 0x00000000,
262 (0x9c00 << 16) | (0x88d4 >> 2),
263 0x00000000,
264 (0x9c00 << 16) | (0x88c8 >> 2),
265 0x00000000,
266 (0x9c00 << 16) | (0x88cc >> 2),
267 0x00000000,
268 (0x9c00 << 16) | (0x89b0 >> 2),
269 0x00000000,
270 (0x9c00 << 16) | (0x8b10 >> 2),
271 0x00000000,
272 (0x9c00 << 16) | (0x8a14 >> 2),
273 0x00000000,
274 (0x9c00 << 16) | (0x9830 >> 2),
275 0x00000000,
276 (0x9c00 << 16) | (0x9834 >> 2),
277 0x00000000,
278 (0x9c00 << 16) | (0x9838 >> 2),
279 0x00000000,
280 (0x9c00 << 16) | (0x9a10 >> 2),
281 0x00000000,
282 (0x8000 << 16) | (0x9870 >> 2),
283 0x00000000,
284 (0x8000 << 16) | (0x9874 >> 2),
285 0x00000000,
286 (0x8001 << 16) | (0x9870 >> 2),
287 0x00000000,
288 (0x8001 << 16) | (0x9874 >> 2),
289 0x00000000,
290 (0x8040 << 16) | (0x9870 >> 2),
291 0x00000000,
292 (0x8040 << 16) | (0x9874 >> 2),
293 0x00000000,
294 (0x8041 << 16) | (0x9870 >> 2),
295 0x00000000,
296 (0x8041 << 16) | (0x9874 >> 2),
297 0x00000000,
298 0x00000000
299};
b403bed8 300
f43cf1b1
MN
301static const u32 tahiti_golden_rlc_registers[] =
302{
303 0xc424, 0xffffffff, 0x00601005,
304 0xc47c, 0xffffffff, 0x10104040,
305 0xc488, 0xffffffff, 0x0100000a,
306 0xc314, 0xffffffff, 0x00000800,
307 0xc30c, 0xffffffff, 0x800000f4,
308 0xf4a8, 0xffffffff, 0x00000000
309};
310
311static const u32 tahiti_golden_registers[] =
312{
313 0x9a10, 0x00010000, 0x00018208,
314 0x9830, 0xffffffff, 0x00000000,
315 0x9834, 0xf00fffff, 0x00000400,
316 0x9838, 0x0002021c, 0x00020200,
317 0xc78, 0x00000080, 0x00000000,
318 0xd030, 0x000300c0, 0x00800040,
319 0xd830, 0x000300c0, 0x00800040,
320 0x5bb0, 0x000000f0, 0x00000070,
321 0x5bc0, 0x00200000, 0x50100000,
322 0x7030, 0x31000311, 0x00000011,
323 0x277c, 0x00000003, 0x000007ff,
324 0x240c, 0x000007ff, 0x00000000,
325 0x8a14, 0xf000001f, 0x00000007,
326 0x8b24, 0xffffffff, 0x00ffffff,
327 0x8b10, 0x0000ff0f, 0x00000000,
328 0x28a4c, 0x07ffffff, 0x4e000000,
329 0x28350, 0x3f3f3fff, 0x2a00126a,
330 0x30, 0x000000ff, 0x0040,
331 0x34, 0x00000040, 0x00004040,
332 0x9100, 0x07ffffff, 0x03000000,
333 0x8e88, 0x01ff1f3f, 0x00000000,
334 0x8e84, 0x01ff1f3f, 0x00000000,
335 0x9060, 0x0000007f, 0x00000020,
336 0x9508, 0x00010000, 0x00010000,
337 0xac14, 0x00000200, 0x000002fb,
338 0xac10, 0xffffffff, 0x0000543b,
339 0xac0c, 0xffffffff, 0xa9210876,
340 0x88d0, 0xffffffff, 0x000fff40,
341 0x88d4, 0x0000001f, 0x00000010,
342 0x1410, 0x20000000, 0x20fffed8,
343 0x15c0, 0x000c0fc0, 0x000c0400
344};
345
346static const u32 tahiti_golden_registers2[] =
347{
348 0xc64, 0x00000001, 0x00000001
349};
350
351static const u32 pitcairn_golden_rlc_registers[] =
352{
353 0xc424, 0xffffffff, 0x00601004,
354 0xc47c, 0xffffffff, 0x10102020,
355 0xc488, 0xffffffff, 0x01000020,
356 0xc314, 0xffffffff, 0x00000800,
357 0xc30c, 0xffffffff, 0x800000a4
358};
359
360static const u32 pitcairn_golden_registers[] =
361{
362 0x9a10, 0x00010000, 0x00018208,
363 0x9830, 0xffffffff, 0x00000000,
364 0x9834, 0xf00fffff, 0x00000400,
365 0x9838, 0x0002021c, 0x00020200,
366 0xc78, 0x00000080, 0x00000000,
367 0xd030, 0x000300c0, 0x00800040,
368 0xd830, 0x000300c0, 0x00800040,
369 0x5bb0, 0x000000f0, 0x00000070,
370 0x5bc0, 0x00200000, 0x50100000,
371 0x7030, 0x31000311, 0x00000011,
372 0x2ae4, 0x00073ffe, 0x000022a2,
373 0x240c, 0x000007ff, 0x00000000,
374 0x8a14, 0xf000001f, 0x00000007,
375 0x8b24, 0xffffffff, 0x00ffffff,
376 0x8b10, 0x0000ff0f, 0x00000000,
377 0x28a4c, 0x07ffffff, 0x4e000000,
378 0x28350, 0x3f3f3fff, 0x2a00126a,
379 0x30, 0x000000ff, 0x0040,
380 0x34, 0x00000040, 0x00004040,
381 0x9100, 0x07ffffff, 0x03000000,
382 0x9060, 0x0000007f, 0x00000020,
383 0x9508, 0x00010000, 0x00010000,
384 0xac14, 0x000003ff, 0x000000f7,
385 0xac10, 0xffffffff, 0x00000000,
386 0xac0c, 0xffffffff, 0x32761054,
387 0x88d4, 0x0000001f, 0x00000010,
388 0x15c0, 0x000c0fc0, 0x000c0400
389};
390
391static const u32 verde_golden_rlc_registers[] =
392{
393 0xc424, 0xffffffff, 0x033f1005,
394 0xc47c, 0xffffffff, 0x10808020,
395 0xc488, 0xffffffff, 0x00800008,
396 0xc314, 0xffffffff, 0x00001000,
397 0xc30c, 0xffffffff, 0x80010014
398};
399
400static const u32 verde_golden_registers[] =
401{
402 0x9a10, 0x00010000, 0x00018208,
403 0x9830, 0xffffffff, 0x00000000,
404 0x9834, 0xf00fffff, 0x00000400,
405 0x9838, 0x0002021c, 0x00020200,
406 0xc78, 0x00000080, 0x00000000,
407 0xd030, 0x000300c0, 0x00800040,
408 0xd030, 0x000300c0, 0x00800040,
409 0xd830, 0x000300c0, 0x00800040,
410 0xd830, 0x000300c0, 0x00800040,
411 0x5bb0, 0x000000f0, 0x00000070,
412 0x5bc0, 0x00200000, 0x50100000,
413 0x7030, 0x31000311, 0x00000011,
414 0x2ae4, 0x00073ffe, 0x000022a2,
415 0x2ae4, 0x00073ffe, 0x000022a2,
416 0x2ae4, 0x00073ffe, 0x000022a2,
417 0x240c, 0x000007ff, 0x00000000,
418 0x240c, 0x000007ff, 0x00000000,
419 0x240c, 0x000007ff, 0x00000000,
420 0x8a14, 0xf000001f, 0x00000007,
421 0x8a14, 0xf000001f, 0x00000007,
422 0x8a14, 0xf000001f, 0x00000007,
423 0x8b24, 0xffffffff, 0x00ffffff,
424 0x8b10, 0x0000ff0f, 0x00000000,
425 0x28a4c, 0x07ffffff, 0x4e000000,
426 0x28350, 0x3f3f3fff, 0x0000124a,
427 0x28350, 0x3f3f3fff, 0x0000124a,
428 0x28350, 0x3f3f3fff, 0x0000124a,
429 0x30, 0x000000ff, 0x0040,
430 0x34, 0x00000040, 0x00004040,
431 0x9100, 0x07ffffff, 0x03000000,
432 0x9100, 0x07ffffff, 0x03000000,
433 0x8e88, 0x01ff1f3f, 0x00000000,
434 0x8e88, 0x01ff1f3f, 0x00000000,
435 0x8e88, 0x01ff1f3f, 0x00000000,
436 0x8e84, 0x01ff1f3f, 0x00000000,
437 0x8e84, 0x01ff1f3f, 0x00000000,
438 0x8e84, 0x01ff1f3f, 0x00000000,
439 0x9060, 0x0000007f, 0x00000020,
440 0x9508, 0x00010000, 0x00010000,
441 0xac14, 0x000003ff, 0x00000003,
442 0xac14, 0x000003ff, 0x00000003,
443 0xac14, 0x000003ff, 0x00000003,
444 0xac10, 0xffffffff, 0x00000000,
445 0xac10, 0xffffffff, 0x00000000,
446 0xac10, 0xffffffff, 0x00000000,
447 0xac0c, 0xffffffff, 0x00001032,
448 0xac0c, 0xffffffff, 0x00001032,
449 0xac0c, 0xffffffff, 0x00001032,
450 0x88d4, 0x0000001f, 0x00000010,
451 0x88d4, 0x0000001f, 0x00000010,
452 0x88d4, 0x0000001f, 0x00000010,
453 0x15c0, 0x000c0fc0, 0x000c0400
454};
455
456static const u32 oland_golden_rlc_registers[] =
457{
458 0xc424, 0xffffffff, 0x00601005,
459 0xc47c, 0xffffffff, 0x10104040,
460 0xc488, 0xffffffff, 0x0100000a,
461 0xc314, 0xffffffff, 0x00000800,
462 0xc30c, 0xffffffff, 0x800000f4
463};
464
465static const u32 oland_golden_registers[] =
466{
467 0x9a10, 0x00010000, 0x00018208,
468 0x9830, 0xffffffff, 0x00000000,
469 0x9834, 0xf00fffff, 0x00000400,
470 0x9838, 0x0002021c, 0x00020200,
471 0xc78, 0x00000080, 0x00000000,
472 0xd030, 0x000300c0, 0x00800040,
473 0xd830, 0x000300c0, 0x00800040,
474 0x5bb0, 0x000000f0, 0x00000070,
475 0x5bc0, 0x00200000, 0x50100000,
476 0x7030, 0x31000311, 0x00000011,
477 0x2ae4, 0x00073ffe, 0x000022a2,
478 0x240c, 0x000007ff, 0x00000000,
479 0x8a14, 0xf000001f, 0x00000007,
480 0x8b24, 0xffffffff, 0x00ffffff,
481 0x8b10, 0x0000ff0f, 0x00000000,
482 0x28a4c, 0x07ffffff, 0x4e000000,
483 0x28350, 0x3f3f3fff, 0x00000082,
484 0x30, 0x000000ff, 0x0040,
485 0x34, 0x00000040, 0x00004040,
486 0x9100, 0x07ffffff, 0x03000000,
487 0x9060, 0x0000007f, 0x00000020,
488 0x9508, 0x00010000, 0x00010000,
489 0xac14, 0x000003ff, 0x000000f3,
490 0xac10, 0xffffffff, 0x00000000,
491 0xac0c, 0xffffffff, 0x00003210,
492 0x88d4, 0x0000001f, 0x00000010,
493 0x15c0, 0x000c0fc0, 0x000c0400
494};
495
496static const u32 hainan_golden_registers[] =
497{
498 0x9a10, 0x00010000, 0x00018208,
499 0x9830, 0xffffffff, 0x00000000,
500 0x9834, 0xf00fffff, 0x00000400,
501 0x9838, 0x0002021c, 0x00020200,
502 0xd0c0, 0xff000fff, 0x00000100,
503 0xd030, 0x000300c0, 0x00800040,
504 0xd8c0, 0xff000fff, 0x00000100,
505 0xd830, 0x000300c0, 0x00800040,
506 0x2ae4, 0x00073ffe, 0x000022a2,
507 0x240c, 0x000007ff, 0x00000000,
508 0x8a14, 0xf000001f, 0x00000007,
509 0x8b24, 0xffffffff, 0x00ffffff,
510 0x8b10, 0x0000ff0f, 0x00000000,
511 0x28a4c, 0x07ffffff, 0x4e000000,
512 0x28350, 0x3f3f3fff, 0x00000000,
513 0x30, 0x000000ff, 0x0040,
514 0x34, 0x00000040, 0x00004040,
515 0x9100, 0x03e00000, 0x03600000,
516 0x9060, 0x0000007f, 0x00000020,
517 0x9508, 0x00010000, 0x00010000,
518 0xac14, 0x000003ff, 0x000000f1,
519 0xac10, 0xffffffff, 0x00000000,
520 0xac0c, 0xffffffff, 0x00003210,
521 0x88d4, 0x0000001f, 0x00000010,
522 0x15c0, 0x000c0fc0, 0x000c0400
523};
524
525static const u32 hainan_golden_registers2[] =
526{
527 0x98f8, 0xffffffff, 0x02010001
528};
529
530static const u32 tahiti_mgcg_cgcg_init[] =
531{
532 0xc400, 0xffffffff, 0xfffffffc,
533 0x802c, 0xffffffff, 0xe0000000,
534 0x9a60, 0xffffffff, 0x00000100,
535 0x92a4, 0xffffffff, 0x00000100,
536 0xc164, 0xffffffff, 0x00000100,
537 0x9774, 0xffffffff, 0x00000100,
538 0x8984, 0xffffffff, 0x06000100,
539 0x8a18, 0xffffffff, 0x00000100,
540 0x92a0, 0xffffffff, 0x00000100,
541 0xc380, 0xffffffff, 0x00000100,
542 0x8b28, 0xffffffff, 0x00000100,
543 0x9144, 0xffffffff, 0x00000100,
544 0x8d88, 0xffffffff, 0x00000100,
545 0x8d8c, 0xffffffff, 0x00000100,
546 0x9030, 0xffffffff, 0x00000100,
547 0x9034, 0xffffffff, 0x00000100,
548 0x9038, 0xffffffff, 0x00000100,
549 0x903c, 0xffffffff, 0x00000100,
550 0xad80, 0xffffffff, 0x00000100,
551 0xac54, 0xffffffff, 0x00000100,
552 0x897c, 0xffffffff, 0x06000100,
553 0x9868, 0xffffffff, 0x00000100,
554 0x9510, 0xffffffff, 0x00000100,
555 0xaf04, 0xffffffff, 0x00000100,
556 0xae04, 0xffffffff, 0x00000100,
557 0x949c, 0xffffffff, 0x00000100,
558 0x802c, 0xffffffff, 0xe0000000,
559 0x9160, 0xffffffff, 0x00010000,
560 0x9164, 0xffffffff, 0x00030002,
561 0x9168, 0xffffffff, 0x00040007,
562 0x916c, 0xffffffff, 0x00060005,
563 0x9170, 0xffffffff, 0x00090008,
564 0x9174, 0xffffffff, 0x00020001,
565 0x9178, 0xffffffff, 0x00040003,
566 0x917c, 0xffffffff, 0x00000007,
567 0x9180, 0xffffffff, 0x00060005,
568 0x9184, 0xffffffff, 0x00090008,
569 0x9188, 0xffffffff, 0x00030002,
570 0x918c, 0xffffffff, 0x00050004,
571 0x9190, 0xffffffff, 0x00000008,
572 0x9194, 0xffffffff, 0x00070006,
573 0x9198, 0xffffffff, 0x000a0009,
574 0x919c, 0xffffffff, 0x00040003,
575 0x91a0, 0xffffffff, 0x00060005,
576 0x91a4, 0xffffffff, 0x00000009,
577 0x91a8, 0xffffffff, 0x00080007,
578 0x91ac, 0xffffffff, 0x000b000a,
579 0x91b0, 0xffffffff, 0x00050004,
580 0x91b4, 0xffffffff, 0x00070006,
581 0x91b8, 0xffffffff, 0x0008000b,
582 0x91bc, 0xffffffff, 0x000a0009,
583 0x91c0, 0xffffffff, 0x000d000c,
584 0x91c4, 0xffffffff, 0x00060005,
585 0x91c8, 0xffffffff, 0x00080007,
586 0x91cc, 0xffffffff, 0x0000000b,
587 0x91d0, 0xffffffff, 0x000a0009,
588 0x91d4, 0xffffffff, 0x000d000c,
589 0x91d8, 0xffffffff, 0x00070006,
590 0x91dc, 0xffffffff, 0x00090008,
591 0x91e0, 0xffffffff, 0x0000000c,
592 0x91e4, 0xffffffff, 0x000b000a,
593 0x91e8, 0xffffffff, 0x000e000d,
594 0x91ec, 0xffffffff, 0x00080007,
595 0x91f0, 0xffffffff, 0x000a0009,
596 0x91f4, 0xffffffff, 0x0000000d,
597 0x91f8, 0xffffffff, 0x000c000b,
598 0x91fc, 0xffffffff, 0x000f000e,
599 0x9200, 0xffffffff, 0x00090008,
600 0x9204, 0xffffffff, 0x000b000a,
601 0x9208, 0xffffffff, 0x000c000f,
602 0x920c, 0xffffffff, 0x000e000d,
603 0x9210, 0xffffffff, 0x00110010,
604 0x9214, 0xffffffff, 0x000a0009,
605 0x9218, 0xffffffff, 0x000c000b,
606 0x921c, 0xffffffff, 0x0000000f,
607 0x9220, 0xffffffff, 0x000e000d,
608 0x9224, 0xffffffff, 0x00110010,
609 0x9228, 0xffffffff, 0x000b000a,
610 0x922c, 0xffffffff, 0x000d000c,
611 0x9230, 0xffffffff, 0x00000010,
612 0x9234, 0xffffffff, 0x000f000e,
613 0x9238, 0xffffffff, 0x00120011,
614 0x923c, 0xffffffff, 0x000c000b,
615 0x9240, 0xffffffff, 0x000e000d,
616 0x9244, 0xffffffff, 0x00000011,
617 0x9248, 0xffffffff, 0x0010000f,
618 0x924c, 0xffffffff, 0x00130012,
619 0x9250, 0xffffffff, 0x000d000c,
620 0x9254, 0xffffffff, 0x000f000e,
621 0x9258, 0xffffffff, 0x00100013,
622 0x925c, 0xffffffff, 0x00120011,
623 0x9260, 0xffffffff, 0x00150014,
624 0x9264, 0xffffffff, 0x000e000d,
625 0x9268, 0xffffffff, 0x0010000f,
626 0x926c, 0xffffffff, 0x00000013,
627 0x9270, 0xffffffff, 0x00120011,
628 0x9274, 0xffffffff, 0x00150014,
629 0x9278, 0xffffffff, 0x000f000e,
630 0x927c, 0xffffffff, 0x00110010,
631 0x9280, 0xffffffff, 0x00000014,
632 0x9284, 0xffffffff, 0x00130012,
633 0x9288, 0xffffffff, 0x00160015,
634 0x928c, 0xffffffff, 0x0010000f,
635 0x9290, 0xffffffff, 0x00120011,
636 0x9294, 0xffffffff, 0x00000015,
637 0x9298, 0xffffffff, 0x00140013,
638 0x929c, 0xffffffff, 0x00170016,
639 0x9150, 0xffffffff, 0x96940200,
640 0x8708, 0xffffffff, 0x00900100,
641 0xc478, 0xffffffff, 0x00000080,
642 0xc404, 0xffffffff, 0x0020003f,
643 0x30, 0xffffffff, 0x0000001c,
644 0x34, 0x000f0000, 0x000f0000,
645 0x160c, 0xffffffff, 0x00000100,
646 0x1024, 0xffffffff, 0x00000100,
647 0x102c, 0x00000101, 0x00000000,
648 0x20a8, 0xffffffff, 0x00000104,
649 0x264c, 0x000c0000, 0x000c0000,
650 0x2648, 0x000c0000, 0x000c0000,
651 0x55e4, 0xff000fff, 0x00000100,
652 0x55e8, 0x00000001, 0x00000001,
653 0x2f50, 0x00000001, 0x00000001,
654 0x30cc, 0xc0000fff, 0x00000104,
655 0xc1e4, 0x00000001, 0x00000001,
656 0xd0c0, 0xfffffff0, 0x00000100,
657 0xd8c0, 0xfffffff0, 0x00000100
658};
659
660static const u32 pitcairn_mgcg_cgcg_init[] =
661{
662 0xc400, 0xffffffff, 0xfffffffc,
663 0x802c, 0xffffffff, 0xe0000000,
664 0x9a60, 0xffffffff, 0x00000100,
665 0x92a4, 0xffffffff, 0x00000100,
666 0xc164, 0xffffffff, 0x00000100,
667 0x9774, 0xffffffff, 0x00000100,
668 0x8984, 0xffffffff, 0x06000100,
669 0x8a18, 0xffffffff, 0x00000100,
670 0x92a0, 0xffffffff, 0x00000100,
671 0xc380, 0xffffffff, 0x00000100,
672 0x8b28, 0xffffffff, 0x00000100,
673 0x9144, 0xffffffff, 0x00000100,
674 0x8d88, 0xffffffff, 0x00000100,
675 0x8d8c, 0xffffffff, 0x00000100,
676 0x9030, 0xffffffff, 0x00000100,
677 0x9034, 0xffffffff, 0x00000100,
678 0x9038, 0xffffffff, 0x00000100,
679 0x903c, 0xffffffff, 0x00000100,
680 0xad80, 0xffffffff, 0x00000100,
681 0xac54, 0xffffffff, 0x00000100,
682 0x897c, 0xffffffff, 0x06000100,
683 0x9868, 0xffffffff, 0x00000100,
684 0x9510, 0xffffffff, 0x00000100,
685 0xaf04, 0xffffffff, 0x00000100,
686 0xae04, 0xffffffff, 0x00000100,
687 0x949c, 0xffffffff, 0x00000100,
688 0x802c, 0xffffffff, 0xe0000000,
689 0x9160, 0xffffffff, 0x00010000,
690 0x9164, 0xffffffff, 0x00030002,
691 0x9168, 0xffffffff, 0x00040007,
692 0x916c, 0xffffffff, 0x00060005,
693 0x9170, 0xffffffff, 0x00090008,
694 0x9174, 0xffffffff, 0x00020001,
695 0x9178, 0xffffffff, 0x00040003,
696 0x917c, 0xffffffff, 0x00000007,
697 0x9180, 0xffffffff, 0x00060005,
698 0x9184, 0xffffffff, 0x00090008,
699 0x9188, 0xffffffff, 0x00030002,
700 0x918c, 0xffffffff, 0x00050004,
701 0x9190, 0xffffffff, 0x00000008,
702 0x9194, 0xffffffff, 0x00070006,
703 0x9198, 0xffffffff, 0x000a0009,
704 0x919c, 0xffffffff, 0x00040003,
705 0x91a0, 0xffffffff, 0x00060005,
706 0x91a4, 0xffffffff, 0x00000009,
707 0x91a8, 0xffffffff, 0x00080007,
708 0x91ac, 0xffffffff, 0x000b000a,
709 0x91b0, 0xffffffff, 0x00050004,
710 0x91b4, 0xffffffff, 0x00070006,
711 0x91b8, 0xffffffff, 0x0008000b,
712 0x91bc, 0xffffffff, 0x000a0009,
713 0x91c0, 0xffffffff, 0x000d000c,
714 0x9200, 0xffffffff, 0x00090008,
715 0x9204, 0xffffffff, 0x000b000a,
716 0x9208, 0xffffffff, 0x000c000f,
717 0x920c, 0xffffffff, 0x000e000d,
718 0x9210, 0xffffffff, 0x00110010,
719 0x9214, 0xffffffff, 0x000a0009,
720 0x9218, 0xffffffff, 0x000c000b,
721 0x921c, 0xffffffff, 0x0000000f,
722 0x9220, 0xffffffff, 0x000e000d,
723 0x9224, 0xffffffff, 0x00110010,
724 0x9228, 0xffffffff, 0x000b000a,
725 0x922c, 0xffffffff, 0x000d000c,
726 0x9230, 0xffffffff, 0x00000010,
727 0x9234, 0xffffffff, 0x000f000e,
728 0x9238, 0xffffffff, 0x00120011,
729 0x923c, 0xffffffff, 0x000c000b,
730 0x9240, 0xffffffff, 0x000e000d,
731 0x9244, 0xffffffff, 0x00000011,
732 0x9248, 0xffffffff, 0x0010000f,
733 0x924c, 0xffffffff, 0x00130012,
734 0x9250, 0xffffffff, 0x000d000c,
735 0x9254, 0xffffffff, 0x000f000e,
736 0x9258, 0xffffffff, 0x00100013,
737 0x925c, 0xffffffff, 0x00120011,
738 0x9260, 0xffffffff, 0x00150014,
739 0x9150, 0xffffffff, 0x96940200,
740 0x8708, 0xffffffff, 0x00900100,
741 0xc478, 0xffffffff, 0x00000080,
742 0xc404, 0xffffffff, 0x0020003f,
743 0x30, 0xffffffff, 0x0000001c,
744 0x34, 0x000f0000, 0x000f0000,
745 0x160c, 0xffffffff, 0x00000100,
746 0x1024, 0xffffffff, 0x00000100,
747 0x102c, 0x00000101, 0x00000000,
748 0x20a8, 0xffffffff, 0x00000104,
749 0x55e4, 0xff000fff, 0x00000100,
750 0x55e8, 0x00000001, 0x00000001,
751 0x2f50, 0x00000001, 0x00000001,
752 0x30cc, 0xc0000fff, 0x00000104,
753 0xc1e4, 0x00000001, 0x00000001,
754 0xd0c0, 0xfffffff0, 0x00000100,
755 0xd8c0, 0xfffffff0, 0x00000100
756};
757
758static const u32 verde_mgcg_cgcg_init[] =
759{
760 0xc400, 0xffffffff, 0xfffffffc,
761 0x802c, 0xffffffff, 0xe0000000,
762 0x9a60, 0xffffffff, 0x00000100,
763 0x92a4, 0xffffffff, 0x00000100,
764 0xc164, 0xffffffff, 0x00000100,
765 0x9774, 0xffffffff, 0x00000100,
766 0x8984, 0xffffffff, 0x06000100,
767 0x8a18, 0xffffffff, 0x00000100,
768 0x92a0, 0xffffffff, 0x00000100,
769 0xc380, 0xffffffff, 0x00000100,
770 0x8b28, 0xffffffff, 0x00000100,
771 0x9144, 0xffffffff, 0x00000100,
772 0x8d88, 0xffffffff, 0x00000100,
773 0x8d8c, 0xffffffff, 0x00000100,
774 0x9030, 0xffffffff, 0x00000100,
775 0x9034, 0xffffffff, 0x00000100,
776 0x9038, 0xffffffff, 0x00000100,
777 0x903c, 0xffffffff, 0x00000100,
778 0xad80, 0xffffffff, 0x00000100,
779 0xac54, 0xffffffff, 0x00000100,
780 0x897c, 0xffffffff, 0x06000100,
781 0x9868, 0xffffffff, 0x00000100,
782 0x9510, 0xffffffff, 0x00000100,
783 0xaf04, 0xffffffff, 0x00000100,
784 0xae04, 0xffffffff, 0x00000100,
785 0x949c, 0xffffffff, 0x00000100,
786 0x802c, 0xffffffff, 0xe0000000,
787 0x9160, 0xffffffff, 0x00010000,
788 0x9164, 0xffffffff, 0x00030002,
789 0x9168, 0xffffffff, 0x00040007,
790 0x916c, 0xffffffff, 0x00060005,
791 0x9170, 0xffffffff, 0x00090008,
792 0x9174, 0xffffffff, 0x00020001,
793 0x9178, 0xffffffff, 0x00040003,
794 0x917c, 0xffffffff, 0x00000007,
795 0x9180, 0xffffffff, 0x00060005,
796 0x9184, 0xffffffff, 0x00090008,
797 0x9188, 0xffffffff, 0x00030002,
798 0x918c, 0xffffffff, 0x00050004,
799 0x9190, 0xffffffff, 0x00000008,
800 0x9194, 0xffffffff, 0x00070006,
801 0x9198, 0xffffffff, 0x000a0009,
802 0x919c, 0xffffffff, 0x00040003,
803 0x91a0, 0xffffffff, 0x00060005,
804 0x91a4, 0xffffffff, 0x00000009,
805 0x91a8, 0xffffffff, 0x00080007,
806 0x91ac, 0xffffffff, 0x000b000a,
807 0x91b0, 0xffffffff, 0x00050004,
808 0x91b4, 0xffffffff, 0x00070006,
809 0x91b8, 0xffffffff, 0x0008000b,
810 0x91bc, 0xffffffff, 0x000a0009,
811 0x91c0, 0xffffffff, 0x000d000c,
812 0x9200, 0xffffffff, 0x00090008,
813 0x9204, 0xffffffff, 0x000b000a,
814 0x9208, 0xffffffff, 0x000c000f,
815 0x920c, 0xffffffff, 0x000e000d,
816 0x9210, 0xffffffff, 0x00110010,
817 0x9214, 0xffffffff, 0x000a0009,
818 0x9218, 0xffffffff, 0x000c000b,
819 0x921c, 0xffffffff, 0x0000000f,
820 0x9220, 0xffffffff, 0x000e000d,
821 0x9224, 0xffffffff, 0x00110010,
822 0x9228, 0xffffffff, 0x000b000a,
823 0x922c, 0xffffffff, 0x000d000c,
824 0x9230, 0xffffffff, 0x00000010,
825 0x9234, 0xffffffff, 0x000f000e,
826 0x9238, 0xffffffff, 0x00120011,
827 0x923c, 0xffffffff, 0x000c000b,
828 0x9240, 0xffffffff, 0x000e000d,
829 0x9244, 0xffffffff, 0x00000011,
830 0x9248, 0xffffffff, 0x0010000f,
831 0x924c, 0xffffffff, 0x00130012,
832 0x9250, 0xffffffff, 0x000d000c,
833 0x9254, 0xffffffff, 0x000f000e,
834 0x9258, 0xffffffff, 0x00100013,
835 0x925c, 0xffffffff, 0x00120011,
836 0x9260, 0xffffffff, 0x00150014,
837 0x9150, 0xffffffff, 0x96940200,
838 0x8708, 0xffffffff, 0x00900100,
839 0xc478, 0xffffffff, 0x00000080,
840 0xc404, 0xffffffff, 0x0020003f,
841 0x30, 0xffffffff, 0x0000001c,
842 0x34, 0x000f0000, 0x000f0000,
843 0x160c, 0xffffffff, 0x00000100,
844 0x1024, 0xffffffff, 0x00000100,
845 0x102c, 0x00000101, 0x00000000,
846 0x20a8, 0xffffffff, 0x00000104,
847 0x264c, 0x000c0000, 0x000c0000,
848 0x2648, 0x000c0000, 0x000c0000,
849 0x55e4, 0xff000fff, 0x00000100,
850 0x55e8, 0x00000001, 0x00000001,
851 0x2f50, 0x00000001, 0x00000001,
852 0x30cc, 0xc0000fff, 0x00000104,
853 0xc1e4, 0x00000001, 0x00000001,
854 0xd0c0, 0xfffffff0, 0x00000100,
855 0xd8c0, 0xfffffff0, 0x00000100
856};
857
858static const u32 oland_mgcg_cgcg_init[] =
859{
860 0xc400, 0xffffffff, 0xfffffffc,
861 0x802c, 0xffffffff, 0xe0000000,
862 0x9a60, 0xffffffff, 0x00000100,
863 0x92a4, 0xffffffff, 0x00000100,
864 0xc164, 0xffffffff, 0x00000100,
865 0x9774, 0xffffffff, 0x00000100,
866 0x8984, 0xffffffff, 0x06000100,
867 0x8a18, 0xffffffff, 0x00000100,
868 0x92a0, 0xffffffff, 0x00000100,
869 0xc380, 0xffffffff, 0x00000100,
870 0x8b28, 0xffffffff, 0x00000100,
871 0x9144, 0xffffffff, 0x00000100,
872 0x8d88, 0xffffffff, 0x00000100,
873 0x8d8c, 0xffffffff, 0x00000100,
874 0x9030, 0xffffffff, 0x00000100,
875 0x9034, 0xffffffff, 0x00000100,
876 0x9038, 0xffffffff, 0x00000100,
877 0x903c, 0xffffffff, 0x00000100,
878 0xad80, 0xffffffff, 0x00000100,
879 0xac54, 0xffffffff, 0x00000100,
880 0x897c, 0xffffffff, 0x06000100,
881 0x9868, 0xffffffff, 0x00000100,
882 0x9510, 0xffffffff, 0x00000100,
883 0xaf04, 0xffffffff, 0x00000100,
884 0xae04, 0xffffffff, 0x00000100,
885 0x949c, 0xffffffff, 0x00000100,
886 0x802c, 0xffffffff, 0xe0000000,
887 0x9160, 0xffffffff, 0x00010000,
888 0x9164, 0xffffffff, 0x00030002,
889 0x9168, 0xffffffff, 0x00040007,
890 0x916c, 0xffffffff, 0x00060005,
891 0x9170, 0xffffffff, 0x00090008,
892 0x9174, 0xffffffff, 0x00020001,
893 0x9178, 0xffffffff, 0x00040003,
894 0x917c, 0xffffffff, 0x00000007,
895 0x9180, 0xffffffff, 0x00060005,
896 0x9184, 0xffffffff, 0x00090008,
897 0x9188, 0xffffffff, 0x00030002,
898 0x918c, 0xffffffff, 0x00050004,
899 0x9190, 0xffffffff, 0x00000008,
900 0x9194, 0xffffffff, 0x00070006,
901 0x9198, 0xffffffff, 0x000a0009,
902 0x919c, 0xffffffff, 0x00040003,
903 0x91a0, 0xffffffff, 0x00060005,
904 0x91a4, 0xffffffff, 0x00000009,
905 0x91a8, 0xffffffff, 0x00080007,
906 0x91ac, 0xffffffff, 0x000b000a,
907 0x91b0, 0xffffffff, 0x00050004,
908 0x91b4, 0xffffffff, 0x00070006,
909 0x91b8, 0xffffffff, 0x0008000b,
910 0x91bc, 0xffffffff, 0x000a0009,
911 0x91c0, 0xffffffff, 0x000d000c,
912 0x91c4, 0xffffffff, 0x00060005,
913 0x91c8, 0xffffffff, 0x00080007,
914 0x91cc, 0xffffffff, 0x0000000b,
915 0x91d0, 0xffffffff, 0x000a0009,
916 0x91d4, 0xffffffff, 0x000d000c,
917 0x9150, 0xffffffff, 0x96940200,
918 0x8708, 0xffffffff, 0x00900100,
919 0xc478, 0xffffffff, 0x00000080,
920 0xc404, 0xffffffff, 0x0020003f,
921 0x30, 0xffffffff, 0x0000001c,
922 0x34, 0x000f0000, 0x000f0000,
923 0x160c, 0xffffffff, 0x00000100,
924 0x1024, 0xffffffff, 0x00000100,
925 0x102c, 0x00000101, 0x00000000,
926 0x20a8, 0xffffffff, 0x00000104,
927 0x264c, 0x000c0000, 0x000c0000,
928 0x2648, 0x000c0000, 0x000c0000,
929 0x55e4, 0xff000fff, 0x00000100,
930 0x55e8, 0x00000001, 0x00000001,
931 0x2f50, 0x00000001, 0x00000001,
932 0x30cc, 0xc0000fff, 0x00000104,
933 0xc1e4, 0x00000001, 0x00000001,
934 0xd0c0, 0xfffffff0, 0x00000100,
935 0xd8c0, 0xfffffff0, 0x00000100
936};
937
938static const u32 hainan_mgcg_cgcg_init[] =
939{
940 0xc400, 0xffffffff, 0xfffffffc,
941 0x802c, 0xffffffff, 0xe0000000,
942 0x9a60, 0xffffffff, 0x00000100,
943 0x92a4, 0xffffffff, 0x00000100,
944 0xc164, 0xffffffff, 0x00000100,
945 0x9774, 0xffffffff, 0x00000100,
946 0x8984, 0xffffffff, 0x06000100,
947 0x8a18, 0xffffffff, 0x00000100,
948 0x92a0, 0xffffffff, 0x00000100,
949 0xc380, 0xffffffff, 0x00000100,
950 0x8b28, 0xffffffff, 0x00000100,
951 0x9144, 0xffffffff, 0x00000100,
952 0x8d88, 0xffffffff, 0x00000100,
953 0x8d8c, 0xffffffff, 0x00000100,
954 0x9030, 0xffffffff, 0x00000100,
955 0x9034, 0xffffffff, 0x00000100,
956 0x9038, 0xffffffff, 0x00000100,
957 0x903c, 0xffffffff, 0x00000100,
958 0xad80, 0xffffffff, 0x00000100,
959 0xac54, 0xffffffff, 0x00000100,
960 0x897c, 0xffffffff, 0x06000100,
961 0x9868, 0xffffffff, 0x00000100,
962 0x9510, 0xffffffff, 0x00000100,
963 0xaf04, 0xffffffff, 0x00000100,
964 0xae04, 0xffffffff, 0x00000100,
965 0x949c, 0xffffffff, 0x00000100,
966 0x802c, 0xffffffff, 0xe0000000,
967 0x9160, 0xffffffff, 0x00010000,
968 0x9164, 0xffffffff, 0x00030002,
969 0x9168, 0xffffffff, 0x00040007,
970 0x916c, 0xffffffff, 0x00060005,
971 0x9170, 0xffffffff, 0x00090008,
972 0x9174, 0xffffffff, 0x00020001,
973 0x9178, 0xffffffff, 0x00040003,
974 0x917c, 0xffffffff, 0x00000007,
975 0x9180, 0xffffffff, 0x00060005,
976 0x9184, 0xffffffff, 0x00090008,
977 0x9188, 0xffffffff, 0x00030002,
978 0x918c, 0xffffffff, 0x00050004,
979 0x9190, 0xffffffff, 0x00000008,
980 0x9194, 0xffffffff, 0x00070006,
981 0x9198, 0xffffffff, 0x000a0009,
982 0x919c, 0xffffffff, 0x00040003,
983 0x91a0, 0xffffffff, 0x00060005,
984 0x91a4, 0xffffffff, 0x00000009,
985 0x91a8, 0xffffffff, 0x00080007,
986 0x91ac, 0xffffffff, 0x000b000a,
987 0x91b0, 0xffffffff, 0x00050004,
988 0x91b4, 0xffffffff, 0x00070006,
989 0x91b8, 0xffffffff, 0x0008000b,
990 0x91bc, 0xffffffff, 0x000a0009,
991 0x91c0, 0xffffffff, 0x000d000c,
992 0x91c4, 0xffffffff, 0x00060005,
993 0x91c8, 0xffffffff, 0x00080007,
994 0x91cc, 0xffffffff, 0x0000000b,
995 0x91d0, 0xffffffff, 0x000a0009,
996 0x91d4, 0xffffffff, 0x000d000c,
997 0x9150, 0xffffffff, 0x96940200,
998 0x8708, 0xffffffff, 0x00900100,
999 0xc478, 0xffffffff, 0x00000080,
1000 0xc404, 0xffffffff, 0x0020003f,
1001 0x30, 0xffffffff, 0x0000001c,
1002 0x34, 0x000f0000, 0x000f0000,
1003 0x160c, 0xffffffff, 0x00000100,
1004 0x1024, 0xffffffff, 0x00000100,
1005 0x20a8, 0xffffffff, 0x00000104,
1006 0x264c, 0x000c0000, 0x000c0000,
1007 0x2648, 0x000c0000, 0x000c0000,
1008 0x2f50, 0x00000001, 0x00000001,
1009 0x30cc, 0xc0000fff, 0x00000104,
1010 0xc1e4, 0x00000001, 0x00000001,
1011 0xd0c0, 0xfffffff0, 0x00000100,
1012 0xd8c0, 0xfffffff0, 0x00000100
1013};
1014
1015static u32 verde_pg_init[] =
1016{
1017 0x353c, 0xffffffff, 0x40000,
1018 0x3538, 0xffffffff, 0x200010ff,
1019 0x353c, 0xffffffff, 0x0,
1020 0x353c, 0xffffffff, 0x0,
1021 0x353c, 0xffffffff, 0x0,
1022 0x353c, 0xffffffff, 0x0,
1023 0x353c, 0xffffffff, 0x0,
1024 0x353c, 0xffffffff, 0x7007,
1025 0x3538, 0xffffffff, 0x300010ff,
1026 0x353c, 0xffffffff, 0x0,
1027 0x353c, 0xffffffff, 0x0,
1028 0x353c, 0xffffffff, 0x0,
1029 0x353c, 0xffffffff, 0x0,
1030 0x353c, 0xffffffff, 0x0,
1031 0x353c, 0xffffffff, 0x400000,
1032 0x3538, 0xffffffff, 0x100010ff,
1033 0x353c, 0xffffffff, 0x0,
1034 0x353c, 0xffffffff, 0x0,
1035 0x353c, 0xffffffff, 0x0,
1036 0x353c, 0xffffffff, 0x0,
1037 0x353c, 0xffffffff, 0x0,
1038 0x353c, 0xffffffff, 0x120200,
1039 0x3538, 0xffffffff, 0x500010ff,
1040 0x353c, 0xffffffff, 0x0,
1041 0x353c, 0xffffffff, 0x0,
1042 0x353c, 0xffffffff, 0x0,
1043 0x353c, 0xffffffff, 0x0,
1044 0x353c, 0xffffffff, 0x0,
1045 0x353c, 0xffffffff, 0x1e1e16,
1046 0x3538, 0xffffffff, 0x600010ff,
1047 0x353c, 0xffffffff, 0x0,
1048 0x353c, 0xffffffff, 0x0,
1049 0x353c, 0xffffffff, 0x0,
1050 0x353c, 0xffffffff, 0x0,
1051 0x353c, 0xffffffff, 0x0,
1052 0x353c, 0xffffffff, 0x171f1e,
1053 0x3538, 0xffffffff, 0x700010ff,
1054 0x353c, 0xffffffff, 0x0,
1055 0x353c, 0xffffffff, 0x0,
1056 0x353c, 0xffffffff, 0x0,
1057 0x353c, 0xffffffff, 0x0,
1058 0x353c, 0xffffffff, 0x0,
1059 0x353c, 0xffffffff, 0x0,
1060 0x3538, 0xffffffff, 0x9ff,
1061 0x3500, 0xffffffff, 0x0,
1062 0x3504, 0xffffffff, 0x10000800,
1063 0x3504, 0xffffffff, 0xf,
1064 0x3504, 0xffffffff, 0xf,
1065 0x3500, 0xffffffff, 0x4,
1066 0x3504, 0xffffffff, 0x1000051e,
1067 0x3504, 0xffffffff, 0xffff,
1068 0x3504, 0xffffffff, 0xffff,
1069 0x3500, 0xffffffff, 0x8,
1070 0x3504, 0xffffffff, 0x80500,
1071 0x3500, 0xffffffff, 0x12,
1072 0x3504, 0xffffffff, 0x9050c,
1073 0x3500, 0xffffffff, 0x1d,
1074 0x3504, 0xffffffff, 0xb052c,
1075 0x3500, 0xffffffff, 0x2a,
1076 0x3504, 0xffffffff, 0x1053e,
1077 0x3500, 0xffffffff, 0x2d,
1078 0x3504, 0xffffffff, 0x10546,
1079 0x3500, 0xffffffff, 0x30,
1080 0x3504, 0xffffffff, 0xa054e,
1081 0x3500, 0xffffffff, 0x3c,
1082 0x3504, 0xffffffff, 0x1055f,
1083 0x3500, 0xffffffff, 0x3f,
1084 0x3504, 0xffffffff, 0x10567,
1085 0x3500, 0xffffffff, 0x42,
1086 0x3504, 0xffffffff, 0x1056f,
1087 0x3500, 0xffffffff, 0x45,
1088 0x3504, 0xffffffff, 0x10572,
1089 0x3500, 0xffffffff, 0x48,
1090 0x3504, 0xffffffff, 0x20575,
1091 0x3500, 0xffffffff, 0x4c,
1092 0x3504, 0xffffffff, 0x190801,
1093 0x3500, 0xffffffff, 0x67,
1094 0x3504, 0xffffffff, 0x1082a,
1095 0x3500, 0xffffffff, 0x6a,
1096 0x3504, 0xffffffff, 0x1b082d,
1097 0x3500, 0xffffffff, 0x87,
1098 0x3504, 0xffffffff, 0x310851,
1099 0x3500, 0xffffffff, 0xba,
1100 0x3504, 0xffffffff, 0x891,
1101 0x3500, 0xffffffff, 0xbc,
1102 0x3504, 0xffffffff, 0x893,
1103 0x3500, 0xffffffff, 0xbe,
1104 0x3504, 0xffffffff, 0x20895,
1105 0x3500, 0xffffffff, 0xc2,
1106 0x3504, 0xffffffff, 0x20899,
1107 0x3500, 0xffffffff, 0xc6,
1108 0x3504, 0xffffffff, 0x2089d,
1109 0x3500, 0xffffffff, 0xca,
1110 0x3504, 0xffffffff, 0x8a1,
1111 0x3500, 0xffffffff, 0xcc,
1112 0x3504, 0xffffffff, 0x8a3,
1113 0x3500, 0xffffffff, 0xce,
1114 0x3504, 0xffffffff, 0x308a5,
1115 0x3500, 0xffffffff, 0xd3,
1116 0x3504, 0xffffffff, 0x6d08cd,
1117 0x3500, 0xffffffff, 0x142,
1118 0x3504, 0xffffffff, 0x2000095a,
1119 0x3504, 0xffffffff, 0x1,
1120 0x3500, 0xffffffff, 0x144,
1121 0x3504, 0xffffffff, 0x301f095b,
1122 0x3500, 0xffffffff, 0x165,
1123 0x3504, 0xffffffff, 0xc094d,
1124 0x3500, 0xffffffff, 0x173,
1125 0x3504, 0xffffffff, 0xf096d,
1126 0x3500, 0xffffffff, 0x184,
1127 0x3504, 0xffffffff, 0x15097f,
1128 0x3500, 0xffffffff, 0x19b,
1129 0x3504, 0xffffffff, 0xc0998,
1130 0x3500, 0xffffffff, 0x1a9,
1131 0x3504, 0xffffffff, 0x409a7,
1132 0x3500, 0xffffffff, 0x1af,
1133 0x3504, 0xffffffff, 0xcdc,
1134 0x3500, 0xffffffff, 0x1b1,
1135 0x3504, 0xffffffff, 0x800,
1136 0x3508, 0xffffffff, 0x6c9b2000,
1137 0x3510, 0xfc00, 0x2000,
1138 0x3544, 0xffffffff, 0xfc0,
1139 0x28d4, 0x00000100, 0x100
1140};
1141
1142static void si_init_golden_registers(struct radeon_device *rdev)
1143{
1144 switch (rdev->family) {
1145 case CHIP_TAHITI:
1146 radeon_program_register_sequence(rdev,
1147 tahiti_golden_registers,
1148 (const u32)ARRAY_SIZE(tahiti_golden_registers));
1149 radeon_program_register_sequence(rdev,
1150 tahiti_golden_rlc_registers,
1151 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1152 radeon_program_register_sequence(rdev,
1153 tahiti_mgcg_cgcg_init,
1154 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1155 radeon_program_register_sequence(rdev,
1156 tahiti_golden_registers2,
1157 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1158 break;
1159 case CHIP_PITCAIRN:
1160 radeon_program_register_sequence(rdev,
1161 pitcairn_golden_registers,
1162 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1163 radeon_program_register_sequence(rdev,
1164 pitcairn_golden_rlc_registers,
1165 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1166 radeon_program_register_sequence(rdev,
1167 pitcairn_mgcg_cgcg_init,
1168 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1169 break;
1170 case CHIP_VERDE:
1171 radeon_program_register_sequence(rdev,
1172 verde_golden_registers,
1173 (const u32)ARRAY_SIZE(verde_golden_registers));
1174 radeon_program_register_sequence(rdev,
1175 verde_golden_rlc_registers,
1176 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1177 radeon_program_register_sequence(rdev,
1178 verde_mgcg_cgcg_init,
1179 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1180 radeon_program_register_sequence(rdev,
1181 verde_pg_init,
1182 (const u32)ARRAY_SIZE(verde_pg_init));
1183 break;
1184 case CHIP_OLAND:
1185 radeon_program_register_sequence(rdev,
1186 oland_golden_registers,
1187 (const u32)ARRAY_SIZE(oland_golden_registers));
1188 radeon_program_register_sequence(rdev,
1189 oland_golden_rlc_registers,
1190 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1191 radeon_program_register_sequence(rdev,
1192 oland_mgcg_cgcg_init,
1193 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1194 break;
1195 case CHIP_HAINAN:
1196 radeon_program_register_sequence(rdev,
1197 hainan_golden_registers,
1198 (const u32)ARRAY_SIZE(hainan_golden_registers));
1199 radeon_program_register_sequence(rdev,
1200 hainan_golden_registers2,
1201 (const u32)ARRAY_SIZE(hainan_golden_registers2));
1202 radeon_program_register_sequence(rdev,
1203 hainan_mgcg_cgcg_init,
1204 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1205 break;
1206 default:
1207 break;
1208 }
1209}
1210
b403bed8
MN
1211#define PCIE_BUS_CLK 10000
1212#define TCLK (PCIE_BUS_CLK / 10)
1213
1214/**
1215 * si_get_xclk - get the xclk
1216 *
1217 * @rdev: radeon_device pointer
1218 *
1219 * Returns the reference clock used by the gfx engine
1220 * (SI).
1221 */
1222u32 si_get_xclk(struct radeon_device *rdev)
1223{
1224 u32 reference_clock = rdev->clock.spll.reference_freq;
1225 u32 tmp;
1226
1227 tmp = RREG32(CG_CLKPIN_CNTL_2);
1228 if (tmp & MUX_TCLK_TO_XCLK)
1229 return TCLK;
1230
1231 tmp = RREG32(CG_CLKPIN_CNTL);
1232 if (tmp & XTALIN_DIVIDE)
1233 return reference_clock / 4;
1234
1235 return reference_clock;
1236}
926deccb
FT
1237
1238/* get temperature in millidegrees */
1239int si_get_temp(struct radeon_device *rdev)
1240{
1241 u32 temp;
1242 int actual_temp = 0;
1243
1244 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
1245 CTF_TEMP_SHIFT;
1246
1247 if (temp & 0x200)
1248 actual_temp = 255;
1249 else
1250 actual_temp = temp & 0x1ff;
1251
1252 actual_temp = (actual_temp * 1000);
1253
1254 return actual_temp;
1255}
1256
1257#define TAHITI_IO_MC_REGS_SIZE 36
1258
1259static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1260 {0x0000006f, 0x03044000},
1261 {0x00000070, 0x0480c018},
1262 {0x00000071, 0x00000040},
1263 {0x00000072, 0x01000000},
1264 {0x00000074, 0x000000ff},
1265 {0x00000075, 0x00143400},
1266 {0x00000076, 0x08ec0800},
1267 {0x00000077, 0x040000cc},
1268 {0x00000079, 0x00000000},
1269 {0x0000007a, 0x21000409},
1270 {0x0000007c, 0x00000000},
1271 {0x0000007d, 0xe8000000},
1272 {0x0000007e, 0x044408a8},
1273 {0x0000007f, 0x00000003},
1274 {0x00000080, 0x00000000},
1275 {0x00000081, 0x01000000},
1276 {0x00000082, 0x02000000},
1277 {0x00000083, 0x00000000},
1278 {0x00000084, 0xe3f3e4f4},
1279 {0x00000085, 0x00052024},
1280 {0x00000087, 0x00000000},
1281 {0x00000088, 0x66036603},
1282 {0x00000089, 0x01000000},
1283 {0x0000008b, 0x1c0a0000},
1284 {0x0000008c, 0xff010000},
1285 {0x0000008e, 0xffffefff},
1286 {0x0000008f, 0xfff3efff},
1287 {0x00000090, 0xfff3efbf},
1288 {0x00000094, 0x00101101},
1289 {0x00000095, 0x00000fff},
1290 {0x00000096, 0x00116fff},
1291 {0x00000097, 0x60010000},
1292 {0x00000098, 0x10010000},
1293 {0x00000099, 0x00006000},
1294 {0x0000009a, 0x00001000},
1295 {0x0000009f, 0x00a77400}
1296};
1297
1298static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1299 {0x0000006f, 0x03044000},
1300 {0x00000070, 0x0480c018},
1301 {0x00000071, 0x00000040},
1302 {0x00000072, 0x01000000},
1303 {0x00000074, 0x000000ff},
1304 {0x00000075, 0x00143400},
1305 {0x00000076, 0x08ec0800},
1306 {0x00000077, 0x040000cc},
1307 {0x00000079, 0x00000000},
1308 {0x0000007a, 0x21000409},
1309 {0x0000007c, 0x00000000},
1310 {0x0000007d, 0xe8000000},
1311 {0x0000007e, 0x044408a8},
1312 {0x0000007f, 0x00000003},
1313 {0x00000080, 0x00000000},
1314 {0x00000081, 0x01000000},
1315 {0x00000082, 0x02000000},
1316 {0x00000083, 0x00000000},
1317 {0x00000084, 0xe3f3e4f4},
1318 {0x00000085, 0x00052024},
1319 {0x00000087, 0x00000000},
1320 {0x00000088, 0x66036603},
1321 {0x00000089, 0x01000000},
1322 {0x0000008b, 0x1c0a0000},
1323 {0x0000008c, 0xff010000},
1324 {0x0000008e, 0xffffefff},
1325 {0x0000008f, 0xfff3efff},
1326 {0x00000090, 0xfff3efbf},
1327 {0x00000094, 0x00101101},
1328 {0x00000095, 0x00000fff},
1329 {0x00000096, 0x00116fff},
1330 {0x00000097, 0x60010000},
1331 {0x00000098, 0x10010000},
1332 {0x00000099, 0x00006000},
1333 {0x0000009a, 0x00001000},
1334 {0x0000009f, 0x00a47400}
1335};
1336
1337static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1338 {0x0000006f, 0x03044000},
1339 {0x00000070, 0x0480c018},
1340 {0x00000071, 0x00000040},
1341 {0x00000072, 0x01000000},
1342 {0x00000074, 0x000000ff},
1343 {0x00000075, 0x00143400},
1344 {0x00000076, 0x08ec0800},
1345 {0x00000077, 0x040000cc},
1346 {0x00000079, 0x00000000},
1347 {0x0000007a, 0x21000409},
1348 {0x0000007c, 0x00000000},
1349 {0x0000007d, 0xe8000000},
1350 {0x0000007e, 0x044408a8},
1351 {0x0000007f, 0x00000003},
1352 {0x00000080, 0x00000000},
1353 {0x00000081, 0x01000000},
1354 {0x00000082, 0x02000000},
1355 {0x00000083, 0x00000000},
1356 {0x00000084, 0xe3f3e4f4},
1357 {0x00000085, 0x00052024},
1358 {0x00000087, 0x00000000},
1359 {0x00000088, 0x66036603},
1360 {0x00000089, 0x01000000},
1361 {0x0000008b, 0x1c0a0000},
1362 {0x0000008c, 0xff010000},
1363 {0x0000008e, 0xffffefff},
1364 {0x0000008f, 0xfff3efff},
1365 {0x00000090, 0xfff3efbf},
1366 {0x00000094, 0x00101101},
1367 {0x00000095, 0x00000fff},
1368 {0x00000096, 0x00116fff},
1369 {0x00000097, 0x60010000},
1370 {0x00000098, 0x10010000},
1371 {0x00000099, 0x00006000},
1372 {0x0000009a, 0x00001000},
1373 {0x0000009f, 0x00a37400}
1374};
1375
b403bed8
MN
1376static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1377 {0x0000006f, 0x03044000},
1378 {0x00000070, 0x0480c018},
1379 {0x00000071, 0x00000040},
1380 {0x00000072, 0x01000000},
1381 {0x00000074, 0x000000ff},
1382 {0x00000075, 0x00143400},
1383 {0x00000076, 0x08ec0800},
1384 {0x00000077, 0x040000cc},
1385 {0x00000079, 0x00000000},
1386 {0x0000007a, 0x21000409},
1387 {0x0000007c, 0x00000000},
1388 {0x0000007d, 0xe8000000},
1389 {0x0000007e, 0x044408a8},
1390 {0x0000007f, 0x00000003},
1391 {0x00000080, 0x00000000},
1392 {0x00000081, 0x01000000},
1393 {0x00000082, 0x02000000},
1394 {0x00000083, 0x00000000},
1395 {0x00000084, 0xe3f3e4f4},
1396 {0x00000085, 0x00052024},
1397 {0x00000087, 0x00000000},
1398 {0x00000088, 0x66036603},
1399 {0x00000089, 0x01000000},
1400 {0x0000008b, 0x1c0a0000},
1401 {0x0000008c, 0xff010000},
1402 {0x0000008e, 0xffffefff},
1403 {0x0000008f, 0xfff3efff},
1404 {0x00000090, 0xfff3efbf},
1405 {0x00000094, 0x00101101},
1406 {0x00000095, 0x00000fff},
1407 {0x00000096, 0x00116fff},
1408 {0x00000097, 0x60010000},
1409 {0x00000098, 0x10010000},
1410 {0x00000099, 0x00006000},
1411 {0x0000009a, 0x00001000},
1412 {0x0000009f, 0x00a17730}
1413};
1414
f43cf1b1
MN
1415static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1416 {0x0000006f, 0x03044000},
1417 {0x00000070, 0x0480c018},
1418 {0x00000071, 0x00000040},
1419 {0x00000072, 0x01000000},
1420 {0x00000074, 0x000000ff},
1421 {0x00000075, 0x00143400},
1422 {0x00000076, 0x08ec0800},
1423 {0x00000077, 0x040000cc},
1424 {0x00000079, 0x00000000},
1425 {0x0000007a, 0x21000409},
1426 {0x0000007c, 0x00000000},
1427 {0x0000007d, 0xe8000000},
1428 {0x0000007e, 0x044408a8},
1429 {0x0000007f, 0x00000003},
1430 {0x00000080, 0x00000000},
1431 {0x00000081, 0x01000000},
1432 {0x00000082, 0x02000000},
1433 {0x00000083, 0x00000000},
1434 {0x00000084, 0xe3f3e4f4},
1435 {0x00000085, 0x00052024},
1436 {0x00000087, 0x00000000},
1437 {0x00000088, 0x66036603},
1438 {0x00000089, 0x01000000},
1439 {0x0000008b, 0x1c0a0000},
1440 {0x0000008c, 0xff010000},
1441 {0x0000008e, 0xffffefff},
1442 {0x0000008f, 0xfff3efff},
1443 {0x00000090, 0xfff3efbf},
1444 {0x00000094, 0x00101101},
1445 {0x00000095, 0x00000fff},
1446 {0x00000096, 0x00116fff},
1447 {0x00000097, 0x60010000},
1448 {0x00000098, 0x10010000},
1449 {0x00000099, 0x00006000},
1450 {0x0000009a, 0x00001000},
1451 {0x0000009f, 0x00a07730}
1452};
1453
926deccb
FT
1454/* ucode loading */
1455static int si_mc_load_microcode(struct radeon_device *rdev)
1456{
1457 const __be32 *fw_data;
1458 u32 running, blackout = 0;
1459 u32 *io_mc_regs;
1460 int i, ucode_size, regs_size;
1461
1462 if (!rdev->mc_fw)
1463 return -EINVAL;
1464
1465 switch (rdev->family) {
1466 case CHIP_TAHITI:
1467 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
1468 ucode_size = SI_MC_UCODE_SIZE;
1469 regs_size = TAHITI_IO_MC_REGS_SIZE;
1470 break;
1471 case CHIP_PITCAIRN:
1472 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
1473 ucode_size = SI_MC_UCODE_SIZE;
1474 regs_size = TAHITI_IO_MC_REGS_SIZE;
1475 break;
1476 case CHIP_VERDE:
1477 default:
1478 io_mc_regs = (u32 *)&verde_io_mc_regs;
1479 ucode_size = SI_MC_UCODE_SIZE;
1480 regs_size = TAHITI_IO_MC_REGS_SIZE;
1481 break;
b403bed8
MN
1482 case CHIP_OLAND:
1483 io_mc_regs = (u32 *)&oland_io_mc_regs;
1484 ucode_size = OLAND_MC_UCODE_SIZE;
1485 regs_size = TAHITI_IO_MC_REGS_SIZE;
1486 break;
f43cf1b1
MN
1487 case CHIP_HAINAN:
1488 io_mc_regs = (u32 *)&hainan_io_mc_regs;
1489 ucode_size = OLAND_MC_UCODE_SIZE;
1490 regs_size = TAHITI_IO_MC_REGS_SIZE;
1491 break;
926deccb
FT
1492 }
1493
1494 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1495
1496 if (running == 0) {
1497 if (running) {
1498 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1499 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1500 }
1501
1502 /* reset the engine and set to writable */
1503 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1504 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1505
1506 /* load mc io regs */
1507 for (i = 0; i < regs_size; i++) {
1508 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1509 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1510 }
1511 /* load the MC ucode */
1512 fw_data = (const __be32 *)rdev->mc_fw->data;
1513 for (i = 0; i < ucode_size; i++)
1514 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1515
1516 /* put the engine back into the active state */
1517 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1518 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1519 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1520
1521 /* wait for training to complete */
1522 for (i = 0; i < rdev->usec_timeout; i++) {
1523 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1524 break;
1525 DRM_UDELAY(1);
1526 }
1527 for (i = 0; i < rdev->usec_timeout; i++) {
1528 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1529 break;
1530 DRM_UDELAY(1);
1531 }
1532
1533 if (running)
1534 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
1535 }
1536
1537 return 0;
1538}
1539
1540static int si_init_microcode(struct radeon_device *rdev)
1541{
1542 const char *chip_name;
1543 const char *rlc_chip_name;
1544 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
57e252bf 1545 size_t smc_req_size;
926deccb
FT
1546 char fw_name[30];
1547 int err;
1548
1549 DRM_DEBUG("\n");
1550
1551 switch (rdev->family) {
1552 case CHIP_TAHITI:
1553 chip_name = "TAHITI";
1554 rlc_chip_name = "TAHITI";
1555 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1556 me_req_size = SI_PM4_UCODE_SIZE * 4;
1557 ce_req_size = SI_CE_UCODE_SIZE * 4;
1558 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1559 mc_req_size = SI_MC_UCODE_SIZE * 4;
57e252bf 1560 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
926deccb
FT
1561 break;
1562 case CHIP_PITCAIRN:
1563 chip_name = "PITCAIRN";
1564 rlc_chip_name = "PITCAIRN";
1565 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1566 me_req_size = SI_PM4_UCODE_SIZE * 4;
1567 ce_req_size = SI_CE_UCODE_SIZE * 4;
1568 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1569 mc_req_size = SI_MC_UCODE_SIZE * 4;
57e252bf 1570 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
926deccb
FT
1571 break;
1572 case CHIP_VERDE:
1573 chip_name = "VERDE";
1574 rlc_chip_name = "VERDE";
1575 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1576 me_req_size = SI_PM4_UCODE_SIZE * 4;
1577 ce_req_size = SI_CE_UCODE_SIZE * 4;
1578 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1579 mc_req_size = SI_MC_UCODE_SIZE * 4;
57e252bf 1580 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
926deccb 1581 break;
b403bed8
MN
1582 case CHIP_OLAND:
1583 chip_name = "OLAND";
1584 rlc_chip_name = "OLAND";
1585 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1586 me_req_size = SI_PM4_UCODE_SIZE * 4;
1587 ce_req_size = SI_CE_UCODE_SIZE * 4;
1588 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1589 mc_req_size = OLAND_MC_UCODE_SIZE * 4;
57e252bf 1590 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
b403bed8 1591 break;
f43cf1b1
MN
1592 case CHIP_HAINAN:
1593 chip_name = "HAINAN";
1594 rlc_chip_name = "HAINAN";
1595 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1596 me_req_size = SI_PM4_UCODE_SIZE * 4;
1597 ce_req_size = SI_CE_UCODE_SIZE * 4;
1598 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1599 mc_req_size = OLAND_MC_UCODE_SIZE * 4;
57e252bf 1600 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
f43cf1b1 1601 break;
926deccb
FT
1602 default: panic("%s: Unsupported family %d", __func__, rdev->family);
1603 }
1604
1605 DRM_INFO("Loading %s Microcode\n", chip_name);
1606 err = 0;
1607
1608 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
1609 rdev->pfp_fw = firmware_get(fw_name);
1610 if (rdev->pfp_fw == NULL) {
1611 err = -ENOENT;
1612 goto out;
1613 }
1614 if (rdev->pfp_fw->datasize != pfp_req_size) {
1615 DRM_ERROR(
1616 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1617 rdev->pfp_fw->datasize, fw_name);
1618 err = -EINVAL;
1619 goto out;
1620 }
1621
1622 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
1623 rdev->me_fw = firmware_get(fw_name);
1624 if (rdev->me_fw == NULL) {
1625 err = -ENOENT;
1626 goto out;
1627 }
1628 if (rdev->me_fw->datasize != me_req_size) {
1629 DRM_ERROR(
1630 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1631 rdev->me_fw->datasize, fw_name);
1632 err = -EINVAL;
1633 }
1634
1635 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_ce", chip_name);
1636 rdev->ce_fw = firmware_get(fw_name);
1637 if (rdev->ce_fw == NULL) {
1638 err = -ENOENT;
1639 goto out;
1640 }
1641 if (rdev->ce_fw->datasize != ce_req_size) {
1642 DRM_ERROR(
1643 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1644 rdev->ce_fw->datasize, fw_name);
1645 err = -EINVAL;
1646 }
1647
1648 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc",
1649 rlc_chip_name);
1650 rdev->rlc_fw = firmware_get(fw_name);
1651 if (rdev->rlc_fw == NULL) {
1652 err = -ENOENT;
1653 goto out;
1654 }
1655 if (rdev->rlc_fw->datasize != rlc_req_size) {
1656 DRM_ERROR(
1657 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
1658 rdev->rlc_fw->datasize, fw_name);
1659 err = -EINVAL;
1660 }
1661
1662 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mc", chip_name);
1663 rdev->mc_fw = firmware_get(fw_name);
1664 if (rdev->mc_fw == NULL) {
1665 err = -ENOENT;
1666 goto out;
1667 }
1668 if (rdev->mc_fw->datasize != mc_req_size) {
1669 DRM_ERROR(
1670 "si_mc: Bogus length %zu in firmware \"%s\"\n",
1671 rdev->mc_fw->datasize, fw_name);
1672 err = -EINVAL;
1673 }
1674
57e252bf
MN
1675 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", chip_name);
1676 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1677 if (err) {
1678 printk(KERN_ERR
1679 "smc: error loading firmware \"%s\"\n",
1680 fw_name);
1681 release_firmware(rdev->smc_fw);
1682 rdev->smc_fw = NULL;
1683 } else if (rdev->smc_fw->datasize != smc_req_size) {
1684 DRM_ERROR(
1685 "si_smc: Bogus length %zu in firmware \"%s\"\n",
1686 rdev->smc_fw->datasize, fw_name);
1687 err = -EINVAL;
1688 }
1689
926deccb
FT
1690out:
1691 if (err) {
1692 if (err != -EINVAL)
1693 DRM_ERROR(
1694 "si_cp: Failed to load firmware \"%s\"\n",
1695 fw_name);
1696 if (rdev->pfp_fw != NULL) {
1697 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD);
1698 rdev->pfp_fw = NULL;
1699 }
1700 if (rdev->me_fw != NULL) {
1701 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
1702 rdev->me_fw = NULL;
1703 }
1704 if (rdev->ce_fw != NULL) {
1705 firmware_put(rdev->ce_fw, FIRMWARE_UNLOAD);
1706 rdev->ce_fw = NULL;
1707 }
1708 if (rdev->rlc_fw != NULL) {
1709 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD);
1710 rdev->rlc_fw = NULL;
1711 }
1712 if (rdev->mc_fw != NULL) {
1713 firmware_put(rdev->mc_fw, FIRMWARE_UNLOAD);
1714 rdev->mc_fw = NULL;
1715 }
57e252bf
MN
1716 if (rdev->smc_fw != NULL) {
1717 firmware_put(rdev->smc_fw, FIRMWARE_UNLOAD);
1718 rdev->smc_fw = NULL;
1719 }
926deccb
FT
1720 }
1721 return err;
1722}
1723
1724/**
1725 * si_fini_microcode - drop the firmwares image references
1726 *
1727 * @rdev: radeon_device pointer
1728 *
1729 * Drop the pfp, me, rlc, mc and ce firmware image references.
1730 * Called at driver shutdown.
1731 */
1732static void si_fini_microcode(struct radeon_device *rdev)
1733{
1734
1735 if (rdev->pfp_fw != NULL) {
1736 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD);
1737 rdev->pfp_fw = NULL;
1738 }
1739
1740 if (rdev->me_fw != NULL) {
1741 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
1742 rdev->me_fw = NULL;
1743 }
1744
1745 if (rdev->rlc_fw != NULL) {
1746 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD);
1747 rdev->rlc_fw = NULL;
1748 }
1749
1750 if (rdev->mc_fw != NULL) {
1751 firmware_put(rdev->mc_fw, FIRMWARE_UNLOAD);
1752 rdev->mc_fw = NULL;
1753 }
1754
57e252bf
MN
1755 if (rdev->smc_fw != NULL) {
1756 firmware_put(rdev->smc_fw, FIRMWARE_UNLOAD);
1757 rdev->smc_fw = NULL;
1758 }
1759
926deccb
FT
1760 if (rdev->ce_fw != NULL) {
1761 firmware_put(rdev->ce_fw, FIRMWARE_UNLOAD);
1762 rdev->ce_fw = NULL;
1763 }
1764}
1765
1766/* watermark setup */
1767static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
1768 struct radeon_crtc *radeon_crtc,
1769 struct drm_display_mode *mode,
1770 struct drm_display_mode *other_mode)
1771{
1772 u32 tmp;
1773 /*
1774 * Line Buffer Setup
1775 * There are 3 line buffers, each one shared by 2 display controllers.
1776 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1777 * the display controllers. The paritioning is done via one of four
1778 * preset allocations specified in bits 21:20:
1779 * 0 - half lb
1780 * 2 - whole lb, other crtc must be disabled
1781 */
1782 /* this can get tricky if we have two large displays on a paired group
1783 * of crtcs. Ideally for multiple large displays we'd assign them to
1784 * non-linked crtcs for maximum line buffer allocation.
1785 */
1786 if (radeon_crtc->base.enabled && mode) {
1787 if (other_mode)
1788 tmp = 0; /* 1/2 */
1789 else
1790 tmp = 2; /* whole */
1791 } else
1792 tmp = 0;
1793
1794 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
1795 DC_LB_MEMORY_CONFIG(tmp));
1796
1797 if (radeon_crtc->base.enabled && mode) {
1798 switch (tmp) {
1799 case 0:
1800 default:
1801 return 4096 * 2;
1802 case 2:
1803 return 8192 * 2;
1804 }
1805 }
1806
1807 /* controller not enabled, so no lb used */
1808 return 0;
1809}
1810
1811static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
1812{
1813 u32 tmp = RREG32(MC_SHARED_CHMAP);
1814
1815 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1816 case 0:
1817 default:
1818 return 1;
1819 case 1:
1820 return 2;
1821 case 2:
1822 return 4;
1823 case 3:
1824 return 8;
1825 case 4:
1826 return 3;
1827 case 5:
1828 return 6;
1829 case 6:
1830 return 10;
1831 case 7:
1832 return 12;
1833 case 8:
1834 return 16;
1835 }
1836}
1837
1838struct dce6_wm_params {
1839 u32 dram_channels; /* number of dram channels */
1840 u32 yclk; /* bandwidth per dram data pin in kHz */
1841 u32 sclk; /* engine clock in kHz */
1842 u32 disp_clk; /* display clock in kHz */
1843 u32 src_width; /* viewport width */
1844 u32 active_time; /* active display time in ns */
1845 u32 blank_time; /* blank time in ns */
1846 bool interlaced; /* mode is interlaced */
1847 fixed20_12 vsc; /* vertical scale ratio */
1848 u32 num_heads; /* number of active crtcs */
1849 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
1850 u32 lb_size; /* line buffer allocated to pipe */
1851 u32 vtaps; /* vertical scaler taps */
1852};
1853
1854static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
1855{
1856 /* Calculate raw DRAM Bandwidth */
1857 fixed20_12 dram_efficiency; /* 0.7 */
1858 fixed20_12 yclk, dram_channels, bandwidth;
1859 fixed20_12 a;
1860
1861 a.full = dfixed_const(1000);
1862 yclk.full = dfixed_const(wm->yclk);
1863 yclk.full = dfixed_div(yclk, a);
1864 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1865 a.full = dfixed_const(10);
1866 dram_efficiency.full = dfixed_const(7);
1867 dram_efficiency.full = dfixed_div(dram_efficiency, a);
1868 bandwidth.full = dfixed_mul(dram_channels, yclk);
1869 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
1870
1871 return dfixed_trunc(bandwidth);
1872}
1873
1874static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
1875{
1876 /* Calculate DRAM Bandwidth and the part allocated to display. */
1877 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
1878 fixed20_12 yclk, dram_channels, bandwidth;
1879 fixed20_12 a;
1880
1881 a.full = dfixed_const(1000);
1882 yclk.full = dfixed_const(wm->yclk);
1883 yclk.full = dfixed_div(yclk, a);
1884 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1885 a.full = dfixed_const(10);
1886 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
1887 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
1888 bandwidth.full = dfixed_mul(dram_channels, yclk);
1889 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
1890
1891 return dfixed_trunc(bandwidth);
1892}
1893
1894static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
1895{
1896 /* Calculate the display Data return Bandwidth */
1897 fixed20_12 return_efficiency; /* 0.8 */
1898 fixed20_12 sclk, bandwidth;
1899 fixed20_12 a;
1900
1901 a.full = dfixed_const(1000);
1902 sclk.full = dfixed_const(wm->sclk);
1903 sclk.full = dfixed_div(sclk, a);
1904 a.full = dfixed_const(10);
1905 return_efficiency.full = dfixed_const(8);
1906 return_efficiency.full = dfixed_div(return_efficiency, a);
1907 a.full = dfixed_const(32);
1908 bandwidth.full = dfixed_mul(a, sclk);
1909 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1910
1911 return dfixed_trunc(bandwidth);
1912}
1913
1914static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
1915{
1916 return 32;
1917}
1918
1919static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
1920{
1921 /* Calculate the DMIF Request Bandwidth */
1922 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1923 fixed20_12 disp_clk, sclk, bandwidth;
1924 fixed20_12 a, b1, b2;
1925 u32 min_bandwidth;
1926
1927 a.full = dfixed_const(1000);
1928 disp_clk.full = dfixed_const(wm->disp_clk);
1929 disp_clk.full = dfixed_div(disp_clk, a);
1930 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
1931 b1.full = dfixed_mul(a, disp_clk);
1932
1933 a.full = dfixed_const(1000);
1934 sclk.full = dfixed_const(wm->sclk);
1935 sclk.full = dfixed_div(sclk, a);
1936 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
1937 b2.full = dfixed_mul(a, sclk);
1938
1939 a.full = dfixed_const(10);
1940 disp_clk_request_efficiency.full = dfixed_const(8);
1941 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1942
1943 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
1944
1945 a.full = dfixed_const(min_bandwidth);
1946 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
1947
1948 return dfixed_trunc(bandwidth);
1949}
1950
1951static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
1952{
1953 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1954 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
1955 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
1956 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
1957
1958 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1959}
1960
1961static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
1962{
1963 /* Calculate the display mode Average Bandwidth
1964 * DisplayMode should contain the source and destination dimensions,
1965 * timing, etc.
1966 */
1967 fixed20_12 bpp;
1968 fixed20_12 line_time;
1969 fixed20_12 src_width;
1970 fixed20_12 bandwidth;
1971 fixed20_12 a;
1972
1973 a.full = dfixed_const(1000);
1974 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1975 line_time.full = dfixed_div(line_time, a);
1976 bpp.full = dfixed_const(wm->bytes_per_pixel);
1977 src_width.full = dfixed_const(wm->src_width);
1978 bandwidth.full = dfixed_mul(src_width, bpp);
1979 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1980 bandwidth.full = dfixed_div(bandwidth, line_time);
1981
1982 return dfixed_trunc(bandwidth);
1983}
1984
1985static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
1986{
1987 /* First calcualte the latency in ns */
1988 u32 mc_latency = 2000; /* 2000 ns. */
1989 u32 available_bandwidth = dce6_available_bandwidth(wm);
1990 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1991 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1992 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1993 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1994 (wm->num_heads * cursor_line_pair_return_time);
1995 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1996 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1997 u32 tmp, dmif_size = 12288;
1998 fixed20_12 a, b, c;
1999
2000 if (wm->num_heads == 0)
2001 return 0;
2002
2003 a.full = dfixed_const(2);
2004 b.full = dfixed_const(1);
2005 if ((wm->vsc.full > a.full) ||
2006 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
2007 (wm->vtaps >= 5) ||
2008 ((wm->vsc.full >= a.full) && wm->interlaced))
2009 max_src_lines_per_dst_line = 4;
2010 else
2011 max_src_lines_per_dst_line = 2;
2012
2013 a.full = dfixed_const(available_bandwidth);
2014 b.full = dfixed_const(wm->num_heads);
2015 a.full = dfixed_div(a, b);
2016
2017 b.full = dfixed_const(mc_latency + 512);
2018 c.full = dfixed_const(wm->disp_clk);
2019 b.full = dfixed_div(b, c);
2020
2021 c.full = dfixed_const(dmif_size);
2022 b.full = dfixed_div(c, b);
2023
2024 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
2025
2026 b.full = dfixed_const(1000);
2027 c.full = dfixed_const(wm->disp_clk);
2028 b.full = dfixed_div(c, b);
2029 c.full = dfixed_const(wm->bytes_per_pixel);
2030 b.full = dfixed_mul(b, c);
2031
2032 lb_fill_bw = min(tmp, dfixed_trunc(b));
2033
2034 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
2035 b.full = dfixed_const(1000);
2036 c.full = dfixed_const(lb_fill_bw);
2037 b.full = dfixed_div(c, b);
2038 a.full = dfixed_div(a, b);
2039 line_fill_time = dfixed_trunc(a);
2040
2041 if (line_fill_time < wm->active_time)
2042 return latency;
2043 else
2044 return latency + (line_fill_time - wm->active_time);
2045
2046}
2047
2048static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2049{
2050 if (dce6_average_bandwidth(wm) <=
2051 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
2052 return true;
2053 else
2054 return false;
2055};
2056
2057static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
2058{
2059 if (dce6_average_bandwidth(wm) <=
2060 (dce6_available_bandwidth(wm) / wm->num_heads))
2061 return true;
2062 else
2063 return false;
2064};
2065
2066static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
2067{
2068 u32 lb_partitions = wm->lb_size / wm->src_width;
2069 u32 line_time = wm->active_time + wm->blank_time;
2070 u32 latency_tolerant_lines;
2071 u32 latency_hiding;
2072 fixed20_12 a;
2073
2074 a.full = dfixed_const(1);
2075 if (wm->vsc.full > a.full)
2076 latency_tolerant_lines = 1;
2077 else {
2078 if (lb_partitions <= (wm->vtaps + 1))
2079 latency_tolerant_lines = 1;
2080 else
2081 latency_tolerant_lines = 2;
2082 }
2083
2084 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
2085
2086 if (dce6_latency_watermark(wm) <= latency_hiding)
2087 return true;
2088 else
2089 return false;
2090}
2091
2092static void dce6_program_watermarks(struct radeon_device *rdev,
2093 struct radeon_crtc *radeon_crtc,
2094 u32 lb_size, u32 num_heads)
2095{
2096 struct drm_display_mode *mode = &radeon_crtc->base.mode;
57e252bf
MN
2097 struct dce6_wm_params wm_low, wm_high;
2098 u32 dram_channels;
926deccb
FT
2099 u32 pixel_period;
2100 u32 line_time = 0;
2101 u32 latency_watermark_a = 0, latency_watermark_b = 0;
2102 u32 priority_a_mark = 0, priority_b_mark = 0;
2103 u32 priority_a_cnt = PRIORITY_OFF;
2104 u32 priority_b_cnt = PRIORITY_OFF;
2105 u32 tmp, arb_control3;
2106 fixed20_12 a, b, c;
2107
2108 if (radeon_crtc->base.enabled && num_heads && mode) {
2109 pixel_period = 1000000 / (u32)mode->clock;
2110 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
2111 priority_a_cnt = 0;
2112 priority_b_cnt = 0;
2113
926deccb 2114 if (rdev->family == CHIP_ARUBA)
57e252bf 2115 dram_channels = evergreen_get_number_of_dram_channels(rdev);
926deccb 2116 else
57e252bf
MN
2117 dram_channels = si_get_number_of_dram_channels(rdev);
2118
2119 /* watermark for high clocks */
2120 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2121 wm_high.yclk =
2122 radeon_dpm_get_mclk(rdev, false) * 10;
2123 wm_high.sclk =
2124 radeon_dpm_get_sclk(rdev, false) * 10;
2125 } else {
2126 wm_high.yclk = rdev->pm.current_mclk * 10;
2127 wm_high.sclk = rdev->pm.current_sclk * 10;
2128 }
2129
2130 wm_high.disp_clk = mode->clock;
2131 wm_high.src_width = mode->crtc_hdisplay;
2132 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
2133 wm_high.blank_time = line_time - wm_high.active_time;
2134 wm_high.interlaced = false;
2135 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2136 wm_high.interlaced = true;
2137 wm_high.vsc = radeon_crtc->vsc;
2138 wm_high.vtaps = 1;
2139 if (radeon_crtc->rmx_type != RMX_OFF)
2140 wm_high.vtaps = 2;
2141 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
2142 wm_high.lb_size = lb_size;
2143 wm_high.dram_channels = dram_channels;
2144 wm_high.num_heads = num_heads;
2145
2146 /* watermark for low clocks */
2147 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2148 wm_low.yclk =
2149 radeon_dpm_get_mclk(rdev, true) * 10;
2150 wm_low.sclk =
2151 radeon_dpm_get_sclk(rdev, true) * 10;
2152 } else {
2153 wm_low.yclk = rdev->pm.current_mclk * 10;
2154 wm_low.sclk = rdev->pm.current_sclk * 10;
2155 }
2156
2157 wm_low.disp_clk = mode->clock;
2158 wm_low.src_width = mode->crtc_hdisplay;
2159 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
2160 wm_low.blank_time = line_time - wm_low.active_time;
2161 wm_low.interlaced = false;
2162 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2163 wm_low.interlaced = true;
2164 wm_low.vsc = radeon_crtc->vsc;
2165 wm_low.vtaps = 1;
2166 if (radeon_crtc->rmx_type != RMX_OFF)
2167 wm_low.vtaps = 2;
2168 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
2169 wm_low.lb_size = lb_size;
2170 wm_low.dram_channels = dram_channels;
2171 wm_low.num_heads = num_heads;
926deccb
FT
2172
2173 /* set for high clocks */
57e252bf 2174 latency_watermark_a = min(dce6_latency_watermark(&wm_high), (u32)65535);
926deccb 2175 /* set for low clocks */
57e252bf 2176 latency_watermark_b = min(dce6_latency_watermark(&wm_low), (u32)65535);
926deccb
FT
2177
2178 /* possibly force display priority to high */
2179 /* should really do this at mode validation time... */
57e252bf
MN
2180 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
2181 !dce6_average_bandwidth_vs_available_bandwidth(&wm_high) ||
2182 !dce6_check_latency_hiding(&wm_high) ||
2183 (rdev->disp_priority == 2)) {
2184 DRM_DEBUG_KMS("force priority to high\n");
2185 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2186 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2187 }
2188 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
2189 !dce6_average_bandwidth_vs_available_bandwidth(&wm_low) ||
2190 !dce6_check_latency_hiding(&wm_low) ||
926deccb
FT
2191 (rdev->disp_priority == 2)) {
2192 DRM_DEBUG_KMS("force priority to high\n");
2193 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2194 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2195 }
2196
2197 a.full = dfixed_const(1000);
2198 b.full = dfixed_const(mode->clock);
2199 b.full = dfixed_div(b, a);
2200 c.full = dfixed_const(latency_watermark_a);
2201 c.full = dfixed_mul(c, b);
2202 c.full = dfixed_mul(c, radeon_crtc->hsc);
2203 c.full = dfixed_div(c, a);
2204 a.full = dfixed_const(16);
2205 c.full = dfixed_div(c, a);
2206 priority_a_mark = dfixed_trunc(c);
2207 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
2208
2209 a.full = dfixed_const(1000);
2210 b.full = dfixed_const(mode->clock);
2211 b.full = dfixed_div(b, a);
2212 c.full = dfixed_const(latency_watermark_b);
2213 c.full = dfixed_mul(c, b);
2214 c.full = dfixed_mul(c, radeon_crtc->hsc);
2215 c.full = dfixed_div(c, a);
2216 a.full = dfixed_const(16);
2217 c.full = dfixed_div(c, a);
2218 priority_b_mark = dfixed_trunc(c);
2219 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
2220 }
2221
2222 /* select wm A */
2223 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2224 tmp = arb_control3;
2225 tmp &= ~LATENCY_WATERMARK_MASK(3);
2226 tmp |= LATENCY_WATERMARK_MASK(1);
2227 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2228 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2229 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
2230 LATENCY_HIGH_WATERMARK(line_time)));
2231 /* select wm B */
2232 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2233 tmp &= ~LATENCY_WATERMARK_MASK(3);
2234 tmp |= LATENCY_WATERMARK_MASK(2);
2235 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2236 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2237 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
2238 LATENCY_HIGH_WATERMARK(line_time)));
2239 /* restore original selection */
2240 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
2241
2242 /* write the priority marks */
2243 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2244 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
2245
57e252bf
MN
2246 /* save values for DPM */
2247 radeon_crtc->line_time = line_time;
2248 radeon_crtc->wm_high = latency_watermark_a;
2249 radeon_crtc->wm_low = latency_watermark_b;
926deccb
FT
2250}
2251
2252void dce6_bandwidth_update(struct radeon_device *rdev)
2253{
2254 struct drm_display_mode *mode0 = NULL;
2255 struct drm_display_mode *mode1 = NULL;
2256 u32 num_heads = 0, lb_size;
2257 int i;
2258
2259 radeon_update_display_priority(rdev);
2260
2261 for (i = 0; i < rdev->num_crtc; i++) {
2262 if (rdev->mode_info.crtcs[i]->base.enabled)
2263 num_heads++;
2264 }
2265 for (i = 0; i < rdev->num_crtc; i += 2) {
2266 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
2267 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
2268 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
2269 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
2270 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
2271 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
2272 }
2273}
2274
2275/*
2276 * Core functions
2277 */
2278static void si_tiling_mode_table_init(struct radeon_device *rdev)
2279{
2280 const u32 num_tile_mode_states = 32;
2281 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
2282
2283 switch (rdev->config.si.mem_row_size_in_kb) {
2284 case 1:
2285 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2286 break;
2287 case 2:
2288 default:
2289 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2290 break;
2291 case 4:
2292 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2293 break;
2294 }
2295
2296 if ((rdev->family == CHIP_TAHITI) ||
2297 (rdev->family == CHIP_PITCAIRN)) {
2298 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2299 switch (reg_offset) {
2300 case 0: /* non-AA compressed depth or any compressed stencil */
2301 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2302 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2303 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2304 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2305 NUM_BANKS(ADDR_SURF_16_BANK) |
2306 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2307 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2308 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2309 break;
2310 case 1: /* 2xAA/4xAA compressed depth only */
2311 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2312 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2313 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2314 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2315 NUM_BANKS(ADDR_SURF_16_BANK) |
2316 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2317 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2318 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2319 break;
2320 case 2: /* 8xAA compressed depth only */
2321 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2322 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2323 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2324 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2325 NUM_BANKS(ADDR_SURF_16_BANK) |
2326 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2327 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2328 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2329 break;
2330 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2331 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2332 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2333 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2334 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2335 NUM_BANKS(ADDR_SURF_16_BANK) |
2336 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2337 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2338 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2339 break;
2340 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2341 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2342 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2343 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2344 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2345 NUM_BANKS(ADDR_SURF_16_BANK) |
2346 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2347 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2348 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2349 break;
2350 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2351 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2352 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2353 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2354 TILE_SPLIT(split_equal_to_row_size) |
2355 NUM_BANKS(ADDR_SURF_16_BANK) |
2356 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2357 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2358 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2359 break;
2360 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2361 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2362 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2363 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2364 TILE_SPLIT(split_equal_to_row_size) |
2365 NUM_BANKS(ADDR_SURF_16_BANK) |
2366 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2367 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2368 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2369 break;
2370 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2371 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2372 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2373 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2374 TILE_SPLIT(split_equal_to_row_size) |
2375 NUM_BANKS(ADDR_SURF_16_BANK) |
2376 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2377 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2378 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2379 break;
2380 case 8: /* 1D and 1D Array Surfaces */
2381 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2382 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2383 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2384 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2385 NUM_BANKS(ADDR_SURF_16_BANK) |
2386 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2387 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2388 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2389 break;
2390 case 9: /* Displayable maps. */
2391 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2392 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2393 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2394 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2395 NUM_BANKS(ADDR_SURF_16_BANK) |
2396 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2397 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2398 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2399 break;
2400 case 10: /* Display 8bpp. */
2401 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2402 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2403 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2404 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2405 NUM_BANKS(ADDR_SURF_16_BANK) |
2406 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2407 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2408 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2409 break;
2410 case 11: /* Display 16bpp. */
2411 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2412 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2413 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2414 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2415 NUM_BANKS(ADDR_SURF_16_BANK) |
2416 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2417 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2418 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2419 break;
2420 case 12: /* Display 32bpp. */
2421 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2422 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2423 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2424 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2425 NUM_BANKS(ADDR_SURF_16_BANK) |
2426 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2427 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2428 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2429 break;
2430 case 13: /* Thin. */
2431 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2432 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2433 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2434 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2435 NUM_BANKS(ADDR_SURF_16_BANK) |
2436 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2439 break;
2440 case 14: /* Thin 8 bpp. */
2441 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2442 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2443 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2444 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2445 NUM_BANKS(ADDR_SURF_16_BANK) |
2446 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2447 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2448 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2449 break;
2450 case 15: /* Thin 16 bpp. */
2451 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2452 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2453 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2454 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2455 NUM_BANKS(ADDR_SURF_16_BANK) |
2456 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2459 break;
2460 case 16: /* Thin 32 bpp. */
2461 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2462 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2463 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2464 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2465 NUM_BANKS(ADDR_SURF_16_BANK) |
2466 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2467 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2468 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2469 break;
2470 case 17: /* Thin 64 bpp. */
2471 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2472 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2473 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2474 TILE_SPLIT(split_equal_to_row_size) |
2475 NUM_BANKS(ADDR_SURF_16_BANK) |
2476 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2477 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2478 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2479 break;
2480 case 21: /* 8 bpp PRT. */
2481 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2482 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2483 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2484 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2485 NUM_BANKS(ADDR_SURF_16_BANK) |
2486 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2488 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2489 break;
2490 case 22: /* 16 bpp PRT */
2491 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2492 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2493 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2494 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2495 NUM_BANKS(ADDR_SURF_16_BANK) |
2496 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2497 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2498 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2499 break;
2500 case 23: /* 32 bpp PRT */
2501 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2502 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2503 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2504 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2505 NUM_BANKS(ADDR_SURF_16_BANK) |
2506 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2509 break;
2510 case 24: /* 64 bpp PRT */
2511 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2512 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2513 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2514 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2515 NUM_BANKS(ADDR_SURF_16_BANK) |
2516 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2517 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2518 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2519 break;
2520 case 25: /* 128 bpp PRT */
2521 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2522 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2523 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2524 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2525 NUM_BANKS(ADDR_SURF_8_BANK) |
2526 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2529 break;
2530 default:
2531 gb_tile_moden = 0;
2532 break;
2533 }
f43cf1b1 2534 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
926deccb
FT
2535 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2536 }
b403bed8 2537 } else if ((rdev->family == CHIP_VERDE) ||
f43cf1b1
MN
2538 (rdev->family == CHIP_OLAND) ||
2539 (rdev->family == CHIP_HAINAN)) {
926deccb
FT
2540 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2541 switch (reg_offset) {
2542 case 0: /* non-AA compressed depth or any compressed stencil */
2543 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2544 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2545 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2546 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2547 NUM_BANKS(ADDR_SURF_16_BANK) |
2548 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2549 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2550 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2551 break;
2552 case 1: /* 2xAA/4xAA compressed depth only */
2553 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2554 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2555 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2556 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2557 NUM_BANKS(ADDR_SURF_16_BANK) |
2558 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2559 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2560 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2561 break;
2562 case 2: /* 8xAA compressed depth only */
2563 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2564 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2565 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2566 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2567 NUM_BANKS(ADDR_SURF_16_BANK) |
2568 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2569 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2570 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2571 break;
2572 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2573 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2574 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2575 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2576 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2577 NUM_BANKS(ADDR_SURF_16_BANK) |
2578 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2579 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2580 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2581 break;
2582 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2583 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2584 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2585 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2586 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2587 NUM_BANKS(ADDR_SURF_16_BANK) |
2588 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2589 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2590 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2591 break;
2592 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2593 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2594 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2595 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2596 TILE_SPLIT(split_equal_to_row_size) |
2597 NUM_BANKS(ADDR_SURF_16_BANK) |
2598 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2599 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2600 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2601 break;
2602 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2603 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2604 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2605 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2606 TILE_SPLIT(split_equal_to_row_size) |
2607 NUM_BANKS(ADDR_SURF_16_BANK) |
2608 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2609 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2610 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2611 break;
2612 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2613 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2614 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2615 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2616 TILE_SPLIT(split_equal_to_row_size) |
2617 NUM_BANKS(ADDR_SURF_16_BANK) |
2618 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2621 break;
2622 case 8: /* 1D and 1D Array Surfaces */
2623 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2624 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2625 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2626 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2627 NUM_BANKS(ADDR_SURF_16_BANK) |
2628 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2629 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2630 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2631 break;
2632 case 9: /* Displayable maps. */
2633 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2634 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2635 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2636 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2637 NUM_BANKS(ADDR_SURF_16_BANK) |
2638 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2640 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2641 break;
2642 case 10: /* Display 8bpp. */
2643 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2644 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2645 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2646 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2647 NUM_BANKS(ADDR_SURF_16_BANK) |
2648 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2649 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2650 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2651 break;
2652 case 11: /* Display 16bpp. */
2653 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2654 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2655 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2656 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2657 NUM_BANKS(ADDR_SURF_16_BANK) |
2658 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2659 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2660 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2661 break;
2662 case 12: /* Display 32bpp. */
2663 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2664 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2665 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2666 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2667 NUM_BANKS(ADDR_SURF_16_BANK) |
2668 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2669 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2670 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2671 break;
2672 case 13: /* Thin. */
2673 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2674 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2675 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2676 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2677 NUM_BANKS(ADDR_SURF_16_BANK) |
2678 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2681 break;
2682 case 14: /* Thin 8 bpp. */
2683 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2684 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2685 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2686 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2687 NUM_BANKS(ADDR_SURF_16_BANK) |
2688 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2689 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2690 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2691 break;
2692 case 15: /* Thin 16 bpp. */
2693 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2694 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2695 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2696 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2697 NUM_BANKS(ADDR_SURF_16_BANK) |
2698 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2699 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2700 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2701 break;
2702 case 16: /* Thin 32 bpp. */
2703 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2704 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2705 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2706 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2707 NUM_BANKS(ADDR_SURF_16_BANK) |
2708 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2709 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2710 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2711 break;
2712 case 17: /* Thin 64 bpp. */
2713 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2714 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2715 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2716 TILE_SPLIT(split_equal_to_row_size) |
2717 NUM_BANKS(ADDR_SURF_16_BANK) |
2718 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2721 break;
2722 case 21: /* 8 bpp PRT. */
2723 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2724 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2725 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2726 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2727 NUM_BANKS(ADDR_SURF_16_BANK) |
2728 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2729 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2730 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2731 break;
2732 case 22: /* 16 bpp PRT */
2733 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2734 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2735 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2736 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2737 NUM_BANKS(ADDR_SURF_16_BANK) |
2738 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2739 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2740 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2741 break;
2742 case 23: /* 32 bpp PRT */
2743 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2744 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2745 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2746 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2747 NUM_BANKS(ADDR_SURF_16_BANK) |
2748 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2749 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2750 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2751 break;
2752 case 24: /* 64 bpp PRT */
2753 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2754 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2755 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2756 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2757 NUM_BANKS(ADDR_SURF_16_BANK) |
2758 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2759 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2760 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2761 break;
2762 case 25: /* 128 bpp PRT */
2763 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2764 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2765 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2766 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2767 NUM_BANKS(ADDR_SURF_8_BANK) |
2768 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2769 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2770 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2771 break;
2772 default:
2773 gb_tile_moden = 0;
2774 break;
2775 }
f43cf1b1 2776 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
926deccb
FT
2777 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2778 }
2779 } else
2780 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
2781}
2782
2783static void si_select_se_sh(struct radeon_device *rdev,
2784 u32 se_num, u32 sh_num)
2785{
2786 u32 data = INSTANCE_BROADCAST_WRITES;
2787
2788 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
f43cf1b1 2789 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
926deccb
FT
2790 else if (se_num == 0xffffffff)
2791 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
2792 else if (sh_num == 0xffffffff)
2793 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
2794 else
2795 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
2796 WREG32(GRBM_GFX_INDEX, data);
2797}
2798
2799static u32 si_create_bitmask(u32 bit_width)
2800{
2801 u32 i, mask = 0;
2802
2803 for (i = 0; i < bit_width; i++) {
2804 mask <<= 1;
2805 mask |= 1;
2806 }
2807 return mask;
2808}
2809
2810static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
2811{
2812 u32 data, mask;
2813
2814 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2815 if (data & 1)
2816 data &= INACTIVE_CUS_MASK;
2817 else
2818 data = 0;
2819 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2820
2821 data >>= INACTIVE_CUS_SHIFT;
2822
2823 mask = si_create_bitmask(cu_per_sh);
2824
2825 return ~data & mask;
2826}
2827
2828static void si_setup_spi(struct radeon_device *rdev,
2829 u32 se_num, u32 sh_per_se,
2830 u32 cu_per_sh)
2831{
2832 int i, j, k;
2833 u32 data, mask, active_cu;
2834
2835 for (i = 0; i < se_num; i++) {
2836 for (j = 0; j < sh_per_se; j++) {
2837 si_select_se_sh(rdev, i, j);
2838 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
2839 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
2840
2841 mask = 1;
2842 for (k = 0; k < 16; k++) {
2843 mask <<= k;
2844 if (active_cu & mask) {
2845 data &= ~mask;
2846 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
2847 break;
2848 }
2849 }
2850 }
2851 }
2852 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
2853}
2854
2855static u32 si_get_rb_disabled(struct radeon_device *rdev,
2856 u32 max_rb_num, u32 se_num,
2857 u32 sh_per_se)
2858{
2859 u32 data, mask;
2860
2861 data = RREG32(CC_RB_BACKEND_DISABLE);
2862 if (data & 1)
2863 data &= BACKEND_DISABLE_MASK;
2864 else
2865 data = 0;
2866 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
2867
2868 data >>= BACKEND_DISABLE_SHIFT;
2869
2870 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
2871
2872 return data & mask;
2873}
2874
2875static void si_setup_rb(struct radeon_device *rdev,
2876 u32 se_num, u32 sh_per_se,
2877 u32 max_rb_num)
2878{
2879 int i, j;
2880 u32 data, mask;
2881 u32 disabled_rbs = 0;
2882 u32 enabled_rbs = 0;
2883
2884 for (i = 0; i < se_num; i++) {
2885 for (j = 0; j < sh_per_se; j++) {
2886 si_select_se_sh(rdev, i, j);
2887 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
2888 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
2889 }
2890 }
2891 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
2892
2893 mask = 1;
2894 for (i = 0; i < max_rb_num; i++) {
2895 if (!(disabled_rbs & mask))
2896 enabled_rbs |= mask;
2897 mask <<= 1;
2898 }
2899
2900 for (i = 0; i < se_num; i++) {
2901 si_select_se_sh(rdev, i, 0xffffffff);
2902 data = 0;
2903 for (j = 0; j < sh_per_se; j++) {
2904 switch (enabled_rbs & 3) {
2905 case 1:
2906 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
2907 break;
2908 case 2:
2909 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
2910 break;
2911 case 3:
2912 default:
2913 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
2914 break;
2915 }
2916 enabled_rbs >>= 2;
2917 }
2918 WREG32(PA_SC_RASTER_CONFIG, data);
2919 }
2920 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
2921}
2922
2923static void si_gpu_init(struct radeon_device *rdev)
2924{
2925 u32 gb_addr_config = 0;
2926 u32 mc_shared_chmap, mc_arb_ramcfg;
2927 u32 sx_debug_1;
2928 u32 hdp_host_path_cntl;
2929 u32 tmp;
2930 int i, j;
2931
2932 switch (rdev->family) {
2933 case CHIP_TAHITI:
2934 rdev->config.si.max_shader_engines = 2;
2935 rdev->config.si.max_tile_pipes = 12;
2936 rdev->config.si.max_cu_per_sh = 8;
2937 rdev->config.si.max_sh_per_se = 2;
2938 rdev->config.si.max_backends_per_se = 4;
2939 rdev->config.si.max_texture_channel_caches = 12;
2940 rdev->config.si.max_gprs = 256;
2941 rdev->config.si.max_gs_threads = 32;
2942 rdev->config.si.max_hw_contexts = 8;
2943
2944 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
2945 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
2946 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
2947 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
2948 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
2949 break;
2950 case CHIP_PITCAIRN:
2951 rdev->config.si.max_shader_engines = 2;
2952 rdev->config.si.max_tile_pipes = 8;
2953 rdev->config.si.max_cu_per_sh = 5;
2954 rdev->config.si.max_sh_per_se = 2;
2955 rdev->config.si.max_backends_per_se = 4;
2956 rdev->config.si.max_texture_channel_caches = 8;
2957 rdev->config.si.max_gprs = 256;
2958 rdev->config.si.max_gs_threads = 32;
2959 rdev->config.si.max_hw_contexts = 8;
2960
2961 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
2962 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
2963 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
2964 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
2965 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
2966 break;
2967 case CHIP_VERDE:
2968 default:
2969 rdev->config.si.max_shader_engines = 1;
2970 rdev->config.si.max_tile_pipes = 4;
f43cf1b1 2971 rdev->config.si.max_cu_per_sh = 5;
926deccb
FT
2972 rdev->config.si.max_sh_per_se = 2;
2973 rdev->config.si.max_backends_per_se = 4;
2974 rdev->config.si.max_texture_channel_caches = 4;
2975 rdev->config.si.max_gprs = 256;
2976 rdev->config.si.max_gs_threads = 32;
2977 rdev->config.si.max_hw_contexts = 8;
2978
b403bed8
MN
2979 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
2980 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
2981 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
2982 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
2983 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
2984 break;
2985 case CHIP_OLAND:
2986 rdev->config.si.max_shader_engines = 1;
2987 rdev->config.si.max_tile_pipes = 4;
2988 rdev->config.si.max_cu_per_sh = 6;
2989 rdev->config.si.max_sh_per_se = 1;
2990 rdev->config.si.max_backends_per_se = 2;
2991 rdev->config.si.max_texture_channel_caches = 4;
2992 rdev->config.si.max_gprs = 256;
2993 rdev->config.si.max_gs_threads = 16;
2994 rdev->config.si.max_hw_contexts = 8;
2995
926deccb
FT
2996 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
2997 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
2998 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
2999 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3000 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3001 break;
f43cf1b1
MN
3002 case CHIP_HAINAN:
3003 rdev->config.si.max_shader_engines = 1;
3004 rdev->config.si.max_tile_pipes = 4;
3005 rdev->config.si.max_cu_per_sh = 5;
3006 rdev->config.si.max_sh_per_se = 1;
3007 rdev->config.si.max_backends_per_se = 1;
3008 rdev->config.si.max_texture_channel_caches = 2;
3009 rdev->config.si.max_gprs = 256;
3010 rdev->config.si.max_gs_threads = 16;
3011 rdev->config.si.max_hw_contexts = 8;
3012
3013 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3014 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3015 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3016 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3017 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
3018 break;
926deccb
FT
3019 }
3020
3021 /* Initialize HDP */
3022 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3023 WREG32((0x2c14 + j), 0x00000000);
3024 WREG32((0x2c18 + j), 0x00000000);
3025 WREG32((0x2c1c + j), 0x00000000);
3026 WREG32((0x2c20 + j), 0x00000000);
3027 WREG32((0x2c24 + j), 0x00000000);
3028 }
3029
3030 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3031
3032 evergreen_fix_pci_max_read_req_size(rdev);
3033
3034 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3035
3036 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3037 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3038
3039 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
3040 rdev->config.si.mem_max_burst_length_bytes = 256;
3041 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3042 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3043 if (rdev->config.si.mem_row_size_in_kb > 4)
3044 rdev->config.si.mem_row_size_in_kb = 4;
3045 /* XXX use MC settings? */
3046 rdev->config.si.shader_engine_tile_size = 32;
3047 rdev->config.si.num_gpus = 1;
3048 rdev->config.si.multi_gpu_tile_size = 64;
3049
3050 /* fix up row size */
3051 gb_addr_config &= ~ROW_SIZE_MASK;
3052 switch (rdev->config.si.mem_row_size_in_kb) {
3053 case 1:
3054 default:
3055 gb_addr_config |= ROW_SIZE(0);
3056 break;
3057 case 2:
3058 gb_addr_config |= ROW_SIZE(1);
3059 break;
3060 case 4:
3061 gb_addr_config |= ROW_SIZE(2);
3062 break;
3063 }
3064
3065 /* setup tiling info dword. gb_addr_config is not adequate since it does
3066 * not have bank info, so create a custom tiling dword.
3067 * bits 3:0 num_pipes
3068 * bits 7:4 num_banks
3069 * bits 11:8 group_size
3070 * bits 15:12 row_size
3071 */
3072 rdev->config.si.tile_config = 0;
3073 switch (rdev->config.si.num_tile_pipes) {
3074 case 1:
3075 rdev->config.si.tile_config |= (0 << 0);
3076 break;
3077 case 2:
3078 rdev->config.si.tile_config |= (1 << 0);
3079 break;
3080 case 4:
3081 rdev->config.si.tile_config |= (2 << 0);
3082 break;
3083 case 8:
3084 default:
3085 /* XXX what about 12? */
3086 rdev->config.si.tile_config |= (3 << 0);
3087 break;
3088 }
3089 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
3090 case 0: /* four banks */
3091 rdev->config.si.tile_config |= 0 << 4;
3092 break;
3093 case 1: /* eight banks */
3094 rdev->config.si.tile_config |= 1 << 4;
3095 break;
3096 case 2: /* sixteen banks */
3097 default:
3098 rdev->config.si.tile_config |= 2 << 4;
3099 break;
3100 }
3101 rdev->config.si.tile_config |=
3102 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3103 rdev->config.si.tile_config |=
3104 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3105
3106 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3107 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
f43cf1b1 3108 WREG32(DMIF_ADDR_CALC, gb_addr_config);
926deccb
FT
3109 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3110 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
3111 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
f43cf1b1
MN
3112 if (rdev->has_uvd) {
3113 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3114 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3115 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3116 }
926deccb
FT
3117
3118 si_tiling_mode_table_init(rdev);
3119
3120 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
3121 rdev->config.si.max_sh_per_se,
3122 rdev->config.si.max_backends_per_se);
3123
3124 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
3125 rdev->config.si.max_sh_per_se,
3126 rdev->config.si.max_cu_per_sh);
3127
3128
3129 /* set HW defaults for 3D engine */
3130 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
3131 ROQ_IB2_START(0x2b)));
3132 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3133
3134 sx_debug_1 = RREG32(SX_DEBUG_1);
3135 WREG32(SX_DEBUG_1, sx_debug_1);
3136
3137 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3138
3139 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
3140 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
3141 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
3142 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
3143
3144 WREG32(VGT_NUM_INSTANCES, 1);
3145
3146 WREG32(CP_PERFMON_CNTL, 0);
3147
3148 WREG32(SQ_CONFIG, 0);
3149
3150 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3151 FORCE_EOV_MAX_REZ_CNT(255)));
3152
3153 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3154 AUTO_INVLD_EN(ES_AND_GS_AUTO));
3155
3156 WREG32(VGT_GS_VERTEX_REUSE, 16);
3157 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3158
3159 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
3160 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
3161 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
3162 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
3163 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
3164 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
3165 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
3166 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
3167
3168 tmp = RREG32(HDP_MISC_CNTL);
3169 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3170 WREG32(HDP_MISC_CNTL, tmp);
3171
3172 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3173 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3174
3175 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3176
3177 DRM_UDELAY(50);
3178}
3179
3180/*
3181 * GPU scratch registers helpers function.
3182 */
3183static void si_scratch_init(struct radeon_device *rdev)
3184{
3185 int i;
3186
3187 rdev->scratch.num_reg = 7;
3188 rdev->scratch.reg_base = SCRATCH_REG0;
3189 for (i = 0; i < rdev->scratch.num_reg; i++) {
3190 rdev->scratch.free[i] = true;
3191 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3192 }
3193}
3194
3195void si_fence_ring_emit(struct radeon_device *rdev,
3196 struct radeon_fence *fence)
3197{
3198 struct radeon_ring *ring = &rdev->ring[fence->ring];
3199 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3200
3201 /* flush read cache over gart */
3202 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3203 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3204 radeon_ring_write(ring, 0);
3205 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3206 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3207 PACKET3_TC_ACTION_ENA |
3208 PACKET3_SH_KCACHE_ACTION_ENA |
3209 PACKET3_SH_ICACHE_ACTION_ENA);
3210 radeon_ring_write(ring, 0xFFFFFFFF);
3211 radeon_ring_write(ring, 0);
3212 radeon_ring_write(ring, 10); /* poll interval */
3213 /* EVENT_WRITE_EOP - flush caches, send int */
3214 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3215 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
3216 radeon_ring_write(ring, addr & 0xffffffff);
3217 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
3218 radeon_ring_write(ring, fence->seq);
3219 radeon_ring_write(ring, 0);
3220}
3221
3222/*
3223 * IB stuff
3224 */
3225void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3226{
3227 struct radeon_ring *ring = &rdev->ring[ib->ring];
3228 u32 header;
3229
3230 if (ib->is_const_ib) {
3231 /* set switch buffer packet before const IB */
3232 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3233 radeon_ring_write(ring, 0);
3234
3235 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3236 } else {
3237 u32 next_rptr;
3238 if (ring->rptr_save_reg) {
3239 next_rptr = ring->wptr + 3 + 4 + 8;
3240 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3241 radeon_ring_write(ring, ((ring->rptr_save_reg -
3242 PACKET3_SET_CONFIG_REG_START) >> 2));
3243 radeon_ring_write(ring, next_rptr);
3244 } else if (rdev->wb.enabled) {
3245 next_rptr = ring->wptr + 5 + 4 + 8;
3246 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3247 radeon_ring_write(ring, (1 << 8));
3248 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3249 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3250 radeon_ring_write(ring, next_rptr);
3251 }
3252
3253 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3254 }
3255
3256 radeon_ring_write(ring, header);
3257 radeon_ring_write(ring,
3258#ifdef __BIG_ENDIAN
3259 (2 << 0) |
3260#endif
3261 (ib->gpu_addr & 0xFFFFFFFC));
3262 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3263 radeon_ring_write(ring, ib->length_dw |
3264 (ib->vm ? (ib->vm->id << 24) : 0));
3265
3266 if (!ib->is_const_ib) {
3267 /* flush read cache over gart for this vmid */
3268 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3269 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3270 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
3271 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3272 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3273 PACKET3_TC_ACTION_ENA |
3274 PACKET3_SH_KCACHE_ACTION_ENA |
3275 PACKET3_SH_ICACHE_ACTION_ENA);
3276 radeon_ring_write(ring, 0xFFFFFFFF);
3277 radeon_ring_write(ring, 0);
3278 radeon_ring_write(ring, 10); /* poll interval */
3279 }
3280}
3281
3282/*
3283 * CP.
3284 */
3285static void si_cp_enable(struct radeon_device *rdev, bool enable)
3286{
3287 if (enable)
3288 WREG32(CP_ME_CNTL, 0);
3289 else {
3290 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3291 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3292 WREG32(SCRATCH_UMSK, 0);
3293 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3294 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3295 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3296 }
3297 DRM_UDELAY(50);
3298}
3299
3300static int si_cp_load_microcode(struct radeon_device *rdev)
3301{
3302 const __be32 *fw_data;
3303 int i;
3304
3305 if (!rdev->me_fw || !rdev->pfp_fw)
3306 return -EINVAL;
3307
3308 si_cp_enable(rdev, false);
3309
3310 /* PFP */
3311 fw_data = (const __be32 *)rdev->pfp_fw->data;
3312 WREG32(CP_PFP_UCODE_ADDR, 0);
3313 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
3314 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
3315 WREG32(CP_PFP_UCODE_ADDR, 0);
3316
3317 /* CE */
3318 fw_data = (const __be32 *)rdev->ce_fw->data;
3319 WREG32(CP_CE_UCODE_ADDR, 0);
3320 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
3321 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
3322 WREG32(CP_CE_UCODE_ADDR, 0);
3323
3324 /* ME */
3325 fw_data = (const __be32 *)rdev->me_fw->data;
3326 WREG32(CP_ME_RAM_WADDR, 0);
3327 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
3328 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
3329 WREG32(CP_ME_RAM_WADDR, 0);
3330
3331 WREG32(CP_PFP_UCODE_ADDR, 0);
3332 WREG32(CP_CE_UCODE_ADDR, 0);
3333 WREG32(CP_ME_RAM_WADDR, 0);
3334 WREG32(CP_ME_RAM_RADDR, 0);
3335 return 0;
3336}
3337
3338static int si_cp_start(struct radeon_device *rdev)
3339{
3340 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3341 int r, i;
3342
3343 r = radeon_ring_lock(rdev, ring, 7 + 4);
3344 if (r) {
3345 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3346 return r;
3347 }
3348 /* init the CP */
3349 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
3350 radeon_ring_write(ring, 0x1);
3351 radeon_ring_write(ring, 0x0);
3352 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
3353 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
3354 radeon_ring_write(ring, 0);
3355 radeon_ring_write(ring, 0);
3356
3357 /* init the CE partitions */
3358 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3359 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3360 radeon_ring_write(ring, 0xc000);
3361 radeon_ring_write(ring, 0xe000);
3362 radeon_ring_unlock_commit(rdev, ring);
3363
3364 si_cp_enable(rdev, true);
3365
3366 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
3367 if (r) {
3368 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3369 return r;
3370 }
3371
3372 /* setup clear context state */
3373 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3374 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3375
3376 for (i = 0; i < si_default_size; i++)
3377 radeon_ring_write(ring, si_default_state[i]);
3378
3379 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3380 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3381
3382 /* set clear context state */
3383 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3384 radeon_ring_write(ring, 0);
3385
3386 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3387 radeon_ring_write(ring, 0x00000316);
3388 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
3389 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
3390
3391 radeon_ring_unlock_commit(rdev, ring);
3392
3393 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
3394 ring = &rdev->ring[i];
3395 r = radeon_ring_lock(rdev, ring, 2);
3396
3397 /* clear the compute context state */
3398 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
3399 radeon_ring_write(ring, 0);
3400
3401 radeon_ring_unlock_commit(rdev, ring);
3402 }
3403
3404 return 0;
3405}
3406
3407static void si_cp_fini(struct radeon_device *rdev)
3408{
3409 struct radeon_ring *ring;
3410 si_cp_enable(rdev, false);
3411
3412 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3413 radeon_ring_fini(rdev, ring);
3414 radeon_scratch_free(rdev, ring->rptr_save_reg);
3415
3416 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3417 radeon_ring_fini(rdev, ring);
3418 radeon_scratch_free(rdev, ring->rptr_save_reg);
3419
3420 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3421 radeon_ring_fini(rdev, ring);
3422 radeon_scratch_free(rdev, ring->rptr_save_reg);
3423}
3424
3425static int si_cp_resume(struct radeon_device *rdev)
3426{
3427 struct radeon_ring *ring;
3428 u32 tmp;
3429 u32 rb_bufsz;
3430 int r;
3431
3432 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
3433 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
3434 SOFT_RESET_PA |
3435 SOFT_RESET_VGT |
3436 SOFT_RESET_SPI |
3437 SOFT_RESET_SX));
3438 RREG32(GRBM_SOFT_RESET);
3439 DRM_MDELAY(15);
3440 WREG32(GRBM_SOFT_RESET, 0);
3441 RREG32(GRBM_SOFT_RESET);
3442
3443 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3444 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
3445
3446 /* Set the write pointer delay */
3447 WREG32(CP_RB_WPTR_DELAY, 0);
3448
3449 WREG32(CP_DEBUG, 0);
3450 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
3451
3452 /* ring 0 - compute and gfx */
3453 /* Set ring buffer size */
3454 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3455 rb_bufsz = drm_order(ring->ring_size / 8);
3456 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3457#ifdef __BIG_ENDIAN
3458 tmp |= BUF_SWAP_32BIT;
3459#endif
3460 WREG32(CP_RB0_CNTL, tmp);
3461
3462 /* Initialize the ring buffer's read and write pointers */
3463 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
3464 ring->wptr = 0;
3465 WREG32(CP_RB0_WPTR, ring->wptr);
3466
3467 /* set the wb address whether it's enabled or not */
3468 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
3469 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
3470
3471 if (rdev->wb.enabled)
3472 WREG32(SCRATCH_UMSK, 0xff);
3473 else {
3474 tmp |= RB_NO_UPDATE;
3475 WREG32(SCRATCH_UMSK, 0);
3476 }
3477
3478 DRM_MDELAY(1);
3479 WREG32(CP_RB0_CNTL, tmp);
3480
3481 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
3482
3483 ring->rptr = RREG32(CP_RB0_RPTR);
3484
3485 /* ring1 - compute only */
3486 /* Set ring buffer size */
3487 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3488 rb_bufsz = drm_order(ring->ring_size / 8);
3489 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3490#ifdef __BIG_ENDIAN
3491 tmp |= BUF_SWAP_32BIT;
3492#endif
3493 WREG32(CP_RB1_CNTL, tmp);
3494
3495 /* Initialize the ring buffer's read and write pointers */
3496 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
3497 ring->wptr = 0;
3498 WREG32(CP_RB1_WPTR, ring->wptr);
3499
3500 /* set the wb address whether it's enabled or not */
3501 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
3502 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
3503
3504 DRM_MDELAY(1);
3505 WREG32(CP_RB1_CNTL, tmp);
3506
3507 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
3508
3509 ring->rptr = RREG32(CP_RB1_RPTR);
3510
3511 /* ring2 - compute only */
3512 /* Set ring buffer size */
3513 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3514 rb_bufsz = drm_order(ring->ring_size / 8);
3515 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3516#ifdef __BIG_ENDIAN
3517 tmp |= BUF_SWAP_32BIT;
3518#endif
3519 WREG32(CP_RB2_CNTL, tmp);
3520
3521 /* Initialize the ring buffer's read and write pointers */
3522 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
3523 ring->wptr = 0;
3524 WREG32(CP_RB2_WPTR, ring->wptr);
3525
3526 /* set the wb address whether it's enabled or not */
3527 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
3528 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
3529
3530 DRM_MDELAY(1);
3531 WREG32(CP_RB2_CNTL, tmp);
3532
3533 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
3534
3535 ring->rptr = RREG32(CP_RB2_RPTR);
3536
3537 /* start the rings */
3538 si_cp_start(rdev);
3539 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
3540 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
3541 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
3542 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3543 if (r) {
3544 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3545 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3546 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3547 return r;
3548 }
3549 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
3550 if (r) {
3551 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3552 }
3553 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
3554 if (r) {
3555 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3556 }
3557
3558 return 0;
3559}
3560
b403bed8 3561static u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
926deccb 3562{
b403bed8
MN
3563 u32 reset_mask = 0;
3564 u32 tmp;
926deccb 3565
b403bed8
MN
3566 /* GRBM_STATUS */
3567 tmp = RREG32(GRBM_STATUS);
3568 if (tmp & (PA_BUSY | SC_BUSY |
3569 BCI_BUSY | SX_BUSY |
3570 TA_BUSY | VGT_BUSY |
3571 DB_BUSY | CB_BUSY |
3572 GDS_BUSY | SPI_BUSY |
3573 IA_BUSY | IA_BUSY_NO_DMA))
3574 reset_mask |= RADEON_RESET_GFX;
926deccb 3575
b403bed8
MN
3576 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
3577 CP_BUSY | CP_COHERENCY_BUSY))
3578 reset_mask |= RADEON_RESET_CP;
926deccb 3579
b403bed8
MN
3580 if (tmp & GRBM_EE_BUSY)
3581 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
926deccb 3582
b403bed8
MN
3583 /* GRBM_STATUS2 */
3584 tmp = RREG32(GRBM_STATUS2);
3585 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
3586 reset_mask |= RADEON_RESET_RLC;
926deccb 3587
b403bed8
MN
3588 /* DMA_STATUS_REG 0 */
3589 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
3590 if (!(tmp & DMA_IDLE))
3591 reset_mask |= RADEON_RESET_DMA;
926deccb 3592
b403bed8
MN
3593 /* DMA_STATUS_REG 1 */
3594 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
3595 if (!(tmp & DMA_IDLE))
3596 reset_mask |= RADEON_RESET_DMA1;
926deccb 3597
b403bed8
MN
3598 /* SRBM_STATUS2 */
3599 tmp = RREG32(SRBM_STATUS2);
3600 if (tmp & DMA_BUSY)
3601 reset_mask |= RADEON_RESET_DMA;
926deccb 3602
b403bed8
MN
3603 if (tmp & DMA1_BUSY)
3604 reset_mask |= RADEON_RESET_DMA1;
926deccb 3605
b403bed8
MN
3606 /* SRBM_STATUS */
3607 tmp = RREG32(SRBM_STATUS);
926deccb 3608
b403bed8
MN
3609 if (tmp & IH_BUSY)
3610 reset_mask |= RADEON_RESET_IH;
926deccb 3611
b403bed8
MN
3612 if (tmp & SEM_BUSY)
3613 reset_mask |= RADEON_RESET_SEM;
3614
3615 if (tmp & GRBM_RQ_PENDING)
3616 reset_mask |= RADEON_RESET_GRBM;
3617
3618 if (tmp & VMC_BUSY)
3619 reset_mask |= RADEON_RESET_VMC;
3620
3621 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
3622 MCC_BUSY | MCD_BUSY))
3623 reset_mask |= RADEON_RESET_MC;
926deccb 3624
b403bed8
MN
3625 if (evergreen_is_display_hung(rdev))
3626 reset_mask |= RADEON_RESET_DISPLAY;
3627
3628 /* VM_L2_STATUS */
3629 tmp = RREG32(VM_L2_STATUS);
3630 if (tmp & L2_BUSY)
3631 reset_mask |= RADEON_RESET_VMC;
3632
3633 /* Skip MC reset as it's mostly likely not hung, just busy */
3634 if (reset_mask & RADEON_RESET_MC) {
3635 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
3636 reset_mask &= ~RADEON_RESET_MC;
3637 }
3638
3639 return reset_mask;
926deccb
FT
3640}
3641
b403bed8 3642static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
926deccb
FT
3643{
3644 struct evergreen_mc_save save;
b403bed8
MN
3645 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3646 u32 tmp;
926deccb
FT
3647
3648 if (reset_mask == 0)
b403bed8 3649 return;
926deccb
FT
3650
3651 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
3652
b403bed8 3653 evergreen_print_gpu_status_regs(rdev);
926deccb
FT
3654 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3655 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3656 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3657 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3658
b403bed8
MN
3659 /* Disable CP parsing/prefetching */
3660 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
3661
3662 if (reset_mask & RADEON_RESET_DMA) {
3663 /* dma0 */
3664 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
3665 tmp &= ~DMA_RB_ENABLE;
3666 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
3667 }
3668 if (reset_mask & RADEON_RESET_DMA1) {
3669 /* dma1 */
3670 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
3671 tmp &= ~DMA_RB_ENABLE;
3672 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
3673 }
3674
3675 DRM_UDELAY(50);
3676
926deccb 3677 evergreen_mc_stop(rdev, &save);
b403bed8 3678 if (evergreen_mc_wait_for_idle(rdev)) {
926deccb
FT
3679 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3680 }
3681
b403bed8
MN
3682 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
3683 grbm_soft_reset = SOFT_RESET_CB |
3684 SOFT_RESET_DB |
3685 SOFT_RESET_GDS |
3686 SOFT_RESET_PA |
3687 SOFT_RESET_SC |
3688 SOFT_RESET_BCI |
3689 SOFT_RESET_SPI |
3690 SOFT_RESET_SX |
3691 SOFT_RESET_TC |
3692 SOFT_RESET_TA |
3693 SOFT_RESET_VGT |
3694 SOFT_RESET_IA;
3695 }
3696
3697 if (reset_mask & RADEON_RESET_CP) {
3698 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
3699
3700 srbm_soft_reset |= SOFT_RESET_GRBM;
3701 }
926deccb
FT
3702
3703 if (reset_mask & RADEON_RESET_DMA)
b403bed8
MN
3704 srbm_soft_reset |= SOFT_RESET_DMA;
3705
3706 if (reset_mask & RADEON_RESET_DMA1)
3707 srbm_soft_reset |= SOFT_RESET_DMA1;
3708
3709 if (reset_mask & RADEON_RESET_DISPLAY)
3710 srbm_soft_reset |= SOFT_RESET_DC;
3711
3712 if (reset_mask & RADEON_RESET_RLC)
3713 grbm_soft_reset |= SOFT_RESET_RLC;
3714
3715 if (reset_mask & RADEON_RESET_SEM)
3716 srbm_soft_reset |= SOFT_RESET_SEM;
3717
3718 if (reset_mask & RADEON_RESET_IH)
3719 srbm_soft_reset |= SOFT_RESET_IH;
3720
3721 if (reset_mask & RADEON_RESET_GRBM)
3722 srbm_soft_reset |= SOFT_RESET_GRBM;
3723
3724 if (reset_mask & RADEON_RESET_VMC)
3725 srbm_soft_reset |= SOFT_RESET_VMC;
3726
3727 if (reset_mask & RADEON_RESET_MC)
3728 srbm_soft_reset |= SOFT_RESET_MC;
3729
3730 if (grbm_soft_reset) {
3731 tmp = RREG32(GRBM_SOFT_RESET);
3732 tmp |= grbm_soft_reset;
3733 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3734 WREG32(GRBM_SOFT_RESET, tmp);
3735 tmp = RREG32(GRBM_SOFT_RESET);
3736
3737 DRM_UDELAY(50);
3738
3739 tmp &= ~grbm_soft_reset;
3740 WREG32(GRBM_SOFT_RESET, tmp);
3741 tmp = RREG32(GRBM_SOFT_RESET);
3742 }
3743
3744 if (srbm_soft_reset) {
3745 tmp = RREG32(SRBM_SOFT_RESET);
3746 tmp |= srbm_soft_reset;
3747 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3748 WREG32(SRBM_SOFT_RESET, tmp);
3749 tmp = RREG32(SRBM_SOFT_RESET);
3750
3751 DRM_UDELAY(50);
3752
3753 tmp &= ~srbm_soft_reset;
3754 WREG32(SRBM_SOFT_RESET, tmp);
3755 tmp = RREG32(SRBM_SOFT_RESET);
3756 }
926deccb
FT
3757
3758 /* Wait a little for things to settle down */
3759 DRM_UDELAY(50);
3760
3761 evergreen_mc_resume(rdev, &save);
b403bed8
MN
3762 DRM_UDELAY(50);
3763
3764 evergreen_print_gpu_status_regs(rdev);
926deccb
FT
3765}
3766
3767int si_asic_reset(struct radeon_device *rdev)
3768{
b403bed8
MN
3769 u32 reset_mask;
3770
3771 reset_mask = si_gpu_check_soft_reset(rdev);
3772
3773 if (reset_mask)
3774 r600_set_bios_scratch_engine_hung(rdev, true);
3775
3776 si_gpu_soft_reset(rdev, reset_mask);
3777
3778 reset_mask = si_gpu_check_soft_reset(rdev);
3779
3780 if (!reset_mask)
3781 r600_set_bios_scratch_engine_hung(rdev, false);
3782
3783 return 0;
3784}
3785
3786/**
3787 * si_gfx_is_lockup - Check if the GFX engine is locked up
3788 *
3789 * @rdev: radeon_device pointer
3790 * @ring: radeon_ring structure holding ring information
3791 *
3792 * Check if the GFX engine is locked up.
3793 * Returns true if the engine appears to be locked up, false if not.
3794 */
3795bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
3796{
3797 u32 reset_mask = si_gpu_check_soft_reset(rdev);
3798
3799 if (!(reset_mask & (RADEON_RESET_GFX |
3800 RADEON_RESET_COMPUTE |
3801 RADEON_RESET_CP))) {
3802 radeon_ring_lockup_update(ring);
3803 return false;
3804 }
3805 /* force CP activities */
3806 radeon_ring_force_activity(rdev, ring);
3807 return radeon_ring_test_lockup(rdev, ring);
3808}
3809
3810/**
3811 * si_dma_is_lockup - Check if the DMA engine is locked up
3812 *
3813 * @rdev: radeon_device pointer
3814 * @ring: radeon_ring structure holding ring information
3815 *
3816 * Check if the async DMA engine is locked up.
3817 * Returns true if the engine appears to be locked up, false if not.
3818 */
3819bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
3820{
3821 u32 reset_mask = si_gpu_check_soft_reset(rdev);
3822 u32 mask;
3823
3824 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
3825 mask = RADEON_RESET_DMA;
3826 else
3827 mask = RADEON_RESET_DMA1;
3828
3829 if (!(reset_mask & mask)) {
3830 radeon_ring_lockup_update(ring);
3831 return false;
3832 }
3833 /* force ring activities */
3834 radeon_ring_force_activity(rdev, ring);
3835 return radeon_ring_test_lockup(rdev, ring);
926deccb
FT
3836}
3837
3838/* MC */
3839static void si_mc_program(struct radeon_device *rdev)
3840{
3841 struct evergreen_mc_save save;
3842 u32 tmp;
3843 int i, j;
3844
3845 /* Initialize HDP */
3846 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3847 WREG32((0x2c14 + j), 0x00000000);
3848 WREG32((0x2c18 + j), 0x00000000);
3849 WREG32((0x2c1c + j), 0x00000000);
3850 WREG32((0x2c20 + j), 0x00000000);
3851 WREG32((0x2c24 + j), 0x00000000);
3852 }
3853 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
3854
3855 evergreen_mc_stop(rdev, &save);
3856 if (radeon_mc_wait_for_idle(rdev)) {
3857 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3858 }
f43cf1b1
MN
3859 if (!ASIC_IS_NODCE(rdev))
3860 /* Lockout access through VGA aperture*/
3861 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
926deccb
FT
3862 /* Update configuration */
3863 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
3864 rdev->mc.vram_start >> 12);
3865 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
3866 rdev->mc.vram_end >> 12);
3867 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
3868 rdev->vram_scratch.gpu_addr >> 12);
3869 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3870 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
3871 WREG32(MC_VM_FB_LOCATION, tmp);
3872 /* XXX double check these! */
3873 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
3874 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
3875 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3876 WREG32(MC_VM_AGP_BASE, 0);
3877 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
3878 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
3879 if (radeon_mc_wait_for_idle(rdev)) {
3880 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3881 }
3882 evergreen_mc_resume(rdev, &save);
f43cf1b1
MN
3883 if (!ASIC_IS_NODCE(rdev)) {
3884 /* we need to own VRAM, so turn off the VGA renderer here
3885 * to stop it overwriting our objects */
3886 rv515_vga_render_disable(rdev);
926deccb 3887 }
926deccb
FT
3888}
3889
57e252bf
MN
3890void si_vram_gtt_location(struct radeon_device *rdev,
3891 struct radeon_mc *mc)
926deccb
FT
3892{
3893 if (mc->mc_vram_size > 0xFFC0000000ULL) {
3894 /* leave room for at least 1024M GTT */
3895 dev_warn(rdev->dev, "limiting VRAM\n");
3896 mc->real_vram_size = 0xFFC0000000ULL;
3897 mc->mc_vram_size = 0xFFC0000000ULL;
3898 }
f43cf1b1 3899 radeon_vram_location(rdev, &rdev->mc, 0);
926deccb 3900 rdev->mc.gtt_base_align = 0;
f43cf1b1 3901 radeon_gtt_location(rdev, mc);
926deccb
FT
3902}
3903
3904static int si_mc_init(struct radeon_device *rdev)
3905{
3906 u32 tmp;
3907 int chansize, numchan;
3908
3909 /* Get VRAM informations */
3910 rdev->mc.vram_is_ddr = true;
3911 tmp = RREG32(MC_ARB_RAMCFG);
3912 if (tmp & CHANSIZE_OVERRIDE) {
3913 chansize = 16;
3914 } else if (tmp & CHANSIZE_MASK) {
3915 chansize = 64;
3916 } else {
3917 chansize = 32;
3918 }
3919 tmp = RREG32(MC_SHARED_CHMAP);
3920 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
3921 case 0:
3922 default:
3923 numchan = 1;
3924 break;
3925 case 1:
3926 numchan = 2;
3927 break;
3928 case 2:
3929 numchan = 4;
3930 break;
3931 case 3:
3932 numchan = 8;
3933 break;
3934 case 4:
3935 numchan = 3;
3936 break;
3937 case 5:
3938 numchan = 6;
3939 break;
3940 case 6:
3941 numchan = 10;
3942 break;
3943 case 7:
3944 numchan = 12;
3945 break;
3946 case 8:
3947 numchan = 16;
3948 break;
3949 }
3950 rdev->mc.vram_width = numchan * chansize;
3951 /* Could aper size report 0 ? */
3952 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
3953 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
3954 /* size in MB on si */
f43cf1b1
MN
3955 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3956 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
926deccb
FT
3957 rdev->mc.visible_vram_size = rdev->mc.aper_size;
3958 si_vram_gtt_location(rdev, &rdev->mc);
3959 radeon_update_bandwidth_info(rdev);
3960
3961 return 0;
3962}
3963
3964/*
3965 * GART
3966 */
3967void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
3968{
3969 /* flush hdp cache */
3970 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3971
3972 /* bits 0-15 are the VM contexts0-15 */
3973 WREG32(VM_INVALIDATE_REQUEST, 1);
3974}
3975
3976static int si_pcie_gart_enable(struct radeon_device *rdev)
3977{
3978 int r, i;
3979
3980 if (rdev->gart.robj == NULL) {
3981 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
3982 return -EINVAL;
3983 }
3984 r = radeon_gart_table_vram_pin(rdev);
3985 if (r)
3986 return r;
3987 radeon_gart_restore(rdev);
3988 /* Setup TLB control */
3989 WREG32(MC_VM_MX_L1_TLB_CNTL,
3990 (0xA << 7) |
3991 ENABLE_L1_TLB |
3992 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
3993 ENABLE_ADVANCED_DRIVER_MODEL |
3994 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
3995 /* Setup L2 cache */
3996 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
3997 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
3998 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
3999 EFFECTIVE_L2_QUEUE_SIZE(7) |
4000 CONTEXT1_IDENTITY_ACCESS_MODE(1));
4001 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
4002 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4003 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
4004 /* setup context0 */
4005 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
4006 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
4007 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
4008 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
4009 (u32)(rdev->dummy_page.addr >> 12));
4010 WREG32(VM_CONTEXT0_CNTL2, 0);
4011 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
4012 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
4013
4014 WREG32(0x15D4, 0);
4015 WREG32(0x15D8, 0);
4016 WREG32(0x15DC, 0);
4017
4018 /* empty context1-15 */
4019 /* set vm size, must be a multiple of 4 */
4020 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
4021 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
4022 /* Assign the pt base to something valid for now; the pts used for
4023 * the VMs are determined by the application and setup and assigned
4024 * on the fly in the vm part of radeon_gart.c
4025 */
4026 for (i = 1; i < 16; i++) {
4027 if (i < 8)
4028 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
4029 rdev->gart.table_addr >> 12);
4030 else
4031 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
4032 rdev->gart.table_addr >> 12);
4033 }
4034
4035 /* enable context1-15 */
4036 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
4037 (u32)(rdev->dummy_page.addr >> 12));
4038 WREG32(VM_CONTEXT1_CNTL2, 4);
4039 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
4040 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4041 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4042 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4043 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4044 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
4045 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
4046 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
4047 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
4048 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
4049 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
4050 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4051 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
4052
4053 si_pcie_gart_tlb_flush(rdev);
4054 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
4055 (unsigned)(rdev->mc.gtt_size >> 20),
4056 (unsigned long long)rdev->gart.table_addr);
4057 rdev->gart.ready = true;
4058 return 0;
4059}
4060
4061static void si_pcie_gart_disable(struct radeon_device *rdev)
4062{
4063 /* Disable all tables */
4064 WREG32(VM_CONTEXT0_CNTL, 0);
4065 WREG32(VM_CONTEXT1_CNTL, 0);
4066 /* Setup TLB control */