x86_64: Remove old IOAPIC code
[dragonfly.git] / sys / platform / pc64 / apic / mpapic.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
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3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
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26 */
27
28#include <sys/param.h>
29#include <sys/systm.h>
46d4e165 30#include <sys/kernel.h>
23b08e03 31#include <sys/bus.h>
e0918665 32#include <sys/machintr.h>
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33#include <machine/globaldata.h>
34#include <machine/smp.h>
46d4e165 35#include <machine/md_var.h>
c2abfdd7 36#include <machine/pmap.h>
c8fe38ae 37#include <machine_base/apic/mpapic.h>
929c940f 38#include <machine_base/apic/ioapic_abi.h>
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39#include <machine/segments.h>
40#include <sys/thread2.h>
41
57a9c56b 42#include <machine/intr_machdep.h>
c8fe38ae 43
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44#include "apicvar.h"
45
68b90e82
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46#define IOAPIC_COUNT_MAX 16
47#define IOAPIC_ID_MASK (IOAPIC_COUNT_MAX - 1)
48
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49/* EISA Edge/Level trigger control registers */
50#define ELCR0 0x4d0 /* eisa irq 0-7 */
51#define ELCR1 0x4d1 /* eisa irq 8-15 */
52
ebf4f417
SZ
53struct ioapic_info {
54 int io_idx;
55 int io_apic_id;
56 void *io_addr;
57 int io_npin;
58 int io_gsi_base;
59
60 TAILQ_ENTRY(ioapic_info) io_link;
61};
62TAILQ_HEAD(ioapic_info_list, ioapic_info);
63
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64struct ioapic_intsrc {
65 int int_gsi;
66 enum intr_trigger int_trig;
67 enum intr_polarity int_pola;
68};
69
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70struct ioapic_conf {
71 struct ioapic_info_list ioc_list;
ae80be10 72 struct ioapic_intsrc ioc_intsrc[16]; /* XXX magic number */
ebf4f417
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73};
74
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75volatile lapic_t *lapic;
76
77static void lapic_timer_calibrate(void);
78static void lapic_timer_set_divisor(int);
79static void lapic_timer_fixup_handler(void *);
80static void lapic_timer_restart_handler(void *);
81
82void lapic_timer_process(void);
83void lapic_timer_process_frame(struct intrframe *);
b9f7ba13 84void lapic_timer_always(struct intrframe *);
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85
86static int lapic_timer_enable = 1;
87TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
88
89static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
90static void lapic_timer_intr_enable(struct cputimer_intr *);
91static void lapic_timer_intr_restart(struct cputimer_intr *);
92static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
93
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94static int lapic_unused_apic_id(int);
95
23b08e03 96static void ioapic_setup(const struct ioapic_info *);
68b90e82 97static int ioapic_alloc_apic_id(int);
23b08e03
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98static void ioapic_set_apic_id(const struct ioapic_info *);
99static void ioapic_gsi_setup(int);
100static const struct ioapic_info *
101 ioapic_gsi_search(int);
ecec8ddc
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102static void ioapic_pin_prog(void *, int, int,
103 enum intr_trigger, enum intr_polarity, uint32_t);
23b08e03 104
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105static struct cputimer_intr lapic_cputimer_intr = {
106 .freq = 0,
107 .reload = lapic_timer_intr_reload,
108 .enable = lapic_timer_intr_enable,
109 .config = cputimer_intr_default_config,
110 .restart = lapic_timer_intr_restart,
111 .pmfixup = lapic_timer_intr_pmfixup,
112 .initclock = cputimer_intr_default_initclock,
113 .next = SLIST_ENTRY_INITIALIZER,
114 .name = "lapic",
115 .type = CPUTIMER_INTR_LAPIC,
116 .prio = CPUTIMER_INTR_PRIO_LAPIC,
117 .caps = CPUTIMER_INTR_CAP_NONE
118};
119
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120/*
121 * pointers to pmapped apic hardware.
122 */
123
124volatile ioapic_t **ioapic;
125
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126static int lapic_timer_divisor_idx = -1;
127static const uint32_t lapic_timer_divisors[] = {
128 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
129 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
130};
c157ff7a 131#define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
46d4e165 132
c5c405ff 133int lapic_id_max;
ebf4f417 134static struct ioapic_conf ioapic_conf;
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135
136void
137lapic_eoi(void)
138{
139
140 lapic->eoi = 0;
141}
a9e511df 142
c8fe38ae 143/*
d99d4acb 144 * Enable LAPIC, configure interrupts.
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145 */
146void
5ddeabb9 147lapic_init(boolean_t bsp)
c8fe38ae 148{
46d4e165 149 uint32_t timer;
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150 u_int temp;
151
dbfb3a5a
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152 /*
153 * Install vectors
154 *
155 * Since IDT is shared between BSP and APs, these vectors
156 * only need to be installed once; we do it on BSP.
157 */
158 if (bsp) {
159 /* Install a 'Spurious INTerrupt' vector */
160 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
161 SDT_SYSIGT, SEL_KPL, 0);
162
163 /* Install an inter-CPU IPI for TLB invalidation */
164 setidt(XINVLTLB_OFFSET, Xinvltlb,
165 SDT_SYSIGT, SEL_KPL, 0);
166
167 /* Install an inter-CPU IPI for IPIQ messaging */
168 setidt(XIPIQ_OFFSET, Xipiq,
169 SDT_SYSIGT, SEL_KPL, 0);
170
171 /* Install a timer vector */
172 setidt(XTIMER_OFFSET, Xtimer,
173 SDT_SYSIGT, SEL_KPL, 0);
174
175 /* Install an inter-CPU IPI for CPU stop/restart */
176 setidt(XCPUSTOP_OFFSET, Xcpustop,
177 SDT_SYSIGT, SEL_KPL, 0);
178 }
179
c8fe38ae 180 /*
d99d4acb 181 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
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182 * aggregate interrupt input from the 8259. The INTA cycle
183 * will be routed to the external controller (the 8259) which
184 * is expected to supply the vector.
185 *
186 * Must be setup edge triggered, active high.
187 *
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188 * Disable LINT0 on BSP, if I/O APIC is enabled.
189 *
d99d4acb 190 * Disable LINT0 on the APs. It doesn't matter what delivery
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191 * mode we use because we leave it masked.
192 */
46d4e165 193 temp = lapic->lvt_lint0;
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194 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
195 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
4d08e038 196 if (bsp) {
c8fe38ae 197 temp |= APIC_LVT_DM_EXTINT;
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198 if (apic_io_enable)
199 temp |= APIC_LVT_MASKED;
200 } else {
c8fe38ae 201 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
4d08e038 202 }
46d4e165 203 lapic->lvt_lint0 = temp;
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204
205 /*
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206 * Setup LINT1 as NMI.
207 *
208 * Must be setup edge trigger, active high.
209 *
210 * Enable LINT1 on BSP, if I/O APIC is enabled.
211 *
212 * Disable LINT1 on the APs.
c8fe38ae 213 */
46d4e165 214 temp = lapic->lvt_lint1;
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215 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
216 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
217 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
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218 if (bsp && apic_io_enable)
219 temp &= ~APIC_LVT_MASKED;
46d4e165 220 lapic->lvt_lint1 = temp;
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221
222 /*
d99d4acb 223 * Mask the LAPIC error interrupt, LAPIC performance counter
46d4e165 224 * interrupt.
c8fe38ae 225 */
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226 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
227 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
228
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229 /*
230 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
231 */
46d4e165
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232 timer = lapic->lvt_timer;
233 timer &= ~APIC_LVTT_VECTOR;
234 timer |= XTIMER_OFFSET;
235 timer |= APIC_LVTT_MASKED;
236 lapic->lvt_timer = timer;
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237
238 /*
239 * Set the Task Priority Register as needed. At the moment allow
240 * interrupts on all cpus (the APs will remain CLId until they are
241 * ready to deal). We could disable all but IPIs by setting
617a6d43 242 * temp |= TPR_IPI for cpu != 0.
c8fe38ae 243 */
46d4e165 244 temp = lapic->tpr;
c8fe38ae 245 temp &= ~APIC_TPR_PRIO; /* clear priority field */
faaf4131
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246#ifdef SMP /* APIC-IO */
247if (!apic_io_enable) {
248#endif
c8fe38ae 249 /*
faaf4131 250 * If we are NOT running the IO APICs, the LAPIC will only be used
c8fe38ae 251 * for IPIs. Set the TPR to prevent any unintentional interrupts.
faaf4131 252 */
617a6d43 253 temp |= TPR_IPI;
faaf4131
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254#ifdef SMP /* APIC-IO */
255}
c8fe38ae 256#endif
46d4e165 257 lapic->tpr = temp;
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258
259 /*
d99d4acb 260 * Enable the LAPIC
c8fe38ae 261 */
46d4e165 262 temp = lapic->svr;
d99d4acb 263 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
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264 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
265
266 /*
267 * Set the spurious interrupt vector. The low 4 bits of the vector
268 * must be 1111.
269 */
270 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
271 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
272 temp &= ~APIC_SVR_VECTOR;
273 temp |= XSPURIOUSINT_OFFSET;
274
46d4e165 275 lapic->svr = temp;
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276
277 /*
278 * Pump out a few EOIs to clean out interrupts that got through
279 * before we were able to set the TPR.
280 */
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281 lapic_eoi();
282 lapic_eoi();
283 lapic_eoi();
284
285 if (bsp) {
286 lapic_timer_calibrate();
287 if (lapic_timer_enable) {
288 cputimer_intr_register(&lapic_cputimer_intr);
289 cputimer_intr_select(&lapic_cputimer_intr, 0);
290 }
291 } else {
292 lapic_timer_set_divisor(lapic_timer_divisor_idx);
293 }
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294
295 if (bootverbose)
296 apic_dump("apic_initialize()");
297}
298
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299static void
300lapic_timer_set_divisor(int divisor_idx)
301{
302 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
303 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
304}
305
306static void
307lapic_timer_oneshot(u_int count)
308{
309 uint32_t value;
310
311 value = lapic->lvt_timer;
312 value &= ~APIC_LVTT_PERIODIC;
313 lapic->lvt_timer = value;
314 lapic->icr_timer = count;
315}
316
317static void
318lapic_timer_oneshot_quick(u_int count)
319{
320 lapic->icr_timer = count;
321}
322
323static void
324lapic_timer_calibrate(void)
325{
326 sysclock_t value;
327
328 /* Try to calibrate the local APIC timer. */
329 for (lapic_timer_divisor_idx = 0;
330 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
331 lapic_timer_divisor_idx++) {
332 lapic_timer_set_divisor(lapic_timer_divisor_idx);
333 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
334 DELAY(2000000);
335 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
336 if (value != APIC_TIMER_MAX_COUNT)
337 break;
338 }
339 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
340 panic("lapic: no proper timer divisor?!\n");
341 lapic_cputimer_intr.freq = value / 2;
342
343 kprintf("lapic: divisor index %d, frequency %u Hz\n",
344 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
345}
346
347static void
348lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
349{
350 sysclock_t count;
351
352 gd->gd_timer_running = 0;
353
354 count = sys_cputimer->count();
355 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
356 systimer_intr(&count, 0, frame);
357}
358
a9e511df 359void
46d4e165
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360lapic_timer_process(void)
361{
362 lapic_timer_process_oncpu(mycpu, NULL);
363}
364
365void
366lapic_timer_process_frame(struct intrframe *frame)
367{
368 lapic_timer_process_oncpu(mycpu, frame);
369}
370
b9f7ba13
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371/*
372 * This manual debugging code is called unconditionally from Xtimer
373 * (the lapic timer interrupt) whether the current thread is in a
374 * critical section or not) and can be useful in tracking down lockups.
cfaeae2a
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375 *
376 * NOTE: MANUAL DEBUG CODE
b9f7ba13 377 */
cfaeae2a
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378#if 0
379static int saveticks[SMP_MAXCPU];
380static int savecounts[SMP_MAXCPU];
381#endif
382
b9f7ba13
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383void
384lapic_timer_always(struct intrframe *frame)
385{
386#if 0
387 globaldata_t gd = mycpu;
388 int cpu = gd->gd_cpuid;
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389 char buf[64];
390 short *gptr;
cfaeae2a 391 int i;
b9f7ba13 392
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393 if (cpu <= 20) {
394 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
395 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
396 ++gptr;
b9f7ba13 397
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398 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
399 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
400 gd->gd_infomsg);
401 for (i = 0; buf[i]; ++i) {
402 gptr[i] = 0x0700 | (unsigned char)buf[i];
403 }
404 }
405#if 0
406 if (saveticks[gd->gd_cpuid] != ticks) {
407 saveticks[gd->gd_cpuid] = ticks;
408 savecounts[gd->gd_cpuid] = 0;
409 }
410 ++savecounts[gd->gd_cpuid];
411 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
412 panic("cpud %d panicing on ticks failure",
413 gd->gd_cpuid);
b9f7ba13 414 }
cfaeae2a
MD
415 for (i = 0; i < ncpus; ++i) {
416 int delta;
417 if (saveticks[i] && panicstr == NULL) {
418 delta = saveticks[i] - ticks;
419 if (delta < -10 || delta > 10) {
420 panic("cpu %d panicing on cpu %d watchdog",
421 gd->gd_cpuid, i);
422 }
423 }
424 }
425#endif
b9f7ba13
MD
426#endif
427}
428
46d4e165
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429static void
430lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
431{
432 struct globaldata *gd = mycpu;
433
434 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
435 if (reload < 2)
436 reload = 2;
437
438 if (gd->gd_timer_running) {
439 if (reload < lapic->ccr_timer)
440 lapic_timer_oneshot_quick(reload);
441 } else {
442 gd->gd_timer_running = 1;
443 lapic_timer_oneshot_quick(reload);
444 }
445}
446
447static void
448lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
449{
450 uint32_t timer;
451
452 timer = lapic->lvt_timer;
453 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
454 lapic->lvt_timer = timer;
455
456 lapic_timer_fixup_handler(NULL);
457}
458
459static void
460lapic_timer_fixup_handler(void *arg)
a9e511df 461{
46d4e165
JG
462 int *started = arg;
463
464 if (started != NULL)
465 *started = 0;
466
467 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
468 /*
469 * Detect the presence of C1E capability mostly on latest
470 * dual-cores (or future) k8 family. This feature renders
471 * the local APIC timer dead, so we disable it by reading
472 * the Interrupt Pending Message register and clearing both
473 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
474 *
475 * Reference:
476 * "BIOS and Kernel Developer's Guide for AMD NPT
477 * Family 0Fh Processors"
478 * #32559 revision 3.00
479 */
480 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
481 (cpu_id & 0x0fff0000) >= 0x00040000) {
482 uint64_t msr;
483
484 msr = rdmsr(0xc0010055);
485 if (msr & 0x18000000) {
486 struct globaldata *gd = mycpu;
487
488 kprintf("cpu%d: AMD C1E detected\n",
489 gd->gd_cpuid);
490 wrmsr(0xc0010055, msr & ~0x18000000ULL);
491
492 /*
493 * We are kinda stalled;
494 * kick start again.
495 */
496 gd->gd_timer_running = 1;
497 lapic_timer_oneshot_quick(2);
498
499 if (started != NULL)
500 *started = 1;
501 }
502 }
503 }
a9e511df 504}
c8fe38ae 505
46d4e165
JG
506static void
507lapic_timer_restart_handler(void *dummy __unused)
508{
509 int started;
510
511 lapic_timer_fixup_handler(&started);
512 if (!started) {
513 struct globaldata *gd = mycpu;
514
515 gd->gd_timer_running = 1;
516 lapic_timer_oneshot_quick(2);
517 }
518}
519
520/*
521 * This function is called only by ACPI-CA code currently:
522 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
523 * module controls PM. So once ACPI-CA is attached, we try
524 * to apply the fixup to prevent LAPIC timer from hanging.
525 */
526static void
527lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
528{
529 lwkt_send_ipiq_mask(smp_active_mask,
530 lapic_timer_fixup_handler, NULL);
531}
532
533static void
534lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
535{
536 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
537}
538
539
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540/*
541 * dump contents of local APIC registers
542 */
543void
544apic_dump(char* str)
545{
546 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
547 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
46d4e165 548 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
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549}
550
551
faaf4131 552#ifdef SMP /* APIC-IO */
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553
554/*
555 * IO APIC code,
556 */
557
558#define IOAPIC_ISA_INTS 16
559#define REDIRCNT_IOAPIC(A) \
560 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
561
562static int trigger (int apic, int pin, u_int32_t * flags);
563static void polarity (int apic, int pin, u_int32_t * flags, int level);
564
565#define DEFAULT_FLAGS \
566 ((u_int32_t) \
567 (IOART_INTMSET | \
568 IOART_DESTPHY | \
569 IOART_DELLOPRI))
570
571#define DEFAULT_ISA_FLAGS \
572 ((u_int32_t) \
573 (IOART_INTMSET | \
574 IOART_TRGREDG | \
575 IOART_INTAHI | \
576 IOART_DESTPHY | \
577 IOART_DELLOPRI))
578
579void
580io_apic_set_id(int apic, int id)
581{
582 u_int32_t ux;
583
e17120aa 584 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* get current contents */
c8fe38ae
MD
585 if (((ux & APIC_ID_MASK) >> 24) != id) {
586 kprintf("Changing APIC ID for IO APIC #%d"
587 " from %d to %d on chip\n",
588 apic, ((ux & APIC_ID_MASK) >> 24), id);
589 ux &= ~APIC_ID_MASK; /* clear the ID field */
590 ux |= (id << 24);
e17120aa
SZ
591 ioapic_write(ioapic[apic], IOAPIC_ID, ux); /* write new value */
592 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* re-read && test */
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593 if (((ux & APIC_ID_MASK) >> 24) != id)
594 panic("can't control IO APIC #%d ID, reg: 0x%08x",
595 apic, ux);
596 }
597}
598
599
600int
601io_apic_get_id(int apic)
602{
e17120aa 603 return (ioapic_read(ioapic[apic], IOAPIC_ID) & APIC_ID_MASK) >> 24;
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604}
605
606
607
608/*
609 * Setup the IO APIC.
610 */
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611void
612io_apic_setup_intpin(int apic, int pin)
613{
614 int bus, bustype, irq;
615 u_char select; /* the select register is 8 bits */
616 u_int32_t flags; /* the window register is 32 bits */
617 u_int32_t target; /* the window register is 32 bits */
618 u_int32_t vector; /* the window register is 32 bits */
619 int level;
46d4e165
JG
620 int cpuid;
621 char envpath[32];
c8fe38ae
MD
622
623 select = pin * 2 + IOAPIC_REDTBL0; /* register */
624
625 /*
626 * Always clear an IO APIC pin before [re]programming it. This is
627 * particularly important if the pin is set up for a level interrupt
628 * as the IOART_REM_IRR bit might be set. When we reprogram the
629 * vector any EOI from pending ints on this pin could be lost and
630 * IRR might never get reset.
631 *
632 * To fix this problem, clear the vector and make sure it is
633 * programmed as an edge interrupt. This should theoretically
634 * clear IRR so we can later, safely program it as a level
635 * interrupt.
636 */
637 imen_lock();
638
e17120aa 639 flags = ioapic_read(ioapic[apic], select) & IOART_RESV;
c8fe38ae
MD
640 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
641 flags |= IOART_DESTPHY | IOART_DELFIXED;
642
e17120aa 643 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
c8fe38ae
MD
644 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
645
646 vector = 0;
647
e17120aa
SZ
648 ioapic_write(ioapic[apic], select, flags | vector);
649 ioapic_write(ioapic[apic], select + 1, target);
c8fe38ae
MD
650
651 imen_unlock();
652
653 /*
654 * We only deal with vectored interrupts here. ? documentation is
655 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
656 * vs ExTINT, etc.
657 *
658 * This test also catches unconfigured pins.
659 */
660 if (apic_int_type(apic, pin) != 0)
661 return;
662
663 /*
664 * Leave the pin unprogrammed if it does not correspond to
665 * an IRQ.
666 */
667 irq = apic_irq(apic, pin);
668 if (irq < 0)
669 return;
670
671 /* determine the bus type for this pin */
672 bus = apic_src_bus_id(apic, pin);
673 if (bus < 0)
674 return;
675 bustype = apic_bus_type(bus);
676
677 if ((bustype == ISA) &&
678 (pin < IOAPIC_ISA_INTS) &&
679 (irq == pin) &&
680 (apic_polarity(apic, pin) == 0x1) &&
681 (apic_trigger(apic, pin) == 0x3)) {
682 /*
683 * A broken BIOS might describe some ISA
684 * interrupts as active-high level-triggered.
685 * Use default ISA flags for those interrupts.
686 */
687 flags = DEFAULT_ISA_FLAGS;
688 } else {
689 /*
690 * Program polarity and trigger mode according to
691 * interrupt entry.
692 */
693 flags = DEFAULT_FLAGS;
694 level = trigger(apic, pin, &flags);
695 if (level == 1)
dfeaac88 696 int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
c8fe38ae
MD
697 polarity(apic, pin, &flags, level);
698 }
46d4e165
JG
699
700 cpuid = 0;
701 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
702 kgetenv_int(envpath, &cpuid);
703
704 /* ncpus may not be available yet */
705 if (cpuid > mp_naps)
706 cpuid = 0;
707
c8fe38ae 708 if (bootverbose) {
46d4e165
JG
709 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
710 apic, pin, irq, cpuid);
c8fe38ae
MD
711 }
712
713 /*
714 * Program the appropriate registers. This routing may be
715 * overridden when an interrupt handler for a device is
716 * actually added (see register_int(), which calls through
717 * the MACHINTR ABI to set up an interrupt handler/vector).
718 *
719 * The order in which we must program the two registers for
720 * safety is unclear! XXX
721 */
722 imen_lock();
723
724 vector = IDT_OFFSET + irq; /* IDT vec */
e17120aa 725 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
46d4e165
JG
726 /* Deliver all interrupts to CPU0 (BSP) */
727 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
728 IOART_HI_DEST_MASK;
e17120aa
SZ
729 flags |= ioapic_read(ioapic[apic], select) & IOART_RESV;
730 ioapic_write(ioapic[apic], select, flags | vector);
731 ioapic_write(ioapic[apic], select + 1, target);
c8fe38ae
MD
732
733 imen_unlock();
734}
735
736int
737io_apic_setup(int apic)
738{
739 int maxpin;
740 int pin;
741
c8fe38ae
MD
742 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
743 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
744
745 for (pin = 0; pin < maxpin; ++pin) {
746 io_apic_setup_intpin(apic, pin);
747 }
748 while (pin < 32) {
749 if (apic_int_type(apic, pin) >= 0) {
750 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
751 " cannot program!\n", apic, pin);
752 }
753 ++pin;
754 }
755
756 /* return GOOD status */
757 return 0;
758}
759#undef DEFAULT_ISA_FLAGS
760#undef DEFAULT_FLAGS
761
762
763#define DEFAULT_EXTINT_FLAGS \
764 ((u_int32_t) \
765 (IOART_INTMSET | \
766 IOART_TRGREDG | \
767 IOART_INTAHI | \
768 IOART_DESTPHY | \
769 IOART_DELLOPRI))
770
771/*
46d4e165 772 * XXX this function is only used by 8254 setup
c8fe38ae
MD
773 * Setup the source of External INTerrupts.
774 */
775int
776ext_int_setup(int apic, int intr)
777{
778 u_char select; /* the select register is 8 bits */
779 u_int32_t flags; /* the window register is 32 bits */
780 u_int32_t target; /* the window register is 32 bits */
781 u_int32_t vector; /* the window register is 32 bits */
46d4e165
JG
782 int cpuid;
783 char envpath[32];
c8fe38ae
MD
784
785 if (apic_int_type(apic, intr) != 3)
786 return -1;
787
46d4e165
JG
788 cpuid = 0;
789 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
790 kgetenv_int(envpath, &cpuid);
791
792 /* ncpus may not be available yet */
793 if (cpuid > mp_naps)
794 cpuid = 0;
795
796 /* Deliver interrupts to CPU0 (BSP) */
797 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
798 IOART_HI_DEST_MASK;
c8fe38ae
MD
799 select = IOAPIC_REDTBL0 + (2 * intr);
800 vector = IDT_OFFSET + intr;
801 flags = DEFAULT_EXTINT_FLAGS;
802
e17120aa
SZ
803 ioapic_write(ioapic[apic], select, flags | vector);
804 ioapic_write(ioapic[apic], select + 1, target);
c8fe38ae
MD
805
806 return 0;
807}
808#undef DEFAULT_EXTINT_FLAGS
809
810
811/*
812 * Set the trigger level for an IO APIC pin.
813 */
814static int
815trigger(int apic, int pin, u_int32_t * flags)
816{
817 int id;
818 int eirq;
819 int level;
820 static int intcontrol = -1;
821
822 switch (apic_trigger(apic, pin)) {
823
824 case 0x00:
825 break;
826
827 case 0x01:
828 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
829 return 0;
830
831 case 0x03:
832 *flags |= IOART_TRGRLVL;
833 return 1;
834
835 case -1:
836 default:
837 goto bad;
838 }
839
840 if ((id = apic_src_bus_id(apic, pin)) == -1)
841 goto bad;
842
843 switch (apic_bus_type(id)) {
844 case ISA:
845 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
846 return 0;
847
848 case EISA:
849 eirq = apic_src_bus_irq(apic, pin);
850
851 if (eirq < 0 || eirq > 15) {
852 kprintf("EISA IRQ %d?!?!\n", eirq);
853 goto bad;
854 }
855
856 if (intcontrol == -1) {
857 intcontrol = inb(ELCR1) << 8;
858 intcontrol |= inb(ELCR0);
859 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
860 }
861
862 /* Use ELCR settings to determine level or edge mode */
863 level = (intcontrol >> eirq) & 1;
864
865 /*
866 * Note that on older Neptune chipset based systems, any
867 * pci interrupts often show up here and in the ELCR as well
868 * as level sensitive interrupts attributed to the EISA bus.
869 */
870
871 if (level)
872 *flags |= IOART_TRGRLVL;
873 else
874 *flags &= ~IOART_TRGRLVL;
875
876 return level;
877
878 case PCI:
879 *flags |= IOART_TRGRLVL;
880 return 1;
881
882 case -1:
883 default:
884 goto bad;
885 }
886
887bad:
888 panic("bad APIC IO INT flags");
889}
890
891
892/*
893 * Set the polarity value for an IO APIC pin.
894 */
895static void
896polarity(int apic, int pin, u_int32_t * flags, int level)
897{
898 int id;
899
900 switch (apic_polarity(apic, pin)) {
901
902 case 0x00:
903 break;
904
905 case 0x01:
906 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
907 return;
908
909 case 0x03:
910 *flags |= IOART_INTALO;
911 return;
912
913 case -1:
914 default:
915 goto bad;
916 }
917
918 if ((id = apic_src_bus_id(apic, pin)) == -1)
919 goto bad;
920
921 switch (apic_bus_type(id)) {
922 case ISA:
923 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
924 return;
925
926 case EISA:
927 /* polarity converter always gives active high */
928 *flags &= ~IOART_INTALO;
929 return;
930
931 case PCI:
932 *flags |= IOART_INTALO;
933 return;
934
935 case -1:
936 default:
937 goto bad;
938 }
939
940bad:
941 panic("bad APIC IO INT flags");
942}
943
944
945/*
906448d8 946 * Print contents of unmasked IRQs.
c8fe38ae 947 */
c8fe38ae
MD
948void
949imen_dump(void)
950{
951 int x;
952
953 kprintf("SMP: enabled INTs: ");
906448d8 954 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
dfeaac88 955 if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
906448d8
MN
956 kprintf("%d ", x);
957 }
958 kprintf("\n");
c8fe38ae
MD
959}
960
961
962/*
963 * Inter Processor Interrupt functions.
964 */
965
faaf4131 966#endif /* SMP APIC-IO */
c8fe38ae
MD
967
968/*
969 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
970 *
971 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
972 * vector is any valid SYSTEM INT vector
973 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
974 *
975 * A backlog of requests can create a deadlock between cpus. To avoid this
976 * we have to be able to accept IPIs at the same time we are trying to send
977 * them. The critical section prevents us from attempting to send additional
978 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
979 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
980 * to occur but fortunately it does not happen too often.
981 */
982int
983apic_ipi(int dest_type, int vector, int delivery_mode)
984{
985 u_long icr_lo;
986
987 crit_enter();
46d4e165
JG
988 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
989 unsigned long rflags = read_rflags();
c8fe38ae 990 cpu_enable_intr();
cfaeae2a 991 DEBUG_PUSH_INFO("apic_ipi");
46d4e165 992 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
c8fe38ae
MD
993 lwkt_process_ipiq();
994 }
cfaeae2a 995 DEBUG_POP_INFO();
46d4e165 996 write_rflags(rflags);
c8fe38ae
MD
997 }
998
46d4e165 999 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
c8fe38ae 1000 delivery_mode | vector;
46d4e165 1001 lapic->icr_lo = icr_lo;
c8fe38ae
MD
1002 crit_exit();
1003 return 0;
1004}
1005
1006void
1007single_apic_ipi(int cpu, int vector, int delivery_mode)
1008{
1009 u_long icr_lo;
1010 u_long icr_hi;
1011
1012 crit_enter();
46d4e165
JG
1013 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
1014 unsigned long rflags = read_rflags();
c8fe38ae 1015 cpu_enable_intr();
cfaeae2a 1016 DEBUG_PUSH_INFO("single_apic_ipi");
46d4e165 1017 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
c8fe38ae
MD
1018 lwkt_process_ipiq();
1019 }
cfaeae2a 1020 DEBUG_POP_INFO();
46d4e165 1021 write_rflags(rflags);
c8fe38ae 1022 }
46d4e165 1023 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
c8fe38ae 1024 icr_hi |= (CPU_TO_ID(cpu) << 24);
46d4e165 1025 lapic->icr_hi = icr_hi;
c8fe38ae 1026
b2f93ae9 1027 /* build ICR_LOW */
46d4e165 1028 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
c8fe38ae
MD
1029 | APIC_DEST_DESTFLD | delivery_mode | vector;
1030
1031 /* write APIC ICR */
46d4e165 1032 lapic->icr_lo = icr_lo;
c8fe38ae
MD
1033 crit_exit();
1034}
1035
1036#if 0
1037
1038/*
1039 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
1040 *
1041 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
1042 * to the target, and the scheduler does not 'poll' for IPI messages.
1043 */
1044int
1045single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
1046{
1047 u_long icr_lo;
1048 u_long icr_hi;
1049
1050 crit_enter();
46d4e165 1051 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
c8fe38ae
MD
1052 crit_exit();
1053 return(0);
1054 }
46d4e165 1055 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
c8fe38ae 1056 icr_hi |= (CPU_TO_ID(cpu) << 24);
46d4e165 1057 lapic->icr_hi = icr_hi;
c8fe38ae
MD
1058
1059 /* build IRC_LOW */
46d4e165 1060 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
c8fe38ae
MD
1061 | APIC_DEST_DESTFLD | delivery_mode | vector;
1062
1063 /* write APIC ICR */
46d4e165 1064 lapic->icr_lo = icr_lo;
c8fe38ae
MD
1065 crit_exit();
1066 return(1);
1067}
1068
1069#endif
1070
1071/*
1072 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
1073 *
1074 * target is a bitmask of destination cpus. Vector is any
1075 * valid system INT vector. Delivery mode may be either
1076 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
1077 */
1078void
da23a592 1079selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
c8fe38ae
MD
1080{
1081 crit_enter();
1082 while (target) {
da23a592
MD
1083 int n = BSFCPUMASK(target);
1084 target &= ~CPUMASK(n);
c8fe38ae
MD
1085 single_apic_ipi(n, vector, delivery_mode);
1086 }
1087 crit_exit();
1088}
1089
1090/*
1091 * Timer code, in development...
1092 * - suggested by rgrimes@gndrsh.aac.dev.com
1093 */
bb467734
MD
1094int
1095get_apic_timer_frequency(void)
1096{
1097 return(lapic_cputimer_intr.freq);
1098}
c8fe38ae 1099
c8fe38ae
MD
1100/*
1101 * Load a 'downcount time' in uSeconds.
1102 */
1103void
46d4e165 1104set_apic_timer(int us)
c8fe38ae 1105{
46d4e165 1106 u_int count;
c8fe38ae
MD
1107
1108 /*
46d4e165
JG
1109 * When we reach here, lapic timer's frequency
1110 * must have been calculated as well as the
1111 * divisor (lapic->dcr_timer is setup during the
1112 * divisor calculation).
c8fe38ae 1113 */
46d4e165
JG
1114 KKASSERT(lapic_cputimer_intr.freq != 0 &&
1115 lapic_timer_divisor_idx >= 0);
1116
1117 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
1118 lapic_timer_oneshot(count);
c8fe38ae
MD
1119}
1120
1121
1122/*
1123 * Read remaining time in timer.
1124 */
1125int
1126read_apic_timer(void)
1127{
1128#if 0
1129 /** XXX FIXME: we need to return the actual remaining time,
1130 * for now we just return the remaining count.
1131 */
1132#else
46d4e165 1133 return lapic->ccr_timer;
c8fe38ae
MD
1134#endif
1135}
1136
1137
1138/*
1139 * Spin-style delay, set delay time in uS, spin till it drains.
1140 */
1141void
1142u_sleep(int count)
1143{
1144 set_apic_timer(count);
1145 while (read_apic_timer())
1146 /* spin */ ;
1147}
c2abfdd7 1148
68b90e82
SZ
1149static int
1150lapic_unused_apic_id(int start)
1151{
1152 int i;
1153
1154 for (i = start; i < NAPICID; ++i) {
1155 if (ID_TO_CPU(i) == -1)
1156 return i;
1157 }
1158 return NAPICID;
1159}
1160
c2abfdd7 1161void
b44f1d28 1162lapic_map(vm_offset_t lapic_addr)
c2abfdd7 1163{
c2abfdd7
MN
1164 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
1165
c2abfdd7
MN
1166 kprintf("lapic: at 0x%08lx\n", lapic_addr);
1167}
91903a05
MN
1168
1169static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1170 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1171
1172void
1173lapic_config(void)
1174{
1175 struct lapic_enumerator *e;
68b90e82
SZ
1176 int error, i;
1177
1178 for (i = 0; i < NAPICID; ++i)
1179 ID_TO_CPU(i) = -1;
91903a05
MN
1180
1181 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1182 error = e->lapic_probe(e);
1183 if (!error)
1184 break;
1185 }
1186 if (e == NULL)
1187 panic("can't config lapic\n");
1188
1189 e->lapic_enumerate(e);
1190}
1191
1192void
1193lapic_enumerator_register(struct lapic_enumerator *ne)
1194{
1195 struct lapic_enumerator *e;
1196
1197 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1198 if (e->lapic_prio < ne->lapic_prio) {
1199 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1200 return;
1201 }
1202 }
1203 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
1204}
65b2387f
SZ
1205
1206static TAILQ_HEAD(, ioapic_enumerator) ioapic_enumerators =
1207 TAILQ_HEAD_INITIALIZER(ioapic_enumerators);
1208
1209void
1210ioapic_config(void)
1211{
1212 struct ioapic_enumerator *e;
7a603b36
SZ
1213 struct ioapic_info *info;
1214 int start_apic_id = 0;
ebf4f417 1215 int error, i;
e0918665 1216 register_t ef = 0;
ebf4f417
SZ
1217
1218 TAILQ_INIT(&ioapic_conf.ioc_list);
1219 /* XXX magic number */
1220 for (i = 0; i < 16; ++i)
ae80be10 1221 ioapic_conf.ioc_intsrc[i].int_gsi = -1;
65b2387f
SZ
1222
1223 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1224 error = e->ioapic_probe(e);
1225 if (!error)
1226 break;
1227 }
1228 if (e == NULL) {
1229#ifdef notyet
1230 panic("can't config I/O APIC\n");
1231#else
1232 kprintf("no I/O APIC\n");
1233 return;
1234#endif
1235 }
1236
7a603b36 1237 crit_enter();
e0918665 1238
7a603b36
SZ
1239 ef = read_rflags();
1240 cpu_disable_intr();
e0918665 1241
7a603b36
SZ
1242 /*
1243 * Switch to I/O APIC MachIntrABI and reconfigure
1244 * the default IDT entries.
1245 */
1246 MachIntrABI = MachIntrABI_IOAPIC;
1247 MachIntrABI.setdefault();
e0918665 1248
65b2387f 1249 e->ioapic_enumerate(e);
0471bb0e 1250
7a603b36
SZ
1251 /*
1252 * Setup index
1253 */
1254 i = 0;
1255 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
1256 info->io_idx = i++;
68b90e82 1257
7a603b36
SZ
1258 if (i > IOAPIC_COUNT_MAX) /* XXX magic number */
1259 panic("ioapic_config: more than 16 I/O APIC\n");
68b90e82 1260
7a603b36
SZ
1261 /*
1262 * Setup APIC ID
1263 */
1264 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1265 int apic_id;
68b90e82 1266
7a603b36
SZ
1267 apic_id = ioapic_alloc_apic_id(start_apic_id);
1268 if (apic_id == NAPICID) {
1269 kprintf("IOAPIC: can't alloc APIC ID for "
1270 "%dth I/O APIC\n", info->io_idx);
1271 break;
68b90e82 1272 }
7a603b36 1273 info->io_apic_id = apic_id;
68b90e82 1274
7a603b36
SZ
1275 start_apic_id = apic_id + 1;
1276 }
1277 if (info != NULL) {
68b90e82 1278 /*
7a603b36
SZ
1279 * xAPIC allows I/O APIC's APIC ID to be same
1280 * as the LAPIC's APIC ID
68b90e82 1281 */
7a603b36
SZ
1282 kprintf("IOAPIC: use xAPIC model to alloc APIC ID "
1283 "for I/O APIC\n");
1284
1285 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
1286 info->io_apic_id = info->io_idx;
1287 }
1288
1289 /*
1290 * Warning about any GSI holes
1291 */
1292 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1293 const struct ioapic_info *prev_info;
1294
1295 prev_info = TAILQ_PREV(info, ioapic_info_list, io_link);
1296 if (prev_info != NULL) {
1297 if (info->io_gsi_base !=
1298 prev_info->io_gsi_base + prev_info->io_npin) {
1299 kprintf("IOAPIC: warning gsi hole "
1300 "[%d, %d]\n",
1301 prev_info->io_gsi_base +
1302 prev_info->io_npin,
1303 info->io_gsi_base - 1);
ebf4f417
SZ
1304 }
1305 }
7a603b36 1306 }
23b08e03 1307
7a603b36
SZ
1308 if (bootverbose) {
1309 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1310 kprintf("IOAPIC: idx %d, apic id %d, "
1311 "gsi base %d, npin %d\n",
1312 info->io_idx,
1313 info->io_apic_id,
1314 info->io_gsi_base,
1315 info->io_npin);
68b90e82 1316 }
7a603b36 1317 }
68b90e82 1318
7a603b36
SZ
1319 /*
1320 * Setup all I/O APIC
1321 */
1322 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
1323 ioapic_setup(info);
1324 ioapic_abi_fixup_irqmap();
23b08e03 1325
7a603b36 1326 write_rflags(ef);
e0918665 1327
7a603b36 1328 MachIntrABI.cleanup();
e0918665 1329
7a603b36 1330 crit_exit();
65b2387f
SZ
1331}
1332
1333void
1334ioapic_enumerator_register(struct ioapic_enumerator *ne)
1335{
1336 struct ioapic_enumerator *e;
1337
1338 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1339 if (e->ioapic_prio < ne->ioapic_prio) {
1340 TAILQ_INSERT_BEFORE(e, ne, ioapic_link);
1341 return;
1342 }
1343 }
1344 TAILQ_INSERT_TAIL(&ioapic_enumerators, ne, ioapic_link);
1345}
ebf4f417
SZ
1346
1347void
1348ioapic_add(void *addr, int gsi_base, int npin)
1349{
1350 struct ioapic_info *info, *ninfo;
1351 int gsi_end;
1352
1353 gsi_end = gsi_base + npin - 1;
1354 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1355 if ((gsi_base >= info->io_gsi_base &&
1356 gsi_base < info->io_gsi_base + info->io_npin) ||
1357 (gsi_end >= info->io_gsi_base &&
1358 gsi_end < info->io_gsi_base + info->io_npin)) {
1359 panic("ioapic_add: overlapped gsi, base %d npin %d, "
1360 "hit base %d, npin %d\n", gsi_base, npin,
1361 info->io_gsi_base, info->io_npin);
1362 }
1363 if (info->io_addr == addr)
1364 panic("ioapic_add: duplicated addr %p\n", addr);
1365 }
1366
1367 ninfo = kmalloc(sizeof(*ninfo), M_DEVBUF, M_WAITOK | M_ZERO);
1368 ninfo->io_addr = addr;
1369 ninfo->io_npin = npin;
1370 ninfo->io_gsi_base = gsi_base;
68b90e82 1371 ninfo->io_apic_id = -1;
ebf4f417
SZ
1372
1373 /*
1374 * Create IOAPIC list in ascending order of GSI base
1375 */
1376 TAILQ_FOREACH_REVERSE(info, &ioapic_conf.ioc_list,
1377 ioapic_info_list, io_link) {
1378 if (ninfo->io_gsi_base > info->io_gsi_base) {
1379 TAILQ_INSERT_AFTER(&ioapic_conf.ioc_list,
1380 info, ninfo, io_link);
1381 break;
1382 }
1383 }
1384 if (info == NULL)
1385 TAILQ_INSERT_HEAD(&ioapic_conf.ioc_list, ninfo, io_link);
1386}
512fb675
SZ
1387
1388void
ae80be10 1389ioapic_intsrc(int irq, int gsi, enum intr_trigger trig, enum intr_polarity pola)
512fb675 1390{
ae80be10
SZ
1391 struct ioapic_intsrc *int_src;
1392
512fb675 1393 KKASSERT(irq < 16);
ae80be10 1394 int_src = &ioapic_conf.ioc_intsrc[irq];
7eb6fb7e
SZ
1395
1396 if (gsi == 0) {
1397 /* Don't allow mixed mode */
1398 kprintf("IOAPIC: warning intsrc irq %d -> gsi 0\n", irq);
1399 return;
1400 }
1401
ae80be10
SZ
1402 if (int_src->int_gsi != -1) {
1403 if (int_src->int_gsi != gsi) {
1404 kprintf("IOAPIC: warning intsrc irq %d, gsi "
1405 "%d -> %d\n", irq, int_src->int_gsi, gsi);
1406 }
1407 if (int_src->int_trig != trig) {
1408 kprintf("IOAPIC: warning intsrc irq %d, trig "
4ecd5d4d
SZ
1409 "%s -> %s\n", irq,
1410 intr_str_trigger(int_src->int_trig),
1411 intr_str_trigger(trig));
ae80be10
SZ
1412 }
1413 if (int_src->int_pola != pola) {
1414 kprintf("IOAPIC: warning intsrc irq %d, pola "
1415 "%s -> %s\n", irq,
4ecd5d4d
SZ
1416 intr_str_polarity(int_src->int_pola),
1417 intr_str_polarity(pola));
ae80be10 1418 }
512fb675 1419 }
ae80be10
SZ
1420 int_src->int_gsi = gsi;
1421 int_src->int_trig = trig;
1422 int_src->int_pola = pola;
512fb675 1423}
23b08e03
SZ
1424
1425static void
1426ioapic_set_apic_id(const struct ioapic_info *info)
1427{
1428 uint32_t id;
68b90e82 1429 int apic_id;
23b08e03
SZ
1430
1431 id = ioapic_read(info->io_addr, IOAPIC_ID);
1432
1433 id &= ~APIC_ID_MASK;
1434 id |= (info->io_apic_id << 24);
1435
1436 ioapic_write(info->io_addr, IOAPIC_ID, id);
1437
1438 /*
1439 * Re-read && test
1440 */
1441 id = ioapic_read(info->io_addr, IOAPIC_ID);
68b90e82
SZ
1442 apic_id = (id & APIC_ID_MASK) >> 24;
1443
1444 /*
1445 * I/O APIC ID is a 4bits field
1446 */
1447 if ((apic_id & IOAPIC_ID_MASK) !=
1448 (info->io_apic_id & IOAPIC_ID_MASK)) {
1449 panic("ioapic_set_apic_id: can't set apic id to %d, "
1450 "currently set to %d\n", info->io_apic_id, apic_id);
23b08e03
SZ
1451 }
1452}
1453
1454static void
1455ioapic_gsi_setup(int gsi)
1456{
1457 enum intr_trigger trig;
1458 enum intr_polarity pola;
1459 int irq;
1460
ecec8ddc
SZ
1461 if (gsi == 0) {
1462 /* ExtINT */
7bceaa10 1463 imen_lock();
ecec8ddc
SZ
1464 ioapic_extpin_setup(ioapic_gsi_ioaddr(gsi),
1465 ioapic_gsi_pin(gsi), 0);
7bceaa10 1466 imen_unlock();
ecec8ddc
SZ
1467 return;
1468 }
1469
23b08e03 1470 for (irq = 0; irq < 16; ++irq) {
ae80be10
SZ
1471 const struct ioapic_intsrc *int_src =
1472 &ioapic_conf.ioc_intsrc[irq];
1473
1474 if (gsi == int_src->int_gsi) {
1475 trig = int_src->int_trig;
1476 pola = int_src->int_pola;
23b08e03
SZ
1477 break;
1478 }
1479 }
1480
1481 if (irq == 16) {
ecec8ddc 1482 if (gsi < 16) {
23b08e03
SZ
1483 trig = INTR_TRIGGER_EDGE;
1484 pola = INTR_POLARITY_HIGH;
1485 } else {
1486 trig = INTR_TRIGGER_LEVEL;
1487 pola = INTR_POLARITY_LOW;
1488 }
1489 irq = gsi;
1490 }
1491
23b08e03 1492 ioapic_abi_set_irqmap(irq, gsi, trig, pola);
23b08e03
SZ
1493}
1494
1495void *
1496ioapic_gsi_ioaddr(int gsi)
1497{
1498 const struct ioapic_info *info;
1499
1500 info = ioapic_gsi_search(gsi);
1501 return info->io_addr;
1502}
1503
1504int
1505ioapic_gsi_pin(int gsi)
1506{
1507 const struct ioapic_info *info;
1508
1509 info = ioapic_gsi_search(gsi);
1510 return gsi - info->io_gsi_base;
1511}
1512
1513static const struct ioapic_info *
1514ioapic_gsi_search(int gsi)
1515{
1516 const struct ioapic_info *info;
1517
1518 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1519 if (gsi >= info->io_gsi_base &&
1520 gsi < info->io_gsi_base + info->io_npin)
1521 return info;
1522 }
1523 panic("ioapic_gsi_search: no I/O APIC\n");
1524}
1525
e90e7ac4
SZ
1526int
1527ioapic_gsi(int idx, int pin)
1528{
1529 const struct ioapic_info *info;
1530
1531 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1532 if (info->io_idx == idx)
1533 break;
1534 }
1535 if (info == NULL)
1536 return -1;
1537 if (pin >= info->io_npin)
1538 return -1;
1539 return info->io_gsi_base + pin;
1540}
1541
ecec8ddc
SZ
1542void
1543ioapic_extpin_setup(void *addr, int pin, int vec)
1544{
ecec8ddc
SZ
1545 ioapic_pin_prog(addr, pin, vec,
1546 INTR_TRIGGER_CONFORM, INTR_POLARITY_CONFORM, IOART_DELEXINT);
ecec8ddc
SZ
1547}
1548
6b809ec7
SZ
1549int
1550ioapic_extpin_gsi(void)
1551{
1552 return 0;
1553}
1554
ecec8ddc
SZ
1555void
1556ioapic_pin_setup(void *addr, int pin, int vec,
1557 enum intr_trigger trig, enum intr_polarity pola)
1558{
1559 /*
1560 * Always clear an I/O APIC pin before [re]programming it. This is
1561 * particularly important if the pin is set up for a level interrupt
1562 * as the IOART_REM_IRR bit might be set. When we reprogram the
1563 * vector any EOI from pending ints on this pin could be lost and
1564 * IRR might never get reset.
1565 *
1566 * To fix this problem, clear the vector and make sure it is
1567 * programmed as an edge interrupt. This should theoretically
1568 * clear IRR so we can later, safely program it as a level
1569 * interrupt.
1570 */
ecec8ddc
SZ
1571 ioapic_pin_prog(addr, pin, vec, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH,
1572 IOART_DELFIXED);
1573 ioapic_pin_prog(addr, pin, vec, trig, pola, IOART_DELFIXED);
ecec8ddc
SZ
1574}
1575
1576static void
1577ioapic_pin_prog(void *addr, int pin, int vec,
1578 enum intr_trigger trig, enum intr_polarity pola, uint32_t del_mode)
1579{
1580 uint32_t flags, target;
1581 int select;
1582
1583 KKASSERT(del_mode == IOART_DELEXINT || del_mode == IOART_DELFIXED);
1584
1585 select = IOAPIC_REDTBL0 + (2 * pin);
1586
1587 flags = ioapic_read(addr, select) & IOART_RESV;
ddb99c82
SZ
1588 flags |= IOART_INTMSET | IOART_DESTPHY;
1589#ifdef foo
1590 flags |= del_mode;
1591#else
1592 /*
1593 * We only support limited I/O APIC mixed mode,
1594 * so even for ExtINT, we still use "fixed"
1595 * delivery mode.
1596 */
1597 flags |= IOART_DELFIXED;
1598#endif
ecec8ddc
SZ
1599
1600 if (del_mode == IOART_DELEXINT) {
1601 KKASSERT(trig == INTR_TRIGGER_CONFORM &&
1602 pola == INTR_POLARITY_CONFORM);
1603 flags |= IOART_TRGREDG | IOART_INTAHI;
1604 } else {
1605 switch (trig) {
1606 case INTR_TRIGGER_EDGE:
1607 flags |= IOART_TRGREDG;
1608 break;
1609
1610 case INTR_TRIGGER_LEVEL:
1611 flags |= IOART_TRGRLVL;
1612 break;
1613
1614 case INTR_TRIGGER_CONFORM:
1615 panic("ioapic_pin_prog: trig conform is not "
1616 "supported\n");
1617 }
1618 switch (pola) {
1619 case INTR_POLARITY_HIGH:
1620 flags |= IOART_INTAHI;
1621 break;
1622
1623 case INTR_POLARITY_LOW:
1624 flags |= IOART_INTALO;
1625 break;
1626
1627 case INTR_POLARITY_CONFORM:
1628 panic("ioapic_pin_prog: pola conform is not "
1629 "supported\n");
1630 }
1631 }
1632
1633 target = ioapic_read(addr, select + 1) & IOART_HI_DEST_RESV;
522f877c
SZ
1634 target |= (CPU_TO_ID(0) << IOART_HI_DEST_SHIFT) &
1635 IOART_HI_DEST_MASK;
ecec8ddc
SZ
1636
1637 ioapic_write(addr, select, flags | vec);
1638 ioapic_write(addr, select + 1, target);
1639}
1640
23b08e03
SZ
1641static void
1642ioapic_setup(const struct ioapic_info *info)
1643{
1644 int i;
1645
1646 ioapic_set_apic_id(info);
1647
1648 for (i = 0; i < info->io_npin; ++i)
1649 ioapic_gsi_setup(info->io_gsi_base + i);
1650}
68b90e82
SZ
1651
1652static int
1653ioapic_alloc_apic_id(int start)
1654{
1655 for (;;) {
1656 const struct ioapic_info *info;
1657 int apic_id, apic_id16;
1658
1659 apic_id = lapic_unused_apic_id(start);
1660 if (apic_id == NAPICID) {
1661 kprintf("IOAPIC: can't find unused APIC ID\n");
1662 return apic_id;
1663 }
1664 apic_id16 = apic_id & IOAPIC_ID_MASK;
1665
1666 /*
1667 * Check against other I/O APIC's APIC ID's lower 4bits.
1668 *
1669 * The new APIC ID will have to be different from others
1670 * in the lower 4bits, no matter whether xAPIC is used
1671 * or not.
1672 */
1673 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1674 if (info->io_apic_id == -1) {
1675 info = NULL;
1676 break;
1677 }
1678 if ((info->io_apic_id & IOAPIC_ID_MASK) == apic_id16)
1679 break;
1680 }
1681 if (info == NULL)
1682 return apic_id;
1683
1684 kprintf("IOAPIC: APIC ID %d has same lower 4bits as "
1685 "%dth I/O APIC, keep searching...\n",
1686 apic_id, info->io_idx);
1687
1688 start = apic_id + 1;
1689 }
1690 panic("ioapic_unused_apic_id: never reached\n");
1691}