x86_64: Remove old IOAPIC code
[dragonfly.git] / sys / platform / pc64 / x86_64 / machdep.c
CommitLineData
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1/*-
2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * William Jolitz.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
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41 */
42
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43//#include "use_npx.h"
44#include "use_isa.h"
45#include "opt_atalk.h"
46#include "opt_compat.h"
47#include "opt_cpu.h"
48#include "opt_ddb.h"
49#include "opt_directio.h"
50#include "opt_inet.h"
51#include "opt_ipx.h"
52#include "opt_msgbuf.h"
53#include "opt_swap.h"
eac0bf8f 54#include "opt_apic.h"
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55
56#include <sys/param.h>
57#include <sys/systm.h>
58#include <sys/sysproto.h>
59#include <sys/signalvar.h>
60#include <sys/kernel.h>
61#include <sys/linker.h>
62#include <sys/malloc.h>
63#include <sys/proc.h>
895c1f85 64#include <sys/priv.h>
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65#include <sys/buf.h>
66#include <sys/reboot.h>
67#include <sys/mbuf.h>
68#include <sys/msgbuf.h>
69#include <sys/sysent.h>
70#include <sys/sysctl.h>
71#include <sys/vmmeter.h>
72#include <sys/bus.h>
73#include <sys/upcall.h>
74#include <sys/usched.h>
75#include <sys/reg.h>
76
77#include <vm/vm.h>
78#include <vm/vm_param.h>
79#include <sys/lock.h>
80#include <vm/vm_kern.h>
81#include <vm/vm_object.h>
82#include <vm/vm_page.h>
83#include <vm/vm_map.h>
84#include <vm/vm_pager.h>
85#include <vm/vm_extern.h>
86
87#include <sys/thread2.h>
684a93c4 88#include <sys/mplock2.h>
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89
90#include <sys/user.h>
91#include <sys/exec.h>
92#include <sys/cons.h>
93
94#include <ddb/ddb.h>
95
96#include <machine/cpu.h>
97#include <machine/clock.h>
98#include <machine/specialreg.h>
99#if JG
100#include <machine/bootinfo.h>
101#endif
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102#include <machine/md_var.h>
103#include <machine/metadata.h>
104#include <machine/pc/bios.h>
105#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
106#include <machine/globaldata.h> /* CPU_prvspace */
107#include <machine/smp.h>
108#ifdef PERFMON
109#include <machine/perfmon.h>
110#endif
111#include <machine/cputypes.h>
57a9c56b 112#include <machine/intr_machdep.h>
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113
114#ifdef OLD_BUS_ARCH
46d4e165 115#include <bus/isa/isa_device.h>
c8fe38ae 116#endif
57a9c56b 117#include <machine_base/isa/isa_intr.h>
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118#include <bus/isa/rtc.h>
119#include <sys/random.h>
120#include <sys/ptrace.h>
121#include <machine/sigframe.h>
122
faaf4131 123#include <sys/machintr.h>
9284cddf 124#include <machine_base/icu/icu_abi.h>
7265a4fe 125#include <machine_base/icu/elcr_var.h>
a3dd9120 126#include <machine_base/apic/ioapic_abi.h>
faaf4131 127
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128#define PHYSMAP_ENTRIES 10
129
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130extern u_int64_t hammer_time(u_int64_t, u_int64_t);
131
132extern void printcpuinfo(void); /* XXX header file */
133extern void identify_cpu(void);
134#if JG
135extern void finishidentcpu(void);
136#endif
137extern void panicifcpuunsupported(void);
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138
139static void cpu_startup(void *);
140#ifndef CPU_DISABLE_SSE
141static void set_fpregs_xmm(struct save87 *, struct savexmm *);
142static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
143#endif /* CPU_DISABLE_SSE */
144#ifdef DIRECTIO
145extern void ffs_rawread_setup(void);
146#endif /* DIRECTIO */
147static void init_locks(void);
148
149SYSINIT(cpu, SI_BOOT2_SMP, SI_ORDER_FIRST, cpu_startup, NULL)
150
151#ifdef DDB
152extern vm_offset_t ksym_start, ksym_end;
153#endif
154
da23a592 155struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
48ffc236 156
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157int _udatasel, _ucodesel, _ucode32sel;
158u_long atdevbase;
159#ifdef SMP
160int64_t tsc_offsets[MAXCPU];
161#else
162int64_t tsc_offsets[1];
163#endif
164
165#if defined(SWTCH_OPTIM_STATS)
166extern int swtch_optim_stats;
167SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
168 CTLFLAG_RD, &swtch_optim_stats, 0, "");
169SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
170 CTLFLAG_RD, &tlb_flush_count, 0, "");
171#endif
172
39d69dae 173long physmem = 0;
c8fe38ae 174
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175u_long ebda_addr = 0;
176
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177static int
178sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
179{
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180 u_long pmem = ctob(physmem);
181
182 int error = sysctl_handle_long(oidp, &pmem, 0, req);
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183 return (error);
184}
185
39d69dae 186SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
9b9532a0 187 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
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188
189static int
190sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
191{
192 int error = sysctl_handle_int(oidp, 0,
193 ctob(physmem - vmstats.v_wire_count), req);
194 return (error);
195}
196
197SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
198 0, 0, sysctl_hw_usermem, "IU", "");
199
200static int
201sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
202{
c8fe38ae 203 int error = sysctl_handle_int(oidp, 0,
b2b3ffcd 204 x86_64_btop(avail_end - avail_start), req);
c8fe38ae 205 return (error);
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206}
207
208SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
209 0, 0, sysctl_hw_availpages, "I", "");
210
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211vm_paddr_t Maxmem;
212vm_paddr_t Realmem;
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213
214/*
215 * The number of PHYSMAP entries must be one less than the number of
216 * PHYSSEG entries because the PHYSMAP entry that spans the largest
217 * physical address that is accessible by ISA DMA is split into two
218 * PHYSSEG entries.
219 */
220#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
221
222vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
223vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
224
225/* must be 2 less so 0 0 can signal end of chunks */
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226#define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
227#define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
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228
229static vm_offset_t buffer_sva, buffer_eva;
230vm_offset_t clean_sva, clean_eva;
231static vm_offset_t pager_sva, pager_eva;
232static struct trapframe proc0_tf;
233
234static void
235cpu_startup(void *dummy)
236{
237 caddr_t v;
238 vm_size_t size = 0;
239 vm_offset_t firstaddr;
240
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241 /*
242 * Good {morning,afternoon,evening,night}.
243 */
244 kprintf("%s", version);
245 startrtclock();
246 printcpuinfo();
247 panicifcpuunsupported();
248#ifdef PERFMON
249 perfmon_init();
250#endif
15dc6550 251 kprintf("real memory = %ju (%ju MB)\n",
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252 (intmax_t)Realmem,
253 (intmax_t)Realmem / 1024 / 1024);
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254 /*
255 * Display any holes after the first chunk of extended memory.
256 */
257 if (bootverbose) {
258 int indx;
259
260 kprintf("Physical memory chunk(s):\n");
261 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
262 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
263
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264 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
265 (intmax_t)phys_avail[indx],
266 (intmax_t)phys_avail[indx + 1] - 1,
267 (intmax_t)size1,
268 (intmax_t)(size1 / PAGE_SIZE));
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269 }
270 }
271
272 /*
273 * Allocate space for system data structures.
274 * The first available kernel virtual address is in "v".
275 * As pages of kernel virtual memory are allocated, "v" is incremented.
276 * As pages of memory are allocated and cleared,
277 * "firstaddr" is incremented.
278 * An index into the kernel page table corresponding to the
279 * virtual memory address maintained in "v" is kept in "mapaddr".
280 */
281
282 /*
283 * Make two passes. The first pass calculates how much memory is
284 * needed and allocates it. The second pass assigns virtual
285 * addresses to the various data structures.
286 */
287 firstaddr = 0;
288again:
289 v = (caddr_t)firstaddr;
290
291#define valloc(name, type, num) \
292 (name) = (type *)v; v = (caddr_t)((name)+(num))
293#define valloclim(name, type, num, lim) \
294 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
295
296 /*
297 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
298 * For the first 64MB of ram nominally allocate sufficient buffers to
299 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
300 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
301 * the buffer cache we limit the eventual kva reservation to
302 * maxbcache bytes.
303 *
304 * factor represents the 1/4 x ram conversion.
305 */
306 if (nbuf == 0) {
307 int factor = 4 * BKVASIZE / 1024;
308 int kbytes = physmem * (PAGE_SIZE / 1024);
309
310 nbuf = 50;
311 if (kbytes > 4096)
312 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
313 if (kbytes > 65536)
314 nbuf += (kbytes - 65536) * 2 / (factor * 5);
315 if (maxbcache && nbuf > maxbcache / BKVASIZE)
316 nbuf = maxbcache / BKVASIZE;
317 }
318
319 /*
320 * Do not allow the buffer_map to be more then 1/2 the size of the
321 * kernel_map.
322 */
323 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
324 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
325 kprintf("Warning: nbufs capped at %d\n", nbuf);
326 }
327
328 nswbuf = max(min(nbuf/4, 256), 16);
329#ifdef NSWBUF_MIN
330 if (nswbuf < NSWBUF_MIN)
331 nswbuf = NSWBUF_MIN;
332#endif
333#ifdef DIRECTIO
334 ffs_rawread_setup();
335#endif
336
337 valloc(swbuf, struct buf, nswbuf);
338 valloc(buf, struct buf, nbuf);
339
340 /*
341 * End of first pass, size has been calculated so allocate memory
342 */
343 if (firstaddr == 0) {
344 size = (vm_size_t)(v - firstaddr);
345 firstaddr = kmem_alloc(&kernel_map, round_page(size));
346 if (firstaddr == 0)
347 panic("startup: no room for tables");
348 goto again;
349 }
350
351 /*
352 * End of second pass, addresses have been assigned
353 */
354 if ((vm_size_t)(v - firstaddr) != size)
355 panic("startup: table size inconsistency");
356
357 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
358 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
359 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
360 (nbuf*BKVASIZE));
361 buffer_map.system_map = 1;
362 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
363 (nswbuf*MAXPHYS) + pager_map_size);
364 pager_map.system_map = 1;
365
366#if defined(USERCONFIG)
367 userconfig();
368 cninit(); /* the preferred console may have changed */
369#endif
370
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371 kprintf("avail memory = %ju (%ju MB)\n",
372 (uintmax_t)ptoa(vmstats.v_free_count),
373 (uintmax_t)ptoa(vmstats.v_free_count) / 1024 / 1024);
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374
375 /*
376 * Set up buffers, so they can be used to read disk labels.
377 */
378 bufinit();
379 vm_pager_bufferinit();
380
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381 /* Log ELCR information */
382 elcr_dump();
383
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384#ifdef SMP
385 /*
386 * OK, enough kmem_alloc/malloc state should be up, lets get on with it!
387 */
388 mp_start(); /* fire up the APs and APICs */
389 mp_announce();
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390#else
391 MachIntrABI.finalize();
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392#endif /* SMP */
393 cpu_setregs();
394}
395
396/*
397 * Send an interrupt to process.
398 *
399 * Stack is set up to allow sigcode stored
400 * at top to call routine, followed by kcall
401 * to sigreturn routine below. After sigreturn
402 * resets the signal mask, the stack, and the
403 * frame pointer, it returns to the user
404 * specified pc, psl.
405 */
406void
407sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
408{
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409 struct lwp *lp = curthread->td_lwp;
410 struct proc *p = lp->lwp_proc;
411 struct trapframe *regs;
412 struct sigacts *psp = p->p_sigacts;
413 struct sigframe sf, *sfp;
414 int oonstack;
a6a09809 415 char *sp;
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416
417 regs = lp->lwp_md.md_regs;
418 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
419
a6a09809 420 /* Save user context */
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421 bzero(&sf, sizeof(struct sigframe));
422 sf.sf_uc.uc_sigmask = *mask;
423 sf.sf_uc.uc_stack = lp->lwp_sigstk;
424 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
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425 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
426 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
c8fe38ae 427
a6a09809 428 /* Make the size of the saved context visible to userland */
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429 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
430
a6a09809 431 /* Save mailbox pending state for syscall interlock semantics */
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432 if (p->p_flag & P_MAILBOX)
433 sf.sf_uc.uc_mcontext.mc_xflags |= PGEX_MAILBOX;
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434
435 /* Allocate and validate space for the signal handler context. */
436 if ((lp->lwp_flag & LWP_ALTSTACK) != 0 && !oonstack &&
437 SIGISMEMBER(psp->ps_sigonstack, sig)) {
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438 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
439 sizeof(struct sigframe));
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440 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
441 } else {
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442 /* We take red zone into account */
443 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
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444 }
445
a6a09809 446 /* Align to 16 bytes */
4117f2fd 447 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
a6a09809 448
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449 /* Translate the signal is appropriate */
450 if (p->p_sysent->sv_sigtbl) {
451 if (sig <= p->p_sysent->sv_sigsize)
452 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
453 }
454
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455 /*
456 * Build the argument list for the signal handler.
457 *
458 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
459 */
460 regs->tf_rdi = sig; /* argument 1 */
461 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
462
c8fe38ae 463 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
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464 /*
465 * Signal handler installed with SA_SIGINFO.
466 *
467 * action(signo, siginfo, ucontext)
468 */
469 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
630d9ab4 470 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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471 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
472
473 /* fill siginfo structure */
474 sf.sf_si.si_signo = sig;
475 sf.sf_si.si_code = code;
630d9ab4 476 sf.sf_si.si_addr = (void *)regs->tf_addr;
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477 } else {
478 /*
479 * Old FreeBSD-style arguments.
480 *
481 * handler (signo, code, [uc], addr)
482 */
483 regs->tf_rsi = (register_t)code; /* argument 2 */
630d9ab4 484 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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485 sf.sf_ahu.sf_handler = catcher;
486 }
487
488 /*
489 * If we're a vm86 process, we want to save the segment registers.
490 * We also change eflags to be our emulated eflags, not the actual
491 * eflags.
492 */
493#if JG
494 if (regs->tf_eflags & PSL_VM) {
495 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
496 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
497
498 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
499 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
500 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
501 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
502
503 if (vm86->vm86_has_vme == 0)
504 sf.sf_uc.uc_mcontext.mc_eflags =
505 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
506 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
507
508 /*
509 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
510 * syscalls made by the signal handler. This just avoids
511 * wasting time for our lazy fixup of such faults. PSL_NT
512 * does nothing in vm86 mode, but vm86 programs can set it
513 * almost legitimately in probes for old cpu types.
514 */
515 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
516 }
517#endif
518
519 /*
520 * Save the FPU state and reinit the FP unit
521 */
c8fe38ae 522 npxpush(&sf.sf_uc.uc_mcontext);
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523
524 /*
525 * Copy the sigframe out to the user's stack.
526 */
527 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
528 /*
529 * Something is wrong with the stack pointer.
530 * ...Kill the process.
531 */
532 sigexit(lp, SIGILL);
533 }
534
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535 regs->tf_rsp = (register_t)sfp;
536 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
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537
538 /*
539 * i386 abi specifies that the direction flag must be cleared
540 * on function entry
541 */
5b9f6cc4 542 regs->tf_rflags &= ~(PSL_T|PSL_D);
c8fe38ae 543
c8fe38ae 544 /*
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545 * 64 bit mode has a code and stack selector but
546 * no data or extra selector. %fs and %gs are not
547 * stored in-context.
c8fe38ae 548 */
a6a09809 549 regs->tf_cs = _ucodesel;
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550 regs->tf_ss = _udatasel;
551}
552
553/*
554 * Sanitize the trapframe for a virtual kernel passing control to a custom
555 * VM context. Remove any items that would otherwise create a privilage
556 * issue.
557 *
558 * XXX at the moment we allow userland to set the resume flag. Is this a
559 * bad idea?
560 */
561int
562cpu_sanitize_frame(struct trapframe *frame)
563{
c8fe38ae 564 frame->tf_cs = _ucodesel;
c8fe38ae 565 frame->tf_ss = _udatasel;
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566 /* XXX VM (8086) mode not supported? */
567 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
568 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
569
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570 return(0);
571}
572
573/*
574 * Sanitize the tls so loading the descriptor does not blow up
b2b3ffcd 575 * on us. For x86_64 we don't have to do anything.
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576 */
577int
578cpu_sanitize_tls(struct savetls *tls)
579{
580 return(0);
581}
582
583/*
584 * sigreturn(ucontext_t *sigcntxp)
585 *
586 * System call to cleanup state after a signal
587 * has been taken. Reset signal mask and
588 * stack state from context left by sendsig (above).
589 * Return to previous pc and psl as specified by
590 * context left by sendsig. Check carefully to
591 * make sure that the user has not modified the
592 * state to gain improper privileges.
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593 *
594 * MPSAFE
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595 */
596#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
597#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
598
599int
600sys_sigreturn(struct sigreturn_args *uap)
601{
602 struct lwp *lp = curthread->td_lwp;
603 struct proc *p = lp->lwp_proc;
604 struct trapframe *regs;
605 ucontext_t uc;
606 ucontext_t *ucp;
5b9f6cc4 607 register_t rflags;
c8fe38ae 608 int cs;
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609 int error;
610
611 /*
612 * We have to copy the information into kernel space so userland
613 * can't modify it while we are sniffing it.
614 */
615 regs = lp->lwp_md.md_regs;
616 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
617 if (error)
618 return (error);
619 ucp = &uc;
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620 rflags = ucp->uc_mcontext.mc_rflags;
621
622 /* VM (8086) mode not supported */
623 rflags &= ~PSL_VM_UNSUPP;
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624
625#if JG
626 if (eflags & PSL_VM) {
627 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
628 struct vm86_kernel *vm86;
629
630 /*
631 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
632 * set up the vm86 area, and we can't enter vm86 mode.
633 */
634 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
635 return (EINVAL);
636 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
637 if (vm86->vm86_inited == 0)
638 return (EINVAL);
639
640 /* go back to user mode if both flags are set */
641 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
642 trapsignal(lp, SIGBUS, 0);
643
644 if (vm86->vm86_has_vme) {
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645 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
646 (eflags & VME_USERCHANGE) | PSL_VM;
c8fe38ae 647 } else {
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648 vm86->vm86_eflags = eflags; /* save VIF, VIP */
649 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
650 (eflags & VM_USERCHANGE) | PSL_VM;
c8fe38ae 651 }
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652 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
653 tf->tf_eflags = eflags;
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654 tf->tf_vm86_ds = tf->tf_ds;
655 tf->tf_vm86_es = tf->tf_es;
656 tf->tf_vm86_fs = tf->tf_fs;
657 tf->tf_vm86_gs = tf->tf_gs;
658 tf->tf_ds = _udatasel;
659 tf->tf_es = _udatasel;
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660 tf->tf_fs = _udatasel;
661 tf->tf_gs = _udatasel;
5b9f6cc4 662 } else
c8fe38ae 663#endif
5b9f6cc4 664 {
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665 /*
666 * Don't allow users to change privileged or reserved flags.
667 */
668 /*
669 * XXX do allow users to change the privileged flag PSL_RF.
670 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
671 * should sometimes set it there too. tf_eflags is kept in
672 * the signal context during signal handling and there is no
673 * other place to remember it, so the PSL_RF bit may be
674 * corrupted by the signal handler without us knowing.
675 * Corruption of the PSL_RF bit at worst causes one more or
676 * one less debugger trap, so allowing it is fairly harmless.
677 */
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678 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
679 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
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680 return(EINVAL);
681 }
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682
683 /*
684 * Don't allow users to load a valid privileged %cs. Let the
685 * hardware check for invalid selectors, excess privilege in
686 * other selectors, invalid %eip's and invalid %esp's.
687 */
688 cs = ucp->uc_mcontext.mc_cs;
689 if (!CS_SECURE(cs)) {
690 kprintf("sigreturn: cs = 0x%x\n", cs);
691 trapsignal(lp, SIGBUS, T_PROTFLT);
692 return(EINVAL);
693 }
5b9f6cc4 694 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
c8fe38ae 695 }
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696
697 /*
698 * Restore the FPU state from the frame
699 */
3919ced0 700 crit_enter();
c8fe38ae 701 npxpop(&ucp->uc_mcontext);
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702
703 /*
704 * Merge saved signal mailbox pending flag to maintain interlock
705 * semantics against system calls.
706 */
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707 if (ucp->uc_mcontext.mc_xflags & PGEX_MAILBOX)
708 p->p_flag |= P_MAILBOX;
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709
710 if (ucp->uc_mcontext.mc_onstack & 1)
711 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
712 else
713 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
714
715 lp->lwp_sigmask = ucp->uc_sigmask;
716 SIG_CANTMASK(lp->lwp_sigmask);
3919ced0 717 crit_exit();
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718 return(EJUSTRETURN);
719}
720
721/*
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722 * Stack frame on entry to function. %rax will contain the function vector,
723 * %rcx will contain the function data. flags, rcx, and rax will have
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724 * already been pushed on the stack.
725 */
726struct upc_frame {
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727 register_t rax;
728 register_t rcx;
729 register_t rdx;
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730 register_t flags;
731 register_t oldip;
732};
733
734void
735sendupcall(struct vmupcall *vu, int morepending)
736{
737 struct lwp *lp = curthread->td_lwp;
738 struct trapframe *regs;
739 struct upcall upcall;
740 struct upc_frame upc_frame;
741 int crit_count = 0;
742
743 /*
744 * If we are a virtual kernel running an emulated user process
745 * context, switch back to the virtual kernel context before
746 * trying to post the signal.
747 */
748 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
749 lp->lwp_md.md_regs->tf_trapno = 0;
750 vkernel_trap(lp, lp->lwp_md.md_regs);
751 }
752
753 /*
754 * Get the upcall data structure
755 */
756 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
757 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
758 ) {
759 vu->vu_pending = 0;
760 kprintf("bad upcall address\n");
761 return;
762 }
763
764 /*
765 * If the data structure is already marked pending or has a critical
766 * section count, mark the data structure as pending and return
767 * without doing an upcall. vu_pending is left set.
768 */
769 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
770 if (upcall.upc_pending < vu->vu_pending) {
771 upcall.upc_pending = vu->vu_pending;
772 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
773 sizeof(upcall.upc_pending));
774 }
775 return;
776 }
777
778 /*
779 * We can run this upcall now, clear vu_pending.
780 *
781 * Bump our critical section count and set or clear the
782 * user pending flag depending on whether more upcalls are
783 * pending. The user will be responsible for calling
784 * upc_dispatch(-1) to process remaining upcalls.
785 */
786 vu->vu_pending = 0;
787 upcall.upc_pending = morepending;
f9235b6d 788 ++crit_count;
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789 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
790 sizeof(upcall.upc_pending));
791 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
792 sizeof(int));
793
794 /*
795 * Construct a stack frame and issue the upcall
796 */
797 regs = lp->lwp_md.md_regs;
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798 upc_frame.rax = regs->tf_rax;
799 upc_frame.rcx = regs->tf_rcx;
800 upc_frame.rdx = regs->tf_rdx;
801 upc_frame.flags = regs->tf_rflags;
802 upc_frame.oldip = regs->tf_rip;
803 if (copyout(&upc_frame, (void *)(regs->tf_rsp - sizeof(upc_frame)),
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804 sizeof(upc_frame)) != 0) {
805 kprintf("bad stack on upcall\n");
806 } else {
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807 regs->tf_rax = (register_t)vu->vu_func;
808 regs->tf_rcx = (register_t)vu->vu_data;
809 regs->tf_rdx = (register_t)lp->lwp_upcall;
810 regs->tf_rip = (register_t)vu->vu_ctx;
811 regs->tf_rsp -= sizeof(upc_frame);
c8fe38ae 812 }
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813}
814
815/*
816 * fetchupcall occurs in the context of a system call, which means that
817 * we have to return EJUSTRETURN in order to prevent eax and edx from
818 * being overwritten by the syscall return value.
819 *
820 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
821 * and the function pointer in %eax.
822 */
823int
824fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
825{
826 struct upc_frame upc_frame;
827 struct lwp *lp = curthread->td_lwp;
828 struct trapframe *regs;
829 int error;
830 struct upcall upcall;
831 int crit_count;
832
833 regs = lp->lwp_md.md_regs;
834
835 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
836 if (error == 0) {
837 if (vu) {
838 /*
839 * This jumps us to the next ready context.
840 */
841 vu->vu_pending = 0;
842 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
843 crit_count = 0;
844 if (error == 0)
845 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 846 ++crit_count;
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847 if (error == 0)
848 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
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849 regs->tf_rax = (register_t)vu->vu_func;
850 regs->tf_rcx = (register_t)vu->vu_data;
851 regs->tf_rdx = (register_t)lp->lwp_upcall;
852 regs->tf_rip = (register_t)vu->vu_ctx;
853 regs->tf_rsp = (register_t)rsp;
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854 } else {
855 /*
856 * This returns us to the originally interrupted code.
857 */
858 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
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859 regs->tf_rax = upc_frame.rax;
860 regs->tf_rcx = upc_frame.rcx;
861 regs->tf_rdx = upc_frame.rdx;
862 regs->tf_rflags = (regs->tf_rflags & ~PSL_USERCHANGE) |
c8fe38ae 863 (upc_frame.flags & PSL_USERCHANGE);
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864 regs->tf_rip = upc_frame.oldip;
865 regs->tf_rsp = (register_t)((char *)rsp + sizeof(upc_frame));
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866 }
867 }
868 if (error == 0)
869 error = EJUSTRETURN;
870 return(error);
871}
872
873/*
874 * Machine dependent boot() routine
875 *
876 * I haven't seen anything to put here yet
877 * Possibly some stuff might be grafted back here from boot()
878 */
879void
880cpu_boot(int howto)
881{
882}
883
884/*
885 * Shutdown the CPU as much as possible
886 */
887void
888cpu_halt(void)
889{
890 for (;;)
891 __asm__ __volatile("hlt");
892}
893
894/*
895 * cpu_idle() represents the idle LWKT. You cannot return from this function
896 * (unless you want to blow things up!). Instead we look for runnable threads
897 * and loop or halt as appropriate. Giant is not held on entry to the thread.
898 *
899 * The main loop is entered with a critical section held, we must release
900 * the critical section before doing anything else. lwkt_switch() will
901 * check for pending interrupts due to entering and exiting its own
902 * critical section.
903 *
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904 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
905 * However, there are cases where the idlethread will be entered with
906 * the possibility that no IPI will occur and in such cases
907 * lwkt_switch() sets TDF_IDLE_NOHLT.
908 *
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909 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
910 * 1 to just use hlt and for debugging purposes.
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911 *
912 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
913 * must occur before it starts using ACPI halt.
c8fe38ae 914 */
46e562ce 915static int cpu_idle_hlt = 2;
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916static int cpu_idle_hltcnt;
917static int cpu_idle_spincnt;
be71787b 918static u_int cpu_idle_repeat = 4;
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919SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
920 &cpu_idle_hlt, 0, "Idle loop HLT enable");
921SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
922 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
923SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
924 &cpu_idle_spincnt, 0, "Idle loop entry spins");
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925SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
926 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
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927
928static void
929cpu_idle_default_hook(void)
930{
931 /*
932 * We must guarentee that hlt is exactly the instruction
933 * following the sti.
934 */
935 __asm __volatile("sti; hlt");
936}
937
938/* Other subsystems (e.g., ACPI) can hook this later. */
939void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
940
941void
942cpu_idle(void)
943{
0f0466c0 944 globaldata_t gd = mycpu;
86232a57 945 struct thread *td __debugvar = gd->gd_curthread;
0f0466c0 946 int reqflags;
be71787b 947 int quick;
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948
949 crit_exit();
f9235b6d 950 KKASSERT(td->td_critcount == 0);
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951 for (;;) {
952 /*
953 * See if there are any LWKTs ready to go.
954 */
955 lwkt_switch();
956
957 /*
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958 * When halting inside a cli we must check for reqflags
959 * races, particularly [re]schedule requests. Running
960 * splz() does the job.
961 *
962 * cpu_idle_hlt:
963 * 0 Never halt, just spin
964 *
965 * 1 Always use HLT (or MONITOR/MWAIT if avail).
966 * This typically eats more power than the
967 * ACPI halt.
968 *
969 * 2 Use HLT/MONITOR/MWAIT up to a point and then
970 * use the ACPI halt (default). This is a hybrid
971 * approach. See machdep.cpu_idle_repeat.
972 *
973 * 3 Always use the ACPI halt. This typically
974 * eats the least amount of power but the cpu
975 * will be slow waking up. Slows down e.g.
976 * compiles and other pipe/event oriented stuff.
977 *
978 * NOTE: Interrupts are enabled and we are not in a critical
979 * section.
980 *
981 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
982 * don't bother capping gd_idle_repeat, it is ok if
983 * it overflows.
c8fe38ae 984 */
be71787b 985 ++gd->gd_idle_repeat;
0f0466c0 986 reqflags = gd->gd_reqflags;
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987 quick = (cpu_idle_hlt == 1) ||
988 (cpu_idle_hlt < 3 &&
989 gd->gd_idle_repeat < cpu_idle_repeat);
990
991 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
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992 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
993 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
be71787b 994 ++cpu_idle_hltcnt;
0f0466c0 995 } else if (cpu_idle_hlt) {
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996 __asm __volatile("cli");
997 splz();
0f0466c0 998 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
be71787b 999 if (quick)
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1000 cpu_idle_default_hook();
1001 else
1002 cpu_idle_hook();
1003 }
7d4d6fdb 1004 __asm __volatile("sti");
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1005 ++cpu_idle_hltcnt;
1006 } else {
c8fe38ae 1007 splz();
c5724852 1008 __asm __volatile("sti");
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1009 ++cpu_idle_spincnt;
1010 }
1011 }
1012}
1013
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1014#ifdef SMP
1015
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1016/*
1017 * This routine is called if a spinlock has been held through the
1018 * exponential backoff period and is seriously contested. On a real cpu
1019 * we let it spin.
1020 */
1021void
1022cpu_spinlock_contested(void)
1023{
1024 cpu_pause();
1025}
1026
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1027#endif
1028
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1029/*
1030 * Clear registers on exec
1031 */
1032void
1033exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1034{
1035 struct thread *td = curthread;
1036 struct lwp *lp = td->td_lwp;
1037 struct pcb *pcb = td->td_pcb;
1038 struct trapframe *regs = lp->lwp_md.md_regs;
1039
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1040 /* was i386_user_cleanup() in NetBSD */
1041 user_ldt_free(pcb);
1042
1043 bzero((char *)regs, sizeof(struct trapframe));
1044 regs->tf_rip = entry;
1045 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1046 regs->tf_rdi = stack; /* argv */
1047 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1048 regs->tf_ss = _udatasel;
1049 regs->tf_cs = _ucodesel;
1050 regs->tf_rbx = ps_strings;
1051
1052 /*
1053 * Reset the hardware debug registers if they were in use.
1054 * They won't have any meaning for the newly exec'd process.
1055 */
1056 if (pcb->pcb_flags & PCB_DBREGS) {
1057 pcb->pcb_dr0 = 0;
1058 pcb->pcb_dr1 = 0;
1059 pcb->pcb_dr2 = 0;
1060 pcb->pcb_dr3 = 0;
1061 pcb->pcb_dr6 = 0;
0855a2af 1062 pcb->pcb_dr7 = 0; /* JG set bit 10? */
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1063 if (pcb == td->td_pcb) {
1064 /*
1065 * Clear the debug registers on the running
1066 * CPU, otherwise they will end up affecting
1067 * the next process we switch to.
1068 */
1069 reset_dbregs();
1070 }
1071 pcb->pcb_flags &= ~PCB_DBREGS;
1072 }
1073
1074 /*
1075 * Initialize the math emulator (if any) for the current process.
1076 * Actually, just clear the bit that says that the emulator has
1077 * been initialized. Initialization is delayed until the process
1078 * traps to the emulator (if it is done at all) mainly because
1079 * emulators don't provide an entry point for initialization.
1080 */
c8fe38ae 1081 pcb->pcb_flags &= ~FP_SOFTFP;
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1082
1083 /*
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1084 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1085 * gd_npxthread. Otherwise a preemptive interrupt thread
1086 * may panic in npxdna().
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1087 */
1088 crit_enter();
1089 load_cr0(rcr0() | CR0_MP);
1090
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1091 /*
1092 * NOTE: The MSR values must be correct so we can return to
1093 * userland. gd_user_fs/gs must be correct so the switch
1094 * code knows what the current MSR values are.
1095 */
1096 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
c8fe38ae 1097 pcb->pcb_gsbase = 0;
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1098 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1099 mdcpu->gd_user_gs = 0;
1100 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1101 wrmsr(MSR_KGSBASE, 0);
c8fe38ae 1102
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1103 /* Initialize the npx (if any) for the current process. */
1104 npxinit(__INITIAL_NPXCW__);
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1105 crit_exit();
1106
1107 pcb->pcb_ds = _udatasel;
1108 pcb->pcb_es = _udatasel;
1109 pcb->pcb_fs = _udatasel;
1110 pcb->pcb_gs = _udatasel;
1111}
1112
1113void
1114cpu_setregs(void)
1115{
1116 register_t cr0;
1117
1118 cr0 = rcr0();
1119 cr0 |= CR0_NE; /* Done by npxinit() */
1120 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1121 cr0 |= CR0_WP | CR0_AM;
1122 load_cr0(cr0);
1123 load_gs(_udatasel);
1124}
1125
1126static int
1127sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1128{
1129 int error;
1130 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1131 req);
1132 if (!error && req->newptr)
1133 resettodr();
1134 return (error);
1135}
1136
1137SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1138 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1139
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1140SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1141 CTLFLAG_RW, &disable_rtc_set, 0, "");
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1142
1143#if JG
1144SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1145 CTLFLAG_RD, &bootinfo, bootinfo, "");
1146#endif
1147
1148SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1149 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1150
1151extern u_long bootdev; /* not a cdev_t - encoding is different */
1152SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1153 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1154
1155/*
1156 * Initialize 386 and configure to run kernel
1157 */
1158
1159/*
1160 * Initialize segments & interrupt table
1161 */
1162
1163int _default_ldt;
1164struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1165static struct gate_descriptor idt0[NIDT];
1166struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1167#if JG
1168union descriptor ldt[NLDT]; /* local descriptor table */
1169#endif
1170
1171/* table descriptors - used to load tables by cpu */
1172struct region_descriptor r_gdt, r_idt;
1173
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1174/* JG proc0paddr is a virtual address */
1175void *proc0paddr;
1176/* JG alignment? */
1177char proc0paddr_buff[LWKT_THREAD_STACK];
1178
1179
1180/* software prototypes -- in more palatable form */
1181struct soft_segment_descriptor gdt_segs[] = {
1182/* GNULL_SEL 0 Null Descriptor */
1183{ 0x0, /* segment base address */
1184 0x0, /* length */
1185 0, /* segment type */
1186 0, /* segment descriptor priority level */
1187 0, /* segment descriptor present */
1188 0, /* long */
1189 0, /* default 32 vs 16 bit size */
1190 0 /* limit granularity (byte/page units)*/ },
1191/* GCODE_SEL 1 Code Descriptor for kernel */
1192{ 0x0, /* segment base address */
1193 0xfffff, /* length - all address space */
1194 SDT_MEMERA, /* segment type */
1195 SEL_KPL, /* segment descriptor priority level */
1196 1, /* segment descriptor present */
1197 1, /* long */
1198 0, /* default 32 vs 16 bit size */
1199 1 /* limit granularity (byte/page units)*/ },
1200/* GDATA_SEL 2 Data Descriptor for kernel */
1201{ 0x0, /* segment base address */
1202 0xfffff, /* length - all address space */
1203 SDT_MEMRWA, /* segment type */
1204 SEL_KPL, /* segment descriptor priority level */
1205 1, /* segment descriptor present */
1206 1, /* long */
1207 0, /* default 32 vs 16 bit size */
1208 1 /* limit granularity (byte/page units)*/ },
1209/* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1210{ 0x0, /* segment base address */
1211 0xfffff, /* length - all address space */
1212 SDT_MEMERA, /* segment type */
1213 SEL_UPL, /* segment descriptor priority level */
1214 1, /* segment descriptor present */
1215 0, /* long */
1216 1, /* default 32 vs 16 bit size */
1217 1 /* limit granularity (byte/page units)*/ },
1218/* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1219{ 0x0, /* segment base address */
1220 0xfffff, /* length - all address space */
1221 SDT_MEMRWA, /* segment type */
1222 SEL_UPL, /* segment descriptor priority level */
1223 1, /* segment descriptor present */
1224 0, /* long */
1225 1, /* default 32 vs 16 bit size */
1226 1 /* limit granularity (byte/page units)*/ },
1227/* GUCODE_SEL 5 64 bit Code Descriptor for user */
1228{ 0x0, /* segment base address */
1229 0xfffff, /* length - all address space */
1230 SDT_MEMERA, /* segment type */
1231 SEL_UPL, /* segment descriptor priority level */
1232 1, /* segment descriptor present */
1233 1, /* long */
1234 0, /* default 32 vs 16 bit size */
1235 1 /* limit granularity (byte/page units)*/ },
1236/* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1237{
1238 0x0, /* segment base address */
b2b3ffcd 1239 sizeof(struct x86_64tss)-1,/* length - all address space */
c8fe38ae
MD
1240 SDT_SYSTSS, /* segment type */
1241 SEL_KPL, /* segment descriptor priority level */
1242 1, /* segment descriptor present */
1243 0, /* long */
1244 0, /* unused - default 32 vs 16 bit size */
1245 0 /* limit granularity (byte/page units)*/ },
1246/* Actually, the TSS is a system descriptor which is double size */
1247{ 0x0, /* segment base address */
1248 0x0, /* length */
1249 0, /* segment type */
1250 0, /* segment descriptor priority level */
1251 0, /* segment descriptor present */
1252 0, /* long */
1253 0, /* default 32 vs 16 bit size */
1254 0 /* limit granularity (byte/page units)*/ },
1255/* GUGS32_SEL 8 32 bit GS Descriptor for user */
1256{ 0x0, /* segment base address */
1257 0xfffff, /* length - all address space */
1258 SDT_MEMRWA, /* segment type */
1259 SEL_UPL, /* segment descriptor priority level */
1260 1, /* segment descriptor present */
1261 0, /* long */
1262 1, /* default 32 vs 16 bit size */
1263 1 /* limit granularity (byte/page units)*/ },
1264};
1265
1266void
1267setidt(int idx, inthand_t *func, int typ, int dpl, int ist)
1268{
1269 struct gate_descriptor *ip;
1270
1271 ip = idt + idx;
1272 ip->gd_looffset = (uintptr_t)func;
1273 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1274 ip->gd_ist = ist;
1275 ip->gd_xx = 0;
1276 ip->gd_type = typ;
1277 ip->gd_dpl = dpl;
1278 ip->gd_p = 1;
1279 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1280}
1281
1282#define IDTVEC(name) __CONCAT(X,name)
1283
1284extern inthand_t
1285 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1286 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1287 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1288 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1289 IDTVEC(xmm), IDTVEC(dblfault),
1290 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1291
1292#ifdef DEBUG_INTERRUPTS
1293extern inthand_t *Xrsvdary[256];
1294#endif
1295
1296void
1297sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1298{
1299 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1300 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1301 ssd->ssd_type = sd->sd_type;
1302 ssd->ssd_dpl = sd->sd_dpl;
1303 ssd->ssd_p = sd->sd_p;
1304 ssd->ssd_def32 = sd->sd_def32;
1305 ssd->ssd_gran = sd->sd_gran;
1306}
1307
1308void
1309ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1310{
1311
1312 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1313 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1314 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1315 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1316 sd->sd_type = ssd->ssd_type;
1317 sd->sd_dpl = ssd->ssd_dpl;
1318 sd->sd_p = ssd->ssd_p;
1319 sd->sd_long = ssd->ssd_long;
1320 sd->sd_def32 = ssd->ssd_def32;
1321 sd->sd_gran = ssd->ssd_gran;
1322}
1323
1324void
1325ssdtosyssd(struct soft_segment_descriptor *ssd,
1326 struct system_segment_descriptor *sd)
1327{
1328
1329 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1330 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1331 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1332 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1333 sd->sd_type = ssd->ssd_type;
1334 sd->sd_dpl = ssd->ssd_dpl;
1335 sd->sd_p = ssd->ssd_p;
1336 sd->sd_gran = ssd->ssd_gran;
1337}
1338
c8fe38ae
MD
1339/*
1340 * Populate the (physmap) array with base/bound pairs describing the
1341 * available physical memory in the system, then test this memory and
1342 * build the phys_avail array describing the actually-available memory.
1343 *
1344 * If we cannot accurately determine the physical memory map, then use
1345 * value from the 0xE801 call, and failing that, the RTC.
1346 *
1347 * Total memory size may be set by the kernel environment variable
1348 * hw.physmem or the compile-time define MAXMEM.
1349 *
b4d9abe2
MD
1350 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1351 * of PAGE_SIZE. This also greatly reduces the memory test time
1352 * which would otherwise be excessive on machines with > 8G of ram.
1353 *
c8fe38ae
MD
1354 * XXX first should be vm_paddr_t.
1355 */
b4d9abe2
MD
1356
1357#define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1358#define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1359
c8fe38ae
MD
1360static void
1361getmemsize(caddr_t kmdp, u_int64_t first)
1362{
b4d9abe2
MD
1363 int off, physmap_idx, pa_indx, da_indx;
1364 int i, j;
1365 vm_paddr_t physmap[PHYSMAP_SIZE];
1366 vm_paddr_t pa;
1367 vm_paddr_t msgbuf_size;
c8fe38ae
MD
1368 u_long physmem_tunable;
1369 pt_entry_t *pte;
1370 struct bios_smap *smapbase, *smap, *smapend;
1371 u_int32_t smapsize;
1372 quad_t dcons_addr, dcons_size;
1373
1374 bzero(physmap, sizeof(physmap));
c8fe38ae
MD
1375 physmap_idx = 0;
1376
1377 /*
1378 * get memory map from INT 15:E820, kindly supplied by the loader.
1379 *
1380 * subr_module.c says:
1381 * "Consumer may safely assume that size value precedes data."
1382 * ie: an int32_t immediately precedes smap.
1383 */
1384 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1385 MODINFO_METADATA | MODINFOMD_SMAP);
1386 if (smapbase == NULL)
1387 panic("No BIOS smap info from loader!");
1388
1389 smapsize = *((u_int32_t *)smapbase - 1);
1390 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1391
1392 for (smap = smapbase; smap < smapend; smap++) {
1393 if (boothowto & RB_VERBOSE)
1394 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1395 smap->type, smap->base, smap->length);
1396
1397 if (smap->type != SMAP_TYPE_MEMORY)
1398 continue;
1399
1400 if (smap->length == 0)
1401 continue;
1402
1403 for (i = 0; i <= physmap_idx; i += 2) {
1404 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD
1405 if (boothowto & RB_VERBOSE) {
1406 kprintf("Overlapping or non-monotonic "
1407 "memory region, ignoring "
1408 "second region\n");
1409 }
c8fe38ae
MD
1410 continue;
1411 }
1412 }
1bda0d3d 1413 Realmem += smap->length;
c8fe38ae
MD
1414
1415 if (smap->base == physmap[physmap_idx + 1]) {
1416 physmap[physmap_idx + 1] += smap->length;
1417 continue;
1418 }
1419
1420 physmap_idx += 2;
1421 if (physmap_idx == PHYSMAP_SIZE) {
1bda0d3d
MD
1422 kprintf("Too many segments in the physical "
1423 "address map, giving up\n");
c8fe38ae
MD
1424 break;
1425 }
1426 physmap[physmap_idx] = smap->base;
1427 physmap[physmap_idx + 1] = smap->base + smap->length;
1428 }
1429
c8fe38ae
MD
1430#ifdef SMP
1431 /* make hole for AP bootstrap code */
1432 physmap[1] = mp_bootaddress(physmap[1] / 1024);
2331304b 1433
927c4c1f
MN
1434 /* Save EBDA address, if any */
1435 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1436 ebda_addr <<= 4;
c8fe38ae
MD
1437#endif
1438
1439 /*
1440 * Maxmem isn't the "maximum memory", it's one larger than the
1441 * highest page of the physical address space. It should be
1442 * called something like "Maxphyspage". We may adjust this
1443 * based on ``hw.physmem'' and the results of the memory test.
1444 */
1445 Maxmem = atop(physmap[physmap_idx + 1]);
1446
1447#ifdef MAXMEM
1448 Maxmem = MAXMEM / 4;
1449#endif
1450
1451 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1452 Maxmem = atop(physmem_tunable);
1453
1454 /*
1455 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1456 * in the system.
1457 */
1458 if (Maxmem > atop(physmap[physmap_idx + 1]))
1459 Maxmem = atop(physmap[physmap_idx + 1]);
1460
8e5ea5f7 1461 /*
b4d9abe2 1462 * Blowing out the DMAP will blow up the system.
8e5ea5f7
MD
1463 */
1464 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1465 kprintf("Limiting Maxmem due to DMAP size\n");
1466 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1467 }
1468
c8fe38ae 1469 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
b4d9abe2 1470 (boothowto & RB_VERBOSE)) {
c8fe38ae 1471 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
b4d9abe2 1472 }
c8fe38ae 1473
b4d9abe2
MD
1474 /*
1475 * Call pmap initialization to make new kernel address space
1476 *
1477 * Mask off page 0.
1478 */
48ffc236 1479 pmap_bootstrap(&first);
b4d9abe2
MD
1480 physmap[0] = PAGE_SIZE;
1481
1482 /*
1483 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1484 * exceeding Maxmem.
1485 */
1486 for (i = j = 0; i <= physmap_idx; i += 2) {
1487 if (physmap[i+1] > ptoa((vm_paddr_t)Maxmem))
1488 physmap[i+1] = ptoa((vm_paddr_t)Maxmem);
1489 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1490 ~PHYSMAP_ALIGN_MASK;
1491 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1492
1493 physmap[j] = physmap[i];
1494 physmap[j+1] = physmap[i+1];
1495
1496 if (physmap[i] < physmap[i+1])
1497 j += 2;
1498 }
1499 physmap_idx = j - 2;
1500
1501 /*
1502 * Align anything else used in the validation loop.
1503 */
1504 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
c8fe38ae
MD
1505
1506 /*
1507 * Size up each available chunk of physical memory.
1508 */
c8fe38ae
MD
1509 pa_indx = 0;
1510 da_indx = 1;
1511 phys_avail[pa_indx++] = physmap[0];
1512 phys_avail[pa_indx] = physmap[0];
1513 dump_avail[da_indx] = physmap[0];
1514 pte = CMAP1;
1515
1516 /*
1517 * Get dcons buffer address
1518 */
1519 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1520 kgetenv_quad("dcons.size", &dcons_size) == 0)
1521 dcons_addr = 0;
1522
1523 /*
b4d9abe2
MD
1524 * Validate the physical memory. The physical memory segments
1525 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1526 * of PAGE_SIZE.
c8fe38ae
MD
1527 */
1528 for (i = 0; i <= physmap_idx; i += 2) {
1529 vm_paddr_t end;
1530
b4d9abe2
MD
1531 end = physmap[i + 1];
1532
1533 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
c8fe38ae
MD
1534 int tmp, page_bad, full;
1535 int *ptr = (int *)CADDR1;
1536
1537 full = FALSE;
1538 /*
1539 * block out kernel memory as not available.
1540 */
1541 if (pa >= 0x100000 && pa < first)
1542 goto do_dump_avail;
1543
1544 /*
1545 * block out dcons buffer
1546 */
1547 if (dcons_addr > 0
1548 && pa >= trunc_page(dcons_addr)
b4d9abe2 1549 && pa < dcons_addr + dcons_size) {
c8fe38ae 1550 goto do_dump_avail;
b4d9abe2 1551 }
c8fe38ae
MD
1552
1553 page_bad = FALSE;
1554
1555 /*
1556 * map page into kernel: valid, read/write,non-cacheable
1557 */
1558 *pte = pa | PG_V | PG_RW | PG_N;
1559 cpu_invltlb();
1560
1561 tmp = *(int *)ptr;
1562 /*
1563 * Test for alternating 1's and 0's
1564 */
1565 *(volatile int *)ptr = 0xaaaaaaaa;
b4d9abe2 1566 cpu_mfence();
c8fe38ae
MD
1567 if (*(volatile int *)ptr != 0xaaaaaaaa)
1568 page_bad = TRUE;
1569 /*
1570 * Test for alternating 0's and 1's
1571 */
1572 *(volatile int *)ptr = 0x55555555;
b4d9abe2 1573 cpu_mfence();
c8fe38ae
MD
1574 if (*(volatile int *)ptr != 0x55555555)
1575 page_bad = TRUE;
1576 /*
1577 * Test for all 1's
1578 */
1579 *(volatile int *)ptr = 0xffffffff;
b4d9abe2 1580 cpu_mfence();
c8fe38ae
MD
1581 if (*(volatile int *)ptr != 0xffffffff)
1582 page_bad = TRUE;
1583 /*
1584 * Test for all 0's
1585 */
1586 *(volatile int *)ptr = 0x0;
b4d9abe2 1587 cpu_mfence();
c8fe38ae
MD
1588 if (*(volatile int *)ptr != 0x0)
1589 page_bad = TRUE;
1590 /*
1591 * Restore original value.
1592 */
1593 *(int *)ptr = tmp;
1594
1595 /*
1596 * Adjust array of valid/good pages.
1597 */
1598 if (page_bad == TRUE)
1599 continue;
1600 /*
1601 * If this good page is a continuation of the
1602 * previous set of good pages, then just increase
1603 * the end pointer. Otherwise start a new chunk.
1604 * Note that "end" points one higher than end,
1605 * making the range >= start and < end.
1606 * If we're also doing a speculative memory
1607 * test and we at or past the end, bump up Maxmem
1608 * so that we keep going. The first bad page
1609 * will terminate the loop.
1610 */
1611 if (phys_avail[pa_indx] == pa) {
b4d9abe2 1612 phys_avail[pa_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1613 } else {
1614 pa_indx++;
1615 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1616 kprintf(
1617 "Too many holes in the physical address space, giving up\n");
1618 pa_indx--;
1619 full = TRUE;
1620 goto do_dump_avail;
1621 }
b4d9abe2
MD
1622 phys_avail[pa_indx++] = pa;
1623 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae 1624 }
7a3eee88 1625 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
c8fe38ae
MD
1626do_dump_avail:
1627 if (dump_avail[da_indx] == pa) {
b4d9abe2 1628 dump_avail[da_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1629 } else {
1630 da_indx++;
1631 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1632 da_indx--;
1633 goto do_next;
1634 }
b4d9abe2
MD
1635 dump_avail[da_indx++] = pa;
1636 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae
MD
1637 }
1638do_next:
1639 if (full)
1640 break;
1641 }
1642 }
1643 *pte = 0;
1644 cpu_invltlb();
1645
1646 /*
c8fe38ae
MD
1647 * The last chunk must contain at least one page plus the message
1648 * buffer to avoid complicating other code (message buffer address
1649 * calculation, etc.).
1650 */
b4d9abe2
MD
1651 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1652
1653 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1654 msgbuf_size >= phys_avail[pa_indx]) {
c8fe38ae
MD
1655 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1656 phys_avail[pa_indx--] = 0;
1657 phys_avail[pa_indx--] = 0;
1658 }
1659
1660 Maxmem = atop(phys_avail[pa_indx]);
1661
1662 /* Trim off space for the message buffer. */
b4d9abe2 1663 phys_avail[pa_indx] -= msgbuf_size;
c8fe38ae 1664
1185babf
JG
1665 avail_end = phys_avail[pa_indx];
1666
c8fe38ae 1667 /* Map the message buffer. */
b4d9abe2
MD
1668 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1669 pmap_kenter((vm_offset_t)msgbufp + off,
1670 phys_avail[pa_indx] + off);
1671 }
c8fe38ae
MD
1672}
1673
faaf4131 1674#ifdef SMP
eac0bf8f
MD
1675#ifdef APIC_IO
1676int apic_io_enable = 1; /* Enabled by default for kernels compiled w/APIC_IO */
1677#else
1678int apic_io_enable = 0; /* Disabled by default for kernels compiled without */
1679#endif
faaf4131
MN
1680#endif
1681
faaf4131
MN
1682struct machintr_abi MachIntrABI;
1683
c8fe38ae
MD
1684/*
1685 * IDT VECTORS:
1686 * 0 Divide by zero
1687 * 1 Debug
1688 * 2 NMI
1689 * 3 BreakPoint
1690 * 4 OverFlow
1691 * 5 Bound-Range
1692 * 6 Invalid OpCode
1693 * 7 Device Not Available (x87)
1694 * 8 Double-Fault
1695 * 9 Coprocessor Segment overrun (unsupported, reserved)
1696 * 10 Invalid-TSS
1697 * 11 Segment not present
1698 * 12 Stack
1699 * 13 General Protection
1700 * 14 Page Fault
1701 * 15 Reserved
1702 * 16 x87 FP Exception pending
1703 * 17 Alignment Check
1704 * 18 Machine Check
1705 * 19 SIMD floating point
1706 * 20-31 reserved
1707 * 32-255 INTn/external sources
1708 */
1709u_int64_t
1710hammer_time(u_int64_t modulep, u_int64_t physfree)
1711{
1712 caddr_t kmdp;
5b9f6cc4
MD
1713 int gsel_tss, x;
1714#if JG
1715 int metadata_missing, off;
1716#endif
c8fe38ae
MD
1717 struct mdglobaldata *gd;
1718 u_int64_t msr;
c8fe38ae 1719
c8fe38ae
MD
1720 /*
1721 * Prevent lowering of the ipl if we call tsleep() early.
1722 */
1723 gd = &CPU_prvspace[0].mdglobaldata;
1724 bzero(gd, sizeof(*gd));
1725
1726 /*
1727 * Note: on both UP and SMP curthread must be set non-NULL
1728 * early in the boot sequence because the system assumes
1729 * that 'curthread' is never NULL.
1730 */
1731
1732 gd->mi.gd_curthread = &thread0;
1733 thread0.td_gd = &gd->mi;
1734
1735 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1736
1737#if JG
1738 metadata_missing = 0;
1739 if (bootinfo.bi_modulep) {
1740 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1741 preload_bootstrap_relocate(KERNBASE);
1742 } else {
1743 metadata_missing = 1;
1744 }
1745 if (bootinfo.bi_envp)
1746 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1747#endif
1748
1749 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1750 preload_bootstrap_relocate(PTOV_OFFSET);
1751 kmdp = preload_search_by_type("elf kernel");
1752 if (kmdp == NULL)
1753 kmdp = preload_search_by_type("elf64 kernel");
1754 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1755 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1756#ifdef DDB
1757 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1758 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1759#endif
1760
27af435a
SZ
1761 if (boothowto & RB_VERBOSE)
1762 bootverbose++;
1763
faaf4131 1764 /*
10db3cc6 1765 * Default MachIntrABI to ICU
faaf4131
MN
1766 */
1767 MachIntrABI = MachIntrABI_ICU;
1768#ifdef SMP
1769 TUNABLE_INT_FETCH("hw.apic_io_enable", &apic_io_enable);
faaf4131
MN
1770#endif
1771
c8fe38ae
MD
1772 /*
1773 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1774 * and ncpus_fit_mask remain 0.
1775 */
1776 ncpus = 1;
1777 ncpus2 = 1;
1778 ncpus_fit = 1;
1779 /* Init basic tunables, hz etc */
1780 init_param1();
1781
1782 /*
1783 * make gdt memory segments
1784 */
1785 gdt_segs[GPROC0_SEL].ssd_base =
1786 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1787
1788 gd->mi.gd_prvspace = &CPU_prvspace[0];
1789
1790 for (x = 0; x < NGDT; x++) {
1791 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1792 ssdtosd(&gdt_segs[x], &gdt[x]);
1793 }
1794 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1795 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
48ffc236 1796
c8fe38ae
MD
1797 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1798 r_gdt.rd_base = (long) gdt;
1799 lgdt(&r_gdt);
1800
1801 wrmsr(MSR_FSBASE, 0); /* User value */
1802 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1803 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1804
1805 mi_gdinit(&gd->mi, 0);
1806 cpu_gdinit(gd, 0);
1807 proc0paddr = proc0paddr_buff;
1808 mi_proc0init(&gd->mi, proc0paddr);
1809 safepri = TDPRI_MAX;
1810
1811 /* spinlocks and the BGL */
1812 init_locks();
1813
1814 /* exceptions */
1815 for (x = 0; x < NIDT; x++)
1816 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1817 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1818 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1819 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
1820 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1821 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1822 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1823 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1824 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1825 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1826 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1827 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1828 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
1829 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
1830 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
1831 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
1832 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
1833 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
1834 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
1835 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
1836
1837 r_idt.rd_limit = sizeof(idt0) - 1;
1838 r_idt.rd_base = (long) idt;
1839 lidt(&r_idt);
1840
1841 /*
1842 * Initialize the console before we print anything out.
1843 */
1844 cninit();
1845
1846#if JG
1847 if (metadata_missing)
1848 kprintf("WARNING: loader(8) metadata is missing!\n");
1849#endif
1850
1851#if NISA >0
e24dd6e0 1852 elcr_probe();
c8fe38ae
MD
1853 isa_defaultirq();
1854#endif
1855 rand_initialize();
1856
a3dd9120
SZ
1857 /*
1858 * Initialize IRQ mapping
1859 *
1860 * NOTE:
1861 * SHOULD be after elcr_probe()
1862 */
1863 MachIntrABI_ICU.initmap();
1864#ifdef SMP
1865 MachIntrABI_IOAPIC.initmap();
1866#endif
1867
c8fe38ae
MD
1868#ifdef DDB
1869 kdb_init();
1870 if (boothowto & RB_KDB)
1871 Debugger("Boot flags requested debugger");
1872#endif
1873
1874#if JG
1875 finishidentcpu(); /* Final stage of CPU initialization */
2883d2d8
MD
1876 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1877 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
c8fe38ae
MD
1878#endif
1879 identify_cpu(); /* Final stage of CPU initialization */
1880 initializecpu(); /* Initialize CPU registers */
1881
1882 /* make an initial tss so cpu can get interrupt stack on syscall! */
5b9f6cc4
MD
1883 gd->gd_common_tss.tss_rsp0 =
1884 (register_t)(thread0.td_kstack +
1885 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
c8fe38ae 1886 /* Ensure the stack is aligned to 16 bytes */
2883d2d8 1887 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
c8fe38ae 1888
093565f2
MD
1889 /* double fault stack */
1890 gd->gd_common_tss.tss_ist1 =
1891 (long)&gd->mi.gd_prvspace->idlestack[
1892 sizeof(gd->mi.gd_prvspace->idlestack)];
c8fe38ae
MD
1893
1894 /* Set the IO permission bitmap (empty due to tss seg limit) */
b2b3ffcd 1895 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
c8fe38ae
MD
1896
1897 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1898 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
1899 gd->gd_common_tssd = *gd->gd_tss_gdt;
1900 ltr(gsel_tss);
1901
1902 /* Set up the fast syscall stuff */
1903 msr = rdmsr(MSR_EFER) | EFER_SCE;
1904 wrmsr(MSR_EFER, msr);
1905 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
1906 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
1907 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
1908 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
1909 wrmsr(MSR_STAR, msr);
1910 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
1911
1912 getmemsize(kmdp, physfree);
1913 init_param2(physmem);
1914
1915 /* now running on new page tables, configured,and u/iom is accessible */
1916
1917 /* Map the message buffer. */
1918#if JG
1919 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
1920 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
1921#endif
1922
1923 msgbufinit(msgbufp, MSGBUF_SIZE);
1924
1925
1926 /* transfer to user mode */
1927
1928 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1929 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1930 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
1931
1932 load_ds(_udatasel);
1933 load_es(_udatasel);
1934 load_fs(_udatasel);
1935
1936 /* setup proc 0's pcb */
1937 thread0.td_pcb->pcb_flags = 0;
c8fe38ae 1938 thread0.td_pcb->pcb_cr3 = KPML4phys;
c8fe38ae 1939 thread0.td_pcb->pcb_ext = 0;
d1368d1a 1940 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
c8fe38ae
MD
1941
1942 /* Location of kernel stack for locore */
1943 return ((u_int64_t)thread0.td_pcb);
1944}
1945
1946/*
1947 * Initialize machine-dependant portions of the global data structure.
1948 * Note that the global data area and cpu0's idlestack in the private
1949 * data space were allocated in locore.
1950 *
1951 * Note: the idlethread's cpl is 0
1952 *
1953 * WARNING! Called from early boot, 'mycpu' may not work yet.
1954 */
1955void
1956cpu_gdinit(struct mdglobaldata *gd, int cpu)
1957{
1958 if (cpu)
1959 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
1960
1961 lwkt_init_thread(&gd->mi.gd_idlethread,
1962 gd->mi.gd_prvspace->idlestack,
1963 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 1964 0, &gd->mi);
c8fe38ae
MD
1965 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
1966 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
1967 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
1968 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
1969}
1970
1971int
1972is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
1973{
1974 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
1975 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
1976 return (TRUE);
1977 }
1978 return (FALSE);
1979}
1980
1981struct globaldata *
1982globaldata_find(int cpu)
1983{
1984 KKASSERT(cpu >= 0 && cpu < ncpus);
1985 return(&CPU_prvspace[cpu].mdglobaldata.mi);
1986}
1987
c8fe38ae
MD
1988int
1989ptrace_set_pc(struct lwp *lp, unsigned long addr)
1990{
5b9f6cc4 1991 lp->lwp_md.md_regs->tf_rip = addr;
c8fe38ae
MD
1992 return (0);
1993}
1994
1995int
1996ptrace_single_step(struct lwp *lp)
1997{
5b9f6cc4 1998 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
c8fe38ae
MD
1999 return (0);
2000}
2001
2002int
2003fill_regs(struct lwp *lp, struct reg *regs)
2004{
c8fe38ae
MD
2005 struct trapframe *tp;
2006
2007 tp = lp->lwp_md.md_regs;
5b9f6cc4 2008 bcopy(&tp->tf_rdi, &regs->r_rdi, sizeof(*regs));
c8fe38ae
MD
2009 return (0);
2010}
2011
2012int
2013set_regs(struct lwp *lp, struct reg *regs)
2014{
c8fe38ae
MD
2015 struct trapframe *tp;
2016
2017 tp = lp->lwp_md.md_regs;
5b9f6cc4 2018 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
c8fe38ae
MD
2019 !CS_SECURE(regs->r_cs))
2020 return (EINVAL);
5b9f6cc4 2021 bcopy(&regs->r_rdi, &tp->tf_rdi, sizeof(*regs));
c8fe38ae
MD
2022 return (0);
2023}
2024
2025#ifndef CPU_DISABLE_SSE
2026static void
2027fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2028{
2029 struct env87 *penv_87 = &sv_87->sv_env;
2030 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2031 int i;
2032
2033 /* FPU control/status */
2034 penv_87->en_cw = penv_xmm->en_cw;
2035 penv_87->en_sw = penv_xmm->en_sw;
2036 penv_87->en_tw = penv_xmm->en_tw;
2037 penv_87->en_fip = penv_xmm->en_fip;
2038 penv_87->en_fcs = penv_xmm->en_fcs;
2039 penv_87->en_opcode = penv_xmm->en_opcode;
2040 penv_87->en_foo = penv_xmm->en_foo;
2041 penv_87->en_fos = penv_xmm->en_fos;
2042
2043 /* FPU registers */
2044 for (i = 0; i < 8; ++i)
2045 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
c8fe38ae
MD
2046}
2047
2048static void
2049set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2050{
2051 struct env87 *penv_87 = &sv_87->sv_env;
2052 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2053 int i;
2054
2055 /* FPU control/status */
2056 penv_xmm->en_cw = penv_87->en_cw;
2057 penv_xmm->en_sw = penv_87->en_sw;
2058 penv_xmm->en_tw = penv_87->en_tw;
2059 penv_xmm->en_fip = penv_87->en_fip;
2060 penv_xmm->en_fcs = penv_87->en_fcs;
2061 penv_xmm->en_opcode = penv_87->en_opcode;
2062 penv_xmm->en_foo = penv_87->en_foo;
2063 penv_xmm->en_fos = penv_87->en_fos;
2064
2065 /* FPU registers */
2066 for (i = 0; i < 8; ++i)
2067 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
c8fe38ae
MD
2068}
2069#endif /* CPU_DISABLE_SSE */
2070
2071int
2072fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2073{
2074#ifndef CPU_DISABLE_SSE
2075 if (cpu_fxsr) {
2076 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2077 (struct save87 *)fpregs);
2078 return (0);
2079 }
2080#endif /* CPU_DISABLE_SSE */
2081 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2082 return (0);
2083}
2084
2085int
2086set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2087{
2088#ifndef CPU_DISABLE_SSE
2089 if (cpu_fxsr) {
2090 set_fpregs_xmm((struct save87 *)fpregs,
2091 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2092 return (0);
2093 }
2094#endif /* CPU_DISABLE_SSE */
2095 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2096 return (0);
2097}
2098
2099int
2100fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2101{
2102 if (lp == NULL) {
0855a2af
JG
2103 dbregs->dr[0] = rdr0();
2104 dbregs->dr[1] = rdr1();
2105 dbregs->dr[2] = rdr2();
2106 dbregs->dr[3] = rdr3();
2107 dbregs->dr[4] = rdr4();
2108 dbregs->dr[5] = rdr5();
2109 dbregs->dr[6] = rdr6();
2110 dbregs->dr[7] = rdr7();
c8fe38ae
MD
2111 } else {
2112 struct pcb *pcb;
2113
2114 pcb = lp->lwp_thread->td_pcb;
0855a2af
JG
2115 dbregs->dr[0] = pcb->pcb_dr0;
2116 dbregs->dr[1] = pcb->pcb_dr1;
2117 dbregs->dr[2] = pcb->pcb_dr2;
2118 dbregs->dr[3] = pcb->pcb_dr3;
2119 dbregs->dr[4] = 0;
2120 dbregs->dr[5] = 0;
2121 dbregs->dr[6] = pcb->pcb_dr6;
2122 dbregs->dr[7] = pcb->pcb_dr7;
c8fe38ae
MD
2123 }
2124 return (0);
2125}
2126
2127int
2128set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2129{
2130 if (lp == NULL) {
0855a2af
JG
2131 load_dr0(dbregs->dr[0]);
2132 load_dr1(dbregs->dr[1]);
2133 load_dr2(dbregs->dr[2]);
2134 load_dr3(dbregs->dr[3]);
2135 load_dr4(dbregs->dr[4]);
2136 load_dr5(dbregs->dr[5]);
2137 load_dr6(dbregs->dr[6]);
2138 load_dr7(dbregs->dr[7]);
c8fe38ae
MD
2139 } else {
2140 struct pcb *pcb;
2141 struct ucred *ucred;
2142 int i;
0855a2af 2143 uint64_t mask1, mask2;
c8fe38ae
MD
2144
2145 /*
2146 * Don't let an illegal value for dr7 get set. Specifically,
2147 * check for undefined settings. Setting these bit patterns
2148 * result in undefined behaviour and can lead to an unexpected
2149 * TRCTRAP.
2150 */
0855a2af
JG
2151 /* JG this loop looks unreadable */
2152 /* Check 4 2-bit fields for invalid patterns.
2153 * These fields are R/Wi, for i = 0..3
2154 */
2155 /* Is 10 in LENi allowed when running in compatibility mode? */
2156 /* Pattern 10 in R/Wi might be used to indicate
2157 * breakpoint on I/O. Further analysis should be
2158 * carried to decide if it is safe and useful to
2159 * provide access to that capability
2160 */
2161 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2162 i++, mask1 <<= 4, mask2 <<= 4)
2163 if ((dbregs->dr[7] & mask1) == mask2)
c8fe38ae 2164 return (EINVAL);
c8fe38ae
MD
2165
2166 pcb = lp->lwp_thread->td_pcb;
2167 ucred = lp->lwp_proc->p_ucred;
2168
2169 /*
2170 * Don't let a process set a breakpoint that is not within the
2171 * process's address space. If a process could do this, it
2172 * could halt the system by setting a breakpoint in the kernel
2173 * (if ddb was enabled). Thus, we need to check to make sure
2174 * that no breakpoints are being enabled for addresses outside
2175 * process's address space, unless, perhaps, we were called by
2176 * uid 0.
2177 *
2178 * XXX - what about when the watched area of the user's
2179 * address space is written into from within the kernel
2180 * ... wouldn't that still cause a breakpoint to be generated
2181 * from within kernel mode?
2182 */
2183
895c1f85 2184 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
0855a2af 2185 if (dbregs->dr[7] & 0x3) {
c8fe38ae 2186 /* dr0 is enabled */
0855a2af 2187 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2188 return (EINVAL);
2189 }
2190
0855a2af 2191 if (dbregs->dr[7] & (0x3<<2)) {
c8fe38ae 2192 /* dr1 is enabled */
0855a2af 2193 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2194 return (EINVAL);
2195 }
2196
0855a2af 2197 if (dbregs->dr[7] & (0x3<<4)) {
c8fe38ae 2198 /* dr2 is enabled */
0855a2af 2199 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2200 return (EINVAL);
2201 }
2202
0855a2af 2203 if (dbregs->dr[7] & (0x3<<6)) {
c8fe38ae 2204 /* dr3 is enabled */
0855a2af 2205 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2206 return (EINVAL);
2207 }
c8fe38ae
MD
2208 }
2209
0855a2af
JG
2210 pcb->pcb_dr0 = dbregs->dr[0];
2211 pcb->pcb_dr1 = dbregs->dr[1];
2212 pcb->pcb_dr2 = dbregs->dr[2];
2213 pcb->pcb_dr3 = dbregs->dr[3];
2214 pcb->pcb_dr6 = dbregs->dr[6];
2215 pcb->pcb_dr7 = dbregs->dr[7];
c8fe38ae
MD
2216
2217 pcb->pcb_flags |= PCB_DBREGS;
2218 }
2219
2220 return (0);
2221}
2222
2223/*
2224 * Return > 0 if a hardware breakpoint has been hit, and the
2225 * breakpoint was in user space. Return 0, otherwise.
2226 */
2227int
2228user_dbreg_trap(void)
2229{
0855a2af
JG
2230 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2231 u_int64_t bp; /* breakpoint bits extracted from dr6 */
c8fe38ae
MD
2232 int nbp; /* number of breakpoints that triggered */
2233 caddr_t addr[4]; /* breakpoint addresses */
2234 int i;
2235
2236 dr7 = rdr7();
0855a2af 2237 if ((dr7 & 0xff) == 0) {
c8fe38ae
MD
2238 /*
2239 * all GE and LE bits in the dr7 register are zero,
2240 * thus the trap couldn't have been caused by the
2241 * hardware debug registers
2242 */
2243 return 0;
2244 }
2245
2246 nbp = 0;
2247 dr6 = rdr6();
0855a2af 2248 bp = dr6 & 0xf;
c8fe38ae 2249
0855a2af 2250 if (bp == 0) {
c8fe38ae
MD
2251 /*
2252 * None of the breakpoint bits are set meaning this
2253 * trap was not caused by any of the debug registers
2254 */
2255 return 0;
2256 }
2257
2258 /*
2259 * at least one of the breakpoints were hit, check to see
2260 * which ones and if any of them are user space addresses
2261 */
2262
2263 if (bp & 0x01) {
2264 addr[nbp++] = (caddr_t)rdr0();
2265 }
2266 if (bp & 0x02) {
2267 addr[nbp++] = (caddr_t)rdr1();
2268 }
2269 if (bp & 0x04) {
2270 addr[nbp++] = (caddr_t)rdr2();
2271 }
2272 if (bp & 0x08) {
2273 addr[nbp++] = (caddr_t)rdr3();
2274 }
2275
2276 for (i=0; i<nbp; i++) {
2277 if (addr[i] <
2278 (caddr_t)VM_MAX_USER_ADDRESS) {
2279 /*
2280 * addr[i] is in user space
2281 */
2282 return nbp;
2283 }
2284 }
2285
2286 /*
2287 * None of the breakpoints are in user space.
2288 */
2289 return 0;
2290}
2291
2292
2293#ifndef DDB
2294void
2295Debugger(const char *msg)
2296{
2297 kprintf("Debugger(\"%s\") called.\n", msg);
2298}
2299#endif /* no DDB */
2300
2301#ifdef DDB
2302
2303/*
2304 * Provide inb() and outb() as functions. They are normally only
2305 * available as macros calling inlined functions, thus cannot be
2306 * called inside DDB.
2307 *
2308 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2309 */
2310
2311#undef inb
2312#undef outb
2313
2314/* silence compiler warnings */
2315u_char inb(u_int);
2316void outb(u_int, u_char);
2317
2318u_char
2319inb(u_int port)
2320{
2321 u_char data;
2322 /*
2323 * We use %%dx and not %1 here because i/o is done at %dx and not at
2324 * %edx, while gcc generates inferior code (movw instead of movl)
2325 * if we tell it to load (u_short) port.
2326 */
2327 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2328 return (data);
2329}
2330
2331void
2332outb(u_int port, u_char data)
2333{
2334 u_char al;
2335 /*
2336 * Use an unnecessary assignment to help gcc's register allocator.
2337 * This make a large difference for gcc-1.40 and a tiny difference
2338 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2339 * best results. gcc-2.6.0 can't handle this.
2340 */
2341 al = data;
2342 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2343}
2344
2345#endif /* DDB */
2346
2347
2348
2349#include "opt_cpu.h"
2350
2351
2352/*
2353 * initialize all the SMP locks
2354 */
2355
2356/* critical region when masking or unmasking interupts */
2357struct spinlock_deprecated imen_spinlock;
2358
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2359/* critical region for old style disable_intr/enable_intr */
2360struct spinlock_deprecated mpintr_spinlock;
2361
2362/* critical region around INTR() routines */
2363struct spinlock_deprecated intr_spinlock;
2364
2365/* lock region used by kernel profiling */
2366struct spinlock_deprecated mcount_spinlock;
2367
2368/* locks com (tty) data/hardware accesses: a FASTINTR() */
2369struct spinlock_deprecated com_spinlock;
2370
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MD
2371/* lock regions around the clock hardware */
2372struct spinlock_deprecated clock_spinlock;
2373
c8fe38ae
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2374static void
2375init_locks(void)
2376{
b5d16701 2377#ifdef SMP
c8fe38ae 2378 /*
b5d16701 2379 * Get the initial mplock with a count of 1 for the BSP.
c8fe38ae
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2380 * This uses a LOGICAL cpu ID, ie BSP == 0.
2381 */
c8fe38ae
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2382 cpu_get_initial_mplock();
2383#endif
2384 /* DEPRECATED */
2385 spin_lock_init(&mcount_spinlock);
c8fe38ae
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2386 spin_lock_init(&intr_spinlock);
2387 spin_lock_init(&mpintr_spinlock);
2388 spin_lock_init(&imen_spinlock);
c8fe38ae
MD
2389 spin_lock_init(&com_spinlock);
2390 spin_lock_init(&clock_spinlock);
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2391
2392 /* our token pool needs to work early */
2393 lwkt_token_pool_init();
2394}
2395