drm/i915: Sync i915_gem_evict.c with Linux 3.8.13
[dragonfly.git] / sys / dev / drm / i915 / i915_drv.c
CommitLineData
7f3c3d6f
HT
1/* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
3 */
4/*-
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
e3adcf8f 30 * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.c,v 1.1 2012/05/22 11:07:44 kib Exp $
7f3c3d6f
HT
31 */
32
18e26a6d 33#include <drm/drmP.h>
5c6c6f23 34#include <drm/i915_drm.h>
c4a9e910 35#include "i915_drv.h"
18e26a6d 36#include <drm/drm_pciids.h>
e3adcf8f 37#include "intel_drv.h"
7f3c3d6f 38
19df918d
FT
39/* "Specify LVDS channel mode "
40 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)" */
41int i915_lvds_channel_mode __read_mostly = 0;
42TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
43
7f3c3d6f
HT
44/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
45static drm_pci_id_list_t i915_pciidlist[] = {
46 i915_PCI_IDS
47};
48
e9243325
FT
49#define INTEL_VGA_DEVICE(id, info_) { \
50 .device = id, \
51 .info = info_, \
52}
53
e3adcf8f
FT
54static const struct intel_device_info intel_i830_info = {
55 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
56 .has_overlay = 1, .overlay_needs_physical = 1,
57};
58
59static const struct intel_device_info intel_845g_info = {
60 .gen = 2,
61 .has_overlay = 1, .overlay_needs_physical = 1,
62};
63
64static const struct intel_device_info intel_i85x_info = {
65 .gen = 2, .is_i85x = 1, .is_mobile = 1,
66 .cursor_needs_physical = 1,
67 .has_overlay = 1, .overlay_needs_physical = 1,
68};
69
70static const struct intel_device_info intel_i865g_info = {
71 .gen = 2,
72 .has_overlay = 1, .overlay_needs_physical = 1,
73};
74
75static const struct intel_device_info intel_i915g_info = {
76 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
77 .has_overlay = 1, .overlay_needs_physical = 1,
78};
79static const struct intel_device_info intel_i915gm_info = {
80 .gen = 3, .is_mobile = 1,
81 .cursor_needs_physical = 1,
82 .has_overlay = 1, .overlay_needs_physical = 1,
83 .supports_tv = 1,
84};
85static const struct intel_device_info intel_i945g_info = {
86 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
87 .has_overlay = 1, .overlay_needs_physical = 1,
88};
89static const struct intel_device_info intel_i945gm_info = {
90 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
91 .has_hotplug = 1, .cursor_needs_physical = 1,
92 .has_overlay = 1, .overlay_needs_physical = 1,
93 .supports_tv = 1,
94};
95
96static const struct intel_device_info intel_i965g_info = {
97 .gen = 4, .is_broadwater = 1,
98 .has_hotplug = 1,
99 .has_overlay = 1,
100};
101
102static const struct intel_device_info intel_i965gm_info = {
103 .gen = 4, .is_crestline = 1,
104 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
105 .has_overlay = 1,
106 .supports_tv = 1,
107};
108
109static const struct intel_device_info intel_g33_info = {
110 .gen = 3, .is_g33 = 1,
111 .need_gfx_hws = 1, .has_hotplug = 1,
112 .has_overlay = 1,
113};
114
115static const struct intel_device_info intel_g45_info = {
116 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
117 .has_pipe_cxsr = 1, .has_hotplug = 1,
118 .has_bsd_ring = 1,
119};
120
121static const struct intel_device_info intel_gm45_info = {
122 .gen = 4, .is_g4x = 1,
123 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
124 .has_pipe_cxsr = 1, .has_hotplug = 1,
125 .supports_tv = 1,
126 .has_bsd_ring = 1,
127};
128
129static const struct intel_device_info intel_pineview_info = {
130 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
131 .need_gfx_hws = 1, .has_hotplug = 1,
132 .has_overlay = 1,
133};
134
135static const struct intel_device_info intel_ironlake_d_info = {
136 .gen = 5,
137 .need_gfx_hws = 1, .has_hotplug = 1,
138 .has_bsd_ring = 1,
139};
140
141static const struct intel_device_info intel_ironlake_m_info = {
142 .gen = 5, .is_mobile = 1,
143 .need_gfx_hws = 1, .has_hotplug = 1,
144 .has_fbc = 0, /* disabled due to buggy hardware */
145 .has_bsd_ring = 1,
146};
147
148static const struct intel_device_info intel_sandybridge_d_info = {
149 .gen = 6,
150 .need_gfx_hws = 1, .has_hotplug = 1,
151 .has_bsd_ring = 1,
152 .has_blt_ring = 1,
153 .has_llc = 1,
e9243325 154 .has_force_wake = 1,
e3adcf8f
FT
155};
156
157static const struct intel_device_info intel_sandybridge_m_info = {
158 .gen = 6, .is_mobile = 1,
159 .need_gfx_hws = 1, .has_hotplug = 1,
160 .has_fbc = 1,
161 .has_bsd_ring = 1,
162 .has_blt_ring = 1,
163 .has_llc = 1,
e9243325 164 .has_force_wake = 1,
e3adcf8f
FT
165};
166
167static const struct intel_device_info intel_ivybridge_d_info = {
168 .is_ivybridge = 1, .gen = 7,
169 .need_gfx_hws = 1, .has_hotplug = 1,
170 .has_bsd_ring = 1,
171 .has_blt_ring = 1,
172 .has_llc = 1,
e9243325 173 .has_force_wake = 1,
e3adcf8f
FT
174};
175
176static const struct intel_device_info intel_ivybridge_m_info = {
177 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
178 .need_gfx_hws = 1, .has_hotplug = 1,
179 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
180 .has_bsd_ring = 1,
181 .has_blt_ring = 1,
182 .has_llc = 1,
e9243325 183 .has_force_wake = 1,
e3adcf8f
FT
184};
185
e9243325
FT
186static const struct intel_device_info intel_valleyview_m_info = {
187 .gen = 7, .is_mobile = 1,
188 .need_gfx_hws = 1, .has_hotplug = 1,
189 .has_fbc = 0,
190 .has_bsd_ring = 1,
191 .has_blt_ring = 1,
192 .is_valleyview = 1,
193};
194
195static const struct intel_device_info intel_valleyview_d_info = {
196 .gen = 7,
197 .need_gfx_hws = 1, .has_hotplug = 1,
198 .has_fbc = 0,
199 .has_bsd_ring = 1,
200 .has_blt_ring = 1,
201 .is_valleyview = 1,
202};
203
204static const struct intel_device_info intel_haswell_d_info = {
205 .is_haswell = 1, .gen = 7,
206 .need_gfx_hws = 1, .has_hotplug = 1,
207 .has_bsd_ring = 1,
208 .has_blt_ring = 1,
209 .has_llc = 1,
210 .has_force_wake = 1,
211};
212
213static const struct intel_device_info intel_haswell_m_info = {
214 .is_haswell = 1, .gen = 7, .is_mobile = 1,
215 .need_gfx_hws = 1, .has_hotplug = 1,
216 .has_bsd_ring = 1,
217 .has_blt_ring = 1,
218 .has_llc = 1,
219 .has_force_wake = 1,
220};
e3adcf8f
FT
221
222static const struct intel_gfx_device_id {
223 int device;
224 const struct intel_device_info *info;
225} pciidlist[] = { /* aka */
e9243325
FT
226 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
227 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
228 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
e3adcf8f 229 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
e9243325
FT
230 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
231 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
232 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
233 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
234 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
235 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
236 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
237 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
238 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
239 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
240 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
241 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
242 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
243 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
244 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
245 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
246 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
247 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
248 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
249 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
250 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
251 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
252 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
e3adcf8f
FT
253 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
254 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
255 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
256 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
257 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
258 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
259 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
260 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
261 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
262 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
263 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
264 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
265 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
266 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
267 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
268 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
269 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
e9243325
FT
270 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
271 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
272 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
273 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
274 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
275 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
276 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
277 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
278 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
279 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
280 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
281 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
282 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
283 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
284 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
285 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
286 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
287 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
288 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
289 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
290 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
291 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
292 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
293 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
294 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
295 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
296 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
297 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
298 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
299 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
300 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
301 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
302 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
303 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
304 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
305 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
306 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
307 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
308 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
e3adcf8f
FT
309 {0, 0}
310};
311
e9243325
FT
312#define PCI_VENDOR_INTEL 0x8086
313
314void intel_detect_pch(struct drm_device *dev)
315{
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 device_t pch;
318
319 /*
320 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
321 * make graphics device passthrough work easy for VMM, that only
322 * need to expose ISA bridge to let driver know the real hardware
323 * underneath. This is a requirement from virtualization team.
324 */
325 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
326 if (pch) {
327 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
328 unsigned short id;
329 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
330 dev_priv->pch_id = id;
331
332 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
333 dev_priv->pch_type = PCH_IBX;
334 dev_priv->num_pch_pll = 2;
335 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
336 WARN_ON(!IS_GEN5(dev));
337 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
338 dev_priv->pch_type = PCH_CPT;
339 dev_priv->num_pch_pll = 2;
340 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
341 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
342 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
343 /* PantherPoint is CPT compatible */
344 dev_priv->pch_type = PCH_CPT;
345 dev_priv->num_pch_pll = 2;
346 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
347 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
348 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
349 dev_priv->pch_type = PCH_LPT;
350 dev_priv->num_pch_pll = 0;
351 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
352 WARN_ON(!IS_HASWELL(dev));
353 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
354 dev_priv->pch_type = PCH_LPT;
355 dev_priv->num_pch_pll = 0;
356 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
357 WARN_ON(!IS_HASWELL(dev));
358 }
359 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
360 }
361#if 0
362 pci_dev_put(pch);
363#endif
364 }
365}
366
3d4007e0
FT
367bool i915_semaphore_is_enabled(struct drm_device *dev)
368{
369 if (INTEL_INFO(dev)->gen < 6)
370 return 0;
371
372 if (i915_semaphores >= 0)
373 return i915_semaphores;
374
375#ifdef CONFIG_INTEL_IOMMU
376 /* Enable semaphores on SNB when IO remapping is off */
377 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
378 return false;
379#endif
380
381 return 1;
382}
383
e3adcf8f 384static int i915_drm_freeze(struct drm_device *dev)
7f3c3d6f 385{
e9243325 386 struct drm_i915_private *dev_priv = dev->dev_private;
b3705d71 387
e3adcf8f
FT
388 drm_kms_helper_poll_disable(dev);
389
390#if 0
391 pci_save_state(dev->pdev);
392#endif
b3705d71 393
e3adcf8f
FT
394 /* If KMS is active, we do the leavevt stuff here */
395 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
e9243325 396 int error = i915_gem_idle(dev);
e3adcf8f 397 if (error) {
6df74fa7 398 device_printf(dev->dev,
e9243325
FT
399 "GEM idle failed, resume might fail");
400 return error;
e3adcf8f 401 }
e9243325
FT
402 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
403
404#if 0
405 intel_modeset_disable(dev);
406#endif
407
e3adcf8f
FT
408 drm_irq_uninstall(dev);
409 }
410
b3705d71 411 i915_save_state(dev);
e3adcf8f
FT
412
413 intel_opregion_fini(dev);
414
415 /* Modeset on resume, not lid events */
416 dev_priv->modeset_on_lid = 0;
b3705d71 417
e3adcf8f 418 return 0;
b3705d71
HT
419}
420
e3adcf8f
FT
421static int
422i915_suspend(device_t kdev)
b3705d71 423{
e3adcf8f
FT
424 struct drm_device *dev;
425 int error;
426
427 dev = device_get_softc(kdev);
428 if (dev == NULL || dev->dev_private == NULL) {
429 DRM_ERROR("DRM not initialized, aborting suspend.\n");
430 return -ENODEV;
431 }
432
433 DRM_DEBUG_KMS("starting suspend\n");
434 error = i915_drm_freeze(dev);
435 if (error)
436 return (error);
437
438 error = bus_generic_suspend(kdev);
439 DRM_DEBUG_KMS("finished suspend %d\n", error);
440 return (error);
441}
442
443static int i915_drm_thaw(struct drm_device *dev)
444{
445 struct drm_i915_private *dev_priv = dev->dev_private;
446 int error = 0;
b3705d71 447
19df918d
FT
448 intel_gt_reset(dev);
449
e3adcf8f 450 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
19df918d 451 DRM_LOCK(dev);
e3adcf8f 452 i915_gem_restore_gtt_mappings(dev);
19df918d 453 DRM_UNLOCK(dev);
e3adcf8f
FT
454 }
455
b3705d71 456 i915_restore_state(dev);
e3adcf8f
FT
457 intel_opregion_setup(dev);
458
459 /* KMS EnterVT equivalent */
460 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
19df918d
FT
461 intel_init_pch_refclk(dev);
462
463 DRM_LOCK(dev);
e3adcf8f
FT
464 dev_priv->mm.suspended = 0;
465
466 error = i915_gem_init_hw(dev);
e3adcf8f 467 DRM_UNLOCK(dev);
e3adcf8f 468
19df918d
FT
469 intel_modeset_init_hw(dev);
470 intel_modeset_setup_hw_state(dev, false);
471 drm_irq_install(dev);
e3adcf8f
FT
472 }
473
474 intel_opregion_init(dev);
475
476 dev_priv->modeset_on_lid = 0;
477
19df918d
FT
478#if 0
479 console_lock();
480 intel_fbdev_set_suspend(dev, 0);
481 console_unlock();
482#endif
e3adcf8f 483 return error;
b3705d71
HT
484}
485
e3adcf8f
FT
486static int
487i915_resume(device_t kdev)
b3705d71 488{
e3adcf8f
FT
489 struct drm_device *dev;
490 int ret;
491
492 dev = device_get_softc(kdev);
493 DRM_DEBUG_KMS("starting resume\n");
494#if 0
495 if (pci_enable_device(dev->pdev))
496 return -EIO;
b3705d71 497
e3adcf8f
FT
498 pci_set_master(dev->pdev);
499#endif
b3705d71 500
e3adcf8f
FT
501 ret = -i915_drm_thaw(dev);
502 if (ret != 0)
503 return (ret);
b3705d71 504
e3adcf8f
FT
505 drm_kms_helper_poll_enable(dev);
506 ret = bus_generic_resume(kdev);
507 DRM_DEBUG_KMS("finished resume %d\n", ret);
508 return (ret);
7f3c3d6f
HT
509}
510
7f3c3d6f 511static int
b3705d71 512i915_probe(device_t kdev)
7f3c3d6f 513{
e3adcf8f 514
b3705d71 515 return drm_probe(kdev, i915_pciidlist);
7f3c3d6f
HT
516}
517
e3adcf8f
FT
518int i915_modeset;
519
7f3c3d6f 520static int
b3705d71 521i915_attach(device_t kdev)
7f3c3d6f 522{
e3adcf8f 523 struct drm_device *dev;
b3705d71 524
e3adcf8f
FT
525 dev = device_get_softc(kdev);
526 if (i915_modeset == 1)
527 i915_driver_info.driver_features |= DRIVER_MODESET;
528 dev->driver = &i915_driver_info;
529 return (drm_attach(kdev, i915_pciidlist));
b3705d71
HT
530}
531
e3adcf8f
FT
532const struct intel_device_info *
533i915_get_device_id(int device)
b3705d71 534{
e3adcf8f 535 const struct intel_gfx_device_id *did;
b3705d71 536
e3adcf8f
FT
537 for (did = &pciidlist[0]; did->device != 0; did++) {
538 if (did->device != device)
539 continue;
540 return (did->info);
541 }
542 return (NULL);
7f3c3d6f
HT
543}
544
545static device_method_t i915_methods[] = {
546 /* Device interface */
547 DEVMETHOD(device_probe, i915_probe),
548 DEVMETHOD(device_attach, i915_attach),
b3705d71
HT
549 DEVMETHOD(device_suspend, i915_suspend),
550 DEVMETHOD(device_resume, i915_resume),
e3adcf8f 551 DEVMETHOD(device_detach, drm_detach),
d3c9c58e 552 DEVMETHOD_END
7f3c3d6f
HT
553};
554
555static driver_t i915_driver = {
7f3c3d6f 556 "drm",
7f3c3d6f 557 i915_methods,
b3705d71 558 sizeof(struct drm_device)
7f3c3d6f
HT
559};
560
561extern devclass_t drm_devclass;
e3adcf8f
FT
562DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
563 SI_ORDER_ANY);
564MODULE_DEPEND(i915kms, drm, 1, 1, 1);
565MODULE_DEPEND(i915kms, agp, 1, 1, 1);
566MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
567MODULE_DEPEND(i915kms, iic, 1, 1, 1);
568MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
569
570int intel_iommu_enabled = 0;
571TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
572
573int i915_semaphores = -1;
574TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
575static int i915_try_reset = 1;
576TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
577unsigned int i915_lvds_downclock = 0;
578TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
579int i915_vbt_sdvo_panel_type = -1;
580TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
581unsigned int i915_powersave = 1;
582TUNABLE_INT("drm.i915.powersave", &i915_powersave);
583int i915_enable_fbc = 0;
584TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
585int i915_enable_rc6 = 0;
586TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
587int i915_panel_use_ssc = -1;
588TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
589int i915_panel_ignore_lid = 0;
590TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
591int i915_modeset = 1;
592TUNABLE_INT("drm.i915.modeset", &i915_modeset);
593int i915_enable_ppgtt = -1;
594TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
595int i915_enable_hangcheck = 1;
596TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
597
00640ec9 598static int i8xx_do_reset(struct drm_device *dev)
e3adcf8f
FT
599{
600 struct drm_i915_private *dev_priv = dev->dev_private;
601
602 if (IS_I85X(dev))
603 return -ENODEV;
604
605 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
606 POSTING_READ(D_STATE);
607
608 if (IS_I830(dev) || IS_845G(dev)) {
609 I915_WRITE(DEBUG_RESET_I830,
610 DEBUG_RESET_DISPLAY |
611 DEBUG_RESET_RENDER |
612 DEBUG_RESET_FULL);
613 POSTING_READ(DEBUG_RESET_I830);
00640ec9 614 msleep(1);
e3adcf8f
FT
615
616 I915_WRITE(DEBUG_RESET_I830, 0);
617 POSTING_READ(DEBUG_RESET_I830);
618 }
619
00640ec9 620 msleep(1);
e3adcf8f
FT
621
622 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
623 POSTING_READ(D_STATE);
624
625 return 0;
626}
627
00640ec9 628static int i965_reset_complete(struct drm_device *dev)
e3adcf8f
FT
629{
630 u8 gdrst;
6df74fa7 631 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
e3adcf8f
FT
632 return (gdrst & 0x1);
633}
634
00640ec9 635static int i965_do_reset(struct drm_device *dev)
e3adcf8f 636{
00640ec9 637 int ret;
e3adcf8f
FT
638 u8 gdrst;
639
640 /*
641 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
642 * well as the reset bit (GR/bit 0). Setting the GR bit
643 * triggers the reset; when done, the hardware will clear it.
644 */
6df74fa7 645 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
00640ec9
FT
646 pci_write_config(dev->dev, I965_GDRST,
647 gdrst | GRDOM_RENDER |
648 GRDOM_RESET_ENABLE, 1);
649 ret = wait_for(i965_reset_complete(dev), 500);
650 if (ret)
651 return ret;
652
653 /* We can't reset render&media without also resetting display ... */
654 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
655 pci_write_config(dev->dev, I965_GDRST,
656 gdrst | GRDOM_MEDIA |
657 GRDOM_RESET_ENABLE, 1);
e3adcf8f 658
00640ec9 659 return wait_for(i965_reset_complete(dev), 500);
e3adcf8f
FT
660}
661
00640ec9 662static int ironlake_do_reset(struct drm_device *dev)
e3adcf8f 663{
00640ec9 664 struct drm_i915_private *dev_priv = dev->dev_private;
e3adcf8f 665 u32 gdrst;
00640ec9 666 int ret;
e3adcf8f 667
e3adcf8f 668 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
00640ec9
FT
669 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
670 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
671 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
672 if (ret)
673 return ret;
674
675 /* We can't reset render&media without also resetting display ... */
676 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
677 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
678 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
679 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
e3adcf8f
FT
680}
681
e9243325 682static int gen6_do_reset(struct drm_device *dev)
e3adcf8f 683{
e9243325 684 struct drm_i915_private *dev_priv = dev->dev_private;
e3adcf8f
FT
685 int ret;
686
687 dev_priv = dev->dev_private;
688
689 /* Hold gt_lock across reset to prevent any register access
690 * with forcewake not set correctly
691 */
692 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
693
694 /* Reset the chip */
695
696 /* GEN6_GDRST is not in the gt power well, no need to check
697 * for fifo space for the write or forcewake the chip for
698 * the read
699 */
700 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
701
702 /* Spin waiting for the device to ack the reset request */
19df918d 703 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
e3adcf8f
FT
704
705 /* If reset with a user forcewake, try to restore, otherwise turn it off */
e9243325
FT
706 if (dev_priv->forcewake_count)
707 dev_priv->gt.force_wake_get(dev_priv);
e3adcf8f 708 else
e9243325 709 dev_priv->gt.force_wake_put(dev_priv);
e3adcf8f
FT
710
711 /* Restore fifo count */
712 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
713
714 lockmgr(&dev_priv->gt_lock, LK_RELEASE);
e9243325 715 return ret;
e3adcf8f
FT
716}
717
00640ec9
FT
718int intel_gpu_reset(struct drm_device *dev)
719{
720 struct drm_i915_private *dev_priv = dev->dev_private;
721 int ret = -ENODEV;
722
723 switch (INTEL_INFO(dev)->gen) {
724 case 7:
725 case 6:
726 ret = gen6_do_reset(dev);
727 break;
728 case 5:
729 ret = ironlake_do_reset(dev);
730 break;
731 case 4:
732 ret = i965_do_reset(dev);
733 break;
734 case 2:
735 ret = i8xx_do_reset(dev);
736 break;
737 }
738
739 /* Also reset the gpu hangman. */
740 if (dev_priv->stop_rings) {
741 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
742 dev_priv->stop_rings = 0;
743 if (ret == -ENODEV) {
744 DRM_ERROR("Reset not implemented, but ignoring "
745 "error for simulated gpu hangs\n");
746 ret = 0;
747 }
748 }
749
750 return ret;
751}
752
e9243325
FT
753/**
754 * i915_reset - reset chip after a hang
755 * @dev: drm device to reset
756 *
757 * Reset the chip. Useful if a hang is detected. Returns zero on successful
758 * reset or otherwise an error code.
759 *
760 * Procedure is fairly simple:
761 * - reset the chip using the reset reg
762 * - re-init context state
763 * - re-init hardware status page
764 * - re-init ring buffer
765 * - re-init interrupt state
766 * - re-init display
767 */
00640ec9 768int i915_reset(struct drm_device *dev)
e3adcf8f
FT
769{
770 drm_i915_private_t *dev_priv = dev->dev_private;
e9243325
FT
771 int ret;
772
773 if (!i915_try_reset)
774 return 0;
775
00640ec9 776 DRM_LOCK(dev);
e3adcf8f
FT
777
778 i915_gem_reset(dev);
779
780 ret = -ENODEV;
00640ec9 781 if (time_uptime - dev_priv->last_gpu_reset < 5)
e3adcf8f 782 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
00640ec9
FT
783 else
784 ret = intel_gpu_reset(dev);
785
e3adcf8f
FT
786 dev_priv->last_gpu_reset = time_uptime;
787 if (ret) {
788 DRM_ERROR("Failed to reset chip.\n");
789 DRM_UNLOCK(dev);
00640ec9 790 return ret;
e3adcf8f
FT
791 }
792
e9243325
FT
793 /* Ok, now get things going again... */
794
795 /*
796 * Everything depends on having the GTT running, so we need to start
797 * there. Fortunately we don't need to do this unless we reset the
798 * chip at a PCI level.
799 *
800 * Next we need to restore the context, but we don't use those
801 * yet either...
802 *
803 * Ring buffer needs to be re-initialized in the KMS case, or if X
804 * was running at the time of the reset (i.e. we weren't VT
805 * switched away).
806 */
e3adcf8f 807 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
00640ec9
FT
808 !dev_priv->mm.suspended) {
809 struct intel_ring_buffer *ring;
810 int i;
811
e3adcf8f
FT
812 dev_priv->mm.suspended = 0;
813
814 i915_gem_init_swizzling(dev);
815
00640ec9
FT
816 for_each_ring(ring, dev_priv, i)
817 ring->init(ring);
e3adcf8f 818
00640ec9
FT
819#if 0 /* XXX: HW context support */
820 i915_gem_context_init(dev);
821#endif
e3adcf8f
FT
822 i915_gem_init_ppgtt(dev);
823
00640ec9
FT
824 /*
825 * It would make sense to re-init all the other hw state, at
826 * least the rps/rc6/emon init done within modeset_init_hw. For
827 * some unknown reason, this blows up my ilk, so don't.
828 */
829
e3adcf8f 830 DRM_UNLOCK(dev);
e3adcf8f 831
00640ec9
FT
832 drm_irq_uninstall(dev);
833 drm_irq_install(dev);
834 } else {
835 DRM_UNLOCK(dev);
e3adcf8f
FT
836 }
837
e9243325
FT
838 return 0;
839}
840
c0bdd5d9
FT
841/* We give fast paths for the really cool registers */
842#define NEEDS_FORCE_WAKE(dev_priv, reg) \
843 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
844 ((reg) < 0x40000) && \
845 ((reg) != FORCEWAKE))
846
e9243325
FT
847static bool IS_DISPLAYREG(u32 reg)
848{
849 /*
850 * This should make it easier to transition modules over to the
851 * new register block scheme, since we can do it incrementally.
852 */
853 if (reg >= VLV_DISPLAY_BASE)
854 return false;
855
856 if (reg >= RENDER_RING_BASE &&
857 reg < RENDER_RING_BASE + 0xff)
858 return false;
859 if (reg >= GEN6_BSD_RING_BASE &&
860 reg < GEN6_BSD_RING_BASE + 0xff)
861 return false;
862 if (reg >= BLT_RING_BASE &&
863 reg < BLT_RING_BASE + 0xff)
864 return false;
865
866 if (reg == PGTBL_ER)
867 return false;
868
869 if (reg >= IPEIR_I965 &&
870 reg < HWSTAM)
871 return false;
872
873 if (reg == MI_MODE)
874 return false;
875
876 if (reg == GFX_MODE_GEN7)
877 return false;
878
879 if (reg == RENDER_HWS_PGA_GEN7 ||
880 reg == BSD_HWS_PGA_GEN7 ||
881 reg == BLT_HWS_PGA_GEN7)
882 return false;
883
884 if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
885 reg == GEN6_BSD_RNCID)
886 return false;
887
888 if (reg == GEN6_BLITTER_ECOSKPD)
889 return false;
890
891 if (reg >= 0x4000c &&
892 reg <= 0x4002c)
893 return false;
894
895 if (reg >= 0x4f000 &&
896 reg <= 0x4f08f)
897 return false;
898
899 if (reg >= 0x4f100 &&
900 reg <= 0x4f11f)
901 return false;
902
903 if (reg >= VLV_MASTER_IER &&
904 reg <= GEN6_PMIER)
905 return false;
906
907 if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
908 reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
909 return false;
910
911 if (reg >= VLV_IIR_RW &&
912 reg <= VLV_ISR)
913 return false;
914
915 if (reg == FORCEWAKE_VLV ||
916 reg == FORCEWAKE_ACK_VLV)
917 return false;
918
919 if (reg == GEN6_GDRST)
920 return false;
921
922 switch (reg) {
923 case _3D_CHICKEN3:
924 case IVB_CHICKEN3:
925 case GEN7_COMMON_SLICE_CHICKEN1:
926 case GEN7_L3CNTLREG1:
927 case GEN7_L3_CHICKEN_MODE_REGISTER:
928 case GEN7_ROW_CHICKEN2:
929 case GEN7_L3SQCREG4:
930 case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
931 case GEN7_HALF_SLICE_CHICKEN1:
932 case GEN6_MBCTL:
933 case GEN6_UCGCTL2:
934 return false;
935 default:
936 break;
937 }
938
939 return true;
940}
941
942static void
943ilk_dummy_write(struct drm_i915_private *dev_priv)
944{
945 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
946 * chip from rc6 before touching it for real. MI_MODE is masked, hence
947 * harmless to write 0 into. */
948 I915_WRITE_NOTRACE(MI_MODE, 0);
e3adcf8f
FT
949}
950
951#define __i915_read(x, y) \
952u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
953 u##x val = 0; \
e9243325
FT
954 if (IS_GEN5(dev_priv->dev)) \
955 ilk_dummy_write(dev_priv); \
e3adcf8f
FT
956 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
957 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); \
958 if (dev_priv->forcewake_count == 0) \
e9243325 959 dev_priv->gt.force_wake_get(dev_priv); \
e3adcf8f
FT
960 val = DRM_READ##y(dev_priv->mmio_map, reg); \
961 if (dev_priv->forcewake_count == 0) \
e9243325 962 dev_priv->gt.force_wake_put(dev_priv); \
e3adcf8f 963 lockmgr(&dev_priv->gt_lock, LK_RELEASE); \
e9243325
FT
964 } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
965 val = DRM_READ##y(dev_priv->mmio_map, reg + 0x180000); \
e3adcf8f
FT
966 } else { \
967 val = DRM_READ##y(dev_priv->mmio_map, reg); \
968 } \
969 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
970 return val; \
971}
972
973__i915_read(8, 8)
974__i915_read(16, 16)
975__i915_read(32, 32)
976__i915_read(64, 64)
977#undef __i915_read
978
979#define __i915_write(x, y) \
980void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
981 u32 __fifo_ret = 0; \
982 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
983 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
984 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
985 } \
e9243325
FT
986 if (IS_GEN5(dev_priv->dev)) \
987 ilk_dummy_write(dev_priv); \
988 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
989 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
990 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
991 } \
992 if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
993 DRM_WRITE##y(dev_priv->mmio_map, reg + 0x180000, val); \
994 } else { \
995 DRM_WRITE##y(dev_priv->mmio_map, reg, val); \
996 } \
997 if (unlikely(__fifo_ret)) { \
e3adcf8f
FT
998 gen6_gt_check_fifodbg(dev_priv); \
999 } \
e9243325
FT
1000 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1001 DRM_ERROR("Unclaimed write to %x\n", reg); \
1002 DRM_WRITE32(dev_priv->mmio_map, GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
1003 } \
e3adcf8f 1004}
e9243325 1005
e3adcf8f
FT
1006__i915_write(8, 8)
1007__i915_write(16, 16)
1008__i915_write(32, 32)
1009__i915_write(64, 64)
1010#undef __i915_write