installer: Fix disk_find() on systems that have both da1 and da10.
[dragonfly.git] / sys / dev / drm / i915 / i915_drv.c
CommitLineData
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1/* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
3 */
4/*-
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
e3adcf8f 30 * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.c,v 1.1 2012/05/22 11:07:44 kib Exp $
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31 */
32
18e26a6d 33#include <drm/drmP.h>
5c6c6f23 34#include <drm/i915_drm.h>
c4a9e910 35#include "i915_drv.h"
18e26a6d 36#include <drm/drm_pciids.h>
e3adcf8f 37#include "intel_drv.h"
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38
39/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
40static drm_pci_id_list_t i915_pciidlist[] = {
41 i915_PCI_IDS
42};
43
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44static const struct intel_device_info intel_i830_info = {
45 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
46 .has_overlay = 1, .overlay_needs_physical = 1,
47};
48
49static const struct intel_device_info intel_845g_info = {
50 .gen = 2,
51 .has_overlay = 1, .overlay_needs_physical = 1,
52};
53
54static const struct intel_device_info intel_i85x_info = {
55 .gen = 2, .is_i85x = 1, .is_mobile = 1,
56 .cursor_needs_physical = 1,
57 .has_overlay = 1, .overlay_needs_physical = 1,
58};
59
60static const struct intel_device_info intel_i865g_info = {
61 .gen = 2,
62 .has_overlay = 1, .overlay_needs_physical = 1,
63};
64
65static const struct intel_device_info intel_i915g_info = {
66 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
67 .has_overlay = 1, .overlay_needs_physical = 1,
68};
69static const struct intel_device_info intel_i915gm_info = {
70 .gen = 3, .is_mobile = 1,
71 .cursor_needs_physical = 1,
72 .has_overlay = 1, .overlay_needs_physical = 1,
73 .supports_tv = 1,
74};
75static const struct intel_device_info intel_i945g_info = {
76 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
77 .has_overlay = 1, .overlay_needs_physical = 1,
78};
79static const struct intel_device_info intel_i945gm_info = {
80 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
81 .has_hotplug = 1, .cursor_needs_physical = 1,
82 .has_overlay = 1, .overlay_needs_physical = 1,
83 .supports_tv = 1,
84};
85
86static const struct intel_device_info intel_i965g_info = {
87 .gen = 4, .is_broadwater = 1,
88 .has_hotplug = 1,
89 .has_overlay = 1,
90};
91
92static const struct intel_device_info intel_i965gm_info = {
93 .gen = 4, .is_crestline = 1,
94 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
95 .has_overlay = 1,
96 .supports_tv = 1,
97};
98
99static const struct intel_device_info intel_g33_info = {
100 .gen = 3, .is_g33 = 1,
101 .need_gfx_hws = 1, .has_hotplug = 1,
102 .has_overlay = 1,
103};
104
105static const struct intel_device_info intel_g45_info = {
106 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
107 .has_pipe_cxsr = 1, .has_hotplug = 1,
108 .has_bsd_ring = 1,
109};
110
111static const struct intel_device_info intel_gm45_info = {
112 .gen = 4, .is_g4x = 1,
113 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
114 .has_pipe_cxsr = 1, .has_hotplug = 1,
115 .supports_tv = 1,
116 .has_bsd_ring = 1,
117};
118
119static const struct intel_device_info intel_pineview_info = {
120 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
121 .need_gfx_hws = 1, .has_hotplug = 1,
122 .has_overlay = 1,
123};
124
125static const struct intel_device_info intel_ironlake_d_info = {
126 .gen = 5,
127 .need_gfx_hws = 1, .has_hotplug = 1,
128 .has_bsd_ring = 1,
129};
130
131static const struct intel_device_info intel_ironlake_m_info = {
132 .gen = 5, .is_mobile = 1,
133 .need_gfx_hws = 1, .has_hotplug = 1,
134 .has_fbc = 0, /* disabled due to buggy hardware */
135 .has_bsd_ring = 1,
136};
137
138static const struct intel_device_info intel_sandybridge_d_info = {
139 .gen = 6,
140 .need_gfx_hws = 1, .has_hotplug = 1,
141 .has_bsd_ring = 1,
142 .has_blt_ring = 1,
143 .has_llc = 1,
144};
145
146static const struct intel_device_info intel_sandybridge_m_info = {
147 .gen = 6, .is_mobile = 1,
148 .need_gfx_hws = 1, .has_hotplug = 1,
149 .has_fbc = 1,
150 .has_bsd_ring = 1,
151 .has_blt_ring = 1,
152 .has_llc = 1,
153};
154
155static const struct intel_device_info intel_ivybridge_d_info = {
156 .is_ivybridge = 1, .gen = 7,
157 .need_gfx_hws = 1, .has_hotplug = 1,
158 .has_bsd_ring = 1,
159 .has_blt_ring = 1,
160 .has_llc = 1,
161};
162
163static const struct intel_device_info intel_ivybridge_m_info = {
164 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
165 .need_gfx_hws = 1, .has_hotplug = 1,
166 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
167 .has_bsd_ring = 1,
168 .has_blt_ring = 1,
169 .has_llc = 1,
170};
171
172#define INTEL_VGA_DEVICE(id, info_) { \
173 .device = id, \
174 .info = info_, \
175}
176
177static const struct intel_gfx_device_id {
178 int device;
179 const struct intel_device_info *info;
180} pciidlist[] = { /* aka */
181 INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
182 INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
183 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
184 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
185 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
186 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
187 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
188 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
189 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
190 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
191 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
192 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
193 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
194 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
195 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
196 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
197 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
198 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
199 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
200 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
201 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
202 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
203 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
204 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
205 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
206 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
207 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),
208 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
209 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
210 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
211 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
212 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
213 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
214 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
215 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
216 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
217 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
218 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
219 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
220 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
221 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
222 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
223 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
224 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
225 {0, 0}
226};
227
228static int i915_drm_freeze(struct drm_device *dev)
7f3c3d6f 229{
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230 struct drm_i915_private *dev_priv;
231 int error;
b3705d71 232
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233 dev_priv = dev->dev_private;
234 drm_kms_helper_poll_disable(dev);
235
236#if 0
237 pci_save_state(dev->pdev);
238#endif
b3705d71 239
5718399f 240 DRM_LOCK(dev);
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241 /* If KMS is active, we do the leavevt stuff here */
242 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
243 error = -i915_gem_idle(dev);
244 if (error) {
245 DRM_UNLOCK(dev);
6df74fa7 246 device_printf(dev->dev,
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247 "GEM idle failed, resume might fail\n");
248 return (error);
249 }
250 drm_irq_uninstall(dev);
251 }
252
b3705d71 253 i915_save_state(dev);
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254
255 intel_opregion_fini(dev);
256
257 /* Modeset on resume, not lid events */
258 dev_priv->modeset_on_lid = 0;
5718399f 259 DRM_UNLOCK(dev);
b3705d71 260
e3adcf8f 261 return 0;
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262}
263
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264static int
265i915_suspend(device_t kdev)
b3705d71 266{
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267 struct drm_device *dev;
268 int error;
269
270 dev = device_get_softc(kdev);
271 if (dev == NULL || dev->dev_private == NULL) {
272 DRM_ERROR("DRM not initialized, aborting suspend.\n");
273 return -ENODEV;
274 }
275
276 DRM_DEBUG_KMS("starting suspend\n");
277 error = i915_drm_freeze(dev);
278 if (error)
279 return (error);
280
281 error = bus_generic_suspend(kdev);
282 DRM_DEBUG_KMS("finished suspend %d\n", error);
283 return (error);
284}
285
286static int i915_drm_thaw(struct drm_device *dev)
287{
288 struct drm_i915_private *dev_priv = dev->dev_private;
289 int error = 0;
b3705d71 290
5718399f 291 DRM_LOCK(dev);
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292 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
293 i915_gem_restore_gtt_mappings(dev);
294 }
295
b3705d71 296 i915_restore_state(dev);
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297 intel_opregion_setup(dev);
298
299 /* KMS EnterVT equivalent */
300 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
301 dev_priv->mm.suspended = 0;
302
303 error = i915_gem_init_hw(dev);
304
305 if (HAS_PCH_SPLIT(dev))
306 ironlake_init_pch_refclk(dev);
307
308 DRM_UNLOCK(dev);
af4b81b9 309 lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE);
e3adcf8f 310 drm_mode_config_reset(dev);
af4b81b9 311 lockmgr(&dev->mode_config.mutex, LK_RELEASE);
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312 drm_irq_install(dev);
313
af4b81b9 314 lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE);
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315 /* Resume the modeset for every activated CRTC */
316 drm_helper_resume_force_mode(dev);
af4b81b9 317 lockmgr(&dev->mode_config.mutex, LK_RELEASE);
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318
319 if (IS_IRONLAKE_M(dev))
320 ironlake_enable_rc6(dev);
321 DRM_LOCK(dev);
322 }
323
324 intel_opregion_init(dev);
325
326 dev_priv->modeset_on_lid = 0;
327
5718399f 328 DRM_UNLOCK(dev);
b3705d71 329
e3adcf8f 330 return error;
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331}
332
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333static int
334i915_resume(device_t kdev)
b3705d71 335{
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336 struct drm_device *dev;
337 int ret;
338
339 dev = device_get_softc(kdev);
340 DRM_DEBUG_KMS("starting resume\n");
341#if 0
342 if (pci_enable_device(dev->pdev))
343 return -EIO;
b3705d71 344
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345 pci_set_master(dev->pdev);
346#endif
b3705d71 347
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348 ret = -i915_drm_thaw(dev);
349 if (ret != 0)
350 return (ret);
b3705d71 351
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352 drm_kms_helper_poll_enable(dev);
353 ret = bus_generic_resume(kdev);
354 DRM_DEBUG_KMS("finished resume %d\n", ret);
355 return (ret);
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356}
357
7f3c3d6f 358static int
b3705d71 359i915_probe(device_t kdev)
7f3c3d6f 360{
e3adcf8f 361
b3705d71 362 return drm_probe(kdev, i915_pciidlist);
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363}
364
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365int i915_modeset;
366
7f3c3d6f 367static int
b3705d71 368i915_attach(device_t kdev)
7f3c3d6f 369{
e3adcf8f 370 struct drm_device *dev;
b3705d71 371
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372 dev = device_get_softc(kdev);
373 if (i915_modeset == 1)
374 i915_driver_info.driver_features |= DRIVER_MODESET;
375 dev->driver = &i915_driver_info;
376 return (drm_attach(kdev, i915_pciidlist));
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377}
378
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379const struct intel_device_info *
380i915_get_device_id(int device)
b3705d71 381{
e3adcf8f 382 const struct intel_gfx_device_id *did;
b3705d71 383
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384 for (did = &pciidlist[0]; did->device != 0; did++) {
385 if (did->device != device)
386 continue;
387 return (did->info);
388 }
389 return (NULL);
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390}
391
392static device_method_t i915_methods[] = {
393 /* Device interface */
394 DEVMETHOD(device_probe, i915_probe),
395 DEVMETHOD(device_attach, i915_attach),
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396 DEVMETHOD(device_suspend, i915_suspend),
397 DEVMETHOD(device_resume, i915_resume),
e3adcf8f 398 DEVMETHOD(device_detach, drm_detach),
d3c9c58e 399 DEVMETHOD_END
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400};
401
402static driver_t i915_driver = {
7f3c3d6f 403 "drm",
7f3c3d6f 404 i915_methods,
b3705d71 405 sizeof(struct drm_device)
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406};
407
408extern devclass_t drm_devclass;
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409DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
410 SI_ORDER_ANY);
411MODULE_DEPEND(i915kms, drm, 1, 1, 1);
412MODULE_DEPEND(i915kms, agp, 1, 1, 1);
413MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
414MODULE_DEPEND(i915kms, iic, 1, 1, 1);
415MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
416
417int intel_iommu_enabled = 0;
418TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
419
420int i915_semaphores = -1;
421TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
422static int i915_try_reset = 1;
423TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
424unsigned int i915_lvds_downclock = 0;
425TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
426int i915_vbt_sdvo_panel_type = -1;
427TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
428unsigned int i915_powersave = 1;
429TUNABLE_INT("drm.i915.powersave", &i915_powersave);
430int i915_enable_fbc = 0;
431TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
432int i915_enable_rc6 = 0;
433TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
434int i915_panel_use_ssc = -1;
435TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
436int i915_panel_ignore_lid = 0;
437TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
438int i915_modeset = 1;
439TUNABLE_INT("drm.i915.modeset", &i915_modeset);
440int i915_enable_ppgtt = -1;
441TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
442int i915_enable_hangcheck = 1;
443TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
444
445#define PCI_VENDOR_INTEL 0x8086
446#define INTEL_PCH_DEVICE_ID_MASK 0xff00
447#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
448#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
449#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
450
451void
452intel_detect_pch(struct drm_device *dev)
453{
454 struct drm_i915_private *dev_priv;
455 device_t pch;
456 uint32_t id;
457
458 dev_priv = dev->dev_private;
459 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
460 if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
461 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
462 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
463 dev_priv->pch_type = PCH_IBX;
464 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
465 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
466 dev_priv->pch_type = PCH_CPT;
467 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
468 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
469 /* PantherPoint is CPT compatible */
470 dev_priv->pch_type = PCH_CPT;
471 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
472 } else
473 DRM_DEBUG_KMS("No PCH detected\n");
474 } else
475 DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
476}
477
478void
479__gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
480{
481 int count;
482
483 count = 0;
484 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
485 DELAY(10);
486
487 I915_WRITE_NOTRACE(FORCEWAKE, 1);
488 POSTING_READ(FORCEWAKE);
489
490 count = 0;
491 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
492 DELAY(10);
493}
494
495void
496__gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
497{
498 int count;
499
500 count = 0;
501 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
502 DELAY(10);
503
504 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
505 POSTING_READ(FORCEWAKE_MT);
506
507 count = 0;
508 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
509 DELAY(10);
510}
511
512void
513gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
514{
515
516 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
517 if (dev_priv->forcewake_count++ == 0)
518 dev_priv->display.force_wake_get(dev_priv);
519 lockmgr(&dev_priv->gt_lock, LK_RELEASE);
520}
521
522static void
523gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
524{
525 u32 gtfifodbg;
526
527 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
528 if ((gtfifodbg & GT_FIFO_CPU_ERROR_MASK) != 0) {
529 kprintf("MMIO read or write has been dropped %x\n", gtfifodbg);
530 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
531 }
532}
533
534void
535__gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
536{
537
538 I915_WRITE_NOTRACE(FORCEWAKE, 0);
539 /* The below doubles as a POSTING_READ */
540 gen6_gt_check_fifodbg(dev_priv);
541}
542
543void
544__gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
545{
546
547 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
548 /* The below doubles as a POSTING_READ */
549 gen6_gt_check_fifodbg(dev_priv);
550}
551
552void
553gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
554{
555
556 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
557 if (--dev_priv->forcewake_count == 0)
558 dev_priv->display.force_wake_put(dev_priv);
559 lockmgr(&dev_priv->gt_lock, LK_RELEASE);
560}
561
562int
563__gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
564{
565 int ret = 0;
566
567 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
568 int loop = 500;
569 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
570 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
571 DELAY(10);
572 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
573 }
574 if (loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES) {
575 kprintf("%s loop\n", __func__);
576 ++ret;
577 }
578 dev_priv->gt_fifo_count = fifo;
579 }
580 dev_priv->gt_fifo_count--;
581
582 return (ret);
583}
584
585static int
586i8xx_do_reset(struct drm_device *dev, u8 flags)
587{
588 struct drm_i915_private *dev_priv = dev->dev_private;
589
590 if (IS_I85X(dev))
591 return -ENODEV;
592
593 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
594 POSTING_READ(D_STATE);
595
596 if (IS_I830(dev) || IS_845G(dev)) {
597 I915_WRITE(DEBUG_RESET_I830,
598 DEBUG_RESET_DISPLAY |
599 DEBUG_RESET_RENDER |
600 DEBUG_RESET_FULL);
601 POSTING_READ(DEBUG_RESET_I830);
602 DELAY(1000);
603
604 I915_WRITE(DEBUG_RESET_I830, 0);
605 POSTING_READ(DEBUG_RESET_I830);
606 }
607
608 DELAY(1000);
609
610 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
611 POSTING_READ(D_STATE);
612
613 return 0;
614}
615
616static int
617i965_reset_complete(struct drm_device *dev)
618{
619 u8 gdrst;
620
6df74fa7 621 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
e3adcf8f
FT
622 return (gdrst & 0x1);
623}
624
625static int
626i965_do_reset(struct drm_device *dev, u8 flags)
627{
628 u8 gdrst;
629
630 /*
631 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
632 * well as the reset bit (GR/bit 0). Setting the GR bit
633 * triggers the reset; when done, the hardware will clear it.
634 */
6df74fa7
FT
635 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
636 pci_write_config(dev->dev, I965_GDRST, gdrst | flags | 0x1, 1);
e3adcf8f
FT
637
638 return (_intel_wait_for(dev, i965_reset_complete(dev), 500, 1,
639 "915rst"));
640}
641
642static int
643ironlake_do_reset(struct drm_device *dev, u8 flags)
644{
645 struct drm_i915_private *dev_priv;
646 u32 gdrst;
647
648 dev_priv = dev->dev_private;
649 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
650 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
651 return (_intel_wait_for(dev,
652 (I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1) != 0,
653 500, 1, "915rst"));
654}
655
656static int
657gen6_do_reset(struct drm_device *dev, u8 flags)
658{
659 struct drm_i915_private *dev_priv;
660 int ret;
661
662 dev_priv = dev->dev_private;
663
664 /* Hold gt_lock across reset to prevent any register access
665 * with forcewake not set correctly
666 */
667 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
668
669 /* Reset the chip */
670
671 /* GEN6_GDRST is not in the gt power well, no need to check
672 * for fifo space for the write or forcewake the chip for
673 * the read
674 */
675 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
676
677 /* Spin waiting for the device to ack the reset request */
678 ret = _intel_wait_for(dev,
679 (I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
680 500, 1, "915rst");
681
682 /* If reset with a user forcewake, try to restore, otherwise turn it off */
683 if (dev_priv->forcewake_count)
684 dev_priv->display.force_wake_get(dev_priv);
685 else
686 dev_priv->display.force_wake_put(dev_priv);
687
688 /* Restore fifo count */
689 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
690
691 lockmgr(&dev_priv->gt_lock, LK_RELEASE);
692 return (ret);
693}
694
695int
696i915_reset(struct drm_device *dev, u8 flags)
697{
698 drm_i915_private_t *dev_priv = dev->dev_private;
699 /*
700 * We really should only reset the display subsystem if we actually
701 * need to
702 */
703 bool need_display = true;
704 int ret;
705
706 if (!i915_try_reset)
707 return (0);
708
709 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
710 return (-EBUSY);
711
712 i915_gem_reset(dev);
713
714 ret = -ENODEV;
715 if (time_uptime - dev_priv->last_gpu_reset < 5) {
716 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
717 } else {
718 switch (INTEL_INFO(dev)->gen) {
719 case 7:
720 case 6:
721 ret = gen6_do_reset(dev, flags);
722 break;
723 case 5:
724 ret = ironlake_do_reset(dev, flags);
725 break;
726 case 4:
727 ret = i965_do_reset(dev, flags);
728 break;
729 case 2:
730 ret = i8xx_do_reset(dev, flags);
731 break;
732 }
733 }
734 dev_priv->last_gpu_reset = time_uptime;
735 if (ret) {
736 DRM_ERROR("Failed to reset chip.\n");
737 DRM_UNLOCK(dev);
738 return (ret);
739 }
740
741 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
742 !dev_priv->mm.suspended) {
743 dev_priv->mm.suspended = 0;
744
745 i915_gem_init_swizzling(dev);
746
ad50ea93 747 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
e3adcf8f 748 if (HAS_BSD(dev))
ad50ea93 749 dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
e3adcf8f 750 if (HAS_BLT(dev))
ad50ea93 751 dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
e3adcf8f
FT
752
753 i915_gem_init_ppgtt(dev);
754
755 drm_irq_uninstall(dev);
756 drm_mode_config_reset(dev);
757 DRM_UNLOCK(dev);
758 drm_irq_install(dev);
759 DRM_LOCK(dev);
760 }
761 DRM_UNLOCK(dev);
762
763 if (need_display) {
af4b81b9 764 lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE);
e3adcf8f 765 drm_helper_resume_force_mode(dev);
af4b81b9 766 lockmgr(&dev->mode_config.mutex, LK_RELEASE);
e3adcf8f
FT
767 }
768
769 return (0);
770}
771
772#define __i915_read(x, y) \
773u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
774 u##x val = 0; \
775 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
776 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); \
777 if (dev_priv->forcewake_count == 0) \
778 dev_priv->display.force_wake_get(dev_priv); \
779 val = DRM_READ##y(dev_priv->mmio_map, reg); \
780 if (dev_priv->forcewake_count == 0) \
781 dev_priv->display.force_wake_put(dev_priv); \
782 lockmgr(&dev_priv->gt_lock, LK_RELEASE); \
783 } else { \
784 val = DRM_READ##y(dev_priv->mmio_map, reg); \
785 } \
786 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
787 return val; \
788}
789
790__i915_read(8, 8)
791__i915_read(16, 16)
792__i915_read(32, 32)
793__i915_read(64, 64)
794#undef __i915_read
795
796#define __i915_write(x, y) \
797void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
798 u32 __fifo_ret = 0; \
799 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
800 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
801 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
802 } \
803 DRM_WRITE##y(dev_priv->mmio_map, reg, val); \
804 if (__predict_false(__fifo_ret)) { \
805 gen6_gt_check_fifodbg(dev_priv); \
806 } \
807}
808__i915_write(8, 8)
809__i915_write(16, 16)
810__i915_write(32, 32)
811__i915_write(64, 64)
812#undef __i915_write