x86_64: Move ioapic_map() from mp_machdep.c to ioapic.c
[dragonfly.git] / sys / platform / pc64 / x86_64 / mp_machdep.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
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26 */
27
28#include "opt_cpu.h"
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/sysctl.h>
34#include <sys/malloc.h>
35#include <sys/memrange.h>
36#include <sys/cons.h> /* cngetc() */
37#include <sys/machintr.h>
38
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39#include <sys/mplock2.h>
40
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41#include <vm/vm.h>
42#include <vm/vm_param.h>
43#include <vm/pmap.h>
44#include <vm/vm_kern.h>
45#include <vm/vm_extern.h>
46#include <sys/lock.h>
47#include <vm/vm_map.h>
48#include <sys/user.h>
49#ifdef GPROF
50#include <sys/gmon.h>
51#endif
52
53#include <machine/smp.h>
54#include <machine_base/apic/apicreg.h>
55#include <machine/atomic.h>
56#include <machine/cpufunc.h>
2b6cd37e 57#include <machine_base/apic/lapic.h>
61452645 58#include <machine_base/apic/ioapic.h>
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59#include <machine/psl.h>
60#include <machine/segments.h>
61#include <machine/tss.h>
62#include <machine/specialreg.h>
63#include <machine/globaldata.h>
4117f2fd 64#include <machine/pmap_inval.h>
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65
66#include <machine/md_var.h> /* setidt() */
57a9c56b 67#include <machine_base/icu/icu.h> /* IPIs */
e0918665 68#include <machine_base/apic/ioapic_abi.h>
57a9c56b 69#include <machine/intr_machdep.h> /* IPIs */
46d4e165 70
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71#define WARMBOOT_TARGET 0
72#define WARMBOOT_OFF (KERNBASE + 0x0467)
73#define WARMBOOT_SEG (KERNBASE + 0x0469)
74
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75#define CMOS_REG (0x70)
76#define CMOS_DATA (0x71)
77#define BIOS_RESET (0x0f)
78#define BIOS_WARM (0x0a)
79
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80/*
81 * this code MUST be enabled here and in mpboot.s.
82 * it follows the very early stages of AP boot by placing values in CMOS ram.
83 * it NORMALLY will never be needed and thus the primitive method for enabling.
84 *
85 */
86#if defined(CHECK_POINTS)
87#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
88#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
89
90#define CHECK_INIT(D); \
91 CHECK_WRITE(0x34, (D)); \
92 CHECK_WRITE(0x35, (D)); \
93 CHECK_WRITE(0x36, (D)); \
94 CHECK_WRITE(0x37, (D)); \
95 CHECK_WRITE(0x38, (D)); \
96 CHECK_WRITE(0x39, (D));
97
98#define CHECK_PRINT(S); \
99 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
100 (S), \
101 CHECK_READ(0x34), \
102 CHECK_READ(0x35), \
103 CHECK_READ(0x36), \
104 CHECK_READ(0x37), \
105 CHECK_READ(0x38), \
106 CHECK_READ(0x39));
107
108#else /* CHECK_POINTS */
109
110#define CHECK_INIT(D)
111#define CHECK_PRINT(S)
112
113#endif /* CHECK_POINTS */
114
115/*
116 * Values to send to the POST hardware.
117 */
118#define MP_BOOTADDRESS_POST 0x10
119#define MP_PROBE_POST 0x11
120#define MPTABLE_PASS1_POST 0x12
121
122#define MP_START_POST 0x13
123#define MP_ENABLE_POST 0x14
124#define MPTABLE_PASS2_POST 0x15
125
126#define START_ALL_APS_POST 0x16
127#define INSTALL_AP_TRAMP_POST 0x17
128#define START_AP_POST 0x18
129
130#define MP_ANNOUNCE_POST 0x19
131
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132/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
133int current_postcode;
134
135/** XXX FIXME: what system files declare these??? */
136extern struct region_descriptor r_gdt, r_idt;
137
46d4e165 138int mp_naps; /* # of Applications processors */
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139extern int nkpt;
140
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141int64_t tsc0_offset;
142extern int64_t tsc_offsets[];
143
faaf4131 144#ifdef SMP /* APIC-IO */
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145struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
146#endif
147
148/*
149 * APIC ID logical/physical mapping structures.
150 * We oversize these to simplify boot-time config.
151 */
152int cpu_num_to_apic_id[NAPICID];
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153int apic_id_to_logical[NAPICID];
154
155/* AP uses this during bootstrap. Do not staticize. */
156char *bootSTK;
157static int bootAP;
158
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159struct pcb stoppcbs[MAXCPU];
160
161extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
162
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163/*
164 * Local data and functions.
165 */
166
46d4e165 167static u_int boot_address;
46d4e165 168static int mp_finish;
c6b1591c 169static int mp_finish_lapic;
46d4e165 170
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171static void mp_enable(u_int boot_addr);
172
46d4e165 173static int start_all_aps(u_int boot_addr);
bfc09ba0 174#if 0
46d4e165 175static void install_ap_tramp(u_int boot_addr);
bfc09ba0 176#endif
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177static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
178static int smitest(void);
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179
180static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
c6b1591c 181static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
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182cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
183SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
184static u_int bootMP_size;
185
2bcdf13e 186u_int base_memory;
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187int imcr_present;
188
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189/*
190 * Calculate usable address in base memory for AP trampoline code.
191 */
192u_int
193mp_bootaddress(u_int basemem)
194{
195 POSTCODE(MP_BOOTADDRESS_POST);
196
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197 base_memory = basemem;
198
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199 bootMP_size = mptramp_end - mptramp_start;
200 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
201 if (((basemem * 1024) - boot_address) < bootMP_size)
202 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
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203 /* 3 levels of page table pages */
204 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
205
206 return mptramp_pagetables;
207}
208
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209/*
210 * Startup the SMP processors.
211 */
212void
213mp_start(void)
214{
215 POSTCODE(MP_START_POST);
a0679cc7 216 mp_enable(boot_address);
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217}
218
219
220/*
221 * Print various information about the SMP system hardware and setup.
222 */
223void
224mp_announce(void)
225{
226 int x;
227
228 POSTCODE(MP_ANNOUNCE_POST);
229
230 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
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231 kprintf(" cpu0 (BSP): apic id: %2d\n", CPU_TO_ID(0));
232 for (x = 1; x <= mp_naps; ++x)
233 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPU_TO_ID(x));
46d4e165 234
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235 if (!apic_io_enable)
236 kprintf(" Warning: APIC I/O disabled\n");
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237}
238
239/*
240 * AP cpu's call this to sync up protected mode.
241 *
ec073ddc 242 * WARNING! %gs is not set up on entry. This routine sets up %gs.
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243 */
244void
245init_secondary(void)
246{
247 int gsel_tss;
248 int x, myid = bootAP;
249 u_int64_t msr, cr0;
250 struct mdglobaldata *md;
251 struct privatespace *ps;
252
253 ps = &CPU_prvspace[myid];
254
255 gdt_segs[GPROC0_SEL].ssd_base =
256 (long) &ps->mdglobaldata.gd_common_tss;
257 ps->mdglobaldata.mi.gd_prvspace = ps;
258
259 /* We fill the 32-bit segment descriptors */
260 for (x = 0; x < NGDT; x++) {
261 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
262 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
263 }
264 /* And now a 64-bit one */
265 ssdtosyssd(&gdt_segs[GPROC0_SEL],
266 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
267
268 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
269 r_gdt.rd_base = (long) &gdt[myid * NGDT];
270 lgdt(&r_gdt); /* does magic intra-segment return */
271
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272 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
273 wrmsr(MSR_FSBASE, 0); /* User value */
274 wrmsr(MSR_GSBASE, (u_int64_t)ps);
275 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
276
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277 lidt(&r_idt);
278
279#if 0
280 lldt(_default_ldt);
281 mdcpu->gd_currentldt = _default_ldt;
282#endif
283
284 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
285 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
286
287 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
288
289 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
290#if 0 /* JG XXX */
291 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
292#endif
293 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
294 md->gd_common_tssd = *md->gd_tss_gdt;
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295
296 /* double fault stack */
297 md->gd_common_tss.tss_ist1 =
298 (long)&md->mi.gd_prvspace->idlestack[
299 sizeof(md->mi.gd_prvspace->idlestack)];
300
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301 ltr(gsel_tss);
302
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303 /*
304 * Set to a known state:
305 * Set by mpboot.s: CR0_PG, CR0_PE
306 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
307 */
308 cr0 = rcr0();
309 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
310 load_cr0(cr0);
311
312 /* Set up the fast syscall stuff */
313 msr = rdmsr(MSR_EFER) | EFER_SCE;
314 wrmsr(MSR_EFER, msr);
315 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
316 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
317 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
318 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
319 wrmsr(MSR_STAR, msr);
320 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
321
322 pmap_set_opt(); /* PSE/4MB pages, etc */
323#if JGXXX
324 /* Initialize the PAT MSR. */
325 pmap_init_pat();
326#endif
327
328 /* set up CPU registers and state */
329 cpu_setregs();
330
331 /* set up SSE/NX registers */
332 initializecpu();
333
334 /* set up FPU state on the AP */
335 npxinit(__INITIAL_NPXCW__);
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336
337 /* disable the APIC, just to be SURE */
338 lapic->svr &= ~APIC_SVR_ENABLE;
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339}
340
341/*******************************************************************
342 * local functions and data
343 */
344
345/*
346 * start the SMP system
347 */
348static void
349mp_enable(u_int boot_addr)
350{
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351 POSTCODE(MP_ENABLE_POST);
352
91903a05 353 lapic_config();
8e4c6923 354
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355 /* Initialize BSP's local APIC */
356 lapic_init(TRUE);
357
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358 /* start each Application Processor */
359 start_all_aps(boot_addr);
360
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361 if (apic_io_enable)
362 ioapic_config();
363
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364 /* Finalize PIC */
365 MachIntrABI.finalize();
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366}
367
368
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369void
370mp_set_cpuids(int cpu_id, int apic_id)
371{
372 CPU_TO_ID(cpu_id) = apic_id;
373 ID_TO_CPU(apic_id) = cpu_id;
374}
375
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376/*
377 * start each AP in our list
378 */
379static int
380start_all_aps(u_int boot_addr)
381{
382 vm_offset_t va = boot_address + KERNBASE;
383 u_int64_t *pt4, *pt3, *pt2;
384 int x, i, pg;
385 int shift;
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386 int smicount;
387 int smibest;
388 int smilast;
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389 u_char mpbiosreason;
390 u_long mpbioswarmvec;
391 struct mdglobaldata *gd;
392 struct privatespace *ps;
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393
394 POSTCODE(START_ALL_APS_POST);
395
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396 /* install the AP 1st level boot code */
397 pmap_kenter(va, boot_address);
bfc09ba0 398 cpu_invlpg((void *)va); /* JG XXX */
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399 bcopy(mptramp_start, (void *)va, bootMP_size);
400
401 /* Locate the page tables, they'll be below the trampoline */
402 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
403 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
404 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
405
406 /* Create the initial 1GB replicated page tables */
407 for (i = 0; i < 512; i++) {
408 /* Each slot of the level 4 pages points to the same level 3 page */
409 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
410 pt4[i] |= PG_V | PG_RW | PG_U;
411
412 /* Each slot of the level 3 pages points to the same level 2 page */
413 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
414 pt3[i] |= PG_V | PG_RW | PG_U;
415
416 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
417 pt2[i] = i * (2 * 1024 * 1024);
418 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
419 }
420
421 /* save the current value of the warm-start vector */
422 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
423 outb(CMOS_REG, BIOS_RESET);
424 mpbiosreason = inb(CMOS_DATA);
425
426 /* setup a vector to our boot code */
427 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
428 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
429 outb(CMOS_REG, BIOS_RESET);
430 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
431
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432 /*
433 * If we have a TSC we can figure out the SMI interrupt rate.
434 * The SMI does not necessarily use a constant rate. Spend
435 * up to 250ms trying to figure it out.
436 */
437 smibest = 0;
438 if (cpu_feature & CPUID_TSC) {
439 set_apic_timer(275000);
440 smilast = read_apic_timer();
441 for (x = 0; x < 20 && read_apic_timer(); ++x) {
442 smicount = smitest();
443 if (smibest == 0 || smilast - smicount < smibest)
444 smibest = smilast - smicount;
445 smilast = smicount;
446 }
447 if (smibest > 250000)
448 smibest = 0;
449 if (smibest) {
450 smibest = smibest * (int64_t)1000000 /
451 get_apic_timer_frequency();
452 }
453 }
454 if (smibest)
455 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
456 1000000 / smibest, smibest);
457
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458 /* start each AP */
459 for (x = 1; x <= mp_naps; ++x) {
460
461 /* This is a bit verbose, it will go away soon. */
462
463 /* first page of AP's private space */
b2b3ffcd 464 pg = x * x86_64_btop(sizeof(struct privatespace));
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465
466 /* allocate new private data page(s) */
467 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
468 MDGLOBALDATA_BASEALLOC_SIZE);
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469
470 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
471 bzero(gd, sizeof(*gd));
472 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
473
474 /* prime data page for it to use */
475 mi_gdinit(&gd->mi, x);
476 cpu_gdinit(gd, x);
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477 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
478 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
479
480 /* setup a vector to our boot code */
481 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
482 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
483 outb(CMOS_REG, BIOS_RESET);
484 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
485
486 /*
487 * Setup the AP boot stack
488 */
489 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
490 bootAP = x;
491
492 /* attempt to start the Application Processor */
493 CHECK_INIT(99); /* setup checkpoints */
bb467734 494 if (!start_ap(gd, boot_addr, smibest)) {
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495 kprintf("\nAP #%d (PHY# %d) failed!\n",
496 x, CPU_TO_ID(x));
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497 CHECK_PRINT("trace"); /* show checkpoints */
498 /* better panic as the AP may be running loose */
499 kprintf("panic y/n? [y] ");
500 if (cngetc() != 'n')
501 panic("bye-bye");
502 }
503 CHECK_PRINT("trace"); /* show checkpoints */
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504 }
505
506 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
507 ncpus = x;
508
509 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
510 for (shift = 0; (1 << shift) <= ncpus; ++shift)
511 ;
512 --shift;
513 ncpus2_shift = shift;
514 ncpus2 = 1 << shift;
515 ncpus2_mask = ncpus2 - 1;
516
517 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
518 if ((1 << shift) < ncpus)
519 ++shift;
520 ncpus_fit = 1 << shift;
521 ncpus_fit_mask = ncpus_fit - 1;
522
523 /* build our map of 'other' CPUs */
da23a592 524 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
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525 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
526 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
527
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528 /* restore the warmstart vector */
529 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
530 outb(CMOS_REG, BIOS_RESET);
531 outb(CMOS_DATA, mpbiosreason);
532
533 /*
534 * NOTE! The idlestack for the BSP was setup by locore. Finish
535 * up, clean out the P==V mapping we did earlier.
536 */
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537 pmap_set_opt();
538
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539 /*
540 * Wait all APs to finish initializing LAPIC
541 */
542 mp_finish_lapic = 1;
543 if (bootverbose)
544 kprintf("SMP: Waiting APs LAPIC initialization\n");
545 if (cpu_feature & CPUID_TSC)
546 tsc0_offset = rdtsc();
547 tsc_offsets[0] = 0;
548 rel_mplock();
549 while (smp_lapic_mask != smp_startup_mask) {
550 cpu_lfence();
551 if (cpu_feature & CPUID_TSC)
552 tsc0_offset = rdtsc();
553 }
554 while (try_mplock() == 0)
555 ;
556
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557 /* number of APs actually started */
558 return ncpus - 1;
559}
560
561
562/*
563 * load the 1st level AP boot code into base memory.
564 */
565
566/* targets for relocation */
567extern void bigJump(void);
568extern void bootCodeSeg(void);
569extern void bootDataSeg(void);
570extern void MPentry(void);
571extern u_int MP_GDT;
572extern u_int mp_gdtbase;
573
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574#if 0
575
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576static void
577install_ap_tramp(u_int boot_addr)
578{
579 int x;
580 int size = *(int *) ((u_long) & bootMP_size);
581 u_char *src = (u_char *) ((u_long) bootMP);
582 u_char *dst = (u_char *) boot_addr + KERNBASE;
583 u_int boot_base = (u_int) bootMP;
584 u_int8_t *dst8;
585 u_int16_t *dst16;
586 u_int32_t *dst32;
587
588 POSTCODE(INSTALL_AP_TRAMP_POST);
589
590 for (x = 0; x < size; ++x)
591 *dst++ = *src++;
592
593 /*
594 * modify addresses in code we just moved to basemem. unfortunately we
595 * need fairly detailed info about mpboot.s for this to work. changes
596 * to mpboot.s might require changes here.
597 */
598
599 /* boot code is located in KERNEL space */
600 dst = (u_char *) boot_addr + KERNBASE;
601
602 /* modify the lgdt arg */
603 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
604 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
605
606 /* modify the ljmp target for MPentry() */
607 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
608 *dst32 = ((u_int) MPentry - KERNBASE);
609
610 /* modify the target for boot code segment */
611 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
612 dst8 = (u_int8_t *) (dst16 + 1);
613 *dst16 = (u_int) boot_addr & 0xffff;
614 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
615
616 /* modify the target for boot data segment */
617 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
618 dst8 = (u_int8_t *) (dst16 + 1);
619 *dst16 = (u_int) boot_addr & 0xffff;
620 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
621}
622
bfc09ba0 623#endif
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624
625/*
bb467734 626 * This function starts the AP (application processor) identified
46d4e165
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627 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
628 * to accomplish this. This is necessary because of the nuances
629 * of the different hardware we might encounter. It ain't pretty,
630 * but it seems to work.
631 *
632 * NOTE: eventually an AP gets to ap_init(), which is called just
633 * before the AP goes into the LWKT scheduler's idle loop.
634 */
635static int
bb467734 636start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
46d4e165
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637{
638 int physical_cpu;
639 int vector;
640 u_long icr_lo, icr_hi;
641
642 POSTCODE(START_AP_POST);
643
644 /* get the PHYSICAL APIC ID# */
645 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
646
647 /* calculate the vector */
648 vector = (boot_addr >> 12) & 0xff;
649
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650 /* We don't want anything interfering */
651 cpu_disable_intr();
652
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653 /* Make sure the target cpu sees everything */
654 wbinvd();
655
bb467734
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656 /*
657 * Try to detect when a SMI has occurred, wait up to 200ms.
658 *
659 * If a SMI occurs during an AP reset but before we issue
660 * the STARTUP command, the AP may brick. To work around
661 * this problem we hold off doing the AP startup until
662 * after we have detected the SMI. Hopefully another SMI
663 * will not occur before we finish the AP startup.
664 *
665 * Retries don't seem to help. SMIs have a window of opportunity
666 * and if USB->legacy keyboard emulation is enabled in the BIOS
667 * the interrupt rate can be quite high.
668 *
669 * NOTE: Don't worry about the L1 cache load, it might bloat
670 * ldelta a little but ndelta will be so huge when the SMI
671 * occurs the detection logic will still work fine.
672 */
673 if (smibest) {
674 set_apic_timer(200000);
675 smitest();
676 }
677
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678 /*
679 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
680 * and running the target CPU. OR this INIT IPI might be latched (P5
681 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
682 * ignored.
bb467734
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683 *
684 * see apic/apicreg.h for icr bit definitions.
685 *
686 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
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687 */
688
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689 /*
690 * Setup the address for the target AP. We can setup
691 * icr_hi once and then just trigger operations with
692 * icr_lo.
693 */
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694 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
695 icr_hi |= (physical_cpu << 24);
46d4e165 696 icr_lo = lapic->icr_lo & 0xfff00000;
bb467734 697 lapic->icr_hi = icr_hi;
46d4e165 698
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699 /*
700 * Do an INIT IPI: assert RESET
701 *
702 * Use edge triggered mode to assert INIT
703 */
704 lapic->icr_lo = icr_lo | 0x00004500;
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705 while (lapic->icr_lo & APIC_DELSTAT_MASK)
706 /* spin */ ;
707
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708 /*
709 * The spec calls for a 10ms delay but we may have to use a
710 * MUCH lower delay to avoid bricking an AP due to a fast SMI
711 * interrupt. We have other loops here too and dividing by 2
712 * doesn't seem to be enough even after subtracting 350us,
713 * so we divide by 4.
714 *
715 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
716 * interrupt was detected we use the full 10ms.
717 */
718 if (smibest == 0)
719 u_sleep(10000);
720 else if (smibest < 150 * 4 + 350)
721 u_sleep(150);
722 else if ((smibest - 350) / 4 < 10000)
723 u_sleep((smibest - 350) / 4);
724 else
725 u_sleep(10000);
46d4e165 726
bb467734
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727 /*
728 * Do an INIT IPI: deassert RESET
729 *
730 * Use level triggered mode to deassert. It is unclear
731 * why we need to do this.
732 */
733 lapic->icr_lo = icr_lo | 0x00008500;
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734 while (lapic->icr_lo & APIC_DELSTAT_MASK)
735 /* spin */ ;
bb467734 736 u_sleep(150); /* wait 150us */
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737
738 /*
bb467734 739 * Next we do a STARTUP IPI: the previous INIT IPI might still be
46d4e165
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740 * latched, (P5 bug) this 1st STARTUP would then terminate
741 * immediately, and the previously started INIT IPI would continue. OR
742 * the previous INIT IPI has already run. and this STARTUP IPI will
743 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
744 * will run.
745 */
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746 lapic->icr_lo = icr_lo | 0x00000600 | vector;
747 while (lapic->icr_lo & APIC_DELSTAT_MASK)
748 /* spin */ ;
749 u_sleep(200); /* wait ~200uS */
750
751 /*
bb467734 752 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
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753 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
754 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
755 * recognized after hardware RESET or INIT IPI.
756 */
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757 lapic->icr_lo = icr_lo | 0x00000600 | vector;
758 while (lapic->icr_lo & APIC_DELSTAT_MASK)
759 /* spin */ ;
bb467734
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760
761 /* Resume normal operation */
762 cpu_enable_intr();
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763
764 /* wait for it to start, see ap_init() */
765 set_apic_timer(5000000);/* == 5 seconds */
766 while (read_apic_timer()) {
da23a592 767 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
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768 return 1; /* return SUCCESS */
769 }
bb467734 770
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771 return 0; /* return FAILURE */
772}
773
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774static
775int
776smitest(void)
777{
778 int64_t ltsc;
779 int64_t ntsc;
780 int64_t ldelta;
781 int64_t ndelta;
782 int count;
783
784 ldelta = 0;
785 ndelta = 0;
786 while (read_apic_timer()) {
787 ltsc = rdtsc();
788 for (count = 0; count < 100; ++count)
789 ntsc = rdtsc(); /* force loop to occur */
790 if (ldelta) {
791 ndelta = ntsc - ltsc;
792 if (ldelta > ndelta)
793 ldelta = ndelta;
794 if (ndelta > ldelta * 2)
795 break;
796 } else {
797 ldelta = ntsc - ltsc;
798 }
799 }
800 return(read_apic_timer());
801}
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802
803/*
7d4d6fdb
MD
804 * Synchronously flush the TLB on all other CPU's. The current cpu's
805 * TLB is not flushed. If the caller wishes to flush the current cpu's
806 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
46d4e165 807 *
7d4d6fdb
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808 * NOTE: If for some reason we were unable to start all cpus we cannot
809 * safely use broadcast IPIs.
46d4e165 810 */
7d4d6fdb
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811
812static cpumask_t smp_invltlb_req;
813
b4b1a37a
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814#define SMP_INVLTLB_DEBUG
815
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816void
817smp_invltlb(void)
818{
819#ifdef SMP
7d4d6fdb 820 struct mdglobaldata *md = mdcpu;
2d910aaf 821#ifdef SMP_INVLTLB_DEBUG
7d4d6fdb 822 long count = 0;
2d910aaf 823 long xcount = 0;
7d4d6fdb 824#endif
4117f2fd 825
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MD
826 crit_enter_gd(&md->mi);
827 md->gd_invltlb_ret = 0;
828 ++md->mi.gd_cnt.v_smpinvltlb;
da23a592 829 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2d910aaf
MD
830#ifdef SMP_INVLTLB_DEBUG
831again:
832#endif
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833 if (smp_startup_mask == smp_active_mask) {
834 all_but_self_ipi(XINVLTLB_OFFSET);
835 } else {
7d4d6fdb
MD
836 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
837 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
46d4e165 838 }
2d910aaf
MD
839
840#ifdef SMP_INVLTLB_DEBUG
841 if (xcount)
842 kprintf("smp_invltlb: ipi sent\n");
843#endif
7d4d6fdb
MD
844 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
845 (smp_active_mask & ~md->mi.gd_cpumask)) {
846 cpu_mfence();
847 cpu_pause();
2d910aaf 848#ifdef SMP_INVLTLB_DEBUG
7d4d6fdb
MD
849 /* DEBUGGING */
850 if (++count == 400000000) {
2d910aaf
MD
851 print_backtrace(-1);
852 kprintf("smp_invltlb: endless loop %08lx %08lx, "
853 "rflags %016jx retry",
7d4d6fdb 854 (long)md->gd_invltlb_ret,
2d910aaf
MD
855 (long)smp_invltlb_req,
856 (intmax_t)read_rflags());
857 __asm __volatile ("sti");
858 ++xcount;
859 if (xcount > 2)
860 lwkt_process_ipiq();
861 if (xcount > 3) {
da23a592
MD
862 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
863 ~md->mi.gd_cpumask &
864 smp_active_mask);
2d910aaf
MD
865 globaldata_t xgd;
866
867 kprintf("bcpu %d\n", bcpu);
868 xgd = globaldata_find(bcpu);
869 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
870 }
871 if (xcount > 5)
872 Debugger("giving up");
873 count = 0;
874 goto again;
7d4d6fdb 875 }
46d4e165 876#endif
7d4d6fdb 877 }
da23a592 878 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
7d4d6fdb 879 crit_exit_gd(&md->mi);
4117f2fd 880#endif
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881}
882
7d4d6fdb
MD
883#ifdef SMP
884
885/*
886 * Called from Xinvltlb assembly with interrupts disabled. We didn't
887 * bother to bump the critical section count or nested interrupt count
888 * so only do very low level operations here.
889 */
890void
891smp_invltlb_intr(void)
892{
893 struct mdglobaldata *md = mdcpu;
894 struct mdglobaldata *omd;
895 cpumask_t mask;
896 int cpu;
897
7d4d6fdb 898 cpu_mfence();
2d910aaf 899 mask = smp_invltlb_req;
7d4d6fdb
MD
900 cpu_invltlb();
901 while (mask) {
da23a592
MD
902 cpu = BSFCPUMASK(mask);
903 mask &= ~CPUMASK(cpu);
7d4d6fdb 904 omd = (struct mdglobaldata *)globaldata_find(cpu);
da23a592 905 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
7d4d6fdb
MD
906 }
907}
908
909#endif
910
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911/*
912 * When called the executing CPU will send an IPI to all other CPUs
913 * requesting that they halt execution.
914 *
915 * Usually (but not necessarily) called with 'other_cpus' as its arg.
916 *
917 * - Signals all CPUs in map to stop.
918 * - Waits for each to stop.
919 *
920 * Returns:
921 * -1: error
922 * 0: NA
923 * 1: ok
924 *
925 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
926 * from executing at same time.
927 */
928int
da23a592 929stop_cpus(cpumask_t map)
46d4e165
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930{
931 map &= smp_active_mask;
932
933 /* send the Xcpustop IPI to all CPUs in map */
934 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
935
936 while ((stopped_cpus & map) != map)
937 /* spin */ ;
938
939 return 1;
940}
941
942
943/*
944 * Called by a CPU to restart stopped CPUs.
945 *
946 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
947 *
948 * - Signals all CPUs in map to restart.
949 * - Waits for each to restart.
950 *
951 * Returns:
952 * -1: error
953 * 0: NA
954 * 1: ok
955 */
956int
da23a592 957restart_cpus(cpumask_t map)
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958{
959 /* signal other cpus to restart */
960 started_cpus = map & smp_active_mask;
961
962 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
963 /* spin */ ;
964
965 return 1;
966}
967
968/*
969 * This is called once the mpboot code has gotten us properly relocated
970 * and the MMU turned on, etc. ap_init() is actually the idle thread,
971 * and when it returns the scheduler will call the real cpu_idle() main
972 * loop for the idlethread. Interrupts are disabled on entry and should
973 * remain disabled at return.
974 */
975void
976ap_init(void)
977{
978 u_int apic_id;
979
980 /*
981 * Adjust smp_startup_mask to signal the BSP that we have started
982 * up successfully. Note that we do not yet hold the BGL. The BSP
983 * is waiting for our signal.
984 *
985 * We can't set our bit in smp_active_mask yet because we are holding
986 * interrupts physically disabled and remote cpus could deadlock
987 * trying to send us an IPI.
988 */
da23a592 989 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
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990 cpu_mfence();
991
992 /*
c6b1591c
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993 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
994 * non-zero, then get the MP lock.
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995 *
996 * Note: We are in a critical section.
997 *
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998 * Note: we are the idle thread, we can only spin.
999 *
1000 * Note: The load fence is memory volatile and prevents the compiler
c6b1591c 1001 * from improperly caching mp_finish_lapic, and the cpu from improperly
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1002 * caching it.
1003 */
c6b1591c 1004 while (mp_finish_lapic == 0)
b5d16701
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1005 cpu_lfence();
1006 while (try_mplock() == 0)
1007 ;
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1008
1009 if (cpu_feature & CPUID_TSC) {
b5d16701
MD
1010 /*
1011 * The BSP is constantly updating tsc0_offset, figure out
1012 * the relative difference to synchronize ktrdump.
1013 */
1014 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
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1015 }
1016
1017 /* BSP may have changed PTD while we're waiting for the lock */
1018 cpu_invltlb();
1019
46d4e165 1020 /* Build our map of 'other' CPUs. */
da23a592 1021 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
46d4e165 1022
46d4e165 1023 /* A quick check from sanity claus */
d53907dd 1024 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
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1025 if (mycpu->gd_cpuid != apic_id) {
1026 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
d53907dd
MD
1027 kprintf("SMP: apic_id = %d lapicid %d\n",
1028 apic_id, (lapic->id & 0xff000000) >> 24);
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1029#if JGXXX
1030 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1031#endif
1032 panic("cpuid mismatch! boom!!");
1033 }
1034
1035 /* Initialize AP's local APIC for irq's */
5ddeabb9 1036 lapic_init(FALSE);
46d4e165 1037
c6b1591c
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1038 /* LAPIC initialization is done */
1039 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1040 cpu_mfence();
1041
1042 /* Let BSP move onto the next initialization stage */
1043 rel_mplock();
1044
1045 /*
1046 * Interlock for finalization. Wait until mp_finish is non-zero,
1047 * then get the MP lock.
1048 *
1049 * Note: We are in a critical section.
1050 *
1051 * Note: we are the idle thread, we can only spin.
1052 *
1053 * Note: The load fence is memory volatile and prevents the compiler
1054 * from improperly caching mp_finish, and the cpu from improperly
1055 * caching it.
1056 */
1057 while (mp_finish == 0)
1058 cpu_lfence();
1059 while (try_mplock() == 0)
1060 ;
1061
1062 /* BSP may have changed PTD while we're waiting for the lock */
1063 cpu_invltlb();
1064
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1065 /* Set memory range attributes for this CPU to match the BSP */
1066 mem_range_AP_init();
1067
1068 /*
1069 * Once we go active we must process any IPIQ messages that may
1070 * have been queued, because no actual IPI will occur until we
1071 * set our bit in the smp_active_mask. If we don't the IPI
1072 * message interlock could be left set which would also prevent
1073 * further IPIs.
1074 *
1075 * The idle loop doesn't expect the BGL to be held and while
1076 * lwkt_switch() normally cleans things up this is a special case
1077 * because we returning almost directly into the idle loop.
1078 *
1079 * The idle thread is never placed on the runq, make sure
1080 * nothing we've done put it there.
1081 */
b5d16701 1082 KKASSERT(get_mplock_count(curthread) == 1);
da23a592 1083 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
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1084
1085 /*
1086 * Enable interrupts here. idle_restore will also do it, but
1087 * doing it here lets us clean up any strays that got posted to
1088 * the CPU during the AP boot while we are still in a critical
1089 * section.
1090 */
1091 __asm __volatile("sti; pause; pause"::);
9611ff20 1092 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
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1093
1094 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1095 lwkt_process_ipiq();
1096
1097 /*
1098 * Releasing the mp lock lets the BSP finish up the SMP init
1099 */
1100 rel_mplock();
1101 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1102}
1103
1104/*
1105 * Get SMP fully working before we start initializing devices.
1106 */
1107static
1108void
1109ap_finish(void)
1110{
1111 mp_finish = 1;
1112 if (bootverbose)
1113 kprintf("Finish MP startup\n");
46d4e165 1114 rel_mplock();
c6b1591c 1115 while (smp_active_mask != smp_startup_mask)
46d4e165 1116 cpu_lfence();
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1117 while (try_mplock() == 0)
1118 ;
da23a592
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1119 if (bootverbose) {
1120 kprintf("Active CPU Mask: %016jx\n",
1121 (uintmax_t)smp_active_mask);
1122 }
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1123}
1124
1125SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1126
1127void
1128cpu_send_ipiq(int dcpu)
1129{
da23a592 1130 if (CPUMASK(dcpu) & smp_active_mask)
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1131 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1132}
1133
1134#if 0 /* single_apic_ipi_passive() not working yet */
1135/*
1136 * Returns 0 on failure, 1 on success
1137 */
1138int
1139cpu_send_ipiq_passive(int dcpu)
1140{
1141 int r = 0;
da23a592 1142 if (CPUMASK(dcpu) & smp_active_mask) {
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1143 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1144 APIC_DELMODE_FIXED);
1145 }
1146 return(r);
1147}
1148#endif