2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/mpapic.h>
60 #include <machine/psl.h>
61 #include <machine/segments.h>
62 #include <machine/tss.h>
63 #include <machine/specialreg.h>
64 #include <machine/globaldata.h>
65 #include <machine/pmap_inval.h>
67 #include <machine/md_var.h> /* setidt() */
68 #include <machine_base/icu/icu.h> /* IPIs */
69 #include <machine/intr_machdep.h> /* IPIs */
71 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_long cpu_signature;
130 u_long feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 #define MPTABLE_POS_USE_DEFAULT(mpt) \
173 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
177 int mb_type; /* MPTABLE_BUS_ */
178 TAILQ_ENTRY(mptable_bus) mb_link;
181 #define MPTABLE_BUS_ISA 0
182 #define MPTABLE_BUS_PCI 1
184 struct mptable_bus_info {
185 TAILQ_HEAD(, mptable_bus) mbi_list;
188 struct mptable_pci_int {
195 TAILQ_ENTRY(mptable_pci_int) mpci_link;
198 struct mptable_ioapic {
202 TAILQ_ENTRY(mptable_ioapic) mio_link;
205 typedef int (*mptable_iter_func)(void *, const void *, int);
208 * this code MUST be enabled here and in mpboot.s.
209 * it follows the very early stages of AP boot by placing values in CMOS ram.
210 * it NORMALLY will never be needed and thus the primitive method for enabling.
213 #if defined(CHECK_POINTS)
214 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
215 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
217 #define CHECK_INIT(D); \
218 CHECK_WRITE(0x34, (D)); \
219 CHECK_WRITE(0x35, (D)); \
220 CHECK_WRITE(0x36, (D)); \
221 CHECK_WRITE(0x37, (D)); \
222 CHECK_WRITE(0x38, (D)); \
223 CHECK_WRITE(0x39, (D));
225 #define CHECK_PRINT(S); \
226 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
235 #else /* CHECK_POINTS */
237 #define CHECK_INIT(D)
238 #define CHECK_PRINT(S)
240 #endif /* CHECK_POINTS */
243 * Values to send to the POST hardware.
245 #define MP_BOOTADDRESS_POST 0x10
246 #define MP_PROBE_POST 0x11
247 #define MPTABLE_PASS1_POST 0x12
249 #define MP_START_POST 0x13
250 #define MP_ENABLE_POST 0x14
251 #define MPTABLE_PASS2_POST 0x15
253 #define START_ALL_APS_POST 0x16
254 #define INSTALL_AP_TRAMP_POST 0x17
255 #define START_AP_POST 0x18
257 #define MP_ANNOUNCE_POST 0x19
259 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
260 int current_postcode;
262 /** XXX FIXME: what system files declare these??? */
263 extern struct region_descriptor r_gdt, r_idt;
265 int mp_naps; /* # of Applications processors */
266 #ifdef SMP /* APIC-IO */
267 static int mp_nbusses; /* # of busses */
268 int mp_napics; /* # of IO APICs */
269 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
270 u_int32_t *io_apic_versions;
274 u_int32_t cpu_apic_versions[MAXCPU];
276 extern int64_t tsc_offsets[];
278 extern u_long ebda_addr;
280 #ifdef SMP /* APIC-IO */
281 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
285 * APIC ID logical/physical mapping structures.
286 * We oversize these to simplify boot-time config.
288 int cpu_num_to_apic_id[NAPICID];
289 #ifdef SMP /* APIC-IO */
290 int io_num_to_apic_id[NAPICID];
292 int apic_id_to_logical[NAPICID];
294 /* AP uses this during bootstrap. Do not staticize. */
298 /* Hotwire a 0->4MB V==P mapping */
299 extern pt_entry_t *KPTphys;
302 * SMP page table page. Setup by locore to point to a page table
303 * page from which we allocate per-cpu privatespace areas io_apics,
307 #define IO_MAPPING_START_INDEX \
308 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
310 extern pt_entry_t *SMPpt;
311 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
313 struct pcb stoppcbs[MAXCPU];
315 static basetable_entry basetable_entry_types[] =
317 {0, 20, "Processor"},
325 * Local data and functions.
328 static u_int boot_address;
329 static u_int base_memory;
330 static int mp_finish;
332 static void mp_enable(u_int boot_addr);
334 static int mptable_iterate_entries(const mpcth_t,
335 mptable_iter_func, void *);
336 static int mptable_search(void);
337 static int mptable_search_sig(u_int32_t target, int count);
338 static int mptable_hyperthread_fixup(cpumask_t, int);
339 #ifdef SMP /* APIC-IO */
340 static void mptable_pass1(struct mptable_pos *);
341 static void mptable_pass2(struct mptable_pos *);
342 static void mptable_default(int type);
343 static void mptable_fix(void);
345 static int mptable_map(struct mptable_pos *);
346 static void mptable_unmap(struct mptable_pos *);
347 static void mptable_imcr(struct mptable_pos *);
348 static void mptable_bus_info_alloc(const mpcth_t,
349 struct mptable_bus_info *);
350 static void mptable_bus_info_free(struct mptable_bus_info *);
352 static int mptable_lapic_probe(struct lapic_enumerator *);
353 static void mptable_lapic_enumerate(struct lapic_enumerator *);
354 static void mptable_lapic_default(void);
356 static int mptable_ioapic_probe(struct ioapic_enumerator *);
357 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
359 #ifdef SMP /* APIC-IO */
360 static void setup_apic_irq_mapping(void);
361 static int apic_int_is_bus_type(int intr, int bus_type);
363 static int start_all_aps(u_int boot_addr);
364 static void install_ap_tramp(u_int boot_addr);
365 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
366 static int smitest(void);
368 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
369 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
370 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
372 static vm_paddr_t mptable_fps_phyaddr;
373 static int mptable_use_default;
374 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
375 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
376 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
377 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
380 * Calculate usable address in base memory for AP trampoline code.
383 mp_bootaddress(u_int basemem)
385 POSTCODE(MP_BOOTADDRESS_POST);
387 base_memory = basemem;
389 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
390 if ((base_memory - boot_address) < bootMP_size)
391 boot_address -= 4096; /* not enough, lower by 4k */
400 struct mptable_pos mpt;
403 KKASSERT(mptable_fps_phyaddr == 0);
405 mptable_fps_phyaddr = mptable_search();
406 if (mptable_fps_phyaddr == 0)
409 error = mptable_map(&mpt);
411 mptable_fps_phyaddr = 0;
415 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
416 kprintf("MPTABLE: use default configuration\n");
417 mptable_use_default = 1;
422 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
425 * Look for an Intel MP spec table (ie, SMP capable hardware).
434 * Make sure our SMPpt[] page table is big enough to hold all the
437 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
439 POSTCODE(MP_PROBE_POST);
441 /* see if EBDA exists */
442 if (ebda_addr != 0) {
443 /* search first 1K of EBDA */
444 target = (u_int32_t)ebda_addr;
445 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
448 /* last 1K of base memory, effective 'top of base' passed in */
449 target = (u_int32_t)(base_memory - 0x400);
450 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
454 /* search the BIOS */
455 target = (u_int32_t)BIOS_BASE;
456 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
459 /* search the extended BIOS */
460 target = (u_int32_t)BIOS_BASE2;
461 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
469 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
471 int count, total_size;
472 const void *position;
474 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
475 total_size = cth->base_table_length - sizeof(struct MPCTH);
476 position = (const uint8_t *)cth + sizeof(struct MPCTH);
477 count = cth->entry_count;
482 KKASSERT(total_size >= 0);
483 if (total_size == 0) {
484 kprintf("invalid base MP table, "
485 "entry count and length mismatch\n");
489 type = *(const uint8_t *)position;
491 case 0: /* processor_entry */
492 case 1: /* bus_entry */
493 case 2: /* io_apic_entry */
494 case 3: /* int_entry */
495 case 4: /* int_entry */
498 kprintf("unknown base MP table entry type %d\n", type);
502 if (total_size < basetable_entry_types[type].length) {
503 kprintf("invalid base MP table length, "
504 "does not contain all entries\n");
507 total_size -= basetable_entry_types[type].length;
509 error = func(arg, position, type);
513 position = (const uint8_t *)position +
514 basetable_entry_types[type].length;
521 * Startup the SMP processors.
526 POSTCODE(MP_START_POST);
527 mp_enable(boot_address);
532 * Print various information about the SMP system hardware and setup.
539 POSTCODE(MP_ANNOUNCE_POST);
541 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
542 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
543 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
544 for (x = 1; x <= mp_naps; ++x) {
545 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
546 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
549 if (apic_io_enable) {
550 for (x = 0; x < mp_napics; ++x) {
551 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
552 kprintf(", version: 0x%08x", io_apic_versions[x]);
553 kprintf(", at 0x%08lx\n", io_apic_address[x]);
556 kprintf(" Warning: APIC I/O disabled\n");
561 * AP cpu's call this to sync up protected mode.
563 * WARNING! We must ensure that the cpu is sufficiently initialized to
564 * be able to use to the FP for our optimized bzero/bcopy code before
565 * we enter more mainstream C code.
567 * WARNING! %fs is not set up on entry. This routine sets up %fs.
573 int x, myid = bootAP;
575 struct mdglobaldata *md;
576 struct privatespace *ps;
578 ps = &CPU_prvspace[myid];
580 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
581 gdt_segs[GPROC0_SEL].ssd_base =
582 (int) &ps->mdglobaldata.gd_common_tss;
583 ps->mdglobaldata.mi.gd_prvspace = ps;
585 for (x = 0; x < NGDT; x++) {
586 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
589 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
590 r_gdt.rd_base = (int) &gdt[myid * NGDT];
591 lgdt(&r_gdt); /* does magic intra-segment return */
596 mdcpu->gd_currentldt = _default_ldt;
598 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
599 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
601 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
603 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
604 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
605 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
606 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
607 md->gd_common_tssd = *md->gd_tss_gdt;
611 * Set to a known state:
612 * Set by mpboot.s: CR0_PG, CR0_PE
613 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
616 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
618 pmap_set_opt(); /* PSE/4MB pages, etc */
620 /* set up CPU registers and state */
623 /* set up FPU state on the AP */
624 npxinit(__INITIAL_NPXCW__);
626 /* set up SSE registers */
630 /*******************************************************************
631 * local functions and data
635 * start the SMP system
638 mp_enable(u_int boot_addr)
642 struct mptable_pos mpt;
644 POSTCODE(MP_ENABLE_POST);
651 if (mptable_fps_phyaddr) {
656 if (apic_io_enable) {
658 if (!mptable_fps_phyaddr)
659 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
664 * Examine the MP table for needed info
671 /* Post scan cleanup */
674 setup_apic_irq_mapping();
676 /* fill the LOGICAL io_apic_versions table */
677 for (apic = 0; apic < mp_napics; ++apic) {
678 ux = ioapic_read(ioapic[apic], IOAPIC_VER);
679 io_apic_versions[apic] = ux;
680 io_apic_set_id(apic, IO_TO_ID(apic));
683 /* program each IO APIC in the system */
684 for (apic = 0; apic < mp_napics; ++apic)
685 if (io_apic_setup(apic) < 0)
686 panic("IO APIC setup failure");
691 * These are required for SMP operation
694 /* install a 'Spurious INTerrupt' vector */
695 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
696 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
698 /* install an inter-CPU IPI for TLB invalidation */
699 setidt(XINVLTLB_OFFSET, Xinvltlb,
700 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
702 /* install an inter-CPU IPI for IPIQ messaging */
703 setidt(XIPIQ_OFFSET, Xipiq,
704 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
706 /* install a timer vector */
707 setidt(XTIMER_OFFSET, Xtimer,
708 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
710 /* install an inter-CPU IPI for CPU stop/restart */
711 setidt(XCPUSTOP_OFFSET, Xcpustop,
712 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
714 /* start each Application Processor */
715 start_all_aps(boot_addr);
720 * look for the MP spec signature
723 /* string defined by the Intel MP Spec as identifying the MP table */
724 #define MP_SIG 0x5f504d5f /* _MP_ */
725 #define NEXT(X) ((X) += 4)
727 mptable_search_sig(u_int32_t target, int count)
733 KKASSERT(target != 0);
735 map_size = count * sizeof(u_int32_t);
736 addr = pmap_mapdev((vm_paddr_t)target, map_size);
739 for (x = 0; x < count; NEXT(x)) {
740 if (addr[x] == MP_SIG) {
741 /* make array index a byte index */
742 ret = target + (x * sizeof(u_int32_t));
747 pmap_unmapdev((vm_offset_t)addr, map_size);
752 typedef struct BUSDATA {
754 enum busTypes bus_type;
757 typedef struct INTDATA {
767 typedef struct BUSTYPENAME {
772 static bus_type_name bus_type_table[] =
778 {UNKNOWN_BUSTYPE, "---"},
781 {UNKNOWN_BUSTYPE, "---"},
782 {UNKNOWN_BUSTYPE, "---"},
783 {UNKNOWN_BUSTYPE, "---"},
784 {UNKNOWN_BUSTYPE, "---"},
785 {UNKNOWN_BUSTYPE, "---"},
787 {UNKNOWN_BUSTYPE, "---"},
788 {UNKNOWN_BUSTYPE, "---"},
789 {UNKNOWN_BUSTYPE, "---"},
790 {UNKNOWN_BUSTYPE, "---"},
792 {UNKNOWN_BUSTYPE, "---"}
794 /* from MP spec v1.4, table 5-1 */
795 static int default_data[7][5] =
797 /* nbus, id0, type0, id1, type1 */
798 {1, 0, ISA, 255, 255},
799 {1, 0, EISA, 255, 255},
800 {1, 0, EISA, 255, 255},
801 {1, 0, MCA, 255, 255},
803 {2, 0, EISA, 1, PCI},
809 static bus_datum *bus_data;
811 /* the IO INT data, one entry per possible APIC INTerrupt */
812 static io_int *io_apic_ints;
815 static int processor_entry (const struct PROCENTRY *entry, int cpu);
816 static int bus_entry (const struct BUSENTRY *entry, int bus);
817 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
818 static int int_entry (const struct INTENTRY *entry, int intr);
819 static int lookup_bus_type (char *name);
822 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
824 const struct IOAPICENTRY *ioapic_ent;
827 case 1: /* bus_entry */
831 case 2: /* io_apic_entry */
833 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
834 io_apic_address[mp_napics++] =
835 (vm_offset_t)ioapic_ent->apic_address;
839 case 3: /* int_entry */
847 * 1st pass on motherboard's Intel MP specification table.
856 mptable_pass1(struct mptable_pos *mpt)
861 POSTCODE(MPTABLE_PASS1_POST);
864 KKASSERT(fps != NULL);
866 /* clear various tables */
867 for (x = 0; x < NAPICID; ++x)
868 io_apic_address[x] = ~0; /* IO APIC address table */
874 /* check for use of 'default' configuration */
875 if (fps->mpfb1 != 0) {
876 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
877 mp_nbusses = default_data[fps->mpfb1 - 1][0];
883 error = mptable_iterate_entries(mpt->mp_cth,
884 mptable_ioapic_pass1_callback, NULL);
886 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
890 struct mptable_ioapic2_cbarg {
897 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
899 struct mptable_ioapic2_cbarg *arg = xarg;
903 if (bus_entry(pos, arg->bus))
908 if (io_apic_entry(pos, arg->apic))
913 if (int_entry(pos, arg->intr))
921 * 2nd pass on motherboard's Intel MP specification table.
924 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
925 * IO_TO_ID(N), logical IO to APIC ID table
930 mptable_pass2(struct mptable_pos *mpt)
932 struct mptable_ioapic2_cbarg arg;
936 POSTCODE(MPTABLE_PASS2_POST);
939 KKASSERT(fps != NULL);
941 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
943 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
944 M_DEVBUF, M_WAITOK | M_ZERO);
945 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
947 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
950 for (x = 0; x < mp_napics; x++)
951 ioapic[x] = ioapic_map(io_apic_address[x]);
953 /* clear various tables */
954 for (x = 0; x < NAPICID; ++x) {
955 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
956 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
959 /* clear bus data table */
960 for (x = 0; x < mp_nbusses; ++x)
961 bus_data[x].bus_id = 0xff;
963 /* clear IO APIC INT table */
964 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
965 io_apic_ints[x].int_type = 0xff;
966 io_apic_ints[x].int_vector = 0xff;
969 /* check for use of 'default' configuration */
970 if (fps->mpfb1 != 0) {
971 mptable_default(fps->mpfb1);
975 bzero(&arg, sizeof(arg));
976 error = mptable_iterate_entries(mpt->mp_cth,
977 mptable_ioapic_pass2_callback, &arg);
979 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
983 * Check if we should perform a hyperthreading "fix-up" to
984 * enumerate any logical CPU's that aren't already listed
987 * XXX: We assume that all of the physical CPUs in the
988 * system have the same number of logical CPUs.
990 * XXX: We assume that APIC ID's are allocated such that
991 * the APIC ID's for a physical processor are aligned
992 * with the number of logical CPU's in the processor.
995 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
997 int i, id, lcpus_max, logical_cpus;
999 if ((cpu_feature & CPUID_HTT) == 0)
1002 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1006 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
1008 * INSTRUCTION SET REFERENCE, A-M (#253666)
1009 * Page 3-181, Table 3-20
1010 * "The nearest power-of-2 integer that is not smaller
1011 * than EBX[23:16] is the number of unique initial APIC
1012 * IDs reserved for addressing different logical
1013 * processors in a physical package."
1015 for (i = 0; ; ++i) {
1016 if ((1 << i) >= lcpus_max) {
1023 KKASSERT(cpu_count != 0);
1024 if (cpu_count == lcpus_max) {
1025 /* We have nothing to fix */
1027 } else if (cpu_count == 1) {
1028 /* XXX this may be incorrect */
1029 logical_cpus = lcpus_max;
1031 int cur, prev, dist;
1034 * Calculate the distances between two nearest
1035 * APIC IDs. If all such distances are same,
1036 * then it is the number of missing cpus that
1037 * we are going to fill later.
1039 dist = cur = prev = -1;
1040 for (id = 0; id < MAXCPU; ++id) {
1041 if ((id_mask & CPUMASK(id)) == 0)
1046 int new_dist = cur - prev;
1052 * Make sure that all distances
1053 * between two nearest APIC IDs
1056 if (dist != new_dist)
1064 /* Must be power of 2 */
1065 if (dist & (dist - 1))
1068 /* Can't exceed CPU package capacity */
1069 if (dist > lcpus_max)
1070 logical_cpus = lcpus_max;
1072 logical_cpus = dist;
1076 * For each APIC ID of a CPU that is set in the mask,
1077 * scan the other candidate APIC ID's for this
1078 * physical processor. If any of those ID's are
1079 * already in the table, then kill the fixup.
1081 for (id = 0; id < MAXCPU; id++) {
1082 if ((id_mask & CPUMASK(id)) == 0)
1084 /* First, make sure we are on a logical_cpus boundary. */
1085 if (id % logical_cpus != 0)
1087 for (i = id + 1; i < id + logical_cpus; i++)
1088 if ((id_mask & CPUMASK(i)) != 0)
1091 return logical_cpus;
1095 mptable_map(struct mptable_pos *mpt)
1099 vm_size_t cth_mapsz = 0;
1101 KKASSERT(mptable_fps_phyaddr != 0);
1103 bzero(mpt, sizeof(*mpt));
1105 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
1106 if (fps->pap != 0) {
1108 * Map configuration table header to get
1109 * the base table size
1111 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1112 cth_mapsz = cth->base_table_length;
1113 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1115 if (cth_mapsz < sizeof(*cth)) {
1116 kprintf("invalid base MP table length %d\n",
1118 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1123 * Map the base table
1125 cth = pmap_mapdev(fps->pap, cth_mapsz);
1130 mpt->mp_cth_mapsz = cth_mapsz;
1136 mptable_unmap(struct mptable_pos *mpt)
1138 if (mpt->mp_cth != NULL) {
1139 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1141 mpt->mp_cth_mapsz = 0;
1143 if (mpt->mp_fps != NULL) {
1144 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1150 assign_apic_irq(int apic, int intpin, int irq)
1154 if (int_to_apicintpin[irq].ioapic != -1)
1155 panic("assign_apic_irq: inconsistent table");
1157 int_to_apicintpin[irq].ioapic = apic;
1158 int_to_apicintpin[irq].int_pin = intpin;
1159 int_to_apicintpin[irq].apic_address = ioapic[apic];
1160 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1162 for (x = 0; x < nintrs; x++) {
1163 if ((io_apic_ints[x].int_type == 0 ||
1164 io_apic_ints[x].int_type == 3) &&
1165 io_apic_ints[x].int_vector == 0xff &&
1166 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1167 io_apic_ints[x].dst_apic_int == intpin)
1168 io_apic_ints[x].int_vector = irq;
1173 revoke_apic_irq(int irq)
1179 if (int_to_apicintpin[irq].ioapic == -1)
1180 panic("revoke_apic_irq: inconsistent table");
1182 oldapic = int_to_apicintpin[irq].ioapic;
1183 oldintpin = int_to_apicintpin[irq].int_pin;
1185 int_to_apicintpin[irq].ioapic = -1;
1186 int_to_apicintpin[irq].int_pin = 0;
1187 int_to_apicintpin[irq].apic_address = NULL;
1188 int_to_apicintpin[irq].redirindex = 0;
1190 for (x = 0; x < nintrs; x++) {
1191 if ((io_apic_ints[x].int_type == 0 ||
1192 io_apic_ints[x].int_type == 3) &&
1193 io_apic_ints[x].int_vector != 0xff &&
1194 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1195 io_apic_ints[x].dst_apic_int == oldintpin)
1196 io_apic_ints[x].int_vector = 0xff;
1204 allocate_apic_irq(int intr)
1210 if (io_apic_ints[intr].int_vector != 0xff)
1211 return; /* Interrupt handler already assigned */
1213 if (io_apic_ints[intr].int_type != 0 &&
1214 (io_apic_ints[intr].int_type != 3 ||
1215 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1216 io_apic_ints[intr].dst_apic_int == 0)))
1217 return; /* Not INT or ExtInt on != (0, 0) */
1220 while (irq < APIC_INTMAPSIZE &&
1221 int_to_apicintpin[irq].ioapic != -1)
1224 if (irq >= APIC_INTMAPSIZE)
1225 return; /* No free interrupt handlers */
1227 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1228 intpin = io_apic_ints[intr].dst_apic_int;
1230 assign_apic_irq(apic, intpin, irq);
1235 swap_apic_id(int apic, int oldid, int newid)
1242 return; /* Nothing to do */
1244 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1245 apic, oldid, newid);
1247 /* Swap physical APIC IDs in interrupt entries */
1248 for (x = 0; x < nintrs; x++) {
1249 if (io_apic_ints[x].dst_apic_id == oldid)
1250 io_apic_ints[x].dst_apic_id = newid;
1251 else if (io_apic_ints[x].dst_apic_id == newid)
1252 io_apic_ints[x].dst_apic_id = oldid;
1255 /* Swap physical APIC IDs in IO_TO_ID mappings */
1256 for (oapic = 0; oapic < mp_napics; oapic++)
1257 if (IO_TO_ID(oapic) == newid)
1260 if (oapic < mp_napics) {
1261 kprintf("Changing APIC ID for IO APIC #%d from "
1262 "%d to %d in MP table\n",
1263 oapic, newid, oldid);
1264 IO_TO_ID(oapic) = oldid;
1266 IO_TO_ID(apic) = newid;
1271 fix_id_to_io_mapping(void)
1275 for (x = 0; x < NAPICID; x++)
1278 for (x = 0; x <= mp_naps; x++)
1279 if (CPU_TO_ID(x) < NAPICID)
1280 ID_TO_IO(CPU_TO_ID(x)) = x;
1282 for (x = 0; x < mp_napics; x++)
1283 if (IO_TO_ID(x) < NAPICID)
1284 ID_TO_IO(IO_TO_ID(x)) = x;
1289 first_free_apic_id(void)
1293 for (freeid = 0; freeid < NAPICID; freeid++) {
1294 for (x = 0; x <= mp_naps; x++)
1295 if (CPU_TO_ID(x) == freeid)
1299 for (x = 0; x < mp_napics; x++)
1300 if (IO_TO_ID(x) == freeid)
1311 io_apic_id_acceptable(int apic, int id)
1313 int cpu; /* Logical CPU number */
1314 int oapic; /* Logical IO APIC number for other IO APIC */
1317 return 0; /* Out of range */
1319 for (cpu = 0; cpu <= mp_naps; cpu++)
1320 if (CPU_TO_ID(cpu) == id)
1321 return 0; /* Conflict with CPU */
1323 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1324 if (IO_TO_ID(oapic) == id)
1325 return 0; /* Conflict with other APIC */
1327 return 1; /* ID is acceptable for IO APIC */
1332 io_apic_find_int_entry(int apic, int pin)
1336 /* search each of the possible INTerrupt sources */
1337 for (x = 0; x < nintrs; ++x) {
1338 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1339 (pin == io_apic_ints[x].dst_apic_int))
1340 return (&io_apic_ints[x]);
1346 * parse an Intel MP specification table
1353 int apic; /* IO APIC unit number */
1354 int freeid; /* Free physical APIC ID */
1355 int physid; /* Current physical IO APIC ID */
1357 int bus_0 = 0; /* Stop GCC warning */
1358 int bus_pci = 0; /* Stop GCC warning */
1362 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1363 * did it wrong. The MP spec says that when more than 1 PCI bus
1364 * exists the BIOS must begin with bus entries for the PCI bus and use
1365 * actual PCI bus numbering. This implies that when only 1 PCI bus
1366 * exists the BIOS can choose to ignore this ordering, and indeed many
1367 * MP motherboards do ignore it. This causes a problem when the PCI
1368 * sub-system makes requests of the MP sub-system based on PCI bus
1369 * numbers. So here we look for the situation and renumber the
1370 * busses and associated INTs in an effort to "make it right".
1373 /* find bus 0, PCI bus, count the number of PCI busses */
1374 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1375 if (bus_data[x].bus_id == 0) {
1378 if (bus_data[x].bus_type == PCI) {
1384 * bus_0 == slot of bus with ID of 0
1385 * bus_pci == slot of last PCI bus encountered
1388 /* check the 1 PCI bus case for sanity */
1389 /* if it is number 0 all is well */
1390 if (num_pci_bus == 1 &&
1391 bus_data[bus_pci].bus_id != 0) {
1393 /* mis-numbered, swap with whichever bus uses slot 0 */
1395 /* swap the bus entry types */
1396 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1397 bus_data[bus_0].bus_type = PCI;
1399 /* swap each relavant INTerrupt entry */
1400 id = bus_data[bus_pci].bus_id;
1401 for (x = 0; x < nintrs; ++x) {
1402 if (io_apic_ints[x].src_bus_id == id) {
1403 io_apic_ints[x].src_bus_id = 0;
1405 else if (io_apic_ints[x].src_bus_id == 0) {
1406 io_apic_ints[x].src_bus_id = id;
1411 /* Assign IO APIC IDs.
1413 * First try the existing ID. If a conflict is detected, try
1414 * the ID in the MP table. If a conflict is still detected, find
1417 * We cannot use the ID_TO_IO table before all conflicts has been
1418 * resolved and the table has been corrected.
1420 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1422 /* First try to use the value set by the BIOS */
1423 physid = io_apic_get_id(apic);
1424 if (io_apic_id_acceptable(apic, physid)) {
1425 if (IO_TO_ID(apic) != physid)
1426 swap_apic_id(apic, IO_TO_ID(apic), physid);
1430 /* Then check if the value in the MP table is acceptable */
1431 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1434 /* Last resort, find a free APIC ID and use it */
1435 freeid = first_free_apic_id();
1436 if (freeid >= NAPICID)
1437 panic("No free physical APIC IDs found");
1439 if (io_apic_id_acceptable(apic, freeid)) {
1440 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1443 panic("Free physical APIC ID not usable");
1445 fix_id_to_io_mapping();
1447 /* detect and fix broken Compaq MP table */
1448 if (apic_int_type(0, 0) == -1) {
1449 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1450 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1451 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1452 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1453 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1454 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1456 } else if (apic_int_type(0, 0) == 0) {
1457 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1458 for (x = 0; x < nintrs; ++x)
1459 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1460 (0 == io_apic_ints[x].dst_apic_int)) {
1461 io_apic_ints[x].int_type = 3;
1462 io_apic_ints[x].int_vector = 0xff;
1468 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1469 * controllers universally come in pairs. If IRQ 14 is specified
1470 * as an ISA interrupt, then IRQ 15 had better be too.
1472 * [ Shuttle XPC / AMD Athlon X2 ]
1473 * The MPTable is missing an entry for IRQ 15. Note that the
1474 * ACPI table has an entry for both 14 and 15.
1476 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1477 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1478 io14 = io_apic_find_int_entry(0, 14);
1479 io_apic_ints[nintrs] = *io14;
1480 io_apic_ints[nintrs].src_bus_irq = 15;
1481 io_apic_ints[nintrs].dst_apic_int = 15;
1486 /* Assign low level interrupt handlers */
1488 setup_apic_irq_mapping(void)
1494 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1495 int_to_apicintpin[x].ioapic = -1;
1496 int_to_apicintpin[x].int_pin = 0;
1497 int_to_apicintpin[x].apic_address = NULL;
1498 int_to_apicintpin[x].redirindex = 0;
1500 /* Default to masked */
1501 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1504 /* First assign ISA/EISA interrupts */
1505 for (x = 0; x < nintrs; x++) {
1506 int_vector = io_apic_ints[x].src_bus_irq;
1507 if (int_vector < APIC_INTMAPSIZE &&
1508 io_apic_ints[x].int_vector == 0xff &&
1509 int_to_apicintpin[int_vector].ioapic == -1 &&
1510 (apic_int_is_bus_type(x, ISA) ||
1511 apic_int_is_bus_type(x, EISA)) &&
1512 io_apic_ints[x].int_type == 0) {
1513 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1514 io_apic_ints[x].dst_apic_int,
1519 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1520 for (x = 0; x < nintrs; x++) {
1521 if (io_apic_ints[x].dst_apic_int == 0 &&
1522 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1523 io_apic_ints[x].int_vector == 0xff &&
1524 int_to_apicintpin[0].ioapic == -1 &&
1525 io_apic_ints[x].int_type == 3) {
1526 assign_apic_irq(0, 0, 0);
1531 /* Assign PCI interrupts */
1532 for (x = 0; x < nintrs; ++x) {
1533 if (io_apic_ints[x].int_type == 0 &&
1534 io_apic_ints[x].int_vector == 0xff &&
1535 apic_int_is_bus_type(x, PCI))
1536 allocate_apic_irq(x);
1541 mp_set_cpuids(int cpu_id, int apic_id)
1543 CPU_TO_ID(cpu_id) = apic_id;
1544 ID_TO_CPU(apic_id) = cpu_id;
1546 if (apic_id > lapic_id_max)
1547 lapic_id_max = apic_id;
1551 processor_entry(const struct PROCENTRY *entry, int cpu)
1555 /* check for usability */
1556 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1559 /* check for BSP flag */
1560 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1561 mp_set_cpuids(0, entry->apic_id);
1562 return 0; /* its already been counted */
1565 /* add another AP to list, if less than max number of CPUs */
1566 else if (cpu < MAXCPU) {
1567 mp_set_cpuids(cpu, entry->apic_id);
1575 bus_entry(const struct BUSENTRY *entry, int bus)
1580 /* encode the name into an index */
1581 for (x = 0; x < 6; ++x) {
1582 if ((c = entry->bus_type[x]) == ' ')
1588 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1589 panic("unknown bus type: '%s'", name);
1591 bus_data[bus].bus_id = entry->bus_id;
1592 bus_data[bus].bus_type = x;
1598 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1600 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1603 IO_TO_ID(apic) = entry->apic_id;
1604 ID_TO_IO(entry->apic_id) = apic;
1610 lookup_bus_type(char *name)
1614 for (x = 0; x < MAX_BUSTYPE; ++x)
1615 if (strcmp(bus_type_table[x].name, name) == 0)
1616 return bus_type_table[x].type;
1618 return UNKNOWN_BUSTYPE;
1622 int_entry(const struct INTENTRY *entry, int intr)
1626 io_apic_ints[intr].int_type = entry->int_type;
1627 io_apic_ints[intr].int_flags = entry->int_flags;
1628 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1629 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1630 if (entry->dst_apic_id == 255) {
1631 /* This signal goes to all IO APICS. Select an IO APIC
1632 with sufficient number of interrupt pins */
1633 for (apic = 0; apic < mp_napics; apic++)
1634 if (((ioapic_read(ioapic[apic], IOAPIC_VER) &
1635 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1636 entry->dst_apic_int)
1638 if (apic < mp_napics)
1639 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1641 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1643 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1644 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1650 apic_int_is_bus_type(int intr, int bus_type)
1654 for (bus = 0; bus < mp_nbusses; ++bus)
1655 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1656 && ((int) bus_data[bus].bus_type == bus_type))
1663 * Given a traditional ISA INT mask, return an APIC mask.
1666 isa_apic_mask(u_int isa_mask)
1671 #if defined(SKIP_IRQ15_REDIRECT)
1672 if (isa_mask == (1 << 15)) {
1673 kprintf("skipping ISA IRQ15 redirect\n");
1676 #endif /* SKIP_IRQ15_REDIRECT */
1678 isa_irq = ffs(isa_mask); /* find its bit position */
1679 if (isa_irq == 0) /* doesn't exist */
1681 --isa_irq; /* make it zero based */
1683 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1687 return (1 << apic_pin); /* convert pin# to a mask */
1691 * Determine which APIC pin an ISA/EISA INT is attached to.
1693 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1694 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1695 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1696 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1698 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1700 isa_apic_irq(int isa_irq)
1704 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1705 if (INTTYPE(intr) == 0) { /* standard INT */
1706 if (SRCBUSIRQ(intr) == isa_irq) {
1707 if (apic_int_is_bus_type(intr, ISA) ||
1708 apic_int_is_bus_type(intr, EISA)) {
1709 if (INTIRQ(intr) == 0xff)
1710 return -1; /* unassigned */
1711 return INTIRQ(intr); /* found */
1716 return -1; /* NOT found */
1721 * Determine which APIC pin a PCI INT is attached to.
1723 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1724 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1725 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1727 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1731 --pciInt; /* zero based */
1733 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1734 if ((INTTYPE(intr) == 0) /* standard INT */
1735 && (SRCBUSID(intr) == pciBus)
1736 && (SRCBUSDEVICE(intr) == pciDevice)
1737 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1738 if (apic_int_is_bus_type(intr, PCI)) {
1739 if (INTIRQ(intr) == 0xff) {
1740 kprintf("IOAPIC: pci_apic_irq() "
1742 return -1; /* unassigned */
1744 return INTIRQ(intr); /* exact match */
1749 return -1; /* NOT found */
1753 next_apic_irq(int irq)
1760 for (intr = 0; intr < nintrs; intr++) {
1761 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1763 bus = SRCBUSID(intr);
1764 bustype = apic_bus_type(bus);
1765 if (bustype != ISA &&
1771 if (intr >= nintrs) {
1774 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1775 if (INTTYPE(ointr) != 0)
1777 if (bus != SRCBUSID(ointr))
1779 if (bustype == PCI) {
1780 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1782 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1785 if (bustype == ISA || bustype == EISA) {
1786 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1789 if (INTPIN(intr) == INTPIN(ointr))
1793 if (ointr >= nintrs) {
1796 return INTIRQ(ointr);
1809 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1812 * Exactly what this means is unclear at this point. It is a solution
1813 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1814 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1815 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1819 undirect_isa_irq(int rirq)
1823 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1824 /** FIXME: tickle the MB redirector chip */
1828 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1835 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1838 undirect_pci_irq(int rirq)
1842 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1844 /** FIXME: tickle the MB redirector chip */
1848 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1856 * given a bus ID, return:
1857 * the bus type if found
1861 apic_bus_type(int id)
1865 for (x = 0; x < mp_nbusses; ++x)
1866 if (bus_data[x].bus_id == id)
1867 return bus_data[x].bus_type;
1873 * given a LOGICAL APIC# and pin#, return:
1874 * the associated src bus ID if found
1878 apic_src_bus_id(int apic, int pin)
1882 /* search each of the possible INTerrupt sources */
1883 for (x = 0; x < nintrs; ++x)
1884 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1885 (pin == io_apic_ints[x].dst_apic_int))
1886 return (io_apic_ints[x].src_bus_id);
1888 return -1; /* NOT found */
1892 * given a LOGICAL APIC# and pin#, return:
1893 * the associated src bus IRQ if found
1897 apic_src_bus_irq(int apic, int pin)
1901 for (x = 0; x < nintrs; x++)
1902 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1903 (pin == io_apic_ints[x].dst_apic_int))
1904 return (io_apic_ints[x].src_bus_irq);
1906 return -1; /* NOT found */
1911 * given a LOGICAL APIC# and pin#, return:
1912 * the associated INTerrupt type if found
1916 apic_int_type(int apic, int pin)
1920 /* search each of the possible INTerrupt sources */
1921 for (x = 0; x < nintrs; ++x) {
1922 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1923 (pin == io_apic_ints[x].dst_apic_int))
1924 return (io_apic_ints[x].int_type);
1926 return -1; /* NOT found */
1930 * Return the IRQ associated with an APIC pin
1933 apic_irq(int apic, int pin)
1938 for (x = 0; x < nintrs; ++x) {
1939 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1940 (pin == io_apic_ints[x].dst_apic_int)) {
1941 res = io_apic_ints[x].int_vector;
1944 if (apic != int_to_apicintpin[res].ioapic)
1945 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1946 if (pin != int_to_apicintpin[res].int_pin)
1947 panic("apic_irq inconsistent table (2)");
1956 * given a LOGICAL APIC# and pin#, return:
1957 * the associated trigger mode if found
1961 apic_trigger(int apic, int pin)
1965 /* search each of the possible INTerrupt sources */
1966 for (x = 0; x < nintrs; ++x)
1967 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1968 (pin == io_apic_ints[x].dst_apic_int))
1969 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1971 return -1; /* NOT found */
1976 * given a LOGICAL APIC# and pin#, return:
1977 * the associated 'active' level if found
1981 apic_polarity(int apic, int pin)
1985 /* search each of the possible INTerrupt sources */
1986 for (x = 0; x < nintrs; ++x)
1987 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1988 (pin == io_apic_ints[x].dst_apic_int))
1989 return (io_apic_ints[x].int_flags & 0x03);
1991 return -1; /* NOT found */
1995 * set data according to MP defaults
1996 * FIXME: probably not complete yet...
1999 mptable_default(int type)
2005 kprintf(" MP default config type: %d\n", type);
2008 kprintf(" bus: ISA, APIC: 82489DX\n");
2011 kprintf(" bus: EISA, APIC: 82489DX\n");
2014 kprintf(" bus: EISA, APIC: 82489DX\n");
2017 kprintf(" bus: MCA, APIC: 82489DX\n");
2020 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2023 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2026 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2029 kprintf(" future type\n");
2035 /* one and only IO APIC */
2036 io_apic_id = (ioapic_read(ioapic[0], IOAPIC_ID) & APIC_ID_MASK) >> 24;
2039 * sanity check, refer to MP spec section 3.6.6, last paragraph
2040 * necessary as some hardware isn't properly setting up the IO APIC
2042 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2043 if (io_apic_id != 2) {
2045 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2046 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2047 io_apic_set_id(0, 2);
2050 IO_TO_ID(0) = io_apic_id;
2051 ID_TO_IO(io_apic_id) = 0;
2053 /* fill out bus entries */
2062 bus_data[0].bus_id = default_data[type - 1][1];
2063 bus_data[0].bus_type = default_data[type - 1][2];
2064 bus_data[1].bus_id = default_data[type - 1][3];
2065 bus_data[1].bus_type = default_data[type - 1][4];
2068 /* case 4: case 7: MCA NOT supported */
2069 default: /* illegal/reserved */
2070 panic("BAD default MP config: %d", type);
2074 /* general cases from MP v1.4, table 5-2 */
2075 for (pin = 0; pin < 16; ++pin) {
2076 io_apic_ints[pin].int_type = 0;
2077 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2078 io_apic_ints[pin].src_bus_id = 0;
2079 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2080 io_apic_ints[pin].dst_apic_id = io_apic_id;
2081 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2084 /* special cases from MP v1.4, table 5-2 */
2086 io_apic_ints[2].int_type = 0xff; /* N/C */
2087 io_apic_ints[13].int_type = 0xff; /* N/C */
2088 #if !defined(APIC_MIXED_MODE)
2090 panic("sorry, can't support type 2 default yet");
2091 #endif /* APIC_MIXED_MODE */
2094 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2097 io_apic_ints[0].int_type = 0xff; /* N/C */
2099 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2103 * Map a physical memory address representing I/O into KVA. The I/O
2104 * block is assumed not to cross a page boundary.
2107 ioapic_map(vm_paddr_t pa)
2113 KKASSERT(pa < 0x100000000LL);
2115 pgeflag = 0; /* not used for SMP yet */
2118 * If the requested physical address has already been incidently
2119 * mapped, just use the existing mapping. Otherwise create a new
2122 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2123 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2124 ((vm_offset_t)pa & PG_FRAME)) {
2128 if (i == SMPpt_alloc_index) {
2129 if (i == NPTEPG - 2) {
2130 panic("permanent_io_mapping: We ran out of space"
2133 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2134 ((vm_offset_t)pa & PG_FRAME));
2135 ++SMPpt_alloc_index;
2137 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2138 ((vm_offset_t)pa & PAGE_MASK);
2139 return ((void *)vaddr);
2143 * start each AP in our list
2146 start_all_aps(u_int boot_addr)
2153 u_char mpbiosreason;
2154 u_long mpbioswarmvec;
2155 struct mdglobaldata *gd;
2156 struct privatespace *ps;
2160 POSTCODE(START_ALL_APS_POST);
2162 /* Initialize BSP's local APIC */
2163 apic_initialize(TRUE);
2166 MachIntrABI.finalize();
2168 /* install the AP 1st level boot code */
2169 install_ap_tramp(boot_addr);
2172 /* save the current value of the warm-start vector */
2173 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2174 outb(CMOS_REG, BIOS_RESET);
2175 mpbiosreason = inb(CMOS_DATA);
2177 /* setup a vector to our boot code */
2178 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2179 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2180 outb(CMOS_REG, BIOS_RESET);
2181 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2184 * If we have a TSC we can figure out the SMI interrupt rate.
2185 * The SMI does not necessarily use a constant rate. Spend
2186 * up to 250ms trying to figure it out.
2189 if (cpu_feature & CPUID_TSC) {
2190 set_apic_timer(275000);
2191 smilast = read_apic_timer();
2192 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2193 smicount = smitest();
2194 if (smibest == 0 || smilast - smicount < smibest)
2195 smibest = smilast - smicount;
2198 if (smibest > 250000)
2201 smibest = smibest * (int64_t)1000000 /
2202 get_apic_timer_frequency();
2206 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2207 1000000 / smibest, smibest);
2210 /* set up temporary P==V mapping for AP boot */
2211 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2212 kptbase = (uintptr_t)(void *)KPTphys;
2213 for (x = 0; x < NKPT; x++) {
2214 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2215 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2220 for (x = 1; x <= mp_naps; ++x) {
2222 /* This is a bit verbose, it will go away soon. */
2224 /* first page of AP's private space */
2225 pg = x * i386_btop(sizeof(struct privatespace));
2227 /* allocate new private data page(s) */
2228 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2229 MDGLOBALDATA_BASEALLOC_SIZE);
2230 /* wire it into the private page table page */
2231 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2232 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2233 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2235 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2237 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2238 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2239 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2240 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2242 /* allocate and set up an idle stack data page */
2243 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2244 for (i = 0; i < UPAGES; i++) {
2245 SMPpt[pg + 4 + i] = (pt_entry_t)
2246 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2249 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2250 bzero(gd, sizeof(*gd));
2251 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2253 /* prime data page for it to use */
2254 mi_gdinit(&gd->mi, x);
2256 gd->gd_CMAP1 = &SMPpt[pg + 0];
2257 gd->gd_CMAP2 = &SMPpt[pg + 1];
2258 gd->gd_CMAP3 = &SMPpt[pg + 2];
2259 gd->gd_PMAP1 = &SMPpt[pg + 3];
2260 gd->gd_CADDR1 = ps->CPAGE1;
2261 gd->gd_CADDR2 = ps->CPAGE2;
2262 gd->gd_CADDR3 = ps->CPAGE3;
2263 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2266 * Per-cpu pmap for get_ptbase().
2268 gd->gd_GDADDR1= (unsigned *)
2269 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2270 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2272 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2273 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2276 * Setup the AP boot stack
2278 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2281 /* attempt to start the Application Processor */
2282 CHECK_INIT(99); /* setup checkpoints */
2283 if (!start_ap(gd, boot_addr, smibest)) {
2284 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2285 CHECK_PRINT("trace"); /* show checkpoints */
2286 /* better panic as the AP may be running loose */
2287 kprintf("panic y/n? [y] ");
2288 if (cngetc() != 'n')
2291 CHECK_PRINT("trace"); /* show checkpoints */
2293 /* record its version info */
2294 cpu_apic_versions[x] = cpu_apic_versions[0];
2297 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2300 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2301 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2304 ncpus2_shift = shift;
2305 ncpus2 = 1 << shift;
2306 ncpus2_mask = ncpus2 - 1;
2308 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2309 if ((1 << shift) < ncpus)
2311 ncpus_fit = 1 << shift;
2312 ncpus_fit_mask = ncpus_fit - 1;
2314 /* build our map of 'other' CPUs */
2315 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2316 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2317 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2319 /* fill in our (BSP) APIC version */
2320 cpu_apic_versions[0] = lapic.version;
2322 /* restore the warmstart vector */
2323 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2324 outb(CMOS_REG, BIOS_RESET);
2325 outb(CMOS_DATA, mpbiosreason);
2328 * NOTE! The idlestack for the BSP was setup by locore. Finish
2329 * up, clean out the P==V mapping we did earlier.
2331 for (x = 0; x < NKPT; x++)
2335 /* number of APs actually started */
2340 * load the 1st level AP boot code into base memory.
2343 /* targets for relocation */
2344 extern void bigJump(void);
2345 extern void bootCodeSeg(void);
2346 extern void bootDataSeg(void);
2347 extern void MPentry(void);
2348 extern u_int MP_GDT;
2349 extern u_int mp_gdtbase;
2352 install_ap_tramp(u_int boot_addr)
2355 int size = *(int *) ((u_long) & bootMP_size);
2356 u_char *src = (u_char *) ((u_long) bootMP);
2357 u_char *dst = (u_char *) boot_addr + KERNBASE;
2358 u_int boot_base = (u_int) bootMP;
2363 POSTCODE(INSTALL_AP_TRAMP_POST);
2365 for (x = 0; x < size; ++x)
2369 * modify addresses in code we just moved to basemem. unfortunately we
2370 * need fairly detailed info about mpboot.s for this to work. changes
2371 * to mpboot.s might require changes here.
2374 /* boot code is located in KERNEL space */
2375 dst = (u_char *) boot_addr + KERNBASE;
2377 /* modify the lgdt arg */
2378 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2379 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2381 /* modify the ljmp target for MPentry() */
2382 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2383 *dst32 = ((u_int) MPentry - KERNBASE);
2385 /* modify the target for boot code segment */
2386 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2387 dst8 = (u_int8_t *) (dst16 + 1);
2388 *dst16 = (u_int) boot_addr & 0xffff;
2389 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2391 /* modify the target for boot data segment */
2392 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2393 dst8 = (u_int8_t *) (dst16 + 1);
2394 *dst16 = (u_int) boot_addr & 0xffff;
2395 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2400 * This function starts the AP (application processor) identified
2401 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2402 * to accomplish this. This is necessary because of the nuances
2403 * of the different hardware we might encounter. It ain't pretty,
2404 * but it seems to work.
2406 * NOTE: eventually an AP gets to ap_init(), which is called just
2407 * before the AP goes into the LWKT scheduler's idle loop.
2410 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2414 u_long icr_lo, icr_hi;
2416 POSTCODE(START_AP_POST);
2418 /* get the PHYSICAL APIC ID# */
2419 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2421 /* calculate the vector */
2422 vector = (boot_addr >> 12) & 0xff;
2424 /* We don't want anything interfering */
2427 /* Make sure the target cpu sees everything */
2431 * Try to detect when a SMI has occurred, wait up to 200ms.
2433 * If a SMI occurs during an AP reset but before we issue
2434 * the STARTUP command, the AP may brick. To work around
2435 * this problem we hold off doing the AP startup until
2436 * after we have detected the SMI. Hopefully another SMI
2437 * will not occur before we finish the AP startup.
2439 * Retries don't seem to help. SMIs have a window of opportunity
2440 * and if USB->legacy keyboard emulation is enabled in the BIOS
2441 * the interrupt rate can be quite high.
2443 * NOTE: Don't worry about the L1 cache load, it might bloat
2444 * ldelta a little but ndelta will be so huge when the SMI
2445 * occurs the detection logic will still work fine.
2448 set_apic_timer(200000);
2453 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2454 * and running the target CPU. OR this INIT IPI might be latched (P5
2455 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2458 * see apic/apicreg.h for icr bit definitions.
2460 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2464 * Setup the address for the target AP. We can setup
2465 * icr_hi once and then just trigger operations with
2468 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2469 icr_hi |= (physical_cpu << 24);
2470 icr_lo = lapic.icr_lo & 0xfff00000;
2471 lapic.icr_hi = icr_hi;
2474 * Do an INIT IPI: assert RESET
2476 * Use edge triggered mode to assert INIT
2478 lapic.icr_lo = icr_lo | 0x0000c500;
2479 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2483 * The spec calls for a 10ms delay but we may have to use a
2484 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2485 * interrupt. We have other loops here too and dividing by 2
2486 * doesn't seem to be enough even after subtracting 350us,
2487 * so we divide by 4.
2489 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2490 * interrupt was detected we use the full 10ms.
2494 else if (smibest < 150 * 4 + 350)
2496 else if ((smibest - 350) / 4 < 10000)
2497 u_sleep((smibest - 350) / 4);
2502 * Do an INIT IPI: deassert RESET
2504 * Use level triggered mode to deassert. It is unclear
2505 * why we need to do this.
2507 lapic.icr_lo = icr_lo | 0x00008500;
2508 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2510 u_sleep(150); /* wait 150us */
2513 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2514 * latched, (P5 bug) this 1st STARTUP would then terminate
2515 * immediately, and the previously started INIT IPI would continue. OR
2516 * the previous INIT IPI has already run. and this STARTUP IPI will
2517 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2520 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2521 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2523 u_sleep(200); /* wait ~200uS */
2526 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2527 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2528 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2529 * recognized after hardware RESET or INIT IPI.
2531 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2532 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2535 /* Resume normal operation */
2538 /* wait for it to start, see ap_init() */
2539 set_apic_timer(5000000);/* == 5 seconds */
2540 while (read_apic_timer()) {
2541 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2542 return 1; /* return SUCCESS */
2545 return 0; /* return FAILURE */
2560 while (read_apic_timer()) {
2562 for (count = 0; count < 100; ++count)
2563 ntsc = rdtsc(); /* force loop to occur */
2565 ndelta = ntsc - ltsc;
2566 if (ldelta > ndelta)
2568 if (ndelta > ldelta * 2)
2571 ldelta = ntsc - ltsc;
2574 return(read_apic_timer());
2578 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2580 * If for some reason we were unable to start all cpus we cannot safely
2581 * use broadcast IPIs.
2584 static cpumask_t smp_invltlb_req;
2585 #define SMP_INVLTLB_DEBUG
2591 struct mdglobaldata *md = mdcpu;
2592 #ifdef SMP_INVLTLB_DEBUG
2597 crit_enter_gd(&md->mi);
2598 md->gd_invltlb_ret = 0;
2599 ++md->mi.gd_cnt.v_smpinvltlb;
2600 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2601 #ifdef SMP_INVLTLB_DEBUG
2604 if (smp_startup_mask == smp_active_mask) {
2605 all_but_self_ipi(XINVLTLB_OFFSET);
2607 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2608 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2611 #ifdef SMP_INVLTLB_DEBUG
2613 kprintf("smp_invltlb: ipi sent\n");
2615 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2616 (smp_active_mask & ~md->mi.gd_cpumask)) {
2619 #ifdef SMP_INVLTLB_DEBUG
2621 if (++count == 400000000) {
2622 print_backtrace(-1);
2623 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2624 "rflags %016lx retry",
2625 (long)md->gd_invltlb_ret,
2626 (long)smp_invltlb_req,
2627 (long)read_eflags());
2628 __asm __volatile ("sti");
2631 lwkt_process_ipiq();
2633 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2634 ~md->mi.gd_cpumask &
2637 kprintf("bcpu %d\n", bcpu);
2638 xgd = globaldata_find(bcpu);
2639 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2648 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2649 crit_exit_gd(&md->mi);
2656 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2657 * bother to bump the critical section count or nested interrupt count
2658 * so only do very low level operations here.
2661 smp_invltlb_intr(void)
2663 struct mdglobaldata *md = mdcpu;
2664 struct mdglobaldata *omd;
2668 mask = smp_invltlb_req;
2672 cpu = BSFCPUMASK(mask);
2673 mask &= ~CPUMASK(cpu);
2674 omd = (struct mdglobaldata *)globaldata_find(cpu);
2675 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2682 * When called the executing CPU will send an IPI to all other CPUs
2683 * requesting that they halt execution.
2685 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2687 * - Signals all CPUs in map to stop.
2688 * - Waits for each to stop.
2695 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2696 * from executing at same time.
2699 stop_cpus(cpumask_t map)
2701 map &= smp_active_mask;
2703 /* send the Xcpustop IPI to all CPUs in map */
2704 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2706 while ((stopped_cpus & map) != map)
2714 * Called by a CPU to restart stopped CPUs.
2716 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2718 * - Signals all CPUs in map to restart.
2719 * - Waits for each to restart.
2727 restart_cpus(cpumask_t map)
2729 /* signal other cpus to restart */
2730 started_cpus = map & smp_active_mask;
2732 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2739 * This is called once the mpboot code has gotten us properly relocated
2740 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2741 * and when it returns the scheduler will call the real cpu_idle() main
2742 * loop for the idlethread. Interrupts are disabled on entry and should
2743 * remain disabled at return.
2751 * Adjust smp_startup_mask to signal the BSP that we have started
2752 * up successfully. Note that we do not yet hold the BGL. The BSP
2753 * is waiting for our signal.
2755 * We can't set our bit in smp_active_mask yet because we are holding
2756 * interrupts physically disabled and remote cpus could deadlock
2757 * trying to send us an IPI.
2759 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2763 * Interlock for finalization. Wait until mp_finish is non-zero,
2764 * then get the MP lock.
2766 * Note: We are in a critical section.
2768 * Note: we are the idle thread, we can only spin.
2770 * Note: The load fence is memory volatile and prevents the compiler
2771 * from improperly caching mp_finish, and the cpu from improperly
2774 while (mp_finish == 0)
2776 while (try_mplock() == 0)
2779 if (cpu_feature & CPUID_TSC) {
2781 * The BSP is constantly updating tsc0_offset, figure out
2782 * the relative difference to synchronize ktrdump.
2784 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2787 /* BSP may have changed PTD while we're waiting for the lock */
2790 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2794 /* Build our map of 'other' CPUs. */
2795 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2797 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2799 /* A quick check from sanity claus */
2800 apic_id = (apic_id_to_logical[(lapic.id & 0xff000000) >> 24]);
2801 if (mycpu->gd_cpuid != apic_id) {
2802 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2803 kprintf("SMP: apic_id = %d\n", apic_id);
2804 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2805 panic("cpuid mismatch! boom!!");
2808 /* Initialize AP's local APIC for irq's */
2809 apic_initialize(FALSE);
2811 /* Set memory range attributes for this CPU to match the BSP */
2812 mem_range_AP_init();
2815 * Once we go active we must process any IPIQ messages that may
2816 * have been queued, because no actual IPI will occur until we
2817 * set our bit in the smp_active_mask. If we don't the IPI
2818 * message interlock could be left set which would also prevent
2821 * The idle loop doesn't expect the BGL to be held and while
2822 * lwkt_switch() normally cleans things up this is a special case
2823 * because we returning almost directly into the idle loop.
2825 * The idle thread is never placed on the runq, make sure
2826 * nothing we've done put it there.
2828 KKASSERT(get_mplock_count(curthread) == 1);
2829 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2832 * Enable interrupts here. idle_restore will also do it, but
2833 * doing it here lets us clean up any strays that got posted to
2834 * the CPU during the AP boot while we are still in a critical
2837 __asm __volatile("sti; pause; pause"::);
2838 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2840 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2841 lwkt_process_ipiq();
2844 * Releasing the mp lock lets the BSP finish up the SMP init
2847 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2851 * Get SMP fully working before we start initializing devices.
2859 kprintf("Finish MP startup\n");
2860 if (cpu_feature & CPUID_TSC)
2861 tsc0_offset = rdtsc();
2864 while (smp_active_mask != smp_startup_mask) {
2866 if (cpu_feature & CPUID_TSC)
2867 tsc0_offset = rdtsc();
2869 while (try_mplock() == 0)
2872 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2875 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2878 cpu_send_ipiq(int dcpu)
2880 if (CPUMASK(dcpu) & smp_active_mask)
2881 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2884 #if 0 /* single_apic_ipi_passive() not working yet */
2886 * Returns 0 on failure, 1 on success
2889 cpu_send_ipiq_passive(int dcpu)
2892 if (CPUMASK(dcpu) & smp_active_mask) {
2893 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2894 APIC_DELMODE_FIXED);
2901 mptable_bus_info_callback(void *xarg, const void *pos, int type)
2903 struct mptable_bus_info *bus_info = xarg;
2904 const struct BUSENTRY *ent;
2905 struct mptable_bus *bus;
2911 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2912 if (bus->mb_id == ent->bus_id) {
2913 kprintf("mptable_bus_info_alloc: duplicated bus id "
2914 "(%d)\n", bus->mb_id);
2920 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
2921 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2922 bus->mb_type = MPTABLE_BUS_PCI;
2923 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
2924 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2925 bus->mb_type = MPTABLE_BUS_ISA;
2929 bus->mb_id = ent->bus_id;
2930 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
2936 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
2940 bzero(bus_info, sizeof(*bus_info));
2941 TAILQ_INIT(&bus_info->mbi_list);
2943 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
2945 mptable_bus_info_free(bus_info);
2949 mptable_bus_info_free(struct mptable_bus_info *bus_info)
2951 struct mptable_bus *bus;
2953 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
2954 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
2959 struct mptable_lapic_cbarg1 {
2962 u_int ht_apicid_mask;
2966 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2968 const struct PROCENTRY *ent;
2969 struct mptable_lapic_cbarg1 *arg = xarg;
2975 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2979 if (ent->apic_id < 32) {
2980 arg->ht_apicid_mask |= 1 << ent->apic_id;
2981 } else if (arg->ht_fixup) {
2982 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2988 struct mptable_lapic_cbarg2 {
2995 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2997 const struct PROCENTRY *ent;
2998 struct mptable_lapic_cbarg2 *arg = xarg;
3004 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3005 KKASSERT(!arg->found_bsp);
3009 if (processor_entry(ent, arg->cpu))
3012 if (arg->logical_cpus) {
3013 struct PROCENTRY proc;
3017 * Create fake mptable processor entries
3018 * and feed them to processor_entry() to
3019 * enumerate the logical CPUs.
3021 bzero(&proc, sizeof(proc));
3023 proc.cpu_flags = PROCENTRY_FLAG_EN;
3024 proc.apic_id = ent->apic_id;
3026 for (i = 1; i < arg->logical_cpus; i++) {
3028 processor_entry(&proc, arg->cpu);
3036 mptable_imcr(struct mptable_pos *mpt)
3038 /* record whether PIC or virtual-wire mode */
3039 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
3040 mpt->mp_fps->mpfb2 & 0x80);
3044 mptable_lapic_default(void)
3046 int ap_apicid, bsp_apicid;
3048 mp_naps = 1; /* exclude BSP */
3050 /* Map local apic before the id field is accessed */
3051 lapic_map(DEFAULT_APIC_BASE);
3053 bsp_apicid = APIC_ID(lapic.id);
3054 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3057 mp_set_cpuids(0, bsp_apicid);
3058 /* one and only AP */
3059 mp_set_cpuids(1, ap_apicid);
3065 * ID_TO_CPU(N), APIC ID to logical CPU table
3066 * CPU_TO_ID(N), logical CPU to APIC ID table
3069 mptable_lapic_enumerate(struct lapic_enumerator *e)
3071 struct mptable_pos mpt;
3072 struct mptable_lapic_cbarg1 arg1;
3073 struct mptable_lapic_cbarg2 arg2;
3075 int error, logical_cpus = 0;
3076 vm_offset_t lapic_addr;
3078 if (mptable_use_default) {
3079 mptable_lapic_default();
3083 error = mptable_map(&mpt);
3085 panic("mptable_lapic_enumerate mptable_map failed\n");
3086 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3090 /* Save local apic address */
3091 lapic_addr = (vm_offset_t)cth->apic_address;
3092 KKASSERT(lapic_addr != 0);
3095 * Find out how many CPUs do we have
3097 bzero(&arg1, sizeof(arg1));
3098 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3100 error = mptable_iterate_entries(cth,
3101 mptable_lapic_pass1_callback, &arg1);
3103 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3104 KKASSERT(arg1.cpu_count != 0);
3106 /* See if we need to fixup HT logical CPUs. */
3107 if (arg1.ht_fixup) {
3108 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3110 if (logical_cpus != 0)
3111 arg1.cpu_count *= logical_cpus;
3113 mp_naps = arg1.cpu_count;
3115 /* Qualify the numbers again, after possible HT fixup */
3116 if (mp_naps > MAXCPU) {
3117 kprintf("Warning: only using %d of %d available CPUs!\n",
3122 --mp_naps; /* subtract the BSP */
3125 * Link logical CPU id to local apic id
3127 bzero(&arg2, sizeof(arg2));
3129 arg2.logical_cpus = logical_cpus;
3131 error = mptable_iterate_entries(cth,
3132 mptable_lapic_pass2_callback, &arg2);
3134 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3135 KKASSERT(arg2.found_bsp);
3137 /* Map local apic */
3138 lapic_map(lapic_addr);
3140 mptable_unmap(&mpt);
3143 struct mptable_lapic_probe_cbarg {
3149 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
3151 const struct PROCENTRY *ent;
3152 struct mptable_lapic_probe_cbarg *arg = xarg;
3158 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3162 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3163 if (arg->found_bsp) {
3164 kprintf("more than one BSP in base MP table\n");
3173 mptable_lapic_probe(struct lapic_enumerator *e)
3175 struct mptable_pos mpt;
3176 struct mptable_lapic_probe_cbarg arg;
3180 if (mptable_fps_phyaddr == 0)
3183 if (mptable_use_default)
3186 error = mptable_map(&mpt);
3189 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3194 if (cth->apic_address == 0)
3197 bzero(&arg, sizeof(arg));
3198 error = mptable_iterate_entries(cth,
3199 mptable_lapic_probe_callback, &arg);
3201 if (arg.cpu_count == 0) {
3202 kprintf("MP table contains no processor entries\n");
3204 } else if (!arg.found_bsp) {
3205 kprintf("MP table does not contains BSP entry\n");
3210 mptable_unmap(&mpt);
3214 static struct lapic_enumerator mptable_lapic_enumerator = {
3215 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3216 .lapic_probe = mptable_lapic_probe,
3217 .lapic_enumerate = mptable_lapic_enumerate
3221 mptable_lapic_enum_register(void)
3223 lapic_enumerator_register(&mptable_lapic_enumerator);
3225 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3226 mptable_lapic_enum_register, 0);
3229 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
3231 const struct IOAPICENTRY *ent;
3232 struct mptable_ioapic *nioapic, *ioapic;
3238 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
3241 if (ent->apic_address == 0) {
3242 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
3246 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3247 if (ioapic->mio_apic_id == ent->apic_id) {
3248 kprintf("mptable_ioapic_create_list: duplicated "
3249 "apic id %d\n", ioapic->mio_apic_id);
3252 if (ioapic->mio_addr == (uint32_t)ent->apic_address) {
3253 kprintf("mptable_ioapic_create_list: overlapped "
3254 "IOAPIC addr 0x%08x", ioapic->mio_addr);
3259 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3260 nioapic->mio_apic_id = ent->apic_id;
3261 nioapic->mio_addr = (uint32_t)ent->apic_address;
3264 * Create IOAPIC list in ascending order of APIC ID
3266 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
3267 mptable_ioapic_list, mio_link) {
3268 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
3269 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
3270 ioapic, nioapic, mio_link);
3275 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
3281 mptable_ioapic_create_list(void)
3283 struct mptable_ioapic *ioapic;
3284 struct mptable_pos mpt;
3287 if (mptable_fps_phyaddr == 0)
3290 if (mptable_use_default) {
3291 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3292 ioapic->mio_idx = 0;
3293 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
3294 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
3296 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
3300 error = mptable_map(&mpt);
3302 panic("mptable_ioapic_create_list: mptable_map failed\n");
3303 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3305 error = mptable_iterate_entries(mpt.mp_cth,
3306 mptable_ioapic_list_callback, NULL);
3308 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
3309 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
3310 kfree(ioapic, M_DEVBUF);
3316 * Assign index number for each IOAPIC
3319 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3320 ioapic->mio_idx = idx;
3324 mptable_unmap(&mpt);
3326 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
3327 mptable_ioapic_create_list, 0);
3330 mptable_pci_int_callback(void *xarg, const void *pos, int type)
3332 const struct mptable_bus_info *bus_info = xarg;
3333 const struct mptable_ioapic *ioapic;
3334 const struct mptable_bus *bus;
3335 struct mptable_pci_int *pci_int;
3336 const struct INTENTRY *ent;
3337 int pci_pin, pci_dev;
3343 if (ent->int_type != 0)
3346 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
3347 if (bus->mb_type == MPTABLE_BUS_PCI &&
3348 bus->mb_id == ent->src_bus_id)
3354 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3355 if (ioapic->mio_apic_id == ent->dst_apic_id)
3358 if (ioapic == NULL) {
3359 kprintf("MPTABLE: warning PCI int dst apic id %d "
3360 "does not exist\n", ent->dst_apic_id);
3364 pci_pin = ent->src_bus_irq & 0x3;
3365 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
3367 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
3368 if (pci_int->mpci_bus == ent->src_bus_id &&
3369 pci_int->mpci_dev == pci_dev &&
3370 pci_int->mpci_pin == pci_pin) {
3371 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
3372 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
3373 kprintf("MPTABLE: warning duplicated "
3374 "PCI int entry for "
3375 "bus %d, dev %d, pin %d\n",
3381 kprintf("mptable_pci_int_register: "
3382 "conflict PCI int entry for "
3383 "bus %d, dev %d, pin %d, "
3384 "IOAPIC %d.%d -> %d.%d\n",
3388 pci_int->mpci_ioapic_idx,
3389 pci_int->mpci_ioapic_pin,
3397 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
3399 pci_int->mpci_bus = ent->src_bus_id;
3400 pci_int->mpci_dev = pci_dev;
3401 pci_int->mpci_pin = pci_pin;
3402 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
3403 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
3405 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
3411 mptable_pci_int_register(void)
3413 struct mptable_bus_info bus_info;
3414 const struct mptable_bus *bus;
3415 struct mptable_pci_int *pci_int;
3416 struct mptable_pos mpt;
3417 int error, force_pci0, npcibus;
3420 if (mptable_fps_phyaddr == 0)
3423 if (mptable_use_default)
3426 if (TAILQ_EMPTY(&mptable_ioapic_list))
3429 error = mptable_map(&mpt);
3431 panic("mptable_pci_int_register: mptable_map failed\n");
3432 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3436 mptable_bus_info_alloc(cth, &bus_info);
3437 if (TAILQ_EMPTY(&bus_info.mbi_list))
3441 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
3442 if (bus->mb_type == MPTABLE_BUS_PCI)
3446 mptable_bus_info_free(&bus_info);
3448 } else if (npcibus == 1) {
3452 error = mptable_iterate_entries(cth,
3453 mptable_pci_int_callback, &bus_info);
3455 mptable_bus_info_free(&bus_info);
3458 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
3459 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
3460 kfree(pci_int, M_DEVBUF);
3466 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
3467 pci_int->mpci_bus = 0;
3470 mptable_unmap(&mpt);
3472 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3473 mptable_pci_int_register, 0);
3475 struct mptable_ioapic_probe_cbarg {
3476 const struct mptable_bus_info *bus_info;
3480 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
3482 struct mptable_ioapic_probe_cbarg *arg = xarg;
3483 const struct mptable_ioapic *ioapic;
3484 const struct mptable_bus *bus;
3485 const struct INTENTRY *ent;
3491 if (ent->int_type != 0)
3494 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3495 if (bus->mb_type == MPTABLE_BUS_ISA &&
3496 bus->mb_id == ent->src_bus_id)
3502 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3503 if (ioapic->mio_apic_id == ent->dst_apic_id)
3506 if (ioapic == NULL) {
3507 kprintf("MPTABLE: warning ISA int dst apic id %d "
3508 "does not exist\n", ent->dst_apic_id);
3512 /* XXX magic number */
3513 if (ent->src_bus_irq >= 16) {
3514 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
3522 mptable_ioapic_probe(struct ioapic_enumerator *e)
3524 struct mptable_ioapic_probe_cbarg arg;
3525 struct mptable_bus_info bus_info;
3526 struct mptable_pos mpt;
3530 if (mptable_fps_phyaddr == 0)
3533 if (mptable_use_default)
3536 if (TAILQ_EMPTY(&mptable_ioapic_list))
3539 error = mptable_map(&mpt);
3541 panic("mptable_ioapic_probe: mptable_map failed\n");
3542 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3546 mptable_bus_info_alloc(cth, &bus_info);
3548 bzero(&arg, sizeof(arg));
3549 arg.bus_info = &bus_info;
3551 error = mptable_iterate_entries(cth,
3552 mptable_ioapic_probe_callback, &arg);
3554 mptable_bus_info_free(&bus_info);
3555 mptable_unmap(&mpt);
3560 struct mptable_ioapic_int_cbarg {
3561 const struct mptable_bus_info *bus_info;
3566 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
3568 struct mptable_ioapic_int_cbarg *arg = xarg;
3569 const struct mptable_bus *bus;
3570 const struct INTENTRY *ent;
3578 if (ent->int_type != 0)
3581 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3582 if (bus->mb_type == MPTABLE_BUS_ISA &&
3583 bus->mb_id == ent->src_bus_id)
3589 /* XXX rough estimation */
3590 if (ent->src_bus_irq != ent->dst_apic_int) {
3592 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3593 ent->src_bus_irq, ent->dst_apic_int);
3600 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
3602 struct mptable_bus_info bus_info;
3603 const struct mptable_ioapic *ioapic;
3604 struct mptable_pos mpt;
3608 KKASSERT(mptable_fps_phyaddr != 0);
3609 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
3611 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3613 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
3614 "apic id %d, idx %d\n",
3616 ioapic->mio_apic_id, ioapic->mio_idx);
3621 if (mptable_use_default) {
3623 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
3624 /* TODO default intsrc */
3628 error = mptable_map(&mpt);
3630 panic("mptable_ioapic_probe: mptable_map failed\n");
3631 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3635 mptable_bus_info_alloc(cth, &bus_info);
3637 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
3639 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
3640 /* TODO default intsrc */
3642 struct mptable_ioapic_int_cbarg arg;
3644 bzero(&arg, sizeof(arg));
3645 arg.bus_info = &bus_info;
3647 error = mptable_iterate_entries(cth,
3648 mptable_ioapic_int_callback, &arg);
3650 panic("mptable_ioapic_int failed\n");
3652 if (arg.ioapic_nint == 0) {
3654 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
3657 /* TODO default intsrc */
3661 mptable_bus_info_free(&bus_info);
3663 mptable_unmap(&mpt);
3666 static struct ioapic_enumerator mptable_ioapic_enumerator = {
3667 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
3668 .ioapic_probe = mptable_ioapic_probe,
3669 .ioapic_enumerate = mptable_ioapic_enumerate
3673 mptable_ioapic_enum_register(void)
3675 ioapic_enumerator_register(&mptable_ioapic_enumerator);
3677 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3678 mptable_ioapic_enum_register, 0);