2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/isa/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_BASE2 (0xe0000)
78 #define BIOS_SIZE (0x10000)
79 #define BIOS_COUNT (BIOS_SIZE/4)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define PROCENTRY_FLAG_EN 0x01
87 #define PROCENTRY_FLAG_BP 0x02
88 #define IOAPICENTRY_FLAG_EN 0x01
91 /* MP Floating Pointer Structure */
92 typedef struct MPFPS {
105 /* MP Configuration Table Header */
106 typedef struct MPCTH {
108 u_short base_table_length;
112 u_char product_id[12];
113 u_int32_t oem_table_pointer;
114 u_short oem_table_size;
116 u_int32_t apic_address;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
123 typedef struct PROCENTRY {
128 u_int32_t cpu_signature;
129 u_int32_t feature_flags;
134 typedef struct BUSENTRY {
140 typedef struct IOAPICENTRY {
145 u_int32_t apic_address;
146 } *io_apic_entry_ptr;
148 typedef struct INTENTRY {
158 /* descriptions of MP basetable entries */
159 typedef struct BASETABLE_ENTRY {
168 vm_size_t mp_cth_mapsz;
171 typedef int (*mptable_iter_func)(void *, const void *, int);
174 * this code MUST be enabled here and in mpboot.s.
175 * it follows the very early stages of AP boot by placing values in CMOS ram.
176 * it NORMALLY will never be needed and thus the primitive method for enabling.
179 #if defined(CHECK_POINTS)
180 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
181 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
183 #define CHECK_INIT(D); \
184 CHECK_WRITE(0x34, (D)); \
185 CHECK_WRITE(0x35, (D)); \
186 CHECK_WRITE(0x36, (D)); \
187 CHECK_WRITE(0x37, (D)); \
188 CHECK_WRITE(0x38, (D)); \
189 CHECK_WRITE(0x39, (D));
191 #define CHECK_PRINT(S); \
192 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
201 #else /* CHECK_POINTS */
203 #define CHECK_INIT(D)
204 #define CHECK_PRINT(S)
206 #endif /* CHECK_POINTS */
209 * Values to send to the POST hardware.
211 #define MP_BOOTADDRESS_POST 0x10
212 #define MP_PROBE_POST 0x11
213 #define MPTABLE_PASS1_POST 0x12
215 #define MP_START_POST 0x13
216 #define MP_ENABLE_POST 0x14
217 #define MPTABLE_PASS2_POST 0x15
219 #define START_ALL_APS_POST 0x16
220 #define INSTALL_AP_TRAMP_POST 0x17
221 #define START_AP_POST 0x18
223 #define MP_ANNOUNCE_POST 0x19
225 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
226 int current_postcode;
228 /** XXX FIXME: what system files declare these??? */
229 extern struct region_descriptor r_gdt, r_idt;
231 int mp_naps; /* # of Applications processors */
232 #ifdef SMP /* APIC-IO */
233 static int mp_nbusses; /* # of busses */
234 int mp_napics; /* # of IO APICs */
235 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
236 u_int32_t *io_apic_versions;
240 u_int32_t cpu_apic_versions[NAPICID]; /* populated during mptable scan */
242 extern int64_t tsc_offsets[];
244 extern u_long ebda_addr;
246 #ifdef SMP /* APIC-IO */
247 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
251 * APIC ID logical/physical mapping structures.
252 * We oversize these to simplify boot-time config.
254 int cpu_num_to_apic_id[NAPICID];
255 #ifdef SMP /* APIC-IO */
256 int io_num_to_apic_id[NAPICID];
258 int apic_id_to_logical[NAPICID];
260 /* AP uses this during bootstrap. Do not staticize. */
264 struct pcb stoppcbs[MAXCPU];
266 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
268 static basetable_entry basetable_entry_types[] =
270 {0, 20, "Processor"},
278 * Local data and functions.
281 static u_int boot_address;
282 static u_int base_memory;
283 static int mp_finish;
285 static void mp_enable(u_int boot_addr);
287 static int mptable_iterate_entries(const mpcth_t,
288 mptable_iter_func, void *);
289 static int mptable_probe(void);
290 static int mptable_search(void);
291 static int mptable_check(vm_paddr_t);
292 static long mptable_search_sig(u_int32_t target, int count);
293 static int mptable_hyperthread_fixup(cpumask_t, int);
294 #ifdef SMP /* APIC-IO */
295 static void mptable_pass1(struct mptable_pos *);
296 static void mptable_pass2(struct mptable_pos *);
297 static void mptable_default(int type);
298 static void mptable_fix(void);
300 static int mptable_map(struct mptable_pos *, vm_paddr_t);
301 static void mptable_unmap(struct mptable_pos *);
302 static void mptable_imcr(struct mptable_pos *);
304 static int mptable_lapic_probe(struct lapic_enumerator *);
305 static void mptable_lapic_enumerate(struct lapic_enumerator *);
306 static void mptable_lapic_default(void);
308 #ifdef SMP /* APIC-IO */
309 static void setup_apic_irq_mapping(void);
310 static int apic_int_is_bus_type(int intr, int bus_type);
312 static int start_all_aps(u_int boot_addr);
314 static void install_ap_tramp(u_int boot_addr);
316 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
317 static int smitest(void);
319 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
320 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
321 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
322 static u_int bootMP_size;
325 * Calculate usable address in base memory for AP trampoline code.
328 mp_bootaddress(u_int basemem)
330 POSTCODE(MP_BOOTADDRESS_POST);
332 base_memory = basemem;
334 bootMP_size = mptramp_end - mptramp_start;
335 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
336 if (((basemem * 1024) - boot_address) < bootMP_size)
337 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
338 /* 3 levels of page table pages */
339 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
341 return mptramp_pagetables;
350 mpfps_paddr = mptable_search();
351 if (mptable_check(mpfps_paddr))
358 * Look for an Intel MP spec table (ie, SMP capable hardware).
366 POSTCODE(MP_PROBE_POST);
368 /* see if EBDA exists */
369 if (ebda_addr != 0) {
370 /* search first 1K of EBDA */
371 target = (u_int32_t)ebda_addr;
372 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
375 /* last 1K of base memory, effective 'top of base' passed in */
376 target = (u_int32_t)(base_memory - 0x400);
377 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
381 /* search the BIOS */
382 target = (u_int32_t)BIOS_BASE;
383 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
386 /* search the extended BIOS */
387 target = (u_int32_t)BIOS_BASE2;
388 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
395 struct mptable_check_cbarg {
401 mptable_check_callback(void *xarg, const void *pos, int type)
403 const struct PROCENTRY *ent;
404 struct mptable_check_cbarg *arg = xarg;
410 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
414 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
415 if (arg->found_bsp) {
416 kprintf("more than one BSP in base MP table\n");
425 mptable_check(vm_paddr_t mpfps_paddr)
427 struct mptable_pos mpt;
428 struct mptable_check_cbarg arg;
432 if (mpfps_paddr == 0)
435 error = mptable_map(&mpt, mpfps_paddr);
439 if (mpt.mp_fps->mpfb1 != 0)
447 if (cth->apic_address == 0)
450 bzero(&arg, sizeof(arg));
451 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
453 if (arg.cpu_count == 0) {
454 kprintf("MP table contains no processor entries\n");
456 } else if (!arg.found_bsp) {
457 kprintf("MP table does not contains BSP entry\n");
467 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
469 int count, total_size;
470 const void *position;
472 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
473 total_size = cth->base_table_length - sizeof(struct MPCTH);
474 position = (const uint8_t *)cth + sizeof(struct MPCTH);
475 count = cth->entry_count;
480 KKASSERT(total_size >= 0);
481 if (total_size == 0) {
482 kprintf("invalid base MP table, "
483 "entry count and length mismatch\n");
487 type = *(const uint8_t *)position;
489 case 0: /* processor_entry */
490 case 1: /* bus_entry */
491 case 2: /* io_apic_entry */
492 case 3: /* int_entry */
493 case 4: /* int_entry */
496 kprintf("unknown base MP table entry type %d\n", type);
500 if (total_size < basetable_entry_types[type].length) {
501 kprintf("invalid base MP table length, "
502 "does not contain all entries\n");
505 total_size -= basetable_entry_types[type].length;
507 error = func(arg, position, type);
511 position = (const uint8_t *)position +
512 basetable_entry_types[type].length;
519 * Startup the SMP processors.
524 POSTCODE(MP_START_POST);
525 mp_enable(boot_address);
530 * Print various information about the SMP system hardware and setup.
537 POSTCODE(MP_ANNOUNCE_POST);
539 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
540 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
541 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
542 for (x = 1; x <= mp_naps; ++x) {
543 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
544 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
547 if (apic_io_enable) {
548 for (x = 0; x < mp_napics; ++x) {
549 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
550 kprintf(", version: 0x%08x", io_apic_versions[x]);
551 kprintf(", at 0x%08lx\n", io_apic_address[x]);
554 kprintf(" Warning: APIC I/O disabled\n");
559 * AP cpu's call this to sync up protected mode.
561 * WARNING! %gs is not set up on entry. This routine sets up %gs.
567 int x, myid = bootAP;
569 struct mdglobaldata *md;
570 struct privatespace *ps;
572 ps = &CPU_prvspace[myid];
574 gdt_segs[GPROC0_SEL].ssd_base =
575 (long) &ps->mdglobaldata.gd_common_tss;
576 ps->mdglobaldata.mi.gd_prvspace = ps;
578 /* We fill the 32-bit segment descriptors */
579 for (x = 0; x < NGDT; x++) {
580 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
581 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
583 /* And now a 64-bit one */
584 ssdtosyssd(&gdt_segs[GPROC0_SEL],
585 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
587 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
588 r_gdt.rd_base = (long) &gdt[myid * NGDT];
589 lgdt(&r_gdt); /* does magic intra-segment return */
591 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
592 wrmsr(MSR_FSBASE, 0); /* User value */
593 wrmsr(MSR_GSBASE, (u_int64_t)ps);
594 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
600 mdcpu->gd_currentldt = _default_ldt;
603 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
604 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
606 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
608 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
610 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
612 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
613 md->gd_common_tssd = *md->gd_tss_gdt;
615 /* double fault stack */
616 md->gd_common_tss.tss_ist1 =
617 (long)&md->mi.gd_prvspace->idlestack[
618 sizeof(md->mi.gd_prvspace->idlestack)];
623 * Set to a known state:
624 * Set by mpboot.s: CR0_PG, CR0_PE
625 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
628 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
631 /* Set up the fast syscall stuff */
632 msr = rdmsr(MSR_EFER) | EFER_SCE;
633 wrmsr(MSR_EFER, msr);
634 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
635 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
636 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
637 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
638 wrmsr(MSR_STAR, msr);
639 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
641 pmap_set_opt(); /* PSE/4MB pages, etc */
643 /* Initialize the PAT MSR. */
647 /* set up CPU registers and state */
650 /* set up SSE/NX registers */
653 /* set up FPU state on the AP */
654 npxinit(__INITIAL_NPXCW__);
656 /* disable the APIC, just to be SURE */
657 lapic->svr &= ~APIC_SVR_ENABLE;
659 /* data returned to BSP */
660 cpu_apic_versions[0] = lapic->version;
663 /*******************************************************************
664 * local functions and data
668 * start the SMP system
671 mp_enable(u_int boot_addr)
675 vm_paddr_t mpfps_paddr;
676 struct mptable_pos mpt;
678 POSTCODE(MP_ENABLE_POST);
682 mpfps_paddr = mptable_probe();
684 mptable_map(&mpt, mpfps_paddr);
688 if (apic_io_enable) {
691 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
693 mptable_map(&mpt, mpfps_paddr);
696 * Examine the MP table for needed info
703 /* Post scan cleanup */
706 setup_apic_irq_mapping();
708 /* fill the LOGICAL io_apic_versions table */
709 for (apic = 0; apic < mp_napics; ++apic) {
710 ux = io_apic_read(apic, IOAPIC_VER);
711 io_apic_versions[apic] = ux;
712 io_apic_set_id(apic, IO_TO_ID(apic));
715 /* program each IO APIC in the system */
716 for (apic = 0; apic < mp_napics; ++apic)
717 if (io_apic_setup(apic) < 0)
718 panic("IO APIC setup failure");
723 * These are required for SMP operation
726 /* install a 'Spurious INTerrupt' vector */
727 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
728 SDT_SYSIGT, SEL_KPL, 0);
730 /* install an inter-CPU IPI for TLB invalidation */
731 setidt(XINVLTLB_OFFSET, Xinvltlb,
732 SDT_SYSIGT, SEL_KPL, 0);
734 /* install an inter-CPU IPI for IPIQ messaging */
735 setidt(XIPIQ_OFFSET, Xipiq,
736 SDT_SYSIGT, SEL_KPL, 0);
738 /* install a timer vector */
739 setidt(XTIMER_OFFSET, Xtimer,
740 SDT_SYSIGT, SEL_KPL, 0);
742 /* install an inter-CPU IPI for CPU stop/restart */
743 setidt(XCPUSTOP_OFFSET, Xcpustop,
744 SDT_SYSIGT, SEL_KPL, 0);
746 /* start each Application Processor */
747 start_all_aps(boot_addr);
752 * look for the MP spec signature
755 /* string defined by the Intel MP Spec as identifying the MP table */
756 #define MP_SIG 0x5f504d5f /* _MP_ */
757 #define NEXT(X) ((X) += 4)
759 mptable_search_sig(u_int32_t target, int count)
765 KKASSERT(target != 0);
767 map_size = count * sizeof(u_int32_t);
768 addr = pmap_mapdev((vm_paddr_t)target, map_size);
771 for (x = 0; x < count; NEXT(x)) {
772 if (addr[x] == MP_SIG) {
773 /* make array index a byte index */
774 ret = target + (x * sizeof(u_int32_t));
779 pmap_unmapdev((vm_offset_t)addr, map_size);
784 typedef struct BUSDATA {
786 enum busTypes bus_type;
789 typedef struct INTDATA {
799 typedef struct BUSTYPENAME {
804 static bus_type_name bus_type_table[] =
810 {UNKNOWN_BUSTYPE, "---"},
813 {UNKNOWN_BUSTYPE, "---"},
814 {UNKNOWN_BUSTYPE, "---"},
815 {UNKNOWN_BUSTYPE, "---"},
816 {UNKNOWN_BUSTYPE, "---"},
817 {UNKNOWN_BUSTYPE, "---"},
819 {UNKNOWN_BUSTYPE, "---"},
820 {UNKNOWN_BUSTYPE, "---"},
821 {UNKNOWN_BUSTYPE, "---"},
822 {UNKNOWN_BUSTYPE, "---"},
824 {UNKNOWN_BUSTYPE, "---"}
827 /* from MP spec v1.4, table 5-1 */
828 static int default_data[7][5] =
830 /* nbus, id0, type0, id1, type1 */
831 {1, 0, ISA, 255, 255},
832 {1, 0, EISA, 255, 255},
833 {1, 0, EISA, 255, 255},
834 {1, 0, MCA, 255, 255},
836 {2, 0, EISA, 1, PCI},
841 static bus_datum *bus_data;
843 /* the IO INT data, one entry per possible APIC INTerrupt */
844 static io_int *io_apic_ints;
847 static int processor_entry (const struct PROCENTRY *entry, int cpu);
848 static int bus_entry (const struct BUSENTRY *entry, int bus);
849 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
850 static int int_entry (const struct INTENTRY *entry, int intr);
851 static int lookup_bus_type (char *name);
854 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
856 const struct IOAPICENTRY *ioapic_ent;
859 case 1: /* bus_entry */
863 case 2: /* io_apic_entry */
865 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
866 io_apic_address[mp_napics++] =
867 (vm_offset_t)ioapic_ent->apic_address;
871 case 3: /* int_entry */
879 * 1st pass on motherboard's Intel MP specification table.
888 mptable_pass1(struct mptable_pos *mpt)
893 POSTCODE(MPTABLE_PASS1_POST);
896 KKASSERT(fps != NULL);
898 /* clear various tables */
899 for (x = 0; x < NAPICID; ++x)
900 io_apic_address[x] = ~0; /* IO APIC address table */
906 /* check for use of 'default' configuration */
907 if (fps->mpfb1 != 0) {
908 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
909 mp_nbusses = default_data[fps->mpfb1 - 1][0];
915 error = mptable_iterate_entries(mpt->mp_cth,
916 mptable_ioapic_pass1_callback, NULL);
918 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
922 struct mptable_ioapic2_cbarg {
929 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
931 struct mptable_ioapic2_cbarg *arg = xarg;
935 if (bus_entry(pos, arg->bus))
940 if (io_apic_entry(pos, arg->apic))
945 if (int_entry(pos, arg->intr))
953 * 2nd pass on motherboard's Intel MP specification table.
956 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
957 * IO_TO_ID(N), logical IO to APIC ID table
962 mptable_pass2(struct mptable_pos *mpt)
964 struct mptable_ioapic2_cbarg arg;
968 POSTCODE(MPTABLE_PASS2_POST);
971 KKASSERT(fps != NULL);
973 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
975 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
976 M_DEVBUF, M_WAITOK | M_ZERO);
977 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
979 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
982 for (x = 0; x < mp_napics; x++)
983 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
985 /* clear various tables */
986 for (x = 0; x < NAPICID; ++x) {
987 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
988 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
991 /* clear bus data table */
992 for (x = 0; x < mp_nbusses; ++x)
993 bus_data[x].bus_id = 0xff;
995 /* clear IO APIC INT table */
996 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
997 io_apic_ints[x].int_type = 0xff;
998 io_apic_ints[x].int_vector = 0xff;
1001 /* check for use of 'default' configuration */
1002 if (fps->mpfb1 != 0) {
1003 mptable_default(fps->mpfb1);
1007 bzero(&arg, sizeof(arg));
1008 error = mptable_iterate_entries(mpt->mp_cth,
1009 mptable_ioapic_pass2_callback, &arg);
1011 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1015 * Check if we should perform a hyperthreading "fix-up" to
1016 * enumerate any logical CPU's that aren't already listed
1019 * XXX: We assume that all of the physical CPUs in the
1020 * system have the same number of logical CPUs.
1022 * XXX: We assume that APIC ID's are allocated such that
1023 * the APIC ID's for a physical processor are aligned
1024 * with the number of logical CPU's in the processor.
1027 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
1029 int i, id, lcpus_max, logical_cpus;
1031 if ((cpu_feature & CPUID_HTT) == 0)
1034 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1038 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1040 * INSTRUCTION SET REFERENCE, A-M (#253666)
1041 * Page 3-181, Table 3-20
1042 * "The nearest power-of-2 integer that is not smaller
1043 * than EBX[23:16] is the number of unique initial APIC
1044 * IDs reserved for addressing different logical
1045 * processors in a physical package."
1047 for (i = 0; ; ++i) {
1048 if ((1 << i) >= lcpus_max) {
1055 KKASSERT(cpu_count != 0);
1056 if (cpu_count == lcpus_max) {
1057 /* We have nothing to fix */
1059 } else if (cpu_count == 1) {
1060 /* XXX this may be incorrect */
1061 logical_cpus = lcpus_max;
1063 int cur, prev, dist;
1066 * Calculate the distances between two nearest
1067 * APIC IDs. If all such distances are same,
1068 * then it is the number of missing cpus that
1069 * we are going to fill later.
1071 dist = cur = prev = -1;
1072 for (id = 0; id < MAXCPU; ++id) {
1073 if ((id_mask & CPUMASK(id)) == 0)
1078 int new_dist = cur - prev;
1084 * Make sure that all distances
1085 * between two nearest APIC IDs
1088 if (dist != new_dist)
1096 /* Must be power of 2 */
1097 if (dist & (dist - 1))
1100 /* Can't exceed CPU package capacity */
1101 if (dist > lcpus_max)
1102 logical_cpus = lcpus_max;
1104 logical_cpus = dist;
1108 * For each APIC ID of a CPU that is set in the mask,
1109 * scan the other candidate APIC ID's for this
1110 * physical processor. If any of those ID's are
1111 * already in the table, then kill the fixup.
1113 for (id = 0; id < MAXCPU; id++) {
1114 if ((id_mask & CPUMASK(id)) == 0)
1116 /* First, make sure we are on a logical_cpus boundary. */
1117 if (id % logical_cpus != 0)
1119 for (i = id + 1; i < id + logical_cpus; i++)
1120 if ((id_mask & CPUMASK(i)) != 0)
1123 return logical_cpus;
1127 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1131 vm_size_t cth_mapsz = 0;
1133 bzero(mpt, sizeof(*mpt));
1135 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1136 if (fps->pap != 0) {
1138 * Map configuration table header to get
1139 * the base table size
1141 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1142 cth_mapsz = cth->base_table_length;
1143 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1145 if (cth_mapsz < sizeof(*cth)) {
1146 kprintf("invalid base MP table length %d\n",
1148 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1153 * Map the base table
1155 cth = pmap_mapdev(fps->pap, cth_mapsz);
1160 mpt->mp_cth_mapsz = cth_mapsz;
1166 mptable_unmap(struct mptable_pos *mpt)
1168 if (mpt->mp_cth != NULL) {
1169 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1171 mpt->mp_cth_mapsz = 0;
1173 if (mpt->mp_fps != NULL) {
1174 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1180 assign_apic_irq(int apic, int intpin, int irq)
1184 if (int_to_apicintpin[irq].ioapic != -1)
1185 panic("assign_apic_irq: inconsistent table");
1187 int_to_apicintpin[irq].ioapic = apic;
1188 int_to_apicintpin[irq].int_pin = intpin;
1189 int_to_apicintpin[irq].apic_address = ioapic[apic];
1190 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1192 for (x = 0; x < nintrs; x++) {
1193 if ((io_apic_ints[x].int_type == 0 ||
1194 io_apic_ints[x].int_type == 3) &&
1195 io_apic_ints[x].int_vector == 0xff &&
1196 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1197 io_apic_ints[x].dst_apic_int == intpin)
1198 io_apic_ints[x].int_vector = irq;
1203 revoke_apic_irq(int irq)
1209 if (int_to_apicintpin[irq].ioapic == -1)
1210 panic("revoke_apic_irq: inconsistent table");
1212 oldapic = int_to_apicintpin[irq].ioapic;
1213 oldintpin = int_to_apicintpin[irq].int_pin;
1215 int_to_apicintpin[irq].ioapic = -1;
1216 int_to_apicintpin[irq].int_pin = 0;
1217 int_to_apicintpin[irq].apic_address = NULL;
1218 int_to_apicintpin[irq].redirindex = 0;
1220 for (x = 0; x < nintrs; x++) {
1221 if ((io_apic_ints[x].int_type == 0 ||
1222 io_apic_ints[x].int_type == 3) &&
1223 io_apic_ints[x].int_vector != 0xff &&
1224 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1225 io_apic_ints[x].dst_apic_int == oldintpin)
1226 io_apic_ints[x].int_vector = 0xff;
1234 allocate_apic_irq(int intr)
1240 if (io_apic_ints[intr].int_vector != 0xff)
1241 return; /* Interrupt handler already assigned */
1243 if (io_apic_ints[intr].int_type != 0 &&
1244 (io_apic_ints[intr].int_type != 3 ||
1245 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1246 io_apic_ints[intr].dst_apic_int == 0)))
1247 return; /* Not INT or ExtInt on != (0, 0) */
1250 while (irq < APIC_INTMAPSIZE &&
1251 int_to_apicintpin[irq].ioapic != -1)
1254 if (irq >= APIC_INTMAPSIZE)
1255 return; /* No free interrupt handlers */
1257 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1258 intpin = io_apic_ints[intr].dst_apic_int;
1260 assign_apic_irq(apic, intpin, irq);
1265 swap_apic_id(int apic, int oldid, int newid)
1272 return; /* Nothing to do */
1274 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1275 apic, oldid, newid);
1277 /* Swap physical APIC IDs in interrupt entries */
1278 for (x = 0; x < nintrs; x++) {
1279 if (io_apic_ints[x].dst_apic_id == oldid)
1280 io_apic_ints[x].dst_apic_id = newid;
1281 else if (io_apic_ints[x].dst_apic_id == newid)
1282 io_apic_ints[x].dst_apic_id = oldid;
1285 /* Swap physical APIC IDs in IO_TO_ID mappings */
1286 for (oapic = 0; oapic < mp_napics; oapic++)
1287 if (IO_TO_ID(oapic) == newid)
1290 if (oapic < mp_napics) {
1291 kprintf("Changing APIC ID for IO APIC #%d from "
1292 "%d to %d in MP table\n",
1293 oapic, newid, oldid);
1294 IO_TO_ID(oapic) = oldid;
1296 IO_TO_ID(apic) = newid;
1301 fix_id_to_io_mapping(void)
1305 for (x = 0; x < NAPICID; x++)
1308 for (x = 0; x <= mp_naps; x++) {
1309 if ((u_int)CPU_TO_ID(x) < NAPICID)
1310 ID_TO_IO(CPU_TO_ID(x)) = x;
1313 for (x = 0; x < mp_napics; x++) {
1314 if ((u_int)IO_TO_ID(x) < NAPICID)
1315 ID_TO_IO(IO_TO_ID(x)) = x;
1321 first_free_apic_id(void)
1325 for (freeid = 0; freeid < NAPICID; freeid++) {
1326 for (x = 0; x <= mp_naps; x++)
1327 if (CPU_TO_ID(x) == freeid)
1331 for (x = 0; x < mp_napics; x++)
1332 if (IO_TO_ID(x) == freeid)
1343 io_apic_id_acceptable(int apic, int id)
1345 int cpu; /* Logical CPU number */
1346 int oapic; /* Logical IO APIC number for other IO APIC */
1348 if ((u_int)id >= NAPICID)
1349 return 0; /* Out of range */
1351 for (cpu = 0; cpu <= mp_naps; cpu++) {
1352 if (CPU_TO_ID(cpu) == id)
1353 return 0; /* Conflict with CPU */
1356 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) {
1357 if (IO_TO_ID(oapic) == id)
1358 return 0; /* Conflict with other APIC */
1361 return 1; /* ID is acceptable for IO APIC */
1366 io_apic_find_int_entry(int apic, int pin)
1370 /* search each of the possible INTerrupt sources */
1371 for (x = 0; x < nintrs; ++x) {
1372 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1373 (pin == io_apic_ints[x].dst_apic_int))
1374 return (&io_apic_ints[x]);
1380 * parse an Intel MP specification table
1387 int apic; /* IO APIC unit number */
1388 int freeid; /* Free physical APIC ID */
1389 int physid; /* Current physical IO APIC ID */
1391 int bus_0 = 0; /* Stop GCC warning */
1392 int bus_pci = 0; /* Stop GCC warning */
1396 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1397 * did it wrong. The MP spec says that when more than 1 PCI bus
1398 * exists the BIOS must begin with bus entries for the PCI bus and use
1399 * actual PCI bus numbering. This implies that when only 1 PCI bus
1400 * exists the BIOS can choose to ignore this ordering, and indeed many
1401 * MP motherboards do ignore it. This causes a problem when the PCI
1402 * sub-system makes requests of the MP sub-system based on PCI bus
1403 * numbers. So here we look for the situation and renumber the
1404 * busses and associated INTs in an effort to "make it right".
1407 /* find bus 0, PCI bus, count the number of PCI busses */
1408 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1409 if (bus_data[x].bus_id == 0) {
1412 if (bus_data[x].bus_type == PCI) {
1418 * bus_0 == slot of bus with ID of 0
1419 * bus_pci == slot of last PCI bus encountered
1422 /* check the 1 PCI bus case for sanity */
1423 /* if it is number 0 all is well */
1424 if (num_pci_bus == 1 &&
1425 bus_data[bus_pci].bus_id != 0) {
1427 /* mis-numbered, swap with whichever bus uses slot 0 */
1429 /* swap the bus entry types */
1430 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1431 bus_data[bus_0].bus_type = PCI;
1433 /* swap each relevant INTerrupt entry */
1434 id = bus_data[bus_pci].bus_id;
1435 for (x = 0; x < nintrs; ++x) {
1436 if (io_apic_ints[x].src_bus_id == id) {
1437 io_apic_ints[x].src_bus_id = 0;
1439 else if (io_apic_ints[x].src_bus_id == 0) {
1440 io_apic_ints[x].src_bus_id = id;
1445 /* Assign IO APIC IDs.
1447 * First try the existing ID. If a conflict is detected, try
1448 * the ID in the MP table. If a conflict is still detected, find
1451 * We cannot use the ID_TO_IO table before all conflicts has been
1452 * resolved and the table has been corrected.
1454 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1456 /* First try to use the value set by the BIOS */
1457 physid = io_apic_get_id(apic);
1458 if (io_apic_id_acceptable(apic, physid)) {
1459 if (IO_TO_ID(apic) != physid)
1460 swap_apic_id(apic, IO_TO_ID(apic), physid);
1464 /* Then check if the value in the MP table is acceptable */
1465 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1468 /* Last resort, find a free APIC ID and use it */
1469 freeid = first_free_apic_id();
1470 if (freeid >= NAPICID)
1471 panic("No free physical APIC IDs found");
1473 if (io_apic_id_acceptable(apic, freeid)) {
1474 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1477 panic("Free physical APIC ID not usable");
1479 fix_id_to_io_mapping();
1481 /* detect and fix broken Compaq MP table */
1482 if (apic_int_type(0, 0) == -1) {
1483 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1484 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1485 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1486 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1487 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1488 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1490 } else if (apic_int_type(0, 0) == 0) {
1491 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1492 for (x = 0; x < nintrs; ++x)
1493 if ((ID_TO_IO(io_apic_ints[x].dst_apic_id) == 0) &&
1494 (io_apic_ints[x].dst_apic_int) == 0) {
1495 io_apic_ints[x].int_type = 3;
1496 io_apic_ints[x].int_vector = 0xff;
1502 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1503 * controllers universally come in pairs. If IRQ 14 is specified
1504 * as an ISA interrupt, then IRQ 15 had better be too.
1506 * [ Shuttle XPC / AMD Athlon X2 ]
1507 * The MPTable is missing an entry for IRQ 15. Note that the
1508 * ACPI table has an entry for both 14 and 15.
1510 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1511 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1512 io14 = io_apic_find_int_entry(0, 14);
1513 io_apic_ints[nintrs] = *io14;
1514 io_apic_ints[nintrs].src_bus_irq = 15;
1515 io_apic_ints[nintrs].dst_apic_int = 15;
1520 /* Assign low level interrupt handlers */
1522 setup_apic_irq_mapping(void)
1528 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1529 int_to_apicintpin[x].ioapic = -1;
1530 int_to_apicintpin[x].int_pin = 0;
1531 int_to_apicintpin[x].apic_address = NULL;
1532 int_to_apicintpin[x].redirindex = 0;
1534 /* Default to masked */
1535 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1538 /* First assign ISA/EISA interrupts */
1539 for (x = 0; x < nintrs; x++) {
1540 int_vector = io_apic_ints[x].src_bus_irq;
1541 if (int_vector < APIC_INTMAPSIZE &&
1542 io_apic_ints[x].int_vector == 0xff &&
1543 int_to_apicintpin[int_vector].ioapic == -1 &&
1544 (apic_int_is_bus_type(x, ISA) ||
1545 apic_int_is_bus_type(x, EISA)) &&
1546 io_apic_ints[x].int_type == 0) {
1547 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1548 io_apic_ints[x].dst_apic_int,
1553 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1554 for (x = 0; x < nintrs; x++) {
1555 if (io_apic_ints[x].dst_apic_int == 0 &&
1556 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1557 io_apic_ints[x].int_vector == 0xff &&
1558 int_to_apicintpin[0].ioapic == -1 &&
1559 io_apic_ints[x].int_type == 3) {
1560 assign_apic_irq(0, 0, 0);
1565 /* Assign PCI interrupts */
1566 for (x = 0; x < nintrs; ++x) {
1567 if (io_apic_ints[x].int_type == 0 &&
1568 io_apic_ints[x].int_vector == 0xff &&
1569 apic_int_is_bus_type(x, PCI))
1570 allocate_apic_irq(x);
1575 mp_set_cpuids(int cpu_id, int apic_id)
1577 CPU_TO_ID(cpu_id) = apic_id;
1578 ID_TO_CPU(apic_id) = cpu_id;
1582 processor_entry(const struct PROCENTRY *entry, int cpu)
1586 /* check for usability */
1587 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1590 /* check for BSP flag */
1591 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1592 mp_set_cpuids(0, entry->apic_id);
1593 return 0; /* its already been counted */
1596 /* add another AP to list, if less than max number of CPUs */
1597 else if (cpu < MAXCPU) {
1598 mp_set_cpuids(cpu, entry->apic_id);
1606 bus_entry(const struct BUSENTRY *entry, int bus)
1611 /* encode the name into an index */
1612 for (x = 0; x < 6; ++x) {
1613 if ((c = entry->bus_type[x]) == ' ')
1619 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1620 panic("unknown bus type: '%s'", name);
1622 bus_data[bus].bus_id = entry->bus_id;
1623 bus_data[bus].bus_type = x;
1629 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1631 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1634 IO_TO_ID(apic) = entry->apic_id;
1635 ID_TO_IO(entry->apic_id) = apic;
1641 lookup_bus_type(char *name)
1645 for (x = 0; x < MAX_BUSTYPE; ++x)
1646 if (strcmp(bus_type_table[x].name, name) == 0)
1647 return bus_type_table[x].type;
1649 return UNKNOWN_BUSTYPE;
1653 int_entry(const struct INTENTRY *entry, int intr)
1657 io_apic_ints[intr].int_type = entry->int_type;
1658 io_apic_ints[intr].int_flags = entry->int_flags;
1659 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1660 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1661 if (entry->dst_apic_id == 255) {
1662 /* This signal goes to all IO APICS. Select an IO APIC
1663 with sufficient number of interrupt pins */
1664 for (apic = 0; apic < mp_napics; apic++)
1665 if (((io_apic_read(apic, IOAPIC_VER) &
1666 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1667 entry->dst_apic_int)
1669 if (apic < mp_napics)
1670 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1672 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1674 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1675 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1681 apic_int_is_bus_type(int intr, int bus_type)
1685 for (bus = 0; bus < mp_nbusses; ++bus)
1686 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1687 && ((int) bus_data[bus].bus_type == bus_type))
1694 * Given a traditional ISA INT mask, return an APIC mask.
1697 isa_apic_mask(u_int isa_mask)
1702 #if defined(SKIP_IRQ15_REDIRECT)
1703 if (isa_mask == (1 << 15)) {
1704 kprintf("skipping ISA IRQ15 redirect\n");
1707 #endif /* SKIP_IRQ15_REDIRECT */
1709 isa_irq = ffs(isa_mask); /* find its bit position */
1710 if (isa_irq == 0) /* doesn't exist */
1712 --isa_irq; /* make it zero based */
1714 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1718 return (1 << apic_pin); /* convert pin# to a mask */
1722 * Determine which APIC pin an ISA/EISA INT is attached to.
1724 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1725 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1726 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1727 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1729 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1731 isa_apic_irq(int isa_irq)
1735 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1736 if (INTTYPE(intr) == 0) { /* standard INT */
1737 if (SRCBUSIRQ(intr) == isa_irq) {
1738 if (apic_int_is_bus_type(intr, ISA) ||
1739 apic_int_is_bus_type(intr, EISA)) {
1740 if (INTIRQ(intr) == 0xff)
1741 return -1; /* unassigned */
1742 return INTIRQ(intr); /* found */
1747 return -1; /* NOT found */
1752 * Determine which APIC pin a PCI INT is attached to.
1754 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1755 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1756 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1758 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1762 --pciInt; /* zero based */
1764 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1765 if ((INTTYPE(intr) == 0) /* standard INT */
1766 && (SRCBUSID(intr) == pciBus)
1767 && (SRCBUSDEVICE(intr) == pciDevice)
1768 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1769 if (apic_int_is_bus_type(intr, PCI)) {
1770 if (INTIRQ(intr) == 0xff) {
1771 kprintf("IOAPIC: pci_apic_irq() "
1773 return -1; /* unassigned */
1775 return INTIRQ(intr); /* exact match */
1780 return -1; /* NOT found */
1784 next_apic_irq(int irq)
1791 for (intr = 0; intr < nintrs; intr++) {
1792 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1794 bus = SRCBUSID(intr);
1795 bustype = apic_bus_type(bus);
1796 if (bustype != ISA &&
1802 if (intr >= nintrs) {
1805 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1806 if (INTTYPE(ointr) != 0)
1808 if (bus != SRCBUSID(ointr))
1810 if (bustype == PCI) {
1811 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1813 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1816 if (bustype == ISA || bustype == EISA) {
1817 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1820 if (INTPIN(intr) == INTPIN(ointr))
1824 if (ointr >= nintrs) {
1827 return INTIRQ(ointr);
1840 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1843 * Exactly what this means is unclear at this point. It is a solution
1844 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1845 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1846 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1850 undirect_isa_irq(int rirq)
1854 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1855 /** FIXME: tickle the MB redirector chip */
1859 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1866 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1869 undirect_pci_irq(int rirq)
1873 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1875 /** FIXME: tickle the MB redirector chip */
1879 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1887 * given a bus ID, return:
1888 * the bus type if found
1892 apic_bus_type(int id)
1896 for (x = 0; x < mp_nbusses; ++x)
1897 if (bus_data[x].bus_id == id)
1898 return bus_data[x].bus_type;
1904 * given a LOGICAL APIC# and pin#, return:
1905 * the associated src bus ID if found
1909 apic_src_bus_id(int apic, int pin)
1913 /* search each of the possible INTerrupt sources */
1914 for (x = 0; x < nintrs; ++x)
1915 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1916 (pin == io_apic_ints[x].dst_apic_int))
1917 return (io_apic_ints[x].src_bus_id);
1919 return -1; /* NOT found */
1923 * given a LOGICAL APIC# and pin#, return:
1924 * the associated src bus IRQ if found
1928 apic_src_bus_irq(int apic, int pin)
1932 for (x = 0; x < nintrs; x++)
1933 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1934 (pin == io_apic_ints[x].dst_apic_int))
1935 return (io_apic_ints[x].src_bus_irq);
1937 return -1; /* NOT found */
1942 * given a LOGICAL APIC# and pin#, return:
1943 * the associated INTerrupt type if found
1947 apic_int_type(int apic, int pin)
1951 /* search each of the possible INTerrupt sources */
1952 for (x = 0; x < nintrs; ++x) {
1953 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1954 (pin == io_apic_ints[x].dst_apic_int))
1955 return (io_apic_ints[x].int_type);
1957 return -1; /* NOT found */
1961 * Return the IRQ associated with an APIC pin
1964 apic_irq(int apic, int pin)
1969 for (x = 0; x < nintrs; ++x) {
1970 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1971 (pin == io_apic_ints[x].dst_apic_int)) {
1972 res = io_apic_ints[x].int_vector;
1975 if (apic != int_to_apicintpin[res].ioapic)
1976 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1977 if (pin != int_to_apicintpin[res].int_pin)
1978 panic("apic_irq inconsistent table (2)");
1987 * given a LOGICAL APIC# and pin#, return:
1988 * the associated trigger mode if found
1992 apic_trigger(int apic, int pin)
1996 /* search each of the possible INTerrupt sources */
1997 for (x = 0; x < nintrs; ++x)
1998 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1999 (pin == io_apic_ints[x].dst_apic_int))
2000 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2002 return -1; /* NOT found */
2007 * given a LOGICAL APIC# and pin#, return:
2008 * the associated 'active' level if found
2012 apic_polarity(int apic, int pin)
2016 /* search each of the possible INTerrupt sources */
2017 for (x = 0; x < nintrs; ++x)
2018 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2019 (pin == io_apic_ints[x].dst_apic_int))
2020 return (io_apic_ints[x].int_flags & 0x03);
2022 return -1; /* NOT found */
2026 * set data according to MP defaults
2027 * FIXME: probably not complete yet...
2030 mptable_default(int type)
2036 kprintf(" MP default config type: %d\n", type);
2039 kprintf(" bus: ISA, APIC: 82489DX\n");
2042 kprintf(" bus: EISA, APIC: 82489DX\n");
2045 kprintf(" bus: EISA, APIC: 82489DX\n");
2048 kprintf(" bus: MCA, APIC: 82489DX\n");
2051 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2054 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2057 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2060 kprintf(" future type\n");
2066 /* one and only IO APIC */
2067 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2070 * sanity check, refer to MP spec section 3.6.6, last paragraph
2071 * necessary as some hardware isn't properly setting up the IO APIC
2073 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2074 if (io_apic_id != 2) {
2076 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2077 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2078 io_apic_set_id(0, 2);
2081 IO_TO_ID(0) = io_apic_id;
2082 ID_TO_IO(io_apic_id) = 0;
2084 /* fill out bus entries */
2093 bus_data[0].bus_id = default_data[type - 1][1];
2094 bus_data[0].bus_type = default_data[type - 1][2];
2095 bus_data[1].bus_id = default_data[type - 1][3];
2096 bus_data[1].bus_type = default_data[type - 1][4];
2099 /* case 4: case 7: MCA NOT supported */
2100 default: /* illegal/reserved */
2101 panic("BAD default MP config: %d", type);
2105 /* general cases from MP v1.4, table 5-2 */
2106 for (pin = 0; pin < 16; ++pin) {
2107 io_apic_ints[pin].int_type = 0;
2108 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2109 io_apic_ints[pin].src_bus_id = 0;
2110 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2111 io_apic_ints[pin].dst_apic_id = io_apic_id;
2112 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2115 /* special cases from MP v1.4, table 5-2 */
2117 io_apic_ints[2].int_type = 0xff; /* N/C */
2118 io_apic_ints[13].int_type = 0xff; /* N/C */
2119 #if !defined(APIC_MIXED_MODE)
2121 panic("sorry, can't support type 2 default yet");
2122 #endif /* APIC_MIXED_MODE */
2125 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2128 io_apic_ints[0].int_type = 0xff; /* N/C */
2130 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2134 * Map a physical memory address representing I/O into KVA. The I/O
2135 * block is assumed not to cross a page boundary.
2138 permanent_io_mapping(vm_paddr_t pa)
2140 KKASSERT(pa < 0x100000000LL);
2142 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2146 * start each AP in our list
2149 start_all_aps(u_int boot_addr)
2151 vm_offset_t va = boot_address + KERNBASE;
2152 u_int64_t *pt4, *pt3, *pt2;
2158 u_char mpbiosreason;
2159 u_long mpbioswarmvec;
2160 struct mdglobaldata *gd;
2161 struct privatespace *ps;
2163 POSTCODE(START_ALL_APS_POST);
2165 /* Initialize BSP's local APIC */
2166 apic_initialize(TRUE);
2168 /* install the AP 1st level boot code */
2169 pmap_kenter(va, boot_address);
2170 cpu_invlpg((void *)va); /* JG XXX */
2171 bcopy(mptramp_start, (void *)va, bootMP_size);
2173 /* Locate the page tables, they'll be below the trampoline */
2174 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2175 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2176 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2178 /* Create the initial 1GB replicated page tables */
2179 for (i = 0; i < 512; i++) {
2180 /* Each slot of the level 4 pages points to the same level 3 page */
2181 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2182 pt4[i] |= PG_V | PG_RW | PG_U;
2184 /* Each slot of the level 3 pages points to the same level 2 page */
2185 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2186 pt3[i] |= PG_V | PG_RW | PG_U;
2188 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2189 pt2[i] = i * (2 * 1024 * 1024);
2190 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2193 /* save the current value of the warm-start vector */
2194 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2195 outb(CMOS_REG, BIOS_RESET);
2196 mpbiosreason = inb(CMOS_DATA);
2198 /* setup a vector to our boot code */
2199 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2200 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2201 outb(CMOS_REG, BIOS_RESET);
2202 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2205 * If we have a TSC we can figure out the SMI interrupt rate.
2206 * The SMI does not necessarily use a constant rate. Spend
2207 * up to 250ms trying to figure it out.
2210 if (cpu_feature & CPUID_TSC) {
2211 set_apic_timer(275000);
2212 smilast = read_apic_timer();
2213 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2214 smicount = smitest();
2215 if (smibest == 0 || smilast - smicount < smibest)
2216 smibest = smilast - smicount;
2219 if (smibest > 250000)
2222 smibest = smibest * (int64_t)1000000 /
2223 get_apic_timer_frequency();
2227 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2228 1000000 / smibest, smibest);
2230 kprintf("SMP: Starting %d APs: ", mp_naps);
2232 for (x = 1; x <= mp_naps; ++x) {
2234 /* This is a bit verbose, it will go away soon. */
2236 /* first page of AP's private space */
2237 pg = x * x86_64_btop(sizeof(struct privatespace));
2239 /* allocate new private data page(s) */
2240 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2241 MDGLOBALDATA_BASEALLOC_SIZE);
2243 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2244 bzero(gd, sizeof(*gd));
2245 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2247 /* prime data page for it to use */
2248 mi_gdinit(&gd->mi, x);
2250 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2251 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2253 /* setup a vector to our boot code */
2254 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2255 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2256 outb(CMOS_REG, BIOS_RESET);
2257 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2260 * Setup the AP boot stack
2262 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2265 /* attempt to start the Application Processor */
2266 CHECK_INIT(99); /* setup checkpoints */
2267 if (!start_ap(gd, boot_addr, smibest)) {
2268 kprintf("\nAP #%d (PHY# %d) failed!\n",
2270 CHECK_PRINT("trace"); /* show checkpoints */
2271 /* better panic as the AP may be running loose */
2272 kprintf("panic y/n? [y] ");
2273 if (cngetc() != 'n')
2276 CHECK_PRINT("trace"); /* show checkpoints */
2278 /* record its version info */
2279 cpu_apic_versions[x] = cpu_apic_versions[0];
2282 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2285 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2286 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2289 ncpus2_shift = shift;
2290 ncpus2 = 1 << shift;
2291 ncpus2_mask = ncpus2 - 1;
2293 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2294 if ((1 << shift) < ncpus)
2296 ncpus_fit = 1 << shift;
2297 ncpus_fit_mask = ncpus_fit - 1;
2299 /* build our map of 'other' CPUs */
2300 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2301 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2302 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2304 /* fill in our (BSP) APIC version */
2305 cpu_apic_versions[0] = lapic->version;
2307 /* restore the warmstart vector */
2308 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2309 outb(CMOS_REG, BIOS_RESET);
2310 outb(CMOS_DATA, mpbiosreason);
2313 * NOTE! The idlestack for the BSP was setup by locore. Finish
2314 * up, clean out the P==V mapping we did earlier.
2318 /* number of APs actually started */
2324 * load the 1st level AP boot code into base memory.
2327 /* targets for relocation */
2328 extern void bigJump(void);
2329 extern void bootCodeSeg(void);
2330 extern void bootDataSeg(void);
2331 extern void MPentry(void);
2332 extern u_int MP_GDT;
2333 extern u_int mp_gdtbase;
2338 install_ap_tramp(u_int boot_addr)
2341 int size = *(int *) ((u_long) & bootMP_size);
2342 u_char *src = (u_char *) ((u_long) bootMP);
2343 u_char *dst = (u_char *) boot_addr + KERNBASE;
2344 u_int boot_base = (u_int) bootMP;
2349 POSTCODE(INSTALL_AP_TRAMP_POST);
2351 for (x = 0; x < size; ++x)
2355 * modify addresses in code we just moved to basemem. unfortunately we
2356 * need fairly detailed info about mpboot.s for this to work. changes
2357 * to mpboot.s might require changes here.
2360 /* boot code is located in KERNEL space */
2361 dst = (u_char *) boot_addr + KERNBASE;
2363 /* modify the lgdt arg */
2364 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2365 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2367 /* modify the ljmp target for MPentry() */
2368 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2369 *dst32 = ((u_int) MPentry - KERNBASE);
2371 /* modify the target for boot code segment */
2372 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2373 dst8 = (u_int8_t *) (dst16 + 1);
2374 *dst16 = (u_int) boot_addr & 0xffff;
2375 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2377 /* modify the target for boot data segment */
2378 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2379 dst8 = (u_int8_t *) (dst16 + 1);
2380 *dst16 = (u_int) boot_addr & 0xffff;
2381 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2387 * This function starts the AP (application processor) identified
2388 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2389 * to accomplish this. This is necessary because of the nuances
2390 * of the different hardware we might encounter. It ain't pretty,
2391 * but it seems to work.
2393 * NOTE: eventually an AP gets to ap_init(), which is called just
2394 * before the AP goes into the LWKT scheduler's idle loop.
2397 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2401 u_long icr_lo, icr_hi;
2403 POSTCODE(START_AP_POST);
2405 /* get the PHYSICAL APIC ID# */
2406 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2408 /* calculate the vector */
2409 vector = (boot_addr >> 12) & 0xff;
2411 /* We don't want anything interfering */
2414 /* Make sure the target cpu sees everything */
2418 * Try to detect when a SMI has occurred, wait up to 200ms.
2420 * If a SMI occurs during an AP reset but before we issue
2421 * the STARTUP command, the AP may brick. To work around
2422 * this problem we hold off doing the AP startup until
2423 * after we have detected the SMI. Hopefully another SMI
2424 * will not occur before we finish the AP startup.
2426 * Retries don't seem to help. SMIs have a window of opportunity
2427 * and if USB->legacy keyboard emulation is enabled in the BIOS
2428 * the interrupt rate can be quite high.
2430 * NOTE: Don't worry about the L1 cache load, it might bloat
2431 * ldelta a little but ndelta will be so huge when the SMI
2432 * occurs the detection logic will still work fine.
2435 set_apic_timer(200000);
2440 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2441 * and running the target CPU. OR this INIT IPI might be latched (P5
2442 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2445 * see apic/apicreg.h for icr bit definitions.
2447 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2451 * Setup the address for the target AP. We can setup
2452 * icr_hi once and then just trigger operations with
2455 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2456 icr_hi |= (physical_cpu << 24);
2457 icr_lo = lapic->icr_lo & 0xfff00000;
2458 lapic->icr_hi = icr_hi;
2461 * Do an INIT IPI: assert RESET
2463 * Use edge triggered mode to assert INIT
2465 lapic->icr_lo = icr_lo | 0x00004500;
2466 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2470 * The spec calls for a 10ms delay but we may have to use a
2471 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2472 * interrupt. We have other loops here too and dividing by 2
2473 * doesn't seem to be enough even after subtracting 350us,
2474 * so we divide by 4.
2476 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2477 * interrupt was detected we use the full 10ms.
2481 else if (smibest < 150 * 4 + 350)
2483 else if ((smibest - 350) / 4 < 10000)
2484 u_sleep((smibest - 350) / 4);
2489 * Do an INIT IPI: deassert RESET
2491 * Use level triggered mode to deassert. It is unclear
2492 * why we need to do this.
2494 lapic->icr_lo = icr_lo | 0x00008500;
2495 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2497 u_sleep(150); /* wait 150us */
2500 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2501 * latched, (P5 bug) this 1st STARTUP would then terminate
2502 * immediately, and the previously started INIT IPI would continue. OR
2503 * the previous INIT IPI has already run. and this STARTUP IPI will
2504 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2507 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2508 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2510 u_sleep(200); /* wait ~200uS */
2513 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2514 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2515 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2516 * recognized after hardware RESET or INIT IPI.
2518 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2519 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2522 /* Resume normal operation */
2525 /* wait for it to start, see ap_init() */
2526 set_apic_timer(5000000);/* == 5 seconds */
2527 while (read_apic_timer()) {
2528 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2529 return 1; /* return SUCCESS */
2532 return 0; /* return FAILURE */
2547 while (read_apic_timer()) {
2549 for (count = 0; count < 100; ++count)
2550 ntsc = rdtsc(); /* force loop to occur */
2552 ndelta = ntsc - ltsc;
2553 if (ldelta > ndelta)
2555 if (ndelta > ldelta * 2)
2558 ldelta = ntsc - ltsc;
2561 return(read_apic_timer());
2565 * Synchronously flush the TLB on all other CPU's. The current cpu's
2566 * TLB is not flushed. If the caller wishes to flush the current cpu's
2567 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
2569 * NOTE: If for some reason we were unable to start all cpus we cannot
2570 * safely use broadcast IPIs.
2573 static cpumask_t smp_invltlb_req;
2575 #define SMP_INVLTLB_DEBUG
2581 struct mdglobaldata *md = mdcpu;
2582 #ifdef SMP_INVLTLB_DEBUG
2587 crit_enter_gd(&md->mi);
2588 md->gd_invltlb_ret = 0;
2589 ++md->mi.gd_cnt.v_smpinvltlb;
2590 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2591 #ifdef SMP_INVLTLB_DEBUG
2594 if (smp_startup_mask == smp_active_mask) {
2595 all_but_self_ipi(XINVLTLB_OFFSET);
2597 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2598 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2601 #ifdef SMP_INVLTLB_DEBUG
2603 kprintf("smp_invltlb: ipi sent\n");
2605 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2606 (smp_active_mask & ~md->mi.gd_cpumask)) {
2609 #ifdef SMP_INVLTLB_DEBUG
2611 if (++count == 400000000) {
2612 print_backtrace(-1);
2613 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2614 "rflags %016jx retry",
2615 (long)md->gd_invltlb_ret,
2616 (long)smp_invltlb_req,
2617 (intmax_t)read_rflags());
2618 __asm __volatile ("sti");
2621 lwkt_process_ipiq();
2623 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2624 ~md->mi.gd_cpumask &
2628 kprintf("bcpu %d\n", bcpu);
2629 xgd = globaldata_find(bcpu);
2630 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2633 Debugger("giving up");
2639 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2640 crit_exit_gd(&md->mi);
2647 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2648 * bother to bump the critical section count or nested interrupt count
2649 * so only do very low level operations here.
2652 smp_invltlb_intr(void)
2654 struct mdglobaldata *md = mdcpu;
2655 struct mdglobaldata *omd;
2660 mask = smp_invltlb_req;
2663 cpu = BSFCPUMASK(mask);
2664 mask &= ~CPUMASK(cpu);
2665 omd = (struct mdglobaldata *)globaldata_find(cpu);
2666 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2673 * When called the executing CPU will send an IPI to all other CPUs
2674 * requesting that they halt execution.
2676 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2678 * - Signals all CPUs in map to stop.
2679 * - Waits for each to stop.
2686 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2687 * from executing at same time.
2690 stop_cpus(cpumask_t map)
2692 map &= smp_active_mask;
2694 /* send the Xcpustop IPI to all CPUs in map */
2695 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2697 while ((stopped_cpus & map) != map)
2705 * Called by a CPU to restart stopped CPUs.
2707 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2709 * - Signals all CPUs in map to restart.
2710 * - Waits for each to restart.
2718 restart_cpus(cpumask_t map)
2720 /* signal other cpus to restart */
2721 started_cpus = map & smp_active_mask;
2723 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2730 * This is called once the mpboot code has gotten us properly relocated
2731 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2732 * and when it returns the scheduler will call the real cpu_idle() main
2733 * loop for the idlethread. Interrupts are disabled on entry and should
2734 * remain disabled at return.
2742 * Adjust smp_startup_mask to signal the BSP that we have started
2743 * up successfully. Note that we do not yet hold the BGL. The BSP
2744 * is waiting for our signal.
2746 * We can't set our bit in smp_active_mask yet because we are holding
2747 * interrupts physically disabled and remote cpus could deadlock
2748 * trying to send us an IPI.
2750 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2754 * Interlock for finalization. Wait until mp_finish is non-zero,
2755 * then get the MP lock.
2757 * Note: We are in a critical section.
2759 * Note: we are the idle thread, we can only spin.
2761 * Note: The load fence is memory volatile and prevents the compiler
2762 * from improperly caching mp_finish, and the cpu from improperly
2765 while (mp_finish == 0)
2767 while (try_mplock() == 0)
2770 if (cpu_feature & CPUID_TSC) {
2772 * The BSP is constantly updating tsc0_offset, figure out
2773 * the relative difference to synchronize ktrdump.
2775 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2778 /* BSP may have changed PTD while we're waiting for the lock */
2781 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2785 /* Build our map of 'other' CPUs. */
2786 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2788 kprintf(" %d", mycpu->gd_cpuid);
2790 /* A quick check from sanity claus */
2791 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
2792 if (mycpu->gd_cpuid != apic_id) {
2793 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2794 kprintf("SMP: apic_id = %d lapicid %d\n",
2795 apic_id, (lapic->id & 0xff000000) >> 24);
2797 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2799 panic("cpuid mismatch! boom!!");
2802 /* Initialize AP's local APIC for irq's */
2803 apic_initialize(FALSE);
2805 /* Set memory range attributes for this CPU to match the BSP */
2806 mem_range_AP_init();
2809 * Once we go active we must process any IPIQ messages that may
2810 * have been queued, because no actual IPI will occur until we
2811 * set our bit in the smp_active_mask. If we don't the IPI
2812 * message interlock could be left set which would also prevent
2815 * The idle loop doesn't expect the BGL to be held and while
2816 * lwkt_switch() normally cleans things up this is a special case
2817 * because we returning almost directly into the idle loop.
2819 * The idle thread is never placed on the runq, make sure
2820 * nothing we've done put it there.
2822 KKASSERT(get_mplock_count(curthread) == 1);
2823 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2826 * Enable interrupts here. idle_restore will also do it, but
2827 * doing it here lets us clean up any strays that got posted to
2828 * the CPU during the AP boot while we are still in a critical
2831 __asm __volatile("sti; pause; pause"::);
2832 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2834 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2835 lwkt_process_ipiq();
2838 * Releasing the mp lock lets the BSP finish up the SMP init
2841 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2845 * Get SMP fully working before we start initializing devices.
2853 kprintf("Finish MP startup\n");
2854 if (cpu_feature & CPUID_TSC)
2855 tsc0_offset = rdtsc();
2858 while (smp_active_mask != smp_startup_mask) {
2860 if (cpu_feature & CPUID_TSC)
2861 tsc0_offset = rdtsc();
2863 while (try_mplock() == 0)
2867 kprintf("Active CPU Mask: %016jx\n",
2868 (uintmax_t)smp_active_mask);
2872 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2875 cpu_send_ipiq(int dcpu)
2877 if (CPUMASK(dcpu) & smp_active_mask)
2878 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2881 #if 0 /* single_apic_ipi_passive() not working yet */
2883 * Returns 0 on failure, 1 on success
2886 cpu_send_ipiq_passive(int dcpu)
2889 if (CPUMASK(dcpu) & smp_active_mask) {
2890 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2891 APIC_DELMODE_FIXED);
2897 struct mptable_lapic_cbarg1 {
2900 u_int ht_apicid_mask;
2904 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2906 const struct PROCENTRY *ent;
2907 struct mptable_lapic_cbarg1 *arg = xarg;
2913 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2917 if (ent->apic_id < 32) {
2918 arg->ht_apicid_mask |= 1 << ent->apic_id;
2919 } else if (arg->ht_fixup) {
2920 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2926 struct mptable_lapic_cbarg2 {
2933 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2935 const struct PROCENTRY *ent;
2936 struct mptable_lapic_cbarg2 *arg = xarg;
2942 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2943 KKASSERT(!arg->found_bsp);
2947 if (processor_entry(ent, arg->cpu))
2950 if (arg->logical_cpus) {
2951 struct PROCENTRY proc;
2955 * Create fake mptable processor entries
2956 * and feed them to processor_entry() to
2957 * enumerate the logical CPUs.
2959 bzero(&proc, sizeof(proc));
2961 proc.cpu_flags = PROCENTRY_FLAG_EN;
2962 proc.apic_id = ent->apic_id;
2964 for (i = 1; i < arg->logical_cpus; i++) {
2966 processor_entry(&proc, arg->cpu);
2974 mptable_imcr(struct mptable_pos *mpt)
2976 /* record whether PIC or virtual-wire mode */
2977 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2978 mpt->mp_fps->mpfb2 & 0x80);
2981 struct mptable_lapic_enumerator {
2982 struct lapic_enumerator enumerator;
2983 vm_paddr_t mpfps_paddr;
2987 mptable_lapic_default(void)
2989 int ap_apicid, bsp_apicid;
2991 mp_naps = 1; /* exclude BSP */
2993 /* Map local apic before the id field is accessed */
2994 lapic_init(DEFAULT_APIC_BASE);
2996 bsp_apicid = APIC_ID(lapic->id);
2997 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3000 mp_set_cpuids(0, bsp_apicid);
3001 /* one and only AP */
3002 mp_set_cpuids(1, ap_apicid);
3008 * ID_TO_CPU(N), APIC ID to logical CPU table
3009 * CPU_TO_ID(N), logical CPU to APIC ID table
3012 mptable_lapic_enumerate(struct lapic_enumerator *e)
3014 struct mptable_pos mpt;
3015 struct mptable_lapic_cbarg1 arg1;
3016 struct mptable_lapic_cbarg2 arg2;
3018 int error, logical_cpus = 0;
3019 vm_offset_t lapic_addr;
3020 vm_paddr_t mpfps_paddr;
3022 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
3023 KKASSERT(mpfps_paddr != 0);
3025 error = mptable_map(&mpt, mpfps_paddr);
3027 panic("mptable_lapic_enumerate mptable_map failed\n");
3029 KKASSERT(mpt.mp_fps != NULL);
3032 * Check for use of 'default' configuration
3034 if (mpt.mp_fps->mpfb1 != 0) {
3035 mptable_lapic_default();
3036 mptable_unmap(&mpt);
3041 KKASSERT(cth != NULL);
3043 /* Save local apic address */
3044 lapic_addr = (vm_offset_t)cth->apic_address;
3045 KKASSERT(lapic_addr != 0);
3048 * Find out how many CPUs do we have
3050 bzero(&arg1, sizeof(arg1));
3051 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3053 error = mptable_iterate_entries(cth,
3054 mptable_lapic_pass1_callback, &arg1);
3056 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3057 KKASSERT(arg1.cpu_count != 0);
3059 /* See if we need to fixup HT logical CPUs. */
3060 if (arg1.ht_fixup) {
3061 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3063 if (logical_cpus != 0)
3064 arg1.cpu_count *= logical_cpus;
3066 mp_naps = arg1.cpu_count;
3068 /* Qualify the numbers again, after possible HT fixup */
3069 if (mp_naps > MAXCPU) {
3070 kprintf("Warning: only using %d of %d available CPUs!\n",
3076 --mp_naps; /* subtract the BSP */
3079 * Link logical CPU id to local apic id
3081 bzero(&arg2, sizeof(arg2));
3083 arg2.logical_cpus = logical_cpus;
3085 error = mptable_iterate_entries(cth,
3086 mptable_lapic_pass2_callback, &arg2);
3088 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3089 KKASSERT(arg2.found_bsp);
3091 /* Map local apic */
3092 lapic_init(lapic_addr);
3094 mptable_unmap(&mpt);
3098 mptable_lapic_probe(struct lapic_enumerator *e)
3100 vm_paddr_t mpfps_paddr;
3102 mpfps_paddr = mptable_probe();
3103 if (mpfps_paddr == 0)
3106 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3110 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3112 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3113 .lapic_probe = mptable_lapic_probe,
3114 .lapic_enumerate = mptable_lapic_enumerate
3119 mptable_apic_register(void)
3121 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
3123 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);