2 * Copyright (c) 1999-2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $Id: maestro_reg.h,v 1.10 2000/08/29 17:27:29 taku Exp $
27 * $FreeBSD: src/sys/dev/sound/pci/maestro_reg.h,v 1.1.2.4 2002/04/22 15:49:32 cg Exp $
28 * $DragonFly: src/sys/dev/sound/pci/maestro_reg.h,v 1.2 2003/06/17 04:28:30 dillon Exp $
31 #ifndef MAESTRO_REG_H_INCLUDED
32 #define MAESTRO_REG_H_INCLUDED
34 /* -----------------------------
35 * PCI config registers
38 /* Legacy emulation */
39 #define CONF_LEGACY 0x40
41 #define LEGACY_DISABLED 0x8000
43 /* Chip configurations */
44 #define CONF_MAESTRO 0x50
45 #define MAESTRO_CHIBUS 0x00100000
46 #define MAESTRO_POSTEDWRITE 0x00000080
47 #define MAESTRO_DMA_PCITIMING 0x00000040
48 #define MAESTRO_SWAP_LR 0x00000010
50 /* ACPI configurations */
51 #define CONF_ACPI_STOPCLOCK 0x54
52 #define ACPI_PART_2ndC_CLOCK 15
53 #define ACPI_PART_CODEC_CLOCK 14
54 #define ACPI_PART_978 13 /* Docking station or something */
55 #define ACPI_PART_SPDIF 12
56 #define ACPI_PART_GLUE 11 /* What? */
57 #define ACPI_PART_DAA 10
58 #define ACPI_PART_PCI_IF 9
59 #define ACPI_PART_HW_VOL 8
60 #define ACPI_PART_GPIO 7
61 #define ACPI_PART_ASSP 6
62 #define ACPI_PART_SB 5
63 #define ACPI_PART_FM 4
64 #define ACPI_PART_RINGBUS 3
65 #define ACPI_PART_MIDI 2
66 #define ACPI_PART_GAME_PORT 1
67 #define ACPI_PART_WP 0
69 /* Power management */
70 #define CONF_PM_PTR 0x34 /* BYTE R */
71 #define PM_CID 0 /* BYTE R */
73 #define PM_CTRL 4 /* BYTE RW */
74 #define PPMI_D0 0 /* Full power */
75 #define PPMI_D1 1 /* Medium power */
76 #define PPMI_D2 2 /* Low power */
77 #define PPMI_D3 3 /* Turned off */
80 /* -----------------------------
84 /* Direct Sound Processor (aka WP) */
85 #define PORT_DSP_DATA 0x00 /* WORD RW */
86 #define PORT_DSP_INDEX 0x02 /* WORD RW */
87 #define PORT_INT_STAT 0x04 /* WORD RW */
88 #define PORT_SAMPLE_CNT 0x06 /* WORD RO */
91 #define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */
92 #define PORT_WAVCACHE_DATA 0x12 /* WORD RW */
93 #define WAVCACHE_PCMBAR 0x1fc
94 #define WAVCACHE_WTBAR 0x1f0
95 #define WAVCACHE_BASEADDR_SHIFT 12
97 #define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8
98 #define WAVCACHE_CHCTL_U8 0x0004
99 #define WAVCACHE_CHCTL_STEREO 0x0002
100 #define WAVCACHE_CHCTL_DECREMENTAL 0x0001
102 #define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */
103 #define WAVCACHE_EXTRA_CH_ENABLED 0x0200
104 #define WAVCACHE_ENABLED 0x0100
105 #define WAVCACHE_CH_60_ENABLED 0x0080
106 #define WAVCACHE_WTSIZE_MASK 0x0060
107 #define WAVCACHE_WTSIZE_1MB 0x0000
108 #define WAVCACHE_WTSIZE_2MB 0x0020
109 #define WAVCACHE_WTSIZE_4MB 0x0040
110 #define WAVCACHE_WTSIZE_8MB 0x0060
111 #define WAVCACHE_SGC_MASK 0x000c
112 #define WAVCACHE_SGC_DISABLED 0x0000
113 #define WAVCACHE_SGC_40_47 0x0004
114 #define WAVCACHE_SGC_32_47 0x0008
115 #define WAVCACHE_TESTMODE 0x0001
117 /* Host Interruption */
118 #define PORT_HOSTINT_CTRL 0x18 /* WORD RW */
119 #define HOSTINT_CTRL_SOFT_RESET 0x8000
120 #define HOSTINT_CTRL_DSOUND_RESET 0x4000
121 #define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400
122 #define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100
123 #define HOSTINT_CTRL_HWVOL_ENABLED 0x0040
124 #define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010
125 #define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008
126 #define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004
127 #define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002
128 #define HOSTINT_CTRL_SB_INT_ENABLED 0x0001
130 #define PORT_HOSTINT_STAT 0x1a /* BYTE RW */
131 #define HOSTINT_STAT_HWVOL 0x40
132 #define HOSTINT_STAT_ASSP 0x10
133 #define HOSTINT_STAT_ISDN 0x08
134 #define HOSTINT_STAT_DSOUND 0x04
135 #define HOSTINT_STAT_MPU401 0x02
136 #define HOSTINT_STAT_SB 0x01
138 /* Hardware volume */
139 #define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */
140 #define PORT_HWVOL_VOICE 0x1d /* BYTE RW */
141 #define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */
142 #define PORT_HWVOL_MASTER 0x1f /* BYTE RW */
143 #define HWVOL_NOP 0x88
144 #define HWVOL_MUTE 0x99
145 #define HWVOL_UP 0xaa
146 #define HWVOL_DOWN 0x66
149 #define PORT_CODEC_CMD 0x30 /* BYTE W */
150 #define CODEC_CMD_READ 0x80
151 #define CODEC_CMD_WRITE 0x00
152 #define CODEC_CMD_ADDR_MASK 0x7f
154 #define PORT_CODEC_STAT 0x30 /* BYTE R */
155 #define CODEC_STAT_MASK 0x01
156 #define CODEC_STAT_RW_DONE 0x00
157 #define CODEC_STAT_PROGLESS 0x01
159 #define PORT_CODEC_REG 0x32 /* WORD RW */
161 /* Ring bus control */
162 #define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */
163 #define RINGBUS_CTRL_I2S_ENABLED 0x80000000
164 #define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000
165 #define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000
166 #define RINGBUS_CTRL_AC97_SWRESET 0x08000000
167 #define RINGBUS_CTRL_IODMA_PLAYBACK_ENABLED 0x04000000
168 #define RINGBUS_CTRL_IODMA_RECORD_ENABLED 0x02000000
170 #define RINGBUS_SRC_MIC 20
171 #define RINGBUS_SRC_I2S 16
172 #define RINGBUS_SRC_ADC 12
173 #define RINGBUS_SRC_MODEM 8
174 #define RINGBUS_SRC_DSOUND 4
175 #define RINGBUS_SRC_ASSP 0
177 #define RINGBUS_DEST_MONORAL 000
178 #define RINGBUS_DEST_STEREO 010
179 #define RINGBUS_DEST_NONE 0
180 #define RINGBUS_DEST_DAC 1
181 #define RINGBUS_DEST_MODEM_IN 2
182 #define RINGBUS_DEST_RESERVED3 3
183 #define RINGBUS_DEST_DSOUND_IN 4
184 #define RINGBUS_DEST_ASSP_IN 5
186 /* General Purpose I/O */
187 #define PORT_GPIO_DATA 0x60 /* WORD RW */
188 #define PORT_GPIO_MASK 0x64 /* WORD RW */
189 #define PORT_GPIO_DIR 0x68 /* WORD RW */
191 /* Application Specific Signal Processor */
192 #define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */
193 #define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */
194 #define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */
195 #define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */
196 #define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */
197 #define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */
198 #define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */
199 #define PORT_ASSP_INT_STAT 0xac /* BYTE RW */
202 /* -----------------------------
203 * Wave Processor Indexed Data Registers.
206 #define WPREG_DATA_PORT 0
207 #define WPREG_CRAM_PTR 1
208 #define WPREG_CRAM_DATA 2
209 #define WPREG_WAVE_DATA 3
210 #define WPREG_WAVE_PTR_LOW 4
211 #define WPREG_WAVE_PTR_HIGH 5
213 #define WPREG_TIMER_FREQ 6
214 #define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */
215 #define WP_TIMER_FREQ_PRESCALE_SHIFT 5
216 #define WP_TIMER_FREQ_DIVIDE_MASK 0x001f
217 #define WP_TIMER_FREQ_DIVIDE_SHIFT 0
219 #define WPREG_WAVE_ROMRAM 7
220 #define WP_WAVE_VIRTUAL_ENABLED 0x0400
221 #define WP_WAVE_8BITRAM_ENABLED 0x0200
222 #define WP_WAVE_DRAM_ENABLED 0x0100
223 #define WP_WAVE_RAMSPLIT_MASK 0x00ff
224 #define WP_WAVE_RAMSPLIT_SHIFT 0
226 #define WPREG_BASE 12
227 #define WP_PARAOUT_BASE_MASK 0xf000
228 #define WP_PARAOUT_BASE_SHIFT 12
229 #define WP_PARAIN_BASE_MASK 0x0f00
230 #define WP_PARAIN_BASE_SHIFT 8
231 #define WP_SERIAL0_BASE_MASK 0x00f0
232 #define WP_SERIAL0_BASE_SHIFT 4
233 #define WP_SERIAL1_BASE_MASK 0x000f
234 #define WP_SERIAL1_BASE_SHIFT 0
236 #define WPREG_TIMER_ENABLE 17
237 #define WPREG_TIMER_START 23
240 /* -----------------------------
241 * Audio Processing Unit.
243 #define APUREG_APUTYPE 0
244 #define APU_DMA_ENABLED 0x4000
245 #define APU_INT_ON_LOOP 0x2000
246 #define APU_ENDCURVE 0x1000
247 #define APU_APUTYPE_MASK 0x00f0
248 #define APU_FILTERTYPE_MASK 0x000c
249 #define APU_FILTERQ_MASK 0x0003
252 #define APU_APUTYPE_SHIFT 4
254 #define APUTYPE_INACTIVE 0
255 #define APUTYPE_16BITLINEAR 1
256 #define APUTYPE_16BITSTEREO 2
257 #define APUTYPE_8BITLINEAR 3
258 #define APUTYPE_8BITSTEREO 4
259 #define APUTYPE_8BITDIFF 5
260 #define APUTYPE_DIGITALDELAY 6
261 #define APUTYPE_DUALTAP_READER 7
262 #define APUTYPE_CORRELATOR 8
263 #define APUTYPE_INPUTMIXER 9
264 #define APUTYPE_WAVETABLE 10
265 #define APUTYPE_RATECONV 11
266 #define APUTYPE_16BITPINGPONG 12
267 /* APU type 13 through 15 are reserved. */
270 #define APU_FILTERTYPE_SHIFT 2
272 #define FILTERTYPE_2POLE_LOPASS 0
273 #define FILTERTYPE_2POLE_BANDPASS 1
274 #define FILTERTYPE_2POLE_HIPASS 2
275 #define FILTERTYPE_1POLE_LOPASS 3
276 #define FILTERTYPE_1POLE_HIPASS 4
277 #define FILTERTYPE_PASSTHROUGH 5
280 #define APU_FILTERQ_SHIFT 0
282 #define FILTERQ_LESSQ 0
283 #define FILTERQ_MOREQ 3
286 #define APUREG_FREQ_LOBYTE 2
287 #define APU_FREQ_LOBYTE_MASK 0xff00
288 #define APU_plus6dB 0x0010
291 #define APUREG_FREQ_HIWORD 3
292 #define APU_FREQ_HIWORD_MASK 0x0fff
295 #define APU_FREQ_LOBYTE_SHIFT 8
296 #define APU_FREQ_HIWORD_SHIFT 0
297 #define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000)
300 #define APUREG_WAVESPACE 4
301 #define APU_STEREO 0x8000
302 #define APU_USE_SYSMEM 0x4000
303 #define APU_PCMBAR_MASK 0x6000
304 #define APU_64KPAGE_MASK 0xff00
306 /* PCM Base Address Register selection */
307 #define APU_PCMBAR_SHIFT 13
309 /* 64KW (==128KB) Page */
310 #define APU_64KPAGE_SHIFT 8
312 /* APU register 5 - 7 */
313 #define APUREG_CURPTR 5
314 #define APUREG_ENDPTR 6
315 #define APUREG_LOOPLEN 7
318 #define APUREG_AMPLITUDE 9
319 #define APU_AMPLITUDE_NOW_MASK 0xff00
320 #define APU_AMPLITUDE_DEST_MASK 0x00ff
323 #define APU_AMPLITUDE_NOW_SHIFT 8
325 /* APU register 10 */
326 #define APUREG_POSITION 10
327 #define APU_RADIUS_MASK 0x00c0
328 #define APU_PAN_MASK 0x003f
330 /* Radius control. */
331 #define APU_RADIUS_SHIFT 6
332 #define RADIUS_CENTERCIRCLE 0
333 #define RADIUS_MIDDLE 1
334 #define RADIUS_OUTSIDE 2
337 #define APU_PAN_SHIFT 0
338 #define PAN_RIGHT 0x00
339 #define PAN_FRONT 0x08
340 #define PAN_LEFT 0x10
343 /* -----------------------------
346 #define WPWA_MAX ((1 << 22) - 1)
347 #define WPWA_MAXADDR ((1 << 23) - 1)
348 #define MAESTRO_MAXADDR ((1 << 28) - 1)
350 #endif /* MAESTRO_REG_H_INCLUDED */