sys/dev/drm/radeon/cayman_blit_shaders.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  *
  26  * $FreeBSD: head/sys/dev/drm2/radeon/cayman_blit_shaders.c 254885 2013-08-25 19:37:15Z dumbbell $
  27  */
  28
  29 #include <drm/drmP.h>
  30
  31 /*
  32  * evergreen cards need to use the 3D engine to blit data which requires
  33  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
  34  * (which normally generates the 3D state) into the DRM, we opt to use
  35  * statically generated state tables.  The regsiter state and shaders
  36  * were hand generated to support blitting functionality.  See the 3D
  37  * driver or documentation for descriptions of the registers and
  38  * shader instructions.
  39  */
  40
  41 const u32 cayman_default_state[] =
  42 {
  43         0xc0066900,
  44         0x00000000,
  45         0x00000060, /* DB_RENDER_CONTROL */
  46         0x00000000, /* DB_COUNT_CONTROL */
  47         0x00000000, /* DB_DEPTH_VIEW */
  48         0x0000002a, /* DB_RENDER_OVERRIDE */
  49         0x00000000, /* DB_RENDER_OVERRIDE2 */
  50         0x00000000, /* DB_HTILE_DATA_BASE */
  51
  52         0xc0026900,
  53         0x0000000a,
  54         0x00000000, /* DB_STENCIL_CLEAR */
  55         0x00000000, /* DB_DEPTH_CLEAR */
  56
  57         0xc0036900,
  58         0x0000000f,
  59         0x00000000, /* DB_DEPTH_INFO */
  60         0x00000000, /* DB_Z_INFO */
  61         0x00000000, /* DB_STENCIL_INFO */
  62
  63         0xc0016900,
  64         0x00000080,
  65         0x00000000, /* PA_SC_WINDOW_OFFSET */
  66
  67         0xc00d6900,
  68         0x00000083,
  69         0x0000ffff, /* PA_SC_CLIPRECT_RULE */
  70         0x00000000, /* PA_SC_CLIPRECT_0_TL */
  71         0x20002000, /* PA_SC_CLIPRECT_0_BR */
  72         0x00000000,
  73         0x20002000,
  74         0x00000000,
  75         0x20002000,
  76         0x00000000,
  77         0x20002000,
  78         0xaaaaaaaa, /* PA_SC_EDGERULE */
  79         0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
  80         0x0000000f, /* CB_TARGET_MASK */
  81         0x0000000f, /* CB_SHADER_MASK */
  82
  83         0xc0226900,
  84         0x00000094,
  85         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
  86         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
  87         0x80000000,
  88         0x20002000,
  89         0x80000000,
  90         0x20002000,
  91         0x80000000,
  92         0x20002000,
  93         0x80000000,
  94         0x20002000,
  95         0x80000000,
  96         0x20002000,
  97         0x80000000,
  98         0x20002000,
  99         0x80000000,
 100         0x20002000,
 101         0x80000000,
 102         0x20002000,
 103         0x80000000,
 104         0x20002000,
 105         0x80000000,
 106         0x20002000,
 107         0x80000000,
 108         0x20002000,
 109         0x80000000,
 110         0x20002000,
 111         0x80000000,
 112         0x20002000,
 113         0x80000000,
 114         0x20002000,
 115         0x80000000,
 116         0x20002000,
 117         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 118         0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
 119
 120         0xc0016900,
 121         0x000000d4,
 122         0x00000000, /* SX_MISC */
 123
 124         0xc0026900,
 125         0x000000d9,
 126         0x00000000, /* CP_RINGID */
 127         0x00000000, /* CP_VMID */
 128
 129         0xc0096900,
 130         0x00000100,
 131         0x00ffffff, /* VGT_MAX_VTX_INDX */
 132         0x00000000, /* VGT_MIN_VTX_INDX */
 133         0x00000000, /* VGT_INDX_OFFSET */
 134         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 135         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 136         0x00000000, /* CB_BLEND_RED */
 137         0x00000000, /* CB_BLEND_GREEN */
 138         0x00000000, /* CB_BLEND_BLUE */
 139         0x00000000, /* CB_BLEND_ALPHA */
 140
 141         0xc0016900,
 142         0x00000187,
 143         0x00000100, /* SPI_VS_OUT_ID_0 */
 144
 145         0xc0026900,
 146         0x00000191,
 147         0x00000100, /* SPI_PS_INPUT_CNTL_0 */
 148         0x00000101, /* SPI_PS_INPUT_CNTL_1 */
 149
 150         0xc0016900,
 151         0x000001b1,
 152         0x00000000, /* SPI_VS_OUT_CONFIG */
 153
 154         0xc0106900,
 155         0x000001b3,
 156         0x20000001, /* SPI_PS_IN_CONTROL_0 */
 157         0x00000000, /* SPI_PS_IN_CONTROL_1 */
 158         0x00000000, /* SPI_INTERP_CONTROL_0 */
 159         0x00000000, /* SPI_INPUT_Z */
 160         0x00000000, /* SPI_FOG_CNTL */
 161         0x00100000, /* SPI_BARYC_CNTL */
 162         0x00000000, /* SPI_PS_IN_CONTROL_2 */
 163         0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
 164         0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
 165         0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
 166         0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
 167         0x00000000, /* SPI_GPR_MGMT */
 168         0x00000000, /* SPI_LDS_MGMT */
 169         0x00000000, /* SPI_STACK_MGMT */
 170         0x00000000, /* SPI_WAVE_MGMT_1 */
 171         0x00000000, /* SPI_WAVE_MGMT_2 */
 172
 173         0xc0016900,
 174         0x000001e0,
 175         0x00000000, /* CB_BLEND0_CONTROL */
 176
 177         0xc00e6900,
 178         0x00000200,
 179         0x00000000, /* DB_DEPTH_CONTROL */
 180         0x00000000, /* DB_EQAA */
 181         0x00cc0010, /* CB_COLOR_CONTROL */
 182         0x00000210, /* DB_SHADER_CONTROL */
 183         0x00010000, /* PA_CL_CLIP_CNTL */
 184         0x00000004, /* PA_SU_SC_MODE_CNTL */
 185         0x00000100, /* PA_CL_VTE_CNTL */
 186         0x00000000, /* PA_CL_VS_OUT_CNTL */
 187         0x00000000, /* PA_CL_NANINF_CNTL */
 188         0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
 189         0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
 190         0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
 191         0x00000000, /*  */
 192         0x00000000, /*  */
 193
 194         0xc0026900,
 195         0x00000229,
 196         0x00000000, /* SQ_PGM_START_FS */
 197         0x00000000,
 198
 199         0xc0016900,
 200         0x0000023b,
 201         0x00000000, /* SQ_LDS_ALLOC_PS */
 202
 203         0xc0066900,
 204         0x00000240,
 205         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
 206         0x00000000,
 207         0x00000000,
 208         0x00000000,
 209         0x00000000,
 210         0x00000000,
 211
 212         0xc0046900,
 213         0x00000247,
 214         0x00000000, /* SQ_GS_VERT_ITEMSIZE */
 215         0x00000000,
 216         0x00000000,
 217         0x00000000,
 218
 219         0xc0116900,
 220         0x00000280,
 221         0x00000000, /* PA_SU_POINT_SIZE */
 222         0x00000000, /* PA_SU_POINT_MINMAX */
 223         0x00000008, /* PA_SU_LINE_CNTL */
 224         0x00000000, /* PA_SC_LINE_STIPPLE */
 225         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 226         0x00000000, /* VGT_HOS_CNTL */
 227         0x00000000,
 228         0x00000000,
 229         0x00000000,
 230         0x00000000,
 231         0x00000000,
 232         0x00000000,
 233         0x00000000,
 234         0x00000000,
 235         0x00000000,
 236         0x00000000,
 237         0x00000000, /* VGT_GS_MODE */
 238
 239         0xc0026900,
 240         0x00000292,
 241         0x00000000, /* PA_SC_MODE_CNTL_0 */
 242         0x00000000, /* PA_SC_MODE_CNTL_1 */
 243
 244         0xc0016900,
 245         0x000002a1,
 246         0x00000000, /* VGT_PRIMITIVEID_EN */
 247
 248         0xc0016900,
 249         0x000002a5,
 250         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
 251
 252         0xc0026900,
 253         0x000002a8,
 254         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 255         0x00000000,
 256
 257         0xc0026900,
 258         0x000002ad,
 259         0x00000000, /* VGT_REUSE_OFF */
 260         0x00000000,
 261
 262         0xc0016900,
 263         0x000002d5,
 264         0x00000000, /* VGT_SHADER_STAGES_EN */
 265
 266         0xc0016900,
 267         0x000002dc,
 268         0x0000aa00, /* DB_ALPHA_TO_MASK */
 269
 270         0xc0066900,
 271         0x000002de,
 272         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 273         0x00000000,
 274         0x00000000,
 275         0x00000000,
 276         0x00000000,
 277         0x00000000,
 278
 279         0xc0026900,
 280         0x000002e5,
 281         0x00000000, /* VGT_STRMOUT_CONFIG */
 282         0x00000000,
 283
 284         0xc01b6900,
 285         0x000002f5,
 286         0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
 287         0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
 288         0x00000000, /* PA_SC_LINE_CNTL */
 289         0x00000000, /* PA_SC_AA_CONFIG */
 290         0x00000005, /* PA_SU_VTX_CNTL */
 291         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 292         0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
 293         0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
 294         0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
 295         0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
 296         0x00000000,
 297         0x00000000,
 298         0x00000000,
 299         0x00000000,
 300         0x00000000,
 301         0x00000000,
 302         0x00000000,
 303         0x00000000,
 304         0x00000000,
 305         0x00000000,
 306         0x00000000,
 307         0x00000000,
 308         0x00000000,
 309         0x00000000,
 310         0x00000000,
 311         0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
 312         0xffffffff,
 313
 314         0xc0026900,
 315         0x00000316,
 316         0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
 317         0x00000010, /*  */
 318 };
 319
 320 const u32 cayman_vs[] =
 321 {
 322         0x00000004,
 323         0x80400400,
 324         0x0000a03c,
 325         0x95000688,
 326         0x00004000,
 327         0x15000688,
 328         0x00000000,
 329         0x88000000,
 330         0x04000000,
 331         0x67961001,
 332 #ifdef __BIG_ENDIAN
 333         0x00020000,
 334 #else
 335         0x00000000,
 336 #endif
 337         0x00000000,
 338         0x04000000,
 339         0x67961000,
 340 #ifdef __BIG_ENDIAN
 341         0x00020008,
 342 #else
 343         0x00000008,
 344 #endif
 345         0x00000000,
 346 };
 347
 348 const u32 cayman_ps[] =
 349 {
 350         0x00000004,
 351         0xa00c0000,
 352         0x00000008,
 353         0x80400000,
 354         0x00000000,
 355         0x95000688,
 356         0x00000000,
 357         0x88000000,
 358         0x00380400,
 359         0x00146b10,
 360         0x00380000,
 361         0x20146b10,
 362         0x00380400,
 363         0x40146b00,
 364         0x80380000,
 365         0x60146b00,
 366         0x00000010,
 367         0x000d1000,
 368         0xb0800000,
 369         0x00000000,
 370 };
 371
 372 const u32 cayman_ps_size = DRM_ARRAY_SIZE(cayman_ps);
 373 const u32 cayman_vs_size = DRM_ARRAY_SIZE(cayman_vs);
 374 const u32 cayman_default_size = DRM_ARRAY_SIZE(cayman_default_state);