sys/dev/drm/radeon/r600_hdmi.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Christian König.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Christian König
  25  *
  26  * $FreeBSD: head/sys/dev/drm2/radeon/r600_hdmi.c 254885 2013-08-25 19:37:15Z dumbbell $
  27  */
  28
  29 #include <linux/hdmi.h>
  30 #include <drm/drmP.h>
  31 #include <uapi_drm/radeon_drm.h>
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "r600d.h"
  35 #include "atom.h"
  36
  37 /*
  38  * HDMI color format
  39  */
  40 enum r600_hdmi_color_format {
  41         RGB = 0,
  42         YCC_422 = 1,
  43         YCC_444 = 2
  44 };
  45
  46 /*
  47  * IEC60958 status bits
  48  */
  49 enum r600_hdmi_iec_status_bits {
  50         AUDIO_STATUS_DIG_ENABLE   = 0x01,
  51         AUDIO_STATUS_V            = 0x02,
  52         AUDIO_STATUS_VCFG         = 0x04,
  53         AUDIO_STATUS_EMPHASIS     = 0x08,
  54         AUDIO_STATUS_COPYRIGHT    = 0x10,
  55         AUDIO_STATUS_NONAUDIO     = 0x20,
  56         AUDIO_STATUS_PROFESSIONAL = 0x40,
  57         AUDIO_STATUS_LEVEL        = 0x80
  58 };
  59
  60 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
  61     /*       32kHz        44.1kHz       48kHz    */
  62     /* Clock      N     CTS      N     CTS      N     CTS */
  63     {  25174,  4576,  28125,  7007,  31250,  6864,  28125 }, /*  25,20/1.001 MHz */
  64     {  25200,  4096,  25200,  6272,  28000,  6144,  25200 }, /*  25.20       MHz */
  65     {  27000,  4096,  27000,  6272,  30000,  6144,  27000 }, /*  27.00       MHz */
  66     {  27027,  4096,  27027,  6272,  30030,  6144,  27027 }, /*  27.00*1.001 MHz */
  67     {  54000,  4096,  54000,  6272,  60000,  6144,  54000 }, /*  54.00       MHz */
  68     {  54054,  4096,  54054,  6272,  60060,  6144,  54054 }, /*  54.00*1.001 MHz */
  69     {  74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /*  74.25/1.001 MHz */
  70     {  74250,  4096,  74250,  6272,  82500,  6144,  74250 }, /*  74.25       MHz */
  71     { 148351, 11648, 421875,  8918, 234375,  5824, 140625 }, /* 148.50/1.001 MHz */
  72     { 148500,  4096, 148500,  6272, 165000,  6144, 148500 }, /* 148.50       MHz */
  73     {      0,  4096,      0,  6272,      0,  6144,      0 }  /* Other */
  74 };
  75
  76 /*
  77  * calculate CTS value if it's not found in the table
  78  */
  79 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
  80 {
  81         if (*CTS == 0)
  82                 *CTS = clock * N / (128 * freq) * 1000;
  83         DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
  84                   N, *CTS, freq);
  85 }
  86
  87 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
  88 {
  89         struct radeon_hdmi_acr res;
  90         u8 i;
  91
  92         for (i = 0; r600_hdmi_predefined_acr[i].clock != clock &&
  93              r600_hdmi_predefined_acr[i].clock != 0; i++)
  94                 ;
  95         res = r600_hdmi_predefined_acr[i];
  96
  97         /* In case some CTS are missing */
  98         r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000);
  99         r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100);
 100         r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000);
 101
 102         return res;
 103 }
 104
 105 /*
 106  * update the N and CTS parameters for a given pixel clock rate
 107  */
 108 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
 109 {
 110         struct drm_device *dev = encoder->dev;
 111         struct radeon_device *rdev = dev->dev_private;
 112         struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
 113         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 114         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 115         uint32_t offset = dig->afmt->offset;
 116
 117         WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
 118         WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
 119
 120         WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
 121         WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
 122
 123         WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
 124         WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
 125 }
 126
 127 /*
 128  * build a HDMI Video Info Frame
 129  */
 130 static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
 131                                            void *buffer, size_t size)
 132 {
 133         struct drm_device *dev = encoder->dev;
 134         struct radeon_device *rdev = dev->dev_private;
 135         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 136         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 137         uint32_t offset = dig->afmt->offset;
 138         uint8_t *frame = (uint8_t*)buffer + 3;
 139
 140         /* Our header values (type, version, length) should be alright, Intel
 141          * is using the same. Checksum function also seems to be OK, it works
 142          * fine for audio infoframe. However calculated value is always lower
 143          * by 2 in comparison to fglrx. It breaks displaying anything in case
 144          * of TVs that strictly check the checksum. Hack it manually here to
 145          * workaround this issue. */
 146         frame[0x0] += 2;
 147
 148         WREG32(HDMI0_AVI_INFO0 + offset,
 149                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 150         WREG32(HDMI0_AVI_INFO1 + offset,
 151                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
 152         WREG32(HDMI0_AVI_INFO2 + offset,
 153                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
 154         WREG32(HDMI0_AVI_INFO3 + offset,
 155                 frame[0xC] | (frame[0xD] << 8));
 156 }
 157
 158 /*
 159  * build a Audio Info Frame
 160  */
 161 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
 162                                              const void *buffer, size_t size)
 163 {
 164         struct drm_device *dev = encoder->dev;
 165         struct radeon_device *rdev = dev->dev_private;
 166         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 167         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 168         uint32_t offset = dig->afmt->offset;
 169         const u8 *frame = (const u8*)buffer + 3;
 170
 171         WREG32(HDMI0_AUDIO_INFO0 + offset,
 172                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 173         WREG32(HDMI0_AUDIO_INFO1 + offset,
 174                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
 175 }
 176
 177 /*
 178  * test if audio buffer is filled enough to start playing
 179  */
 180 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
 181 {
 182         struct drm_device *dev = encoder->dev;
 183         struct radeon_device *rdev = dev->dev_private;
 184         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 185         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 186         uint32_t offset = dig->afmt->offset;
 187
 188         return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
 189 }
 190
 191 /*
 192  * have buffer status changed since last call?
 193  */
 194 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
 195 {
 196         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 197         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 198         int status, result;
 199
 200         if (!dig->afmt || !dig->afmt->enabled)
 201                 return 0;
 202
 203         status = r600_hdmi_is_audio_buffer_filled(encoder);
 204         result = dig->afmt->last_buffer_filled_status != status;
 205         dig->afmt->last_buffer_filled_status = status;
 206
 207         return result;
 208 }
 209
 210 /*
 211  * write the audio workaround status to the hardware
 212  */
 213 static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
 214 {
 215         struct drm_device *dev = encoder->dev;
 216         struct radeon_device *rdev = dev->dev_private;
 217         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 218         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 219         uint32_t offset = dig->afmt->offset;
 220         bool hdmi_audio_workaround = false; /* FIXME */
 221         u32 value;
 222
 223         if (!hdmi_audio_workaround ||
 224             r600_hdmi_is_audio_buffer_filled(encoder))
 225                 value = 0; /* disable workaround */
 226         else
 227                 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
 228         WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
 229                  value, ~HDMI0_AUDIO_TEST_EN);
 230 }
 231
 232
 233 /*
 234  * update the info frames with the data from the current display mode
 235  */
 236 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
 237 {
 238         struct drm_device *dev = encoder->dev;
 239         struct radeon_device *rdev = dev->dev_private;
 240         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 241         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 242         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 243         struct hdmi_avi_infoframe frame;
 244         uint32_t offset;
 245         ssize_t err;
 246
 247         /* Silent, r600_hdmi_enable will raise WARN for us */
 248         if (!dig->afmt->enabled)
 249                 return;
 250         offset = dig->afmt->offset;
 251
 252         r600_audio_set_clock(encoder, mode->clock);
 253
 254         WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
 255                HDMI0_NULL_SEND); /* send null packets when required */
 256
 257         WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
 258
 259         if (ASIC_IS_DCE32(rdev)) {
 260                 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
 261                        HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
 262                        HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
 263                 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
 264                        AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
 265                        AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 266         } else {
 267                 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
 268                        HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
 269                        HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
 270                        HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
 271                        HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 272         }
 273
 274         WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
 275                HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
 276                HDMI0_ACR_SOURCE); /* select SW CTS value */
 277
 278         WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
 279                HDMI0_NULL_SEND | /* send null packets when required */
 280                HDMI0_GC_SEND | /* send general control packets */
 281                HDMI0_GC_CONT); /* send general control packets every frame */
 282
 283         /* TODO: HDMI0_AUDIO_INFO_UPDATE */
 284         WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
 285                HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
 286                HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
 287                HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
 288                HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
 289
 290         WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
 291                HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
 292                HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
 293
 294         WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
 295
 296         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 297         if (err < 0) {
 298                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
 299                 return;
 300         }
 301
 302         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 303         if (err < 0) {
 304                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
 305                 return;
 306         }
 307
 308         r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 309         r600_hdmi_update_ACR(encoder, mode->clock);
 310
 311         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 312         WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 313         WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
 314         WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
 315         WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
 316
 317         r600_hdmi_audio_workaround(encoder);
 318 }
 319
 320 /*
 321  * update settings with current parameters from audio engine
 322  */
 323 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
 324 {
 325         struct drm_device *dev = encoder->dev;
 326         struct radeon_device *rdev = dev->dev_private;
 327         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 328         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 329         struct r600_audio audio = r600_audio_status(rdev);
 330         uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
 331         struct hdmi_audio_infoframe frame;
 332         uint32_t offset;
 333         uint32_t iec;
 334         ssize_t err;
 335
 336         if (!dig->afmt || !dig->afmt->enabled)
 337                 return;
 338         offset = dig->afmt->offset;
 339
 340         DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
 341                  r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
 342                   audio.channels, audio.rate, audio.bits_per_sample);
 343         DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
 344                   (int)audio.status_bits, (int)audio.category_code);
 345
 346         iec = 0;
 347         if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)
 348                 iec |= 1 << 0;
 349         if (audio.status_bits & AUDIO_STATUS_NONAUDIO)
 350                 iec |= 1 << 1;
 351         if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)
 352                 iec |= 1 << 2;
 353         if (audio.status_bits & AUDIO_STATUS_EMPHASIS)
 354                 iec |= 1 << 3;
 355
 356         iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);
 357
 358         switch (audio.rate) {
 359         case 32000:
 360                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
 361                 break;
 362         case 44100:
 363                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
 364                 break;
 365         case 48000:
 366                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
 367                 break;
 368         case 88200:
 369                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
 370                 break;
 371         case 96000:
 372                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
 373                 break;
 374         case 176400:
 375                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
 376                 break;
 377         case 192000:
 378                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
 379                 break;
 380         }
 381
 382         WREG32(HDMI0_60958_0 + offset, iec);
 383
 384         iec = 0;
 385         switch (audio.bits_per_sample) {
 386         case 16:
 387                 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);
 388                 break;
 389         case 20:
 390                 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);
 391                 break;
 392         case 24:
 393                 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);
 394                 break;
 395         }
 396         if (audio.status_bits & AUDIO_STATUS_V)
 397                 iec |= 0x5 << 16;
 398         WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
 399
 400         err = hdmi_audio_infoframe_init(&frame);
 401         if (err < 0) {
 402                 DRM_ERROR("failed to setup audio infoframe\n");
 403                 return;
 404         }
 405
 406         frame.channels = audio.channels;
 407
 408         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
 409         if (err < 0) {
 410                 DRM_ERROR("failed to pack audio infoframe\n");
 411                 return;
 412         }
 413
 414         r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
 415         r600_hdmi_audio_workaround(encoder);
 416 }
 417
 418 /*
 419  * enable the HDMI engine
 420  */
 421 void r600_hdmi_enable(struct drm_encoder *encoder)
 422 {
 423         struct drm_device *dev = encoder->dev;
 424         struct radeon_device *rdev = dev->dev_private;
 425         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 426         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 427         uint32_t offset;
 428         u32 hdmi;
 429
 430         if (ASIC_IS_DCE6(rdev))
 431                 return;
 432
 433         /* Silent, r600_hdmi_enable will raise WARN for us */
 434         if (dig->afmt->enabled)
 435                 return;
 436         offset = dig->afmt->offset;
 437
 438         /* Older chipsets require setting HDMI and routing manually */
 439         if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
 440                 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;
 441                 switch (radeon_encoder->encoder_id) {
 442                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 443                         WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
 444                                  ~AVIVO_TMDSA_CNTL_HDMI_EN);
 445                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
 446                         break;
 447                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 448                         WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
 449                                  ~AVIVO_LVTMA_CNTL_HDMI_EN);
 450                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
 451                         break;
 452                 case ENCODER_OBJECT_ID_INTERNAL_DDI:
 453                         WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN);
 454                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
 455                         break;
 456                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 457                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
 458                         break;
 459                 default:
 460                         dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
 461                                 radeon_encoder->encoder_id);
 462                         break;
 463                 }
 464                 WREG32(HDMI0_CONTROL + offset, hdmi);
 465         }
 466
 467         if (rdev->irq.installed) {
 468                 /* if irq is available use it */
 469                 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
 470         }
 471
 472         dig->afmt->enabled = true;
 473
 474         DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
 475                   offset, radeon_encoder->encoder_id);
 476 }
 477
 478 /*
 479  * disable the HDMI engine
 480  */
 481 void r600_hdmi_disable(struct drm_encoder *encoder)
 482 {
 483         struct drm_device *dev = encoder->dev;
 484         struct radeon_device *rdev = dev->dev_private;
 485         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 486         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 487         uint32_t offset;
 488
 489         if (ASIC_IS_DCE6(rdev))
 490                 return;
 491
 492         /* Called for ATOM_ENCODER_MODE_HDMI only */
 493         if (!dig || !dig->afmt) {
 494                 return;
 495         }
 496         if (!dig->afmt->enabled)
 497                 return;
 498         offset = dig->afmt->offset;
 499
 500         DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
 501                   offset, radeon_encoder->encoder_id);
 502
 503         /* disable irq */
 504         radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
 505
 506         /* Older chipsets not handled by AtomBIOS */
 507         if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
 508                 switch (radeon_encoder->encoder_id) {
 509                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 510                         WREG32_P(AVIVO_TMDSA_CNTL, 0,
 511                                  ~AVIVO_TMDSA_CNTL_HDMI_EN);
 512                         break;
 513                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 514                         WREG32_P(AVIVO_LVTMA_CNTL, 0,
 515                                  ~AVIVO_LVTMA_CNTL_HDMI_EN);
 516                         break;
 517                 case ENCODER_OBJECT_ID_INTERNAL_DDI:
 518                         WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN);
 519                         break;
 520                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 521                         break;
 522                 default:
 523                         dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
 524                                 radeon_encoder->encoder_id);
 525                         break;
 526                 }
 527                 WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK);
 528         }
 529
 530         dig->afmt->enabled = false;
 531 }