2 * Copyright (c) 2000, 2002 M. Warner Losh. All Rights Reserved.
3 * Copyright (c) 1997 Ted Faber All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice immediately at the beginning of the file, without modification,
11 * this list of conditions, and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Absolutely no warranty of function or purpose is made by the author
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/pccard/pcic_pci.c,v 1.54.2.22 2003/02/26 18:42:00 imp Exp $
30 * $DragonFly: src/sys/bus/pccard/Attic/pcic_pci.c,v 1.2 2003/06/17 04:28:55 dillon Exp $
33 #include <sys/param.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/sysctl.h>
38 #include <sys/systm.h>
40 #if __FreeBSD_version < 500000
41 #include <pci/pcireg.h>
42 #include <pci/pcivar.h>
44 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pcivar.h>
48 #include <pccard/pcic_pci.h>
49 #include <pccard/i82365.h>
50 #include <pccard/cardinfo.h>
51 #include <pccard/slot.h>
52 #include <pccard/pcicvar.h>
54 #include <dev/pccard/pccardvar.h>
57 #define PRVERB(x) do { \
58 if (bootverbose) { device_printf x; } \
61 static int pcic_pci_get_memory(device_t dev);
63 SYSCTL_DECL(_hw_pcic);
65 static int pcic_ignore_function_1 = 0;
66 TUNABLE_INT("hw.pcic.ignore_function_1", &pcic_ignore_function_1);
67 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_function_1, CTLFLAG_RD,
68 &pcic_ignore_function_1, 0,
69 "When set, driver ignores pci function 1 of the bridge. This option\n\
70 is obsolete and will be deleted before FreeBSD 4.8.");
73 * The following should be a hint, so we can do it on a per device
74 * instance, but this is convenient. Do not set this unless pci
75 * routing doesn't work. It is purposely vague and undocumented
76 * at the moment. Sadly, this seems to be needed way too often.
78 static int pcic_intr_path = (int)pcic_iw_pci;
79 TUNABLE_INT("hw.pcic.intr_path", &pcic_intr_path);
80 SYSCTL_INT(_hw_pcic, OID_AUTO, intr_path, CTLFLAG_RD, &pcic_intr_path, 0,
81 "Which path to send the interrupts over. Normally interrupts for\n\
82 cardbus bridges are routed over the PCI bus (2). However, some laptops\n\
83 will hang when using PCI interrupts due to bugs in this code. Those\n\
84 bugs can be worked around by forcings ISA interrupts (1).");
86 static int pcic_init_routing = 0;
87 TUNABLE_INT("hw.pcic.init_routing", &pcic_init_routing);
88 SYSCTL_INT(_hw_pcic, OID_AUTO, init_routing, CTLFLAG_RD,
89 &pcic_init_routing, 0,
90 "Force the interrupt routing to be initialized on those bridges where\n\
91 doing so will cause probelms. This is very rare and generally is not\n\
92 needed. The default of 0 is almost always appropriate. Only set to 1 if\n\
93 instructed to do so for debugging. Only TI bridges are affected by this\n\
94 option, and what the code does is of dubious value. This option is obsolete\n\
95 and will be deleted before FreeBSD 4.8.");
97 static int pcic_ignore_pci = 0;
98 TUNABLE_INT("hw.pcic.ignore_pci", &pcic_ignore_pci);
99 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_pci, CTLFLAG_RD,
101 "When set, driver ignores pci cardbus bridges it would otherwise claim.\n\
102 Generally speaking, this option is not needed for anything other than as an\n\
105 static int pcic_pd6729_intr_path = (int)pcic_iw_isa;
106 TUNABLE_INT("hw.pcic.pd6729_intr_path", &pcic_pd6729_intr_path);
107 SYSCTL_INT(_hw_pcic, OID_AUTO, pd6729_intr_path, CTLFLAG_RD,
108 &pcic_pd6729_intr_path, 0,
109 "Determine the interrupt path or method for Cirrus Logic PD6729 and\n\
110 similar I/O space based pcmcia bridge. Chips on a PCI expansion card need\n\
111 a value of 2, while chips installed in a laptop need a value of 1 (which is\n\
112 also the default). This is similar to hw.pcic.intr_path, but separate so\n\
113 that it can default to ISA when intr_path defaults to PCI.");
115 static int pcic_ti12xx_enable_pci_clock = 0;
116 TUNABLE_INT("hw.pcic.ti12xx_enable_pci_clock", &pcic_ti12xx_enable_pci_clock);
117 SYSCTL_INT(_hw_pcic, OID_AUTO, ti12xx_enable_pci_clock, CTLFLAG_RD,
118 &pcic_ti12xx_enable_pci_clock, 0,
119 "Some TI-12xx parts need to have the PCI clock enabled. These designs do\n\
120 not provide a clock themselves. Most of the reference boards have the\n\
121 required oscillator parts, so the number of machines that needs this to be\n\
122 set is vanishingly small.");
124 static void pcic_pci_cardbus_init(device_t);
125 static pcic_intr_way_t pcic_pci_gen_func;
126 static pcic_intr_way_t pcic_pci_gen_csc;
127 static pcic_intr_mapirq_t pcic_pci_gen_mapirq;
129 static pcic_intr_way_t pcic_pci_oz67xx_func;
130 static pcic_intr_way_t pcic_pci_oz67xx_csc;
131 static pcic_init_t pcic_pci_oz67xx_init;
133 static pcic_intr_way_t pcic_pci_oz68xx_func;
134 static pcic_intr_way_t pcic_pci_oz68xx_csc;
135 static pcic_init_t pcic_pci_oz68xx_init;
137 static pcic_intr_way_t pcic_pci_pd6729_func;
138 static pcic_intr_way_t pcic_pci_pd6729_csc;
139 static pcic_init_t pcic_pci_pd6729_init;
141 static pcic_intr_way_t pcic_pci_pd68xx_func;
142 static pcic_intr_way_t pcic_pci_pd68xx_csc;
143 static pcic_init_t pcic_pci_pd68xx_init;
145 static pcic_intr_way_t pcic_pci_ricoh_func;
146 static pcic_intr_way_t pcic_pci_ricoh_csc;
147 static pcic_init_t pcic_pci_ricoh_init;
149 static pcic_intr_way_t pcic_pci_ti113x_func;
150 static pcic_intr_way_t pcic_pci_ti113x_csc;
151 static pcic_init_t pcic_pci_ti_init;
153 static pcic_intr_way_t pcic_pci_ti12xx_func;
154 static pcic_intr_way_t pcic_pci_ti12xx_csc;
156 static pcic_intr_way_t pcic_pci_topic_func;
157 static pcic_intr_way_t pcic_pci_topic_csc;
158 static pcic_init_t pcic_pci_topic_init;
160 static struct pcic_chip pcic_pci_oz67xx_chip = {
161 pcic_pci_oz67xx_func,
167 static struct pcic_chip pcic_pci_oz68xx_chip = {
168 pcic_pci_oz68xx_func,
174 static struct pcic_chip pcic_pci_pd6729_chip = {
175 pcic_pci_pd6729_func,
181 static struct pcic_chip pcic_pci_pd68xx_chip = {
182 pcic_pci_pd68xx_func,
188 static struct pcic_chip pcic_pci_ricoh_chip = {
195 static struct pcic_chip pcic_pci_ti113x_chip = {
196 pcic_pci_ti113x_func,
202 static struct pcic_chip pcic_pci_ti12xx_chip = {
203 pcic_pci_ti12xx_func,
209 static struct pcic_chip pcic_pci_topic_chip = {
216 static struct pcic_chip pcic_pci_generic_chip = {
220 pcic_pci_cardbus_init
223 /* Chipset specific flags */
224 #define TI_NO_MFUNC 0x10000
226 struct pcic_pci_table
232 struct pcic_chip *chip;
233 } pcic_pci_devs[] = {
234 { PCIC_ID_OMEGA_82C094, "Omega 82C094G",
235 PCIC_I82365, PCIC_DF_POWER, &pcic_pci_pd6729_chip },
236 { PCIC_ID_CLPD6729, "Cirrus Logic PD6729/6730 PCI-PCMCIA Bridge",
237 PCIC_PD6729, PCIC_PD_POWER, &pcic_pci_pd6729_chip },
238 { PCIC_ID_CLPD6832, "Cirrus Logic PD6832 PCI-CardBus Bridge",
239 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
240 { PCIC_ID_CLPD6833, "Cirrus Logic PD6833 PCI-CardBus Bridge",
241 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
242 { PCIC_ID_CLPD6834, "Cirrus Logic PD6834 PCI-CardBus Bridge",
243 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
244 { PCIC_ID_OZ6729, "O2micro OZ6729 PC-Card Bridge",
245 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
246 { PCIC_ID_OZ6730, "O2micro OZ6730 PC-Card Bridge",
247 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
248 { PCIC_ID_OZ6832, "O2micro 6832/6833 PCI-Cardbus Bridge",
249 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
250 { PCIC_ID_OZ6860, "O2micro 6836/6860 PCI-Cardbus Bridge",
251 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
252 { PCIC_ID_OZ6872, "O2micro 6812/6872 PCI-Cardbus Bridge",
253 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
254 { PCIC_ID_OZ6912, "O2micro 6912 PCI-Cardbus Bridge",
255 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
256 { PCIC_ID_OZ6922, "O2micro 6922 PCI-Cardbus Bridge",
257 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
258 { PCIC_ID_OZ6933, "O2micro 6933 PCI-Cardbus Bridge",
259 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
260 { PCIC_ID_RICOH_RL5C465, "Ricoh RL5C465 PCI-CardBus Bridge",
261 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
262 { PCIC_ID_RICOH_RL5C475, "Ricoh RL5C475 PCI-CardBus Bridge",
263 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
264 { PCIC_ID_RICOH_RL5C476, "Ricoh RL5C476 PCI-CardBus Bridge",
265 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
266 { PCIC_ID_RICOH_RL5C477, "Ricoh RL5C477 PCI-CardBus Bridge",
267 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
268 { PCIC_ID_RICOH_RL5C478, "Ricoh RL5C478 PCI-CardBus Bridge",
269 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
270 { PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge",
271 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_generic_chip },
272 { PCIC_ID_TI1031, "TI PCI-1031 PCI-PCMCIA Bridge",
273 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
274 { PCIC_ID_TI1130, "TI PCI-1130 PCI-CardBus Bridge",
275 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
276 { PCIC_ID_TI1131, "TI PCI-1131 PCI-CardBus Bridge",
277 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
278 { PCIC_ID_TI1210, "TI PCI-1210 PCI-CardBus Bridge",
279 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
280 { PCIC_ID_TI1211, "TI PCI-1211 PCI-CardBus Bridge",
281 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
282 { PCIC_ID_TI1220, "TI PCI-1220 PCI-CardBus Bridge",
283 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
284 { PCIC_ID_TI1221, "TI PCI-1221 PCI-CardBus Bridge",
285 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
286 { PCIC_ID_TI1225, "TI PCI-1225 PCI-CardBus Bridge",
287 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
288 { PCIC_ID_TI1250, "TI PCI-1250 PCI-CardBus Bridge",
289 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
290 &pcic_pci_ti12xx_chip },
291 { PCIC_ID_TI1251, "TI PCI-1251 PCI-CardBus Bridge",
292 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
293 &pcic_pci_ti12xx_chip },
294 { PCIC_ID_TI1251B, "TI PCI-1251B PCI-CardBus Bridge",
295 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
296 &pcic_pci_ti12xx_chip },
297 { PCIC_ID_TI1260, "TI PCI-1260 PCI-CardBus Bridge",
298 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
299 { PCIC_ID_TI1260B, "TI PCI-1260B PCI-CardBus Bridge",
300 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
301 { PCIC_ID_TI1410, "TI PCI-1410 PCI-CardBus Bridge",
302 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
303 { PCIC_ID_TI1420, "TI PCI-1420 PCI-CardBus Bridge",
304 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
305 { PCIC_ID_TI1421, "TI PCI-1421 PCI-CardBus Bridge",
306 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
307 { PCIC_ID_TI1450, "TI PCI-1450 PCI-CardBus Bridge",
308 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
309 &pcic_pci_ti12xx_chip },
310 { PCIC_ID_TI1451, "TI PCI-1451 PCI-CardBus Bridge",
311 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
312 { PCIC_ID_TI1510, "TI PCI-1510 PCI-CardBus Bridge",
313 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
314 { PCIC_ID_TI1520, "TI PCI-1520 PCI-CardBus Bridge",
315 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
316 { PCIC_ID_TI4410, "TI PCI-4410 PCI-CardBus Bridge",
317 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
318 { PCIC_ID_TI4450, "TI PCI-4450 PCI-CardBus Bridge",
319 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
320 { PCIC_ID_TI4451, "TI PCI-4451 PCI-CardBus Bridge",
321 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
322 { PCIC_ID_TI4510, "TI PCI-4510 PCI-CardBus Bridge",
323 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
324 { PCIC_ID_TOPIC95, "Toshiba ToPIC95 PCI-CardBus Bridge",
325 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
326 { PCIC_ID_TOPIC95B, "Toshiba ToPIC95B PCI-CardBus Bridge",
327 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
328 { PCIC_ID_TOPIC97, "Toshiba ToPIC97 PCI-CardBus Bridge",
329 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
330 { PCIC_ID_TOPIC100, "Toshiba ToPIC100 PCI-CardBus Bridge",
331 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
332 { 0, NULL, 0, 0, NULL }
336 * Read a register from the PCIC.
339 pcic_pci_getb2(struct pcic_slot *sp, int reg)
341 return (bus_space_read_1(sp->bst, sp->bsh, sp->offset + reg));
345 * Write a register on the PCIC
348 pcic_pci_putb2(struct pcic_slot *sp, int reg, unsigned char val)
350 bus_space_write_1(sp->bst, sp->bsh, sp->offset + reg, val);
354 * lookup inside the table
356 static struct pcic_pci_table *
357 pcic_pci_lookup(u_int32_t devid, struct pcic_pci_table *tbl)
360 if (tbl->devid == devid)
368 * The standard way to control fuction interrupts is via bit 7 in the BCR
369 * register. Some data sheets indicate that this is just for "intterupts"
370 * while others are clear that it is for function interrupts. When this
371 * bit is set, function interrupts are routed via the ExCA register. When
372 * this bit is clear, they are routed via the PCI bus, usually via the int
373 * in the INTPIN register.
376 pcic_pci_gen_func(struct pcic_slot *sp, enum pcic_intr_way way)
380 bcr = pci_read_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, 2);
381 if (way == pcic_iw_pci)
382 bcr &= ~CB_BCR_INT_EXCA;
384 bcr |= CB_BCR_INT_EXCA;
385 pci_write_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
390 pcic_pci_gen_csc(struct pcic_slot *sp, enum pcic_intr_way way)
396 * The O2micro OZ67xx chips functions.
399 pcic_pci_oz67xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
401 return (pcic_pci_gen_func(sp, way));
405 pcic_pci_oz67xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
408 * Need datasheet to find out what's going on. However, the
409 * 68xx datasheets are so vague that it is hard to know what
410 * the right thing to do is.
418 pcic_pci_oz67xx_init(device_t dev)
420 device_printf(dev, "Warning: O2micro OZ67xx chips may not work\n");
421 pcic_pci_cardbus_init(dev);
425 * The O2micro OZ68xx chips functions.
428 pcic_pci_oz68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
430 return (pcic_pci_gen_func(sp, way));
434 pcic_pci_oz68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
437 * The 68xx datasheets make it hard to know what the right thing
438 * to do here is. We do what we know, which is nothing, and
446 pcic_pci_oz68xx_init(device_t dev)
449 * This is almost certainly incomplete.
451 device_printf(dev, "Warning: O2micro OZ68xx chips may not work\n");
452 pcic_pci_cardbus_init(dev);
456 * The Cirrus Logic PD6729/30. These are weird beasts, so be careful.
457 * They are ISA parts glued to the PCI bus and do not follow the yenta
458 * specification for cardbus bridges. They seem to be similar to the
459 * intel parts that were also cloned by o2micro and maybe others, but
460 * they are so much more common that the author doesn't have experience
461 * with them to know for sure.
464 pcic_pci_pd6729_func(struct pcic_slot *sp, enum pcic_intr_way way)
467 * For pci interrupts, we need to set bit 3 of extension register
468 * 3 to 1. For ISA interrupts, we need to clear it.
470 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
471 if (way == pcic_iw_pci)
472 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
474 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
480 pcic_pci_pd6729_csc(struct pcic_slot *sp, enum pcic_intr_way way)
483 * For pci interrupts, we need to set bit 4 of extension register
484 * 3 to 1. For ISA interrupts, we need to clear it.
486 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
487 if (way == pcic_iw_pci)
488 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
490 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
497 pcic_pci_pd6729_init(device_t dev)
499 struct pcic_softc *sc = device_get_softc(dev);
502 * Tell the chip to do its routing thing.
504 pcic_pci_pd6729_func(&sc->slots[0], sc->func_route);
505 pcic_pci_pd6729_csc(&sc->slots[0], sc->csc_route);
509 * Set up the CL-PD6832, 6833 and 6834.
512 pcic_pci_pd68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
514 return (pcic_pci_gen_func(sp, way));
518 pcic_pci_pd68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
520 struct pcic_softc *sc = sp->sc;
521 device_t dev = sc->dev;
522 u_int32_t device_id = pci_get_devid(dev);
527 * CLPD6832 management interrupt enable bit is bit 11
528 * (MGMT_IRQ_ENA) in bridge control register(offset 0x3d).
529 * When on, card status interrupts are ISA controlled by
530 * the ExCA register 0x05.
532 * The CLPD6833 does things differently. It doesn't have bit
533 * 11 in the bridge control register. Instead, this
534 * functionality appears to be in the "Configuration
535 * Miscellaneous 1" register bit 1.
537 * I'm assuming that the CLPD6834 does things like the '33
539 if (device_id == PCIC_ID_CLPD6832) {
540 bcr = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
541 if (way == pcic_iw_pci)
542 bcr &= ~CLPD6832_BCR_MGMT_IRQ_ENA;
544 bcr |= CLPD6832_BCR_MGMT_IRQ_ENA;
545 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
547 if (device_id != PCIC_ID_CLPD6832) {
548 cm1 = pci_read_config(dev, CLPD6833_CFG_MISC_1, 4);
549 if (way == pcic_iw_pci)
550 cm1 &= ~CLPD6833_CM1_MGMT_EXCA_ENA;
552 cm1 |= CLPD6833_CM1_MGMT_EXCA_ENA;
553 pci_write_config(dev, CLPD6833_CFG_MISC_1, cm1, 4);
559 pcic_pci_pd68xx_init(device_t dev)
561 pcic_pci_cardbus_init(dev);
565 pcic_pci_ricoh_func(struct pcic_slot *sp, enum pcic_intr_way way)
567 return (pcic_pci_gen_func(sp, way));
571 pcic_pci_ricoh_csc(struct pcic_slot *sp, enum pcic_intr_way way)
573 struct pcic_softc *sc = sp->sc;
574 device_t dev = sc->dev;
578 * For CSC interrupts via ISA, we can't do that exactly.
579 * However, we can disable INT# routing, which is usually what
580 * we want. This is bit 7 in the field. Note, bit 6 looks
581 * interesting, but appears to be unnecessary.
583 mcr2 = pci_read_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, 2);
584 if (way == pcic_iw_pci)
585 mcr2 &= ~R5C47X_MCR2_CSC_TO_INTX_DISABLE;
587 mcr2 |= R5C47X_MCR2_CSC_TO_INTX_DISABLE;
588 pci_write_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, mcr2, 2);
594 pcic_pci_ricoh_init(device_t dev)
597 u_int32_t device_id = pci_get_devid(dev);
600 case PCIC_ID_RICOH_RL5C465:
601 case PCIC_ID_RICOH_RL5C466:
603 * Ricoh chips have a legacy bridge enable different than most
604 * Code cribbed from NEWBUS's bridge code since I can't find a
605 * datasheet for them that has register definitions.
607 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
608 brgcntl &= ~(CB_BCR_RL_3E2_EN | CB_BCR_RL_3E0_EN);
609 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
612 pcic_pci_cardbus_init(dev);
616 * TI 1030, 1130, and 1131.
619 pcic_pci_ti113x_func(struct pcic_slot *sp, enum pcic_intr_way way)
622 device_t dev = sp->sc->dev;
625 * The TI-1130 (and 1030 and 1131) have a different interrupt
626 * routing control than the newer chips. assume we're not
627 * routing either csc or func interrupts via PCI, but enable
628 * as necessary when we find someone uses PCI interrupts. In
629 * order to get any pci interrupts, PCI_IRQ_ENA (bit 5) must
630 * be set. If either PCI_IREQ (bit 4) or PCI_CSC (bit 3) are
631 * set, then set bit 5 at the same time, since setting them
632 * enables the PCI interrupt routing.
634 * It also appears necessary to set the function routing bit
635 * in the bridge control register, but cardbus_init does that
638 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
639 if (way == pcic_iw_pci)
640 cardcntl |= TI113X_CARDCNTL_PCI_IREQ;
642 cardcntl &= ~TI113X_CARDCNTL_PCI_IREQ;
643 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
644 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
646 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
647 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
649 return (pcic_pci_gen_func(sp, way));
653 pcic_pci_ti113x_csc(struct pcic_slot *sp, enum pcic_intr_way way)
656 device_t dev = sp->sc->dev;
659 * The TI-1130 (and 1030 and 1131) have a different interrupt
660 * routing control than the newer cards. assume we're not
661 * routing PCI, but enable as necessary when we find someone
662 * uses PCI interrupts. In order to get any pci interrupts,
663 * PCI_IRQ_ENA (bit 5) must be set. If either PCI_IREQ (bit
664 * 4) or PCI_CSC (bit 3) are set, then set bit 5 at the same
665 * time, since setting them enables the PCI interrupt routing.
667 * It also appears necessary to set the function routing bit
668 * in the bridge control register, but cardbus_init does that
671 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
672 if (way == pcic_iw_pci)
673 cardcntl |= TI113X_CARDCNTL_PCI_CSC;
675 cardcntl &= ~TI113X_CARDCNTL_PCI_CSC;
676 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
677 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
679 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
680 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
686 pcic_pci_ti12xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
688 u_int32_t syscntl, devcntl, cardcntl, mfunc;
689 device_t dev = sp->sc->dev;
691 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
692 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
693 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
696 * Special code for the Orinoco cards (and a few others). They
697 * seem to need this special code to make them work only over pci
698 * interrupts. Sadly, doing this code also causes problems for
699 * many laptops, so we have to make it controlled by a tunable.
700 * Actually, experience has shown that this rarely, if ever,
703 if (way == pcic_iw_pci) {
705 * pcic_init_routing seems to do nothing useful towards
706 * fixing the hang problems. I plan on removing it in
709 if (pcic_init_routing) {
710 devcntl &= ~TI113X_DEVCNTL_INTR_MASK;
711 pci_write_config(dev, TI113X_PCI_DEVICE_CONTROL,
713 syscntl |= TI113X_SYSCNTL_INTRTIE;
717 * I've had reports that we need the pci clock enabled,
718 * provide a hook to do so. The number of cards that
719 * require this is quite small.
721 if (pcic_ti12xx_enable_pci_clock) {
722 syscntl |= TI12XX_SYSCNTL_PCI_CLOCK;
723 pci_write_config(dev, TI113X_PCI_SYSTEM_CONTROL,
728 * Some PCI add-in cards don't have good EEPROMs on them,
729 * so they get this MUX register wrong. The MUX register
730 * defaults to 0, which is usually wrong for this register,
731 * so we initialize it to make sense.
733 * We don't bother to turn it off in the ISA case since it
734 * is an initialization issue.
736 * A few weird TI bridges don't have MFUNC, so filter
739 if ((sp->sc->flags & TI_NO_MFUNC) == 0) {
740 mfunc = pci_read_config(dev, TI12XX_PCI_MFUNC, 4);
742 mfunc = (mfunc & ~TI12XX_MFUNC_PIN0) |
743 TI12XX_MFUNC_PIN0_INTA;
744 if ((syscntl & TI113X_SYSCNTL_INTRTIE) == 0)
745 mfunc = (mfunc & ~TI12XX_MFUNC_PIN1) |
746 TI12XX_MFUNC_PIN1_INTB;
747 pci_write_config(dev, TI12XX_PCI_MFUNC, mfunc,
753 return (pcic_pci_gen_func(sp, way));
757 pcic_pci_ti12xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
760 * Nothing happens here. The TI12xx parts will route the
761 * CSC interrupt via PCI if ExCA register tells it to use
762 * interrupt 0. And via IRQ otherwise (except for reserved
763 * values which may or may not do anything).
765 * We just hope for the best here that doing nothing is the
772 * TI PCI-CardBus Host Adapter specific function code.
773 * This function is separated from pcic_pci_attach().
774 * Takeshi Shibagaki(shiba@jp.freebsd.org).
777 pcic_pci_ti_init(device_t dev)
779 u_int32_t syscntl, diagctl, devcntl, cardcntl;
780 u_int32_t device_id = pci_get_devid(dev);
781 int ti113x = (device_id == PCIC_ID_TI1031) ||
782 (device_id == PCIC_ID_TI1130) ||
783 (device_id == PCIC_ID_TI1131);
785 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
786 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
787 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
790 device_printf(dev, "TI113X PCI Config Reg: ");
791 if (syscntl & TI113X_SYSCNTL_CLKRUN_ENA) {
792 if (syscntl & TI113X_SYSCNTL_CLKRUN_SEL)
793 printf("[clkrun irq 12]");
795 printf("[clkrun irq 10]");
798 device_printf(dev, "TI12XX PCI Config Reg: ");
801 * Turn on async CSC interrupts. This appears to
802 * be the default, but the old, pre pci-aware, code
803 * did this and it appears PAO does as well.
805 diagctl = pci_read_config(dev, TI12XX_PCI_DIAGNOSTIC, 1);
806 diagctl |= TI12XX_DIAG_CSC_INTR;
807 pci_write_config(dev, TI12XX_PCI_DIAGNOSTIC, diagctl, 1);
810 * Turn off Zoom Video. Some cards have this enabled,
811 * some do not but it causes problems when enabled. This
812 * register doesn't exist on the 1130 (and likely the 1131,
813 * but without a datasheet it is impossible to know).
814 * Some 12xx chips may not have it, but setting it is
815 * believed to be harmless on those models.
817 pci_write_config(dev, TI12XX_PCI_MULTIMEDIA_CONTROL, 0, 4);
819 if (cardcntl & TI113X_CARDCNTL_RING_ENA)
820 printf("[ring enable]");
821 if (cardcntl & TI113X_CARDCNTL_SPKR_ENA)
822 printf("[speaker enable]");
823 if (syscntl & TI113X_SYSCNTL_PWRSAVINGS)
824 printf("[pwr save]");
825 switch(devcntl & TI113X_DEVCNTL_INTR_MASK){
826 case TI113X_DEVCNTL_INTR_ISA :
827 printf("[CSC parallel isa irq]");
829 case TI113X_DEVCNTL_INTR_SERIAL :
830 printf("[CSC serial isa irq]");
832 case TI113X_DEVCNTL_INTR_NONE :
833 printf("[pci only]");
835 case TI12XX_DEVCNTL_INTR_ALLSERIAL :
836 printf("[FUNC pci int + CSC serial isa irq]");
840 pcic_pci_cardbus_init(dev);
844 * Code for TOPIC chips
847 pcic_pci_topic_func(struct pcic_slot *sp, enum pcic_intr_way way)
849 #ifdef THIS_BRAEKS_THINGS
850 device_t dev = sp->sc->dev;
853 scr = pci_read_config(dev, TOPIC_SOCKET_CTRL, 4);
854 if (way == pcic_iw_pci)
855 scr |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
857 scr &= ~TOPIC_SOCKET_CTRL_SCR_IRQSEL;
858 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
860 return (pcic_pci_gen_func(sp, way));
864 pcic_pci_topic_csc(struct pcic_slot *sp, enum pcic_intr_way way)
866 device_t dev = sp->sc->dev;
870 device_id = pci_get_devid(dev);
871 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
872 scr = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
873 if (way == pcic_iw_pci)
874 scr |= TOPIC97_SLOT_CTRL_PCIINT;
876 scr &= ~TOPIC97_SLOT_CTRL_PCIINT;
877 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
884 pcic_pci_topic_init(device_t dev)
886 struct pcic_softc *sc = device_get_softc(dev);
890 device_id = pci_get_devid(dev);
891 reg = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
892 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
893 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
894 reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
895 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
896 reg |= TOPIC97_SLOT_CTRL_PCIINT;
897 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
899 pci_write_config(dev, TOPIC_SLOT_CTRL, reg, 4);
900 pcic_pci_cardbus_init(dev);
902 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
904 * We need to enable voltage sense and 3V cards explicitly
905 * in the bridge. The datasheets I have for both the
906 * ToPIC 97 and 100 both lists these ports. Without
907 * datasheets for the ToPIC95s, I can't tell if we need
908 * to do it there or not.
910 pcic_setb(&sc->slots[0], PCIC_TOPIC_FCR,
911 PCIC_FCR_3V_EN | PCIC_FCR_VS_EN);
916 pcic_pci_cardbus_init(device_t dev)
918 struct pcic_softc *sc = device_get_softc(dev);
922 unit = device_get_unit(dev);
924 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
925 brgcntl |= CB_BCR_WRITE_POST_EN | CB_BCR_MASTER_ABORT;
926 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
928 /* Turn off legacy address */
929 pci_write_config(dev, CB_PCI_LEGACY16_IOADDR, 0, 2);
932 * Write zeros into the remaining memory I/O windows. This
933 * seems to turn off the pci configuration of these things and
934 * make the cardbus bridge use the values for memory
935 * programmed into the pcic registers.
937 pci_write_config(dev, CB_PCI_MEMBASE0, 0, 4);
938 pci_write_config(dev, CB_PCI_MEMLIMIT0, 0, 4);
939 pci_write_config(dev, CB_PCI_MEMBASE1, 0, 4);
940 pci_write_config(dev, CB_PCI_MEMLIMIT1, 0, 4);
941 pci_write_config(dev, CB_PCI_IOBASE0, 0, 4);
942 pci_write_config(dev, CB_PCI_IOLIMIT0, 0, 4);
943 pci_write_config(dev, CB_PCI_IOBASE1, 0, 4);
944 pci_write_config(dev, CB_PCI_IOLIMIT1, 0, 4);
947 * Tell the chip to do its routing thing.
949 sc->chip->func_intr_way(&sc->slots[0], sc->func_route);
950 sc->chip->csc_intr_way(&sc->slots[0], sc->csc_route);
956 pcic_pci_cardtype(u_int32_t stat)
958 if (stat & CB_SS_NOTCARD)
959 return ("unrecognized by bridge");
960 if ((stat & (CB_SS_16BIT | CB_SS_CB)) == (CB_SS_16BIT | CB_SS_CB))
961 return ("16-bit and 32-bit (can't happen)");
962 if (stat & CB_SS_16BIT)
963 return ("16-bit pccard");
965 return ("32-bit cardbus");
966 return ("none (can't happen)");
970 * Card insertion and removal code. The insertion events need to be
971 * debounced so that the noisy insertion/removal events don't result
972 * in the hardware being initialized many times, only to be torn down
973 * as well. This may also cause races with pccardd. Instead, we wait
974 * for the insertion signal to be stable for 0.5 seconds before we declare
975 * it to be a real insertion event. Removal is also debounced. We turn
976 * off interrupt servicing during the settling time to prevent infinite
977 * loops in the driver.
979 * Note: We only handle the card detect change events. We don't handle
980 * power events and status change events.
983 pcic_cd_change(void *arg)
985 struct pcic_softc *sc = (struct pcic_softc *) arg;
986 struct pcic_slot *sp = &sc->slots[0];
990 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
992 /* Status changed while present; remove the card from the system. */
993 if (sc->cd_present) {
995 pccard_event(sp->slt, card_removed);
997 /* Nothing to do if the debounced state is 'not present'. */
998 if ((stat & CB_SS_CD) != 0)
1002 if (bootverbose && (stat & CB_SS_BADVCC) != 0)
1003 device_printf(sc->dev, "BAD Vcc request: 0x%x\n", stat);
1004 if ((stat & CB_SS_16BIT) == 0)
1005 device_printf(sp->sc->dev, "Card type %s is unsupported\n",
1006 pcic_pci_cardtype(stat));
1008 pccard_event(sp->slt, card_inserted);
1012 pcic_pci_intr(void *arg)
1014 struct pcic_softc *sc = (struct pcic_softc *) arg;
1015 struct pcic_slot *sp = &sc->slots[0];
1018 event = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_EVENT);
1021 device_printf(sc->dev, "Event mask 0x%x\n", event);
1024 * Treat all card-detect signal transitions the same way
1025 * since we can't reliably tell if this is an insert or a
1026 * remove event. Stop the card from getting interrupts and
1027 * defer the insert/remove event until the CB_SOCKET_STATE
1028 * signals have had time to settle.
1030 if ((event & CB_SE_CD) != 0) {
1031 if (sc->cd_pending) {
1032 untimeout(pcic_cd_change, arg, sc->cd_ch);
1036 sc->cd_ch = timeout(pcic_cd_change, arg, hz/2);
1037 sc->func_intr = NULL;
1040 /* Ack the interrupt */
1041 bus_space_write_4(sp->bst, sp->bsh, 0, event);
1045 * Some TI chips also require us to read the old ExCA register for
1046 * card status change when we route CSC via PCI! So, we go ahead
1047 * and read it to clear the bits. Maybe we should check the status
1048 * ala the ISA interrupt handler, but those changes should be caught
1051 * We have to check it every interrupt because these bits can sometimes
1052 * show up indepentently of the CB_SOCKET_EVENT register above.
1054 sp->getb(sp, PCIC_STAT_CHG);
1058 * Return the ID string for the controller if the vendor/product id
1059 * matches, NULL otherwise.
1062 pcic_pci_probe(device_t dev)
1067 u_int32_t device_id;
1068 struct pcic_pci_table *itm;
1069 struct resource *res;
1072 if (pcic_ignore_pci)
1074 device_id = pci_get_devid(dev);
1076 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1077 if (pcic_ignore_function_1 && pci_get_function(dev) == 1) {
1079 PRVERB((dev, "Ignoring function 1\n"));
1084 if (desc == NULL && pci_get_class(dev) == PCIC_BRIDGE) {
1085 subclass = pci_get_subclass(dev);
1086 progif = pci_get_progif(dev);
1087 if (subclass == PCIS_BRIDGE_PCMCIA && progif == 0)
1088 desc = "Generic PCI-PCMCIA Bridge";
1089 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0)
1090 desc = "YENTA PCI-CardBus Bridge";
1091 if (bootverbose && desc)
1092 printf("Found unknown %s devid 0x%x\n", desc, device_id);
1096 device_set_desc(dev, desc);
1099 * Take us out of power down mode, if necessary. It also
1100 * appears that even reading the power register is enough on
1101 * some systems to cause correct behavior.
1103 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1104 /* Reset the power state. */
1105 device_printf(dev, "chip is in D%d power mode "
1106 "-- setting to D0\n", pci_get_powerstate(dev));
1107 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1111 * Allocated/deallocate interrupt. This forces the PCI BIOS or
1112 * other MD method to route the interrupts to this card.
1113 * This so we get the interrupt number in the probe message.
1114 * We only need to route interrupts when we're doing pci
1115 * parallel interrupt routing.
1117 * We use two different variables for the memory based and I/O
1118 * based cards, so the check here is a little more complex than
1119 * one would otherwise hope.
1121 * XXX The bus code for PCI really should do this for us.
1123 if ((pcic_intr_path == pcic_iw_pci &&
1124 device_id != PCIC_ID_CLPD6729) ||
1125 (pcic_pd6729_intr_path == pcic_iw_pci &&
1126 device_id == PCIC_ID_CLPD6729)) {
1130 * IRQ 0 is invalid on x86, but not other platforms.
1131 * If we have irq 0, then write 255 to force a new, non-
1132 * bogus one to be assigned. I think that in -current
1133 * the code in this ifdef may be obsolete with the new
1134 * invalid mapping that we're doing in the pci layer -- imp
1136 if (pci_get_irq(dev) == 0) {
1137 pci_set_irq(dev, 255);
1138 pci_write_config(dev, PCIR_INTLINE, 255, 1);
1141 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1144 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
1151 pcic_pci_shutdown(device_t dev)
1154 * More reports of things working w/o this code than with it.
1157 struct pcic_softc *sc;
1158 struct pcic_slot *sp;
1160 sc = (struct pcic_softc *) device_get_softc(dev);
1164 * Turn off the power to the slot in an attempt to
1165 * keep the system from hanging on reboot. We also turn off
1166 * card interrupts in an attempt to control interrupt storms.
1167 * on some (all?) this has the effect of also turning off
1168 * card status change interrupts. A side effect of writing 0
1169 * to INT_GEN is that the card is placed into "reset" mode
1170 * where nothing happens until it is taken out of "reset"
1173 * Also, turn off the generation of status interrupts too.
1175 sp->putb(sp, PCIC_INT_GEN, 0);
1176 sp->putb(sp, PCIC_STAT_INT, 0);
1177 sp->putb(sp, PCIC_POWER, 0);
1181 * Writing to INT_GEN can cause an interrupt, so we blindly
1182 * ack all possible interrupts here. Reading the stat change
1183 * shouldn't be necessary, but some TI chipsets need it in the
1184 * normal course of operations, so we do it here too. We can't
1185 * lose any interrupts after this point, so go ahead and ack
1186 * everything. The bits in INT_GEN clear upon reading them.
1187 * We also set the interrupt mask to 0, in an effort to avoid
1188 * getting further interrupts.
1190 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_MASK, 0);
1191 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_EVENT, 0xffffffff);
1192 sp->getb(sp, PCIC_STAT_CHG);
1197 * Print out the config space
1200 pcic_pci_print_config(device_t dev)
1204 device_printf(dev, "PCI Configuration space:");
1205 for (i = 0; i < 256; i += 4) {
1207 printf("\n 0x%02x: ", i);
1208 printf("0x%08x ", pci_read_config(dev, i, 4));
1214 * Generic pci interrupt attach routine. It tries to understand all parts,
1215 * and do sane things for those parts it does not understand.
1218 pcic_pci_attach(device_t dev)
1220 u_int32_t device_id = pci_get_devid(dev);
1222 struct pcic_slot *sp;
1223 struct pcic_softc *sc;
1226 struct pcic_pci_table *itm;
1229 struct resource *r = NULL;
1232 driver_intr_t *intr = NULL;
1235 * In sys/pci/pcireg.h, PCIR_COMMAND must be separated
1236 * PCI_COMMAND_REG(0x04) and PCI_STATUS_REG(0x06).
1237 * Takeshi Shibagaki(shiba@jp.freebsd.org).
1239 command = pci_read_config(dev, PCIR_COMMAND, 4);
1240 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN;
1241 pci_write_config(dev, PCIR_COMMAND, command, 4);
1243 sc = (struct pcic_softc *) device_get_softc(dev);
1246 sockbase = pci_read_config(dev, 0x10, 4);
1247 if (sockbase & 0x1) {
1248 sc->iorid = CB_PCI_SOCKET_BASE;
1249 sc->iores = bus_alloc_resource(dev, SYS_RES_IOPORT,
1250 &sc->iorid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
1251 if (sc->iores == NULL)
1254 sc->flags = PCIC_PD_POWER;
1255 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1256 for (i = 0; i < 2; i++) {
1257 sp[i].bst = rman_get_bustag(sc->iores);
1258 sp[i].bsh = rman_get_bushandle(sc->iores);
1261 sp[i].getb = pcic_getb_io;
1262 sp[i].putb = pcic_putb_io;
1263 sp[i].offset = i * PCIC_SLOT_SIZE;
1264 sp[i].controller = itm ? itm->type : PCIC_PD6729;
1265 if ((sp[i].getb(&sp[i], PCIC_ID_REV) & 0xc0) == 0x80)
1266 sp[i].slt = (struct slot *) 1;
1268 sc->csc_route = sc->func_route = pcic_pd6729_intr_path;
1270 sc->flags = itm->flags;
1272 * We have to use the ISA interrupt routine for status
1273 * changes since we don't have any "yenta" pci registers.
1274 * We have to do this even when we're using pci type
1275 * interrupts because on these cards the interrupts are
1276 * cleared in the same way that the ISA cards clear them.
1278 intr = pcic_isa_intr;
1280 sc->memrid = CB_PCI_SOCKET_BASE;
1281 sc->memres = bus_alloc_resource(dev, SYS_RES_MEMORY,
1282 &sc->memrid, 0, ~0, 1, RF_ACTIVE);
1283 if (sc->memres == NULL && pcic_pci_get_memory(dev) != 0)
1285 sp->getb = pcic_pci_getb2;
1286 sp->putb = pcic_pci_putb2;
1287 sp->offset = CB_EXCA_OFFSET;
1288 sp->bst = rman_get_bustag(sc->memres);
1289 sp->bsh = rman_get_bushandle(sc->memres);
1290 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1292 sp->controller = itm->type;
1294 sc->flags = itm->flags;
1296 /* By default, assume we're a D step compatible */
1297 sp->controller = PCIC_I82365SL_DF;
1299 sc->flags = PCIC_CARDBUS_POWER;
1301 /* All memory mapped cardbus bridges have these registers */
1302 sc->flags |= PCIC_YENTA_HIGH_MEMORY;
1303 sp->slt = (struct slot *) 1;
1304 sc->csc_route = pcic_intr_path;
1305 sc->func_route = pcic_intr_path;
1306 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1307 sc->cd_present = (stat & CB_SS_CD) == 0;
1311 sc->chip = itm->chip;
1313 sc->chip = &pcic_pci_generic_chip;
1315 if (sc->csc_route == pcic_iw_pci) {
1317 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1318 RF_ACTIVE | RF_SHAREABLE);
1320 sc->csc_route = pcic_iw_isa;
1321 sc->func_route = pcic_iw_isa;
1323 "No PCI interrupt routed, trying ISA.\n");
1326 intr = pcic_pci_intr;
1327 irq = rman_get_start(r);
1330 if (sc->csc_route == pcic_iw_isa) {
1332 irq = pcic_override_irq;
1334 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, irq,
1338 "Can't route ISA CSC interrupt.\n");
1343 "Management interrupt on ISA IRQ %ld\n", irq);
1345 intr = pcic_isa_intr;
1347 sc->slot_poll = pcic_timeout;
1348 sc->timeout_ch = timeout(sc->slot_poll, sc, hz/2);
1349 device_printf(dev, "Polling mode\n");
1355 * Initialize AFTER we figure out what kind of interrupt we're
1356 * going to be using, if any.
1359 panic("Bug: sc->chip not set!\n");
1360 sc->chip->init(dev);
1363 * Now install the interrupt handler, if necessary.
1369 error = bus_setup_intr(dev, r, INTR_TYPE_AV, intr, sc, &sc->ih);
1376 pcic_pci_print_config(dev);
1377 return (pcic_attach(dev));
1381 pcic_pci_detach(device_t dev)
1383 return (EBUSY); /* Can't detach this device */
1387 * The PCI bus should do this for us. However, it doesn't quite yet, so
1388 * we cope by doing it ourselves. If it ever does, this code can go quietly
1389 * into that good night.
1392 pcic_pci_get_memory(device_t dev)
1394 struct pcic_softc *sc;
1397 sc = (struct pcic_softc *) device_get_softc(dev);
1398 sockbase = pci_read_config(dev, sc->memrid, 4);
1399 if (sockbase >= 0x100000 && sockbase < 0xfffffff0) {
1400 device_printf(dev, "Could not map register memory 0x%x\n",
1404 pci_write_config(dev, sc->memrid, 0xffffffff, 4);
1405 sockbase = pci_read_config(dev, sc->memrid, 4);
1406 sockbase = (sockbase & 0xfffffff0) & -(sockbase & 0xfffffff0);
1407 #define CARDBUS_SYS_RES_MEMORY_START 0x88000000
1408 #define CARDBUS_SYS_RES_MEMORY_END 0xFFFFFFFF
1409 sc->memres = bus_generic_alloc_resource(device_get_parent(dev),
1410 dev, SYS_RES_MEMORY, &sc->memrid,
1411 CARDBUS_SYS_RES_MEMORY_START, CARDBUS_SYS_RES_MEMORY_END,
1412 sockbase, RF_ACTIVE | rman_make_alignment_flags(sockbase));
1413 if (sc->memres == NULL) {
1414 device_printf(dev, "Could not grab register memory\n");
1417 sockbase = rman_get_start(sc->memres);
1418 pci_write_config(dev, sc->memrid, sockbase, 4);
1419 device_printf(dev, "PCI Memory allocated: 0x%08x\n", sockbase);
1424 pcic_pci_gen_mapirq(struct pcic_slot *sp, int irq)
1427 * If we're doing ISA interrupt routing, then just go to the
1428 * generic ISA routine. Also, irq 0 means turn off the interrupts
1431 if (sp->sc->func_route == pcic_iw_isa || irq == 0)
1432 return (pcic_isa_mapirq(sp, irq));
1435 * Ohterwise we're doing PCI interrupts. For those cardbus bridges
1436 * that follow yenta (and the one pcmcia bridge that does), we don't
1437 * do a thing to get the IRQ mapped into the system. However,
1438 * for other controllers that are PCI, but not yetna compliant, we
1439 * need to do some special mapping.
1441 * XXX Maybe we shouldn't assume INTA#, but rather as the function
1442 * XXX what Intline to use.
1444 if (sp->controller == PCIC_PD6729) {
1451 sp->putb(sp, PCIC_INT_GEN, /* Assume INTA# */
1452 (sp->getb(sp, PCIC_INT_GEN) & 0xF0) | 3);
1459 pcic_pci_func_intr(void *arg)
1461 struct pcic_softc *sc = (struct pcic_softc *) arg;
1462 struct pcic_slot *sp = &sc->slots[0];
1467 * The 6729 controller is a weird one, and we have to use
1468 * the ISA registers to check to see if the card is there.
1469 * Otherwise we look at the PCI state register to find out
1470 * if the card is there.
1472 if (sp->controller == PCIC_PD6729) {
1473 if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) == PCIC_CD)
1477 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1478 if ((stat & CB_SS_CD) == 0 && sc->func_intr != 0)
1481 if (doit && sc->func_intr != NULL)
1482 sc->func_intr(sc->func_arg);
1486 pcic_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
1487 int flags, driver_intr_t *intr, void *arg, void **cookiep)
1489 struct pcic_softc *sc = device_get_softc(dev);
1490 struct pcic_slot *sp = &sc->slots[0];
1493 if (sc->func_route == pcic_iw_isa)
1494 return(pcic_setup_intr(dev, child, irq, flags, intr, arg,
1497 #if __FreeBSD_version >= 500000
1498 if ((flags & INTR_FAST) != 0)
1500 if ((flags & INTR_TYPE_FAST) != 0)
1503 if (sc->func_intr != NULL) {
1504 device_printf(child, "Can't establish another ISR\n");
1508 err = bus_generic_setup_intr(dev, child, irq, flags,
1509 pcic_pci_func_intr, sc, cookiep);
1512 sc->chip->map_irq(sp, rman_get_start(irq));
1513 sc->func_intr = intr;
1519 pcic_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
1522 struct pcic_softc *sc = device_get_softc(dev);
1524 if (sc->func_route == pcic_iw_isa)
1525 return (pcic_teardown_intr(dev, child, irq, cookie));
1526 sc->func_intr = NULL;
1527 return (bus_generic_teardown_intr(dev, child, irq, cookie));
1531 pcic_pci_resume(device_t dev)
1533 struct pcic_softc *sc = device_get_softc(dev);
1536 * Some BIOSes will not save the BARs for the pci chips, so we
1537 * must do it ourselves. If the BAR is reset to 0 for an I/O
1538 * device, it will read back as 0x1, so no explicit test for
1539 * memory devices are needed.
1541 * Note: The PCI bus code should do this automatically for us on
1542 * suspend/resume, but until it does, we have to cope.
1544 if (pci_read_config(dev, CB_PCI_SOCKET_BASE, 4) == 0)
1545 pci_write_config(dev, CB_PCI_SOCKET_BASE,
1546 rman_get_start(sc->memres), 4);
1547 return (bus_generic_resume(dev));
1550 static device_method_t pcic_pci_methods[] = {
1551 /* Device interface */
1552 DEVMETHOD(device_probe, pcic_pci_probe),
1553 DEVMETHOD(device_attach, pcic_pci_attach),
1554 DEVMETHOD(device_detach, pcic_pci_detach),
1555 DEVMETHOD(device_suspend, bus_generic_suspend),
1556 DEVMETHOD(device_resume, pcic_pci_resume),
1557 DEVMETHOD(device_shutdown, pcic_pci_shutdown),
1560 DEVMETHOD(bus_print_child, bus_generic_print_child),
1561 DEVMETHOD(bus_alloc_resource, pcic_alloc_resource),
1562 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
1563 DEVMETHOD(bus_activate_resource, pcic_activate_resource),
1564 DEVMETHOD(bus_deactivate_resource, pcic_deactivate_resource),
1565 DEVMETHOD(bus_setup_intr, pcic_pci_setup_intr),
1566 DEVMETHOD(bus_teardown_intr, pcic_pci_teardown_intr),
1568 /* Card interface */
1569 DEVMETHOD(card_set_res_flags, pcic_set_res_flags),
1570 DEVMETHOD(card_get_res_flags, pcic_get_res_flags),
1571 DEVMETHOD(card_set_memory_offset, pcic_set_memory_offset),
1572 DEVMETHOD(card_get_memory_offset, pcic_get_memory_offset),
1577 static driver_t pcic_pci_driver = {
1580 sizeof(struct pcic_softc)
1583 DRIVER_MODULE(pcic, pci, pcic_pci_driver, pcic_devclass, 0, 0);