1 /* $FreeBSD: src/sys/dev/snc/if_sncreg.h,v 1.1.2.1 2000/10/21 03:30:03 nyan Exp $ */
2 /* $DragonFly: src/sys/dev/netif/snc/Attic/if_sncreg.h,v 1.2 2003/06/17 04:28:30 dillon Exp $ */
3 /* $NecBSD: if_snreg.h,v 1.3 1999/01/24 01:39:52 kmatsuda Exp $ */
7 * Copyright (c) 1997, 1998, 1999
8 * Kouichi Matsuda. All rights reserved.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Kouichi Matsuda for
22 * 4. The name of the author may not be used to endorse or promote products
23 * derived from this software without specific prior written permission
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Modified for NetBSD/pc98 1.2.1 from NetBSD/mac68k 1.2D by Kouichi Matsuda.
38 * Make adapted for NEC PC-9801-83, 84, PC-9801-103, 104, PC-9801N-25 and
39 * PC-9801N-J02R, which uses National Semiconductor DP83934AVQB as
40 * Ethernet Controller and National Semiconductor NS46C46 as (64 * 16 bits)
41 * Microwire Serial EEPROM.
45 * XXX: Should not be HERE. (Should be shared with...)
49 * NEC/SONIC port mappings, offset from iobase.
51 #define SNEC_CTRL 0 /* SONIC control port (word) */
52 #define SNEC_CTRLB 1 /* NEC/SONIC control port (byte) */
53 #define SNEC_RSVD0 2 /* not used */
54 #define SNEC_ADDR 3 /* SONIC, NEC/SONIC register address set port */
55 #define SNEC_RSVD1 4 /* not used */
56 #define SNEC_RSVD2 5 /* not used */
60 /* bank memory size */
61 #define SNEC_NMEMS (NBPG * 2)
63 #define SNEC_NBANK 0x10
64 /* internal buffer size */
65 #define SNEC_NBUF (SNEC_NMEMS * SNEC_NBANK)
69 * NEC/SONIC specific internal registers.
73 * Memory Bank Select Register (MEMBS)
75 #define SNECR_MEMBS 0x80
76 #define SNECR_MEMBS_BSEN 0x01 /* enable memory bank select */
77 #define SNECR_MEMBS_EBNMSK 0x1c /* encoded bank select number */
78 /* Translate bank number to encoded bank select number. */
79 #define SNECR_MEMBS_B2EB(bank) (bank << 2)
80 #define SNECR_MEMBS_PCMCIABUS 0x80 /* bus type identification */
83 * Memory Base Address Select Register (MEMSEL)
85 #define SNECR_MEMSEL 0x82
86 /* Translate base phys address to encoded select number. */
87 #define SNECR_MEMSEL_PHYS2EN(maddr) ((maddr >> 13) & 0x0f)
90 * Encoded Irq Select Register (IRQSEL)
92 #define SNECR_IRQSEL 0x84
95 * EEPROM Access Register (EEP)
97 #define SNECR_EEP 0x86
98 #define SNECR_EEP_DI 0x10 /* EEPROM Serial Data Input (high) */
99 #define SNECR_EEP_CS 0x20 /* EEPROM Chip Select (high) */
100 #define SNECR_EEP_SK 0x40 /* EEPROM Serial Data Clock (high) */
101 #define SNECR_EEP_DO 0x80 /* EEPROM Serial Data Output (high) */
103 /* EEPROM data locations */
104 #define SNEC_EEPROM_KEY0 6 /* Station Address Check Sum Key #1 */
105 #define SNEC_EEPROM_KEY1 7 /* Station Address Check Sum Key #2 */
106 #define SNEC_EEPROM_SA0 8 /* Station Address #1 */
107 #define SNEC_EEPROM_SA1 9 /* Station Address #2 */
108 #define SNEC_EEPROM_SA2 10 /* Station Address #3 */
109 #define SNEC_EEPROM_SA3 11 /* Station Address #4 */
110 #define SNEC_EEPROM_SA4 12 /* Station Address #5 */
111 #define SNEC_EEPROM_SA5 13 /* Station Address #6 */
112 #define SNEC_EEPROM_CKSUM 14 /* Station Address Check Sum */
114 #define SNEC_EEPROM_SIZE 32 /* valid EEPROM data (max 128 bytes) */
117 * Bus and Mode Identification Register (IDENT)
119 #define SNECR_IDENT 0x88
120 /* Bit 0: Bus Identification. */
121 #define SNECR_IDENT_CBUS 0x01 /* on PC-98 C-Bus */
122 #define SNECR_IDENT_PCMCIABUS 0x00 /* on PCMCIA Bus */
123 /* Bit 2: always 1 */
124 #define SNECR_IDENT_MAGIC 0x04
125 /* Bit 4: Bus Configuration Mode Identification. */
126 #define SNECR_IDENT_PNP 0x10 /* Plug and Play (C-Bus and PCMCIA) */
127 #define SNECR_IDENT_LEGACY 0x00 /* Legacy C-Bus */
129 #define SNECR_IDENT_LEGACY_CBUS \
130 (SNECR_IDENT_LEGACY | SNECR_IDENT_MAGIC | SNECR_IDENT_CBUS)
131 #define SNECR_IDENT_PNP_CBUS \
132 (SNECR_IDENT_PNP | SNECR_IDENT_MAGIC | SNECR_IDENT_CBUS)
133 #define SNECR_IDENT_PNP_PCMCIABUS \
134 (SNECR_IDENT_PNP | SNECR_IDENT_MAGIC | SNECR_IDENT_PCMCIABUS)
137 * XXX: parent bus type aliases
139 #define SNEC_TYPE_LEGACY 0
140 #define SNEC_TYPE_PNP 1